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imxmmc: Checkpatch cleanup
[net-next-2.6.git] / drivers / mmc / host / imxmmc.c
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56ca9040 1/*
70f10482 2 * linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver
56ca9040
PP		 3 *
4 * Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
5 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
6 *
7 * derived from pxamci.c by Russell King
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
56ca9040 13 */
56ca9040 14
56ca9040
PP		 15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/ioport.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
20#include <linux/blkdev.h>
21#include <linux/dma-mapping.h>
22#include <linux/mmc/host.h>
23#include <linux/mmc/card.h>
56ca9040 24#include <linux/delay.h>
38a41fdf 25#include <linux/clk.h>
4b7c0e4c 26#include <linux/io.h>
56ca9040
PP		 27
28#include <asm/dma.h>
56ca9040
PP		 29#include <asm/irq.h>
30#include <asm/sizes.h>
a09e64fb
RK		 31#include <mach/mmc.h>
32#include <mach/imx-dma.h>
56ca9040
PP		 33
34#include "imxmmc.h"
35
36#define DRIVER_NAME "imx-mmc"
37
38#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
4b7c0e4c
MKB		 39 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
40 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
56ca9040
PP		 41
42struct imxmci_host {
43 struct mmc_host *mmc;
44 spinlock_t lock;
45 struct resource *res;
46 int irq;
47 imx_dmach_t dma;
48 unsigned int clkrt;
49 unsigned int cmdat;
50 volatile unsigned int imask;
51 unsigned int power_mode;
52 unsigned int present;
53 struct imxmmc_platform_data *pdata;
54
55 struct mmc_request *req;
56 struct mmc_command *cmd;
57 struct mmc_data *data;
58
59 struct timer_list timer;
60 struct tasklet_struct tasklet;
61 unsigned int status_reg;
62 unsigned long pending_events;
4b7c0e4c 63 /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
56ca9040
PP		 64 u16 *data_ptr;
65 unsigned int data_cnt;
66 atomic_t stuck_timeout;
67
68 unsigned int dma_nents;
69 unsigned int dma_size;
70 unsigned int dma_dir;
71 int dma_allocated;
72
73 unsigned char actual_bus_width;
148f93d5
PP		 74
75 int prev_cmd_code;
38a41fdf
SH		 76
77 struct clk *clk;
56ca9040
PP		 78};
79
80#define IMXMCI_PEND_IRQ_b 0
81#define IMXMCI_PEND_DMA_END_b 1
82#define IMXMCI_PEND_DMA_ERR_b 2
83#define IMXMCI_PEND_WAIT_RESP_b 3
84#define IMXMCI_PEND_DMA_DATA_b 4
85#define IMXMCI_PEND_CPU_DATA_b 5
86#define IMXMCI_PEND_CARD_XCHG_b 6
87#define IMXMCI_PEND_SET_INIT_b 7
81d38428 88#define IMXMCI_PEND_STARTED_b 8
56ca9040
PP		 89
90#define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b)
91#define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b)
92#define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b)
93#define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
94#define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b)
95#define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b)
96#define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
97#define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b)
81d38428 98#define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b)
56ca9040
PP		 99
100static void imxmci_stop_clock(struct imxmci_host *host)
101{
102 int i = 0;
103 MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
4b7c0e4c
MKB		 104 while (i < 0x1000) {
105 if (!(i & 0x7f))
56ca9040
PP		 106 MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
107
4b7c0e4c 108 if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
56ca9040 109 /* Check twice before cut */
4b7c0e4c 110 if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
56ca9040
PP		 111 return;
112 }
113
114 i++;
115 }
116 dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
117}
118
81d38428 119static int imxmci_start_clock(struct imxmci_host *host)
56ca9040 120{
81d38428
PP		 121 unsigned int trials = 0;
122 unsigned int delay_limit = 128;
123 unsigned long flags;
124
56ca9040 125 MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
56ca9040 126
81d38428
PP		 127 clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
128
129 /*
130 * Command start of the clock, this usually succeeds in less
131 * then 6 delay loops, but during card detection (low clockrate)
132 * it takes up to 5000 delay loops and sometimes fails for the first time
133 */
134 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
135
136 do {
137 unsigned int delay = delay_limit;
138
4b7c0e4c
MKB		 139 while (delay--) {
140 if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
81d38428 141 /* Check twice before cut */
4b7c0e4c 142 if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
81d38428
PP		 143 return 0;
144
4b7c0e4c 145 if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
81d38428 146 return 0;
56ca9040
PP		 147 }
148
81d38428
PP		 149 local_irq_save(flags);
150 /*
151 * Ensure, that request is not doubled under all possible circumstances.
152 * It is possible, that cock running state is missed, because some other
153 * IRQ or schedule delays this function execution and the clocks has
154 * been already stopped by other means (response processing, SDHC HW)
155 */
4b7c0e4c 156 if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
81d38428
PP		 157 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
158 local_irq_restore(flags);
159
4b7c0e4c 160 } while (++trials < 256);
81d38428
PP		 161
162 dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
163
164 return -1;
56ca9040
PP		 165}
166
167static void imxmci_softreset(void)
168{
169 /* reset sequence */
170 MMC_STR_STP_CLK = 0x8;
171 MMC_STR_STP_CLK = 0xD;
172 MMC_STR_STP_CLK = 0x5;
173 MMC_STR_STP_CLK = 0x5;
174 MMC_STR_STP_CLK = 0x5;
175 MMC_STR_STP_CLK = 0x5;
176 MMC_STR_STP_CLK = 0x5;
177 MMC_STR_STP_CLK = 0x5;
178 MMC_STR_STP_CLK = 0x5;
179 MMC_STR_STP_CLK = 0x5;
180
181 MMC_RES_TO = 0xff;
182 MMC_BLK_LEN = 512;
183 MMC_NOB = 1;
184}
185
186static int imxmci_busy_wait_for_status(struct imxmci_host *host,
4b7c0e4c
MKB		 187 unsigned int *pstat, unsigned int stat_mask,
188 int timeout, const char *where)
56ca9040 189{
4b7c0e4c
MKB		 190 int loops = 0;
191
192 while (!(*pstat & stat_mask)) {
193 loops += 2;
194 if (loops >= timeout) {
56ca9040
PP		 195 dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
196 where, *pstat, stat_mask);
197 return -1;
198 }
199 udelay(2);
200 *pstat |= MMC_STATUS;
201 }
4b7c0e4c 202 if (!loops)
56ca9040
PP		 203 return 0;
204
2c171bf1 205 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
4b7c0e4c 206 if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
2c171bf1 207 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
4b7c0e4c 208 loops, where, *pstat, stat_mask);
56ca9040
PP		 209 return loops;
210}
211
212static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
213{
214 unsigned int nob = data->blocks;
a3fd4a1b 215 unsigned int blksz = data->blksz;
56ca9040
PP		 216 unsigned int datasz = nob * blksz;
217 int i;
218
219 if (data->flags & MMC_DATA_STREAM)
220 nob = 0xffff;
221
222 host->data = data;
223 data->bytes_xfered = 0;
224
225 MMC_NOB = nob;
226 MMC_BLK_LEN = blksz;
227
228 /*
229 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
230 * We are in big troubles for non-512 byte transfers according to note in the paragraph
231 * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
232 * The situation is even more complex in reality. The SDHC in not able to handle wll
233 * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
234 * This is required for SCR read at least.
235 */
148f93d5 236 if (datasz < 512) {
56ca9040
PP		 237 host->dma_size = datasz;
238 if (data->flags & MMC_DATA_READ) {
239 host->dma_dir = DMA_FROM_DEVICE;
240
241 /* Hack to enable read SCR */
148f93d5
PP		 242 MMC_NOB = 1;
243 MMC_BLK_LEN = 512;
56ca9040
PP		 244 } else {
245 host->dma_dir = DMA_TO_DEVICE;
246 }
247
248 /* Convert back to virtual address */
4b7c0e4c 249 host->data_ptr = (u16 *)sg_virt(data->sg);
56ca9040
PP		 250 host->data_cnt = 0;
251
252 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
253 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
254
255 return;
256 }
257
258 if (data->flags & MMC_DATA_READ) {
259 host->dma_dir = DMA_FROM_DEVICE;
260 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
4b7c0e4c 261 data->sg_len, host->dma_dir);
56ca9040
PP		 262
263 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
4b7c0e4c 264 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
56ca9040
PP		 265
266 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
267 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
268 } else {
269 host->dma_dir = DMA_TO_DEVICE;
270
271 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
4b7c0e4c 272 data->sg_len, host->dma_dir);
56ca9040
PP		 273
274 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
4b7c0e4c 275 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
56ca9040
PP		 276
277 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
278 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
279 }
280
281#if 1 /* This code is there only for consistency checking and can be disabled in future */
282 host->dma_size = 0;
4b7c0e4c
MKB		 283 for (i = 0; i < host->dma_nents; i++)
284 host->dma_size += data->sg[i].length;
56ca9040
PP		 285
286 if (datasz > host->dma_size) {
287 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
4b7c0e4c 288 datasz, host->dma_size);
56ca9040
PP		 289 }
290#endif
291
292 host->dma_size = datasz;
293
294 wmb();
295
4b7c0e4c 296 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
56ca9040
PP		 297 BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */
298 else
299 BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */
300
301 RSSR(host->dma) = DMA_REQ_SDHC;
302
303 set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
304 clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
305
306 /* start DMA engine for read, write is delayed after initial response */
4b7c0e4c 307 if (host->dma_dir == DMA_FROM_DEVICE)
56ca9040 308 imx_dma_enable(host->dma);
56ca9040
PP		 309}
310
311static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
312{
313 unsigned long flags;
314 u32 imask;
315
316 WARN_ON(host->cmd != NULL);
317 host->cmd = cmd;
318
2c171bf1
PP		 319 /* Ensure, that clock are stopped else command programming and start fails */
320 imxmci_stop_clock(host);
321
56ca9040
PP		 322 if (cmd->flags & MMC_RSP_BUSY)
323 cmdat |= CMD_DAT_CONT_BUSY;
324
325 switch (mmc_resp_type(cmd)) {
326 case MMC_RSP_R1: /* short CRC, OPCODE */
327 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
328 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
329 break;
330 case MMC_RSP_R2: /* long 136 bit + CRC */
331 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
332 break;
333 case MMC_RSP_R3: /* short */
334 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
335 break;
56ca9040
PP		 336 default:
337 break;
338 }
339
4b7c0e4c 340 if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
56ca9040
PP		 341 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
342
4b7c0e4c 343 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
56ca9040
PP		 344 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
345
346 MMC_CMD = cmd->opcode;
347 MMC_ARGH = cmd->arg >> 16;
348 MMC_ARGL = cmd->arg & 0xffff;
349 MMC_CMD_DAT_CONT = cmdat;
350
351 atomic_set(&host->stuck_timeout, 0);
352 set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
353
354
355 imask = IMXMCI_INT_MASK_DEFAULT;
356 imask &= ~INT_MASK_END_CMD_RES;
4b7c0e4c
MKB		 357 if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
358 /* imask &= ~INT_MASK_BUF_READY; */
56ca9040 359 imask &= ~INT_MASK_DATA_TRAN;
4b7c0e4c 360 if (cmdat & CMD_DAT_CONT_WRITE)
56ca9040 361 imask &= ~INT_MASK_WRITE_OP_DONE;
4b7c0e4c 362 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
56ca9040
PP		 363 imask &= ~INT_MASK_BUF_READY;
364 }
365
366 spin_lock_irqsave(&host->lock, flags);
367 host->imask = imask;
368 MMC_INT_MASK = host->imask;
369 spin_unlock_irqrestore(&host->lock, flags);
370
371 dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
372 cmd->opcode, cmd->opcode, imask);
373
374 imxmci_start_clock(host);
375}
376
377static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
378{
379 unsigned long flags;
380
381 spin_lock_irqsave(&host->lock, flags);
382
383 host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
4b7c0e4c 384 IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
56ca9040
PP		 385
386 host->imask = IMXMCI_INT_MASK_DEFAULT;
387 MMC_INT_MASK = host->imask;
388
389 spin_unlock_irqrestore(&host->lock, flags);
390
4b7c0e4c 391 if (req && req->cmd)
148f93d5
PP		 392 host->prev_cmd_code = req->cmd->opcode;
393
56ca9040
PP		 394 host->req = NULL;
395 host->cmd = NULL;
396 host->data = NULL;
397 mmc_request_done(host->mmc, req);
398}
399
400static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
401{
402 struct mmc_data *data = host->data;
403 int data_error;
404
4b7c0e4c 405 if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
56ca9040
PP		 406 imx_dma_disable(host->dma);
407 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
408 host->dma_dir);
409 }
410
4b7c0e4c
MKB		 411 if (stat & STATUS_ERR_MASK) {
412 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
413 if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
17b0429d 414 data->error = -EILSEQ;
4b7c0e4c 415 else if (stat & STATUS_TIME_OUT_READ)
17b0429d 416 data->error = -ETIMEDOUT;
56ca9040 417 else
17b0429d 418 data->error = -EIO;
56ca9040
PP		 419 } else {
420 data->bytes_xfered = host->dma_size;
421 }
422
423 data_error = data->error;
424
425 host->data = NULL;
426
427 return data_error;
428}
429
430static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
431{
432 struct mmc_command *cmd = host->cmd;
433 int i;
4b7c0e4c 434 u32 a, b, c;
56ca9040
PP		 435 struct mmc_data *data = host->data;
436
437 if (!cmd)
438 return 0;
439
440 host->cmd = NULL;
441
442 if (stat & STATUS_TIME_OUT_RESP) {
443 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
17b0429d 444 cmd->error = -ETIMEDOUT;
56ca9040
PP		 445 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
446 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
17b0429d 447 cmd->error = -EILSEQ;
56ca9040
PP		 448 }
449
4b7c0e4c
MKB		 450 if (cmd->flags & MMC_RSP_PRESENT) {
451 if (cmd->flags & MMC_RSP_136) {
56ca9040 452 for (i = 0; i < 4; i++) {
4b7c0e4c
MKB		 453 u32 d = MMC_RES_FIFO & 0xffff;
454 u32 e = MMC_RES_FIFO & 0xffff;
455 cmd->resp[i] = d << 16 | e;
56ca9040
PP		 456 }
457 } else {
458 a = MMC_RES_FIFO & 0xffff;
459 b = MMC_RES_FIFO & 0xffff;
460 c = MMC_RES_FIFO & 0xffff;
4b7c0e4c 461 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
56ca9040
PP		 462 }
463 }
464
465 dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
466 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
467
17b0429d 468 if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) {
56ca9040
PP		 469 if (host->req->data->flags & MMC_DATA_WRITE) {
470
471 /* Wait for FIFO to be empty before starting DMA write */
472
473 stat = MMC_STATUS;
4b7c0e4c
MKB		 474 if (imxmci_busy_wait_for_status(host, &stat,
475 STATUS_APPL_BUFF_FE,
476 40, "imxmci_cmd_done DMA WR") < 0) {
17b0429d 477 cmd->error = -EIO;
56ca9040 478 imxmci_finish_data(host, stat);
4b7c0e4c 479 if (host->req)
56ca9040
PP		 480 imxmci_finish_request(host, host->req);
481 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
4b7c0e4c 482 stat);
56ca9040
PP		 483 return 0;
484 }
485
4b7c0e4c 486 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
56ca9040 487 imx_dma_enable(host->dma);
56ca9040
PP		 488 }
489 } else {
490 struct mmc_request *req;
491 imxmci_stop_clock(host);
492 req = host->req;
493
4b7c0e4c 494 if (data)
56ca9040
PP		 495 imxmci_finish_data(host, stat);
496
4b7c0e4c 497 if (req)
56ca9040 498 imxmci_finish_request(host, req);
4b7c0e4c 499 else
56ca9040 500 dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
56ca9040
PP		 501 }
502
503 return 1;
504}
505
506static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
507{
508 struct mmc_data *data = host->data;
509 int data_error;
510
511 if (!data)
512 return 0;
513
514 data_error = imxmci_finish_data(host, stat);
515
58741e8b 516 if (host->req->stop) {
56ca9040
PP		 517 imxmci_stop_clock(host);
518 imxmci_start_cmd(host, host->req->stop, 0);
519 } else {
520 struct mmc_request *req;
521 req = host->req;
4b7c0e4c 522 if (req)
56ca9040 523 imxmci_finish_request(host, req);
4b7c0e4c 524 else
56ca9040 525 dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
56ca9040
PP		 526 }
527
528 return 1;
529}
530
531static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
532{
533 int i;
534 int burst_len;
56ca9040
PP		 535 int trans_done = 0;
536 unsigned int stat = *pstat;
537
4b7c0e4c 538 if (host->actual_bus_width != MMC_BUS_WIDTH_4)
56ca9040
PP		 539 burst_len = 16;
540 else
541 burst_len = 64;
542
543 /* This is unfortunately required */
544 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
545 stat);
546
148f93d5
PP		 547 udelay(20); /* required for clocks < 8MHz*/
548
4b7c0e4c 549 if (host->dma_dir == DMA_FROM_DEVICE) {
56ca9040 550 imxmci_busy_wait_for_status(host, &stat,
4b7c0e4c
MKB		 551 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
552 STATUS_TIME_OUT_READ,
553 50, "imxmci_cpu_driven_data read");
56ca9040 554
4b7c0e4c
MKB		 555 while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
556 !(stat & STATUS_TIME_OUT_READ) &&
557 (host->data_cnt < 512)) {
148f93d5
PP		 558
559 udelay(20); /* required for clocks < 8MHz*/
56ca9040 560
4b7c0e4c 561 for (i = burst_len; i >= 2 ; i -= 2) {
148f93d5
PP		 562 u16 data;
563 data = MMC_BUFFER_ACCESS;
564 udelay(10); /* required for clocks < 8MHz*/
4b7c0e4c 565 if (host->data_cnt+2 <= host->dma_size) {
148f93d5
PP		 566 *(host->data_ptr++) = data;
567 } else {
4b7c0e4c
MKB		 568 if (host->data_cnt < host->dma_size)
569 *(u8 *)(host->data_ptr) = data;
148f93d5
PP		 570 }
571 host->data_cnt += 2;
56ca9040
PP		 572 }
573
56ca9040
PP		 574 stat = MMC_STATUS;
575
148f93d5
PP		 576 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
577 host->data_cnt, burst_len, stat);
56ca9040 578 }
148f93d5 579
4b7c0e4c 580 if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
148f93d5
PP		 581 trans_done = 1;
582
4b7c0e4c 583 if (host->dma_size & 0x1ff)
148f93d5
PP		 584 stat &= ~STATUS_CRC_READ_ERR;
585
4b7c0e4c 586 if (stat & STATUS_TIME_OUT_READ) {
2cb3320b
PP		 587 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
588 stat);
589 trans_done = -1;
590 }
591
56ca9040
PP		 592 } else {
593 imxmci_busy_wait_for_status(host, &stat,
4b7c0e4c
MKB		 594 STATUS_APPL_BUFF_FE,
595 20, "imxmci_cpu_driven_data write");
56ca9040 596
4b7c0e4c
MKB		 597 while ((stat & STATUS_APPL_BUFF_FE) &&
598 (host->data_cnt < host->dma_size)) {
599 if (burst_len >= host->dma_size - host->data_cnt) {
56ca9040
PP		 600 burst_len = host->dma_size - host->data_cnt;
601 host->data_cnt = host->dma_size;
602 trans_done = 1;
603 } else {
604 host->data_cnt += burst_len;
605 }
606
4b7c0e4c 607 for (i = burst_len; i > 0 ; i -= 2)
56ca9040
PP		 608 MMC_BUFFER_ACCESS = *(host->data_ptr++);
609
610 stat = MMC_STATUS;
611
612 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
613 burst_len, stat);
614 }
615 }
616
617 *pstat = stat;
618
619 return trans_done;
620}
621
7d12e780 622static void imxmci_dma_irq(int dma, void *devid)
56ca9040
PP		 623{
624 struct imxmci_host *host = devid;
625 uint32_t stat = MMC_STATUS;
626
627 atomic_set(&host->stuck_timeout, 0);
628 host->status_reg = stat;
629 set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
630 tasklet_schedule(&host->tasklet);
631}
632
7d12e780 633static irqreturn_t imxmci_irq(int irq, void *devid)
56ca9040
PP		 634{
635 struct imxmci_host *host = devid;
636 uint32_t stat = MMC_STATUS;
637 int handled = 1;
638
639 MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
640
641 atomic_set(&host->stuck_timeout, 0);
642 host->status_reg = stat;
643 set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
81d38428 644 set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
56ca9040
PP		 645 tasklet_schedule(&host->tasklet);
646
647 return IRQ_RETVAL(handled);;
648}
649
650static void imxmci_tasklet_fnc(unsigned long data)
651{
652 struct imxmci_host *host = (struct imxmci_host *)data;
653 u32 stat;
654 unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
655 int timeout = 0;
656
4b7c0e4c 657 if (atomic_read(&host->stuck_timeout) > 4) {
56ca9040
PP		 658 char *what;
659 timeout = 1;
660 stat = MMC_STATUS;
661 host->status_reg = stat;
662 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
663 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
664 what = "RESP+DMA";
665 else
666 what = "RESP";
667 else
668 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
4b7c0e4c 669 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
56ca9040
PP		 670 what = "DATA";
671 else
672 what = "DMA";
673 else
674 what = "???";
675
676 dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
4b7c0e4c 677 what, stat, MMC_INT_MASK);
56ca9040 678 dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
4b7c0e4c 679 MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
148f93d5 680 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
4b7c0e4c 681 host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1 << host->actual_bus_width, host->dma_size);
56ca9040
PP		 682 }
683
4b7c0e4c 684 if (!host->present || timeout)
56ca9040 685 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
4b7c0e4c 686 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
56ca9040 687
4b7c0e4c 688 if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
56ca9040
PP		 689 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
690
691 stat = MMC_STATUS;
692 /*
693 * This is not required in theory, but there is chance to miss some flag
694 * which clears automatically by mask write, FreeScale original code keeps
695 * stat from IRQ time so do I
696 */
697 stat |= host->status_reg;
698
4b7c0e4c 699 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
2cb3320b
PP		 700 stat &= ~STATUS_CRC_READ_ERR;
701
4b7c0e4c 702 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
56ca9040 703 imxmci_busy_wait_for_status(host, &stat,
4b7c0e4c
MKB		 704 STATUS_END_CMD_RESP | STATUS_ERR_MASK,
705 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
56ca9040
PP		 706 }
707
4b7c0e4c
MKB		 708 if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
709 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
56ca9040 710 imxmci_cmd_done(host, stat);
4b7c0e4c 711 if (host->data && (stat & STATUS_ERR_MASK))
56ca9040
PP		 712 imxmci_data_done(host, stat);
713 }
714
4b7c0e4c 715 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
56ca9040 716 stat |= MMC_STATUS;
4b7c0e4c
MKB		 717 if (imxmci_cpu_driven_data(host, &stat)) {
718 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
56ca9040
PP		 719 imxmci_cmd_done(host, stat);
720 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
4b7c0e4c 721 &host->pending_events);
56ca9040
PP		 722 imxmci_data_done(host, stat);
723 }
724 }
725 }
726
4b7c0e4c
MKB		 727 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
728 !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
56ca9040
PP		 729
730 stat = MMC_STATUS;
731 /* Same as above */
732 stat |= host->status_reg;
733
4b7c0e4c 734 if (host->dma_dir == DMA_TO_DEVICE)
56ca9040 735 data_dir_mask = STATUS_WRITE_OP_DONE;
4b7c0e4c 736 else
56ca9040 737 data_dir_mask = STATUS_DATA_TRANS_DONE;
56ca9040 738
4b7c0e4c 739 if (stat & data_dir_mask) {
56ca9040
PP		 740 clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
741 imxmci_data_done(host, stat);
742 }
743 }
744
4b7c0e4c 745 if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
56ca9040 746
4b7c0e4c 747 if (host->cmd)
56ca9040
PP		 748 imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
749
4b7c0e4c 750 if (host->data)
56ca9040
PP		 751 imxmci_data_done(host, STATUS_TIME_OUT_READ |
752 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
753
4b7c0e4c 754 if (host->req)
56ca9040
PP		 755 imxmci_finish_request(host, host->req);
756
757 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
758
759 }
760}
761
762static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
763{
764 struct imxmci_host *host = mmc_priv(mmc);
765 unsigned int cmdat;
766
767 WARN_ON(host->req != NULL);
768
769 host->req = req;
770
771 cmdat = 0;
772
773 if (req->data) {
774 imxmci_setup_data(host, req->data);
775
776 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
777
778 if (req->data->flags & MMC_DATA_WRITE)
779 cmdat |= CMD_DAT_CONT_WRITE;
780
4b7c0e4c 781 if (req->data->flags & MMC_DATA_STREAM)
56ca9040 782 cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
56ca9040
PP		 783 }
784
785 imxmci_start_cmd(host, req->cmd, cmdat);
786}
787
788#define CLK_RATE 19200000
789
790static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
791{
792 struct imxmci_host *host = mmc_priv(mmc);
793 int prescaler;
794
4b7c0e4c 795 if (ios->bus_width == MMC_BUS_WIDTH_4) {
56ca9040
PP		 796 host->actual_bus_width = MMC_BUS_WIDTH_4;
797 imx_gpio_mode(PB11_PF_SD_DAT3);
4b7c0e4c 798 } else {
56ca9040
PP		 799 host->actual_bus_width = MMC_BUS_WIDTH_1;
800 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
801 }
802
4b7c0e4c 803 if (host->power_mode != ios->power_mode) {
56ca9040
PP		 804 switch (ios->power_mode) {
805 case MMC_POWER_OFF:
4b7c0e4c 806 break;
56ca9040
PP		 807 case MMC_POWER_UP:
808 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
4b7c0e4c 809 break;
56ca9040 810 case MMC_POWER_ON:
4b7c0e4c 811 break;
56ca9040
PP		 812 }
813 host->power_mode = ios->power_mode;
814 }
815
4b7c0e4c 816 if (ios->clock) {
56ca9040
PP		 817 unsigned int clk;
818
819 /* The prescaler is 5 for PERCLK2 equal to 96MHz
820 * then 96MHz / 5 = 19.2 MHz
821 */
38a41fdf 822 clk = clk_get_rate(host->clk);
4b7c0e4c
MKB		 823 prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
824 switch (prescaler) {
56ca9040
PP		 825 case 0:
826 case 1: prescaler = 0;
827 break;
828 case 2: prescaler = 1;
829 break;
830 case 3: prescaler = 2;
831 break;
832 case 4: prescaler = 4;
833 break;
834 default:
835 case 5: prescaler = 5;
836 break;
837 }
838
839 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
840 clk, prescaler);
841
4b7c0e4c 842 for (clk = 0; clk < 8; clk++) {
56ca9040 843 int x;
4b7c0e4c
MKB		 844 x = CLK_RATE / (1 << clk);
845 if (x <= ios->clock)
56ca9040
PP		 846 break;
847 }
848
849 MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
850
851 imxmci_stop_clock(host);
4b7c0e4c 852 MMC_CLK_RATE = (prescaler << 3) | clk;
2c171bf1
PP		 853 /*
854 * Under my understanding, clock should not be started there, because it would
855 * initiate SDHC sequencer and send last or random command into card
856 */
4b7c0e4c 857 /* imxmci_start_clock(host); */
56ca9040
PP		 858
859 dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
860 } else {
861 imxmci_stop_clock(host);
862 }
863}
864
faf39ede
PP		 865static int imxmci_get_ro(struct mmc_host *mmc)
866{
867 struct imxmci_host *host = mmc_priv(mmc);
868
869 if (host->pdata && host->pdata->get_ro)
08f80bb5
AV		 870 return !!host->pdata->get_ro(mmc_dev(mmc));
871 /*
872 * Board doesn't support read only detection; let the mmc core
873 * decide what to do.
874 */
875 return -ENOSYS;
faf39ede
PP		 876}
877
878
ab7aefd0 879static const struct mmc_host_ops imxmci_ops = {
56ca9040
PP		 880 .request = imxmci_request,
881 .set_ios = imxmci_set_ios,
faf39ede 882 .get_ro = imxmci_get_ro,
56ca9040
PP		 883};
884
56ca9040
PP		 885static void imxmci_check_status(unsigned long data)
886{
887 struct imxmci_host *host = (struct imxmci_host *)data;
888
c5d5e9c4
PZ		 889 if (host->pdata && host->pdata->card_present &&
890 host->pdata->card_present(mmc_dev(host->mmc)) != host->present) {
56ca9040
PP		 891 host->present ^= 1;
892 dev_info(mmc_dev(host->mmc), "card %s\n",
893 host->present ? "inserted" : "removed");
894
895 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
896 tasklet_schedule(&host->tasklet);
897 }
898
4b7c0e4c
MKB		 899 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
900 test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
56ca9040 901 atomic_inc(&host->stuck_timeout);
4b7c0e4c 902 if (atomic_read(&host->stuck_timeout) > 4)
56ca9040
PP		 903 tasklet_schedule(&host->tasklet);
904 } else {
905 atomic_set(&host->stuck_timeout, 0);
906
907 }
908
909 mod_timer(&host->timer, jiffies + (HZ>>1));
910}
911
912static int imxmci_probe(struct platform_device *pdev)
913{
914 struct mmc_host *mmc;
915 struct imxmci_host *host = NULL;
916 struct resource *r;
917 int ret = 0, irq;
918
919 printk(KERN_INFO "i.MX mmc driver\n");
920
5fc63dfb
PZ		 921 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
922 irq = platform_get_irq(pdev, 0);
923 if (!r || irq < 0)
56ca9040
PP		 924 return -ENXIO;
925
5fc63dfb 926 if (!request_mem_region(r->start, 0x100, pdev->name))
56ca9040
PP		 927 return -EBUSY;
928
929 mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
930 if (!mmc) {
931 ret = -ENOMEM;
932 goto out;
933 }
934
935 mmc->ops = &imxmci_ops;
936 mmc->f_min = 150000;
937 mmc->f_max = CLK_RATE/2;
938 mmc->ocr_avail = MMC_VDD_32_33;
255d01af 939 mmc->caps = MMC_CAP_4_BIT_DATA;
56ca9040
PP		 940
941 /* MMC core transfer sizes tunable parameters */
942 mmc->max_hw_segs = 64;
943 mmc->max_phys_segs = 64;
56ca9040 944 mmc->max_seg_size = 64*512; /* default PAGE_CACHE_SIZE */
55db890a 945 mmc->max_req_size = 64*512; /* default PAGE_CACHE_SIZE */
fe4a3c7a 946 mmc->max_blk_size = 2048;
55db890a 947 mmc->max_blk_count = 65535;
56ca9040
PP		 948
949 host = mmc_priv(mmc);
950 host->mmc = mmc;
951 host->dma_allocated = 0;
952 host->pdata = pdev->dev.platform_data;
c5d5e9c4
PZ		 953 if (!host->pdata)
954 dev_warn(&pdev->dev, "No platform data provided!\n");
56ca9040
PP		 955
956 spin_lock_init(&host->lock);
957 host->res = r;
958 host->irq = irq;
959
38a41fdf
SH		 960 host->clk = clk_get(&pdev->dev, "perclk2");
961 if (IS_ERR(host->clk)) {
962 ret = PTR_ERR(host->clk);
963 goto out;
964 }
965 clk_enable(host->clk);
966
56ca9040
PP		 967 imx_gpio_mode(PB8_PF_SD_DAT0);
968 imx_gpio_mode(PB9_PF_SD_DAT1);
969 imx_gpio_mode(PB10_PF_SD_DAT2);
970 /* Configured as GPIO with pull-up to ensure right MCC card mode */
971 /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
972 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
973 /* imx_gpio_mode(PB11_PF_SD_DAT3); */
974 imx_gpio_mode(PB12_PF_SD_CLK);
975 imx_gpio_mode(PB13_PF_SD_CMD);
976
977 imxmci_softreset();
978
4b7c0e4c 979 if (MMC_REV_NO != 0x390) {
56ca9040 980 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
4b7c0e4c 981 MMC_REV_NO);
56ca9040
PP		 982 goto out;
983 }
984
985 MMC_READ_TO = 0x2db4; /* recommended in data sheet */
986
987 host->imask = IMXMCI_INT_MASK_DEFAULT;
988 MMC_INT_MASK = host->imask;
989
f7def13e
PZ		 990 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
991 if(host->dma < 0) {
56ca9040
PP		 992 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
993 ret = -EBUSY;
994 goto out;
995 }
4b7c0e4c 996 host->dma_allocated = 1;
56ca9040
PP		 997 imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
998
999 tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
1000 host->status_reg=0;
1001 host->pending_events=0;
1002
1003 ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
1004 if (ret)
1005 goto out;
1006
c5d5e9c4
PZ		 1007 if (host->pdata && host->pdata->card_present)
1008 host->present = host->pdata->card_present(mmc_dev(mmc));
1009 else /* if there is no way to detect assume that card is present */
1010 host->present = 1;
1011
56ca9040
PP		 1012 init_timer(&host->timer);
1013 host->timer.data = (unsigned long)host;
1014 host->timer.function = imxmci_check_status;
1015 add_timer(&host->timer);
4b7c0e4c 1016 mod_timer(&host->timer, jiffies + (HZ >> 1));
56ca9040
PP		 1017
1018 platform_set_drvdata(pdev, mmc);
1019
1020 mmc_add_host(mmc);
1021
1022 return 0;
1023
1024out:
1025 if (host) {
4b7c0e4c 1026 if (host->dma_allocated) {
56ca9040 1027 imx_dma_free(host->dma);
4b7c0e4c 1028 host->dma_allocated = 0;
56ca9040 1029 }
38a41fdf
SH		 1030 if (host->clk) {
1031 clk_disable(host->clk);
1032 clk_put(host->clk);
1033 }
56ca9040
PP		 1034 }
1035 if (mmc)
1036 mmc_free_host(mmc);
5fc63dfb 1037 release_mem_region(r->start, 0x100);
56ca9040
PP		 1038 return ret;
1039}
1040
1041static int imxmci_remove(struct platform_device *pdev)
1042{
1043 struct mmc_host *mmc = platform_get_drvdata(pdev);
1044
1045 platform_set_drvdata(pdev, NULL);
1046
1047 if (mmc) {
1048 struct imxmci_host *host = mmc_priv(mmc);
1049
1050 tasklet_disable(&host->tasklet);
1051
1052 del_timer_sync(&host->timer);
1053 mmc_remove_host(mmc);
1054
1055 free_irq(host->irq, host);
4b7c0e4c 1056 if (host->dma_allocated) {
56ca9040 1057 imx_dma_free(host->dma);
4b7c0e4c 1058 host->dma_allocated = 0;
56ca9040
PP		 1059 }
1060
1061 tasklet_kill(&host->tasklet);
1062
38a41fdf
SH		 1063 clk_disable(host->clk);
1064 clk_put(host->clk);
1065
5fc63dfb 1066 release_mem_region(host->res->start, 0x100);
56ca9040
PP		 1067
1068 mmc_free_host(mmc);
1069 }
1070 return 0;
1071}
1072
1073#ifdef CONFIG_PM
1074static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
1075{
1076 struct mmc_host *mmc = platform_get_drvdata(dev);
1077 int ret = 0;
1078
1079 if (mmc)
1080 ret = mmc_suspend_host(mmc, state);
1081
1082 return ret;
1083}
1084
1085static int imxmci_resume(struct platform_device *dev)
1086{
1087 struct mmc_host *mmc = platform_get_drvdata(dev);
1088 struct imxmci_host *host;
1089 int ret = 0;
1090
1091 if (mmc) {
1092 host = mmc_priv(mmc);
4b7c0e4c 1093 if (host)
56ca9040
PP		 1094 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1095 ret = mmc_resume_host(mmc);
1096 }
1097
1098 return ret;
1099}
1100#else
1101#define imxmci_suspend NULL
1102#define imxmci_resume NULL
1103#endif /* CONFIG_PM */
1104
1105static struct platform_driver imxmci_driver = {
1106 .probe = imxmci_probe,
1107 .remove = imxmci_remove,
1108 .suspend = imxmci_suspend,
1109 .resume = imxmci_resume,
1110 .driver = {
1111 .name = DRIVER_NAME,
bc65c724 1112 .owner = THIS_MODULE,
56ca9040
PP		 1113 }
1114};
1115
1116static int __init imxmci_init(void)
1117{
1118 return platform_driver_register(&imxmci_driver);
1119}
1120
1121static void __exit imxmci_exit(void)
1122{
1123 platform_driver_unregister(&imxmci_driver);
1124}
1125
1126module_init(imxmci_init);
1127module_exit(imxmci_exit);
1128
1129MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1130MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1131MODULE_LICENSE("GPL");
bc65c724 1132MODULE_ALIAS("platform:imx-mmc");
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