[net-next-2.6.git] / drivers / mfd / max8925-core.c

/*
 * Base driver for Maxim MAX8925
 *
 * Copyright (C) 2009-2010 Marvell International Ltd.
 *	Haojian Zhuang <haojian.zhuang@marvell.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/max8925.h>

static struct resource backlight_resources[] = {
	{
		.name	= "max8925-backlight",
		.start	= MAX8925_WLED_MODE_CNTL,
		.end	= MAX8925_WLED_CNTL,
		.flags	= IORESOURCE_IO,
	},
};

static struct mfd_cell backlight_devs[] = {
	{
		.name		= "max8925-backlight",
		.num_resources	= 1,
		.resources	= &backlight_resources[0],
		.id		= -1,
	},
};

static struct resource touch_resources[] = {
	{
		.name	= "max8925-tsc",
		.start	= MAX8925_TSC_IRQ,
		.end	= MAX8925_ADC_RES_END,
		.flags	= IORESOURCE_IO,
	},
};

static struct mfd_cell touch_devs[] = {
	{
		.name		= "max8925-touch",
		.num_resources	= 1,
		.resources	= &touch_resources[0],
		.id		= -1,
	},
};

static struct resource power_supply_resources[] = {
	{
		.name	= "max8925-power",
		.start	= MAX8925_CHG_IRQ1,
		.end	= MAX8925_CHG_IRQ1_MASK,
		.flags	= IORESOURCE_IO,
	},
};

static struct mfd_cell power_devs[] = {
	{
		.name		= "max8925-power",
		.num_resources	= 1,
		.resources	= &power_supply_resources[0],
		.id		= -1,
	},
};

static struct resource rtc_resources[] = {
	{
		.name	= "max8925-rtc",
		.start	= MAX8925_RTC_IRQ,
		.end	= MAX8925_RTC_IRQ_MASK,
		.flags	= IORESOURCE_IO,
	},
};

static struct mfd_cell rtc_devs[] = {
	{
		.name		= "max8925-rtc",
		.num_resources	= 1,
		.resources	= &rtc_resources[0],
		.id		= -1,
	},
};

static struct resource onkey_resources[] = {
	{
		.name	= "max8925-onkey",
		.start	= MAX8925_IRQ_GPM_SW_3SEC,
		.end	= MAX8925_IRQ_GPM_SW_3SEC,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mfd_cell onkey_devs[] = {
	{
		.name		= "max8925-onkey",
		.num_resources	= 1,
		.resources	= &onkey_resources[0],
		.id		= -1,
	},
};

#define MAX8925_REG_RESOURCE(_start, _end)	\
{						\
	.start	= MAX8925_##_start,		\
	.end	= MAX8925_##_end,		\
	.flags	= IORESOURCE_IO,		\
}

static struct resource regulator_resources[] = {
	MAX8925_REG_RESOURCE(SDCTL1, SDCTL1),
	MAX8925_REG_RESOURCE(SDCTL2, SDCTL2),
	MAX8925_REG_RESOURCE(SDCTL3, SDCTL3),
	MAX8925_REG_RESOURCE(LDOCTL1, LDOCTL1),
	MAX8925_REG_RESOURCE(LDOCTL2, LDOCTL2),
	MAX8925_REG_RESOURCE(LDOCTL3, LDOCTL3),
	MAX8925_REG_RESOURCE(LDOCTL4, LDOCTL4),
	MAX8925_REG_RESOURCE(LDOCTL5, LDOCTL5),
	MAX8925_REG_RESOURCE(LDOCTL6, LDOCTL6),
	MAX8925_REG_RESOURCE(LDOCTL7, LDOCTL7),
	MAX8925_REG_RESOURCE(LDOCTL8, LDOCTL8),
	MAX8925_REG_RESOURCE(LDOCTL9, LDOCTL9),
	MAX8925_REG_RESOURCE(LDOCTL10, LDOCTL10),
	MAX8925_REG_RESOURCE(LDOCTL11, LDOCTL11),
	MAX8925_REG_RESOURCE(LDOCTL12, LDOCTL12),
	MAX8925_REG_RESOURCE(LDOCTL13, LDOCTL13),
	MAX8925_REG_RESOURCE(LDOCTL14, LDOCTL14),
	MAX8925_REG_RESOURCE(LDOCTL15, LDOCTL15),
	MAX8925_REG_RESOURCE(LDOCTL16, LDOCTL16),
	MAX8925_REG_RESOURCE(LDOCTL17, LDOCTL17),
	MAX8925_REG_RESOURCE(LDOCTL18, LDOCTL18),
	MAX8925_REG_RESOURCE(LDOCTL19, LDOCTL19),
	MAX8925_REG_RESOURCE(LDOCTL20, LDOCTL20),
};

#define MAX8925_REG_DEVS(_id)						\
{									\
	.name		= "max8925-regulator",				\
	.num_resources	= 1,						\
	.resources	= &regulator_resources[MAX8925_ID_##_id],	\
	.id		= MAX8925_ID_##_id,				\
}

static struct mfd_cell regulator_devs[] = {
	MAX8925_REG_DEVS(SD1),
	MAX8925_REG_DEVS(SD2),
	MAX8925_REG_DEVS(SD3),
	MAX8925_REG_DEVS(LDO1),
	MAX8925_REG_DEVS(LDO2),
	MAX8925_REG_DEVS(LDO3),
	MAX8925_REG_DEVS(LDO4),
	MAX8925_REG_DEVS(LDO5),
	MAX8925_REG_DEVS(LDO6),
	MAX8925_REG_DEVS(LDO7),
	MAX8925_REG_DEVS(LDO8),
	MAX8925_REG_DEVS(LDO9),
	MAX8925_REG_DEVS(LDO10),
	MAX8925_REG_DEVS(LDO11),
	MAX8925_REG_DEVS(LDO12),
	MAX8925_REG_DEVS(LDO13),
	MAX8925_REG_DEVS(LDO14),
	MAX8925_REG_DEVS(LDO15),
	MAX8925_REG_DEVS(LDO16),
	MAX8925_REG_DEVS(LDO17),
	MAX8925_REG_DEVS(LDO18),
	MAX8925_REG_DEVS(LDO19),
	MAX8925_REG_DEVS(LDO20),
};

enum {
	FLAGS_ADC = 1,	/* register in ADC component */
	FLAGS_RTC,	/* register in RTC component */
};

struct max8925_irq_data {
	int	reg;
	int	mask_reg;
	int	enable;		/* enable or not */
	int	offs;		/* bit offset in mask register */
	int	flags;
	int	tsc_irq;
};

static struct max8925_irq_data max8925_irqs[] = {
	[MAX8925_IRQ_VCHG_DC_OVP] = {
		.reg		= MAX8925_CHG_IRQ1,
		.mask_reg	= MAX8925_CHG_IRQ1_MASK,
		.offs		= 1 << 0,
	},
	[MAX8925_IRQ_VCHG_DC_F] = {
		.reg		= MAX8925_CHG_IRQ1,
		.mask_reg	= MAX8925_CHG_IRQ1_MASK,
		.offs		= 1 << 1,
	},
	[MAX8925_IRQ_VCHG_DC_R] = {
		.reg		= MAX8925_CHG_IRQ1,
		.mask_reg	= MAX8925_CHG_IRQ1_MASK,
		.offs		= 1 << 2,
	},
	[MAX8925_IRQ_VCHG_USB_OVP] = {
		.reg		= MAX8925_CHG_IRQ1,
		.mask_reg	= MAX8925_CHG_IRQ1_MASK,
		.offs		= 1 << 3,
	},
	[MAX8925_IRQ_VCHG_USB_F] =  {
		.reg		= MAX8925_CHG_IRQ1,
		.mask_reg	= MAX8925_CHG_IRQ1_MASK,
		.offs		= 1 << 4,
	},
	[MAX8925_IRQ_VCHG_USB_R] = {
		.reg		= MAX8925_CHG_IRQ1,
		.mask_reg	= MAX8925_CHG_IRQ1_MASK,
		.offs		= 1 << 5,
	},
	[MAX8925_IRQ_VCHG_THM_OK_R] = {
		.reg		= MAX8925_CHG_IRQ2,
		.mask_reg	= MAX8925_CHG_IRQ2_MASK,
		.offs		= 1 << 0,
	},
	[MAX8925_IRQ_VCHG_THM_OK_F] = {
		.reg		= MAX8925_CHG_IRQ2,
		.mask_reg	= MAX8925_CHG_IRQ2_MASK,
		.offs		= 1 << 1,
	},
	[MAX8925_IRQ_VCHG_SYSLOW_F] = {
		.reg		= MAX8925_CHG_IRQ2,
		.mask_reg	= MAX8925_CHG_IRQ2_MASK,
		.offs		= 1 << 2,
	},
	[MAX8925_IRQ_VCHG_SYSLOW_R] = {
		.reg		= MAX8925_CHG_IRQ2,
		.mask_reg	= MAX8925_CHG_IRQ2_MASK,
		.offs		= 1 << 3,
	},
	[MAX8925_IRQ_VCHG_RST] = {
		.reg		= MAX8925_CHG_IRQ2,
		.mask_reg	= MAX8925_CHG_IRQ2_MASK,
		.offs		= 1 << 4,
	},
	[MAX8925_IRQ_VCHG_DONE] = {
		.reg		= MAX8925_CHG_IRQ2,
		.mask_reg	= MAX8925_CHG_IRQ2_MASK,
		.offs		= 1 << 5,
	},
	[MAX8925_IRQ_VCHG_TOPOFF] = {
		.reg		= MAX8925_CHG_IRQ2,
		.mask_reg	= MAX8925_CHG_IRQ2_MASK,
		.offs		= 1 << 6,
	},
	[MAX8925_IRQ_VCHG_TMR_FAULT] = {
		.reg		= MAX8925_CHG_IRQ2,
		.mask_reg	= MAX8925_CHG_IRQ2_MASK,
		.offs		= 1 << 7,
	},
	[MAX8925_IRQ_GPM_RSTIN] = {
		.reg		= MAX8925_ON_OFF_IRQ1,
		.mask_reg	= MAX8925_ON_OFF_IRQ1_MASK,
		.offs		= 1 << 0,
	},
	[MAX8925_IRQ_GPM_MPL] = {
		.reg		= MAX8925_ON_OFF_IRQ1,
		.mask_reg	= MAX8925_ON_OFF_IRQ1_MASK,
		.offs		= 1 << 1,
	},
	[MAX8925_IRQ_GPM_SW_3SEC] = {
		.reg		= MAX8925_ON_OFF_IRQ1,
		.mask_reg	= MAX8925_ON_OFF_IRQ1_MASK,
		.offs		= 1 << 2,
	},
	[MAX8925_IRQ_GPM_EXTON_F] = {
		.reg		= MAX8925_ON_OFF_IRQ1,
		.mask_reg	= MAX8925_ON_OFF_IRQ1_MASK,
		.offs		= 1 << 3,
	},
	[MAX8925_IRQ_GPM_EXTON_R] = {
		.reg		= MAX8925_ON_OFF_IRQ1,
		.mask_reg	= MAX8925_ON_OFF_IRQ1_MASK,
		.offs		= 1 << 4,
	},
	[MAX8925_IRQ_GPM_SW_1SEC] = {
		.reg		= MAX8925_ON_OFF_IRQ1,
		.mask_reg	= MAX8925_ON_OFF_IRQ1_MASK,
		.offs		= 1 << 5,
	},
	[MAX8925_IRQ_GPM_SW_F] = {
		.reg		= MAX8925_ON_OFF_IRQ1,
		.mask_reg	= MAX8925_ON_OFF_IRQ1_MASK,
		.offs		= 1 << 6,
	},
	[MAX8925_IRQ_GPM_SW_R] = {
		.reg		= MAX8925_ON_OFF_IRQ1,
		.mask_reg	= MAX8925_ON_OFF_IRQ1_MASK,
		.offs		= 1 << 7,
	},
	[MAX8925_IRQ_GPM_SYSCKEN_F] = {
		.reg		= MAX8925_ON_OFF_IRQ2,
		.mask_reg	= MAX8925_ON_OFF_IRQ2_MASK,
		.offs		= 1 << 0,
	},
	[MAX8925_IRQ_GPM_SYSCKEN_R] = {
		.reg		= MAX8925_ON_OFF_IRQ2,
		.mask_reg	= MAX8925_ON_OFF_IRQ2_MASK,
		.offs		= 1 << 1,
	},
	[MAX8925_IRQ_RTC_ALARM1] = {
		.reg		= MAX8925_RTC_IRQ,
		.mask_reg	= MAX8925_RTC_IRQ_MASK,
		.offs		= 1 << 2,
		.flags		= FLAGS_RTC,
	},
	[MAX8925_IRQ_RTC_ALARM0] = {
		.reg		= MAX8925_RTC_IRQ,
		.mask_reg	= MAX8925_RTC_IRQ_MASK,
		.offs		= 1 << 3,
		.flags		= FLAGS_RTC,
	},
	[MAX8925_IRQ_TSC_STICK] = {
		.reg		= MAX8925_TSC_IRQ,
		.mask_reg	= MAX8925_TSC_IRQ_MASK,
		.offs		= 1 << 0,
		.flags		= FLAGS_ADC,
		.tsc_irq	= 1,
	},
	[MAX8925_IRQ_TSC_NSTICK] = {
		.reg		= MAX8925_TSC_IRQ,
		.mask_reg	= MAX8925_TSC_IRQ_MASK,
		.offs		= 1 << 1,
		.flags		= FLAGS_ADC,
		.tsc_irq	= 1,
	},
};

static inline struct max8925_irq_data *irq_to_max8925(struct max8925_chip *chip,
						      int irq)
{
	return &max8925_irqs[irq - chip->irq_base];
}

static irqreturn_t max8925_irq(int irq, void *data)
{
	struct max8925_chip *chip = data;
	struct max8925_irq_data *irq_data;
	struct i2c_client *i2c;
	int read_reg = -1, value = 0;
	int i;

	for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
		irq_data = &max8925_irqs[i];
		/* TSC IRQ should be serviced in max8925_tsc_irq() */
		if (irq_data->tsc_irq)
			continue;
		if (irq_data->flags == FLAGS_RTC)
			i2c = chip->rtc;
		else if (irq_data->flags == FLAGS_ADC)
			i2c = chip->adc;
		else
			i2c = chip->i2c;
		if (read_reg != irq_data->reg) {
			read_reg = irq_data->reg;
			value = max8925_reg_read(i2c, irq_data->reg);
		}
		if (value & irq_data->enable)
			handle_nested_irq(chip->irq_base + i);
	}
	return IRQ_HANDLED;
}

static irqreturn_t max8925_tsc_irq(int irq, void *data)
{
	struct max8925_chip *chip = data;
	struct max8925_irq_data *irq_data;
	struct i2c_client *i2c;
	int read_reg = -1, value = 0;
	int i;

	for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
		irq_data = &max8925_irqs[i];
		/* non TSC IRQ should be serviced in max8925_irq() */
		if (!irq_data->tsc_irq)
			continue;
		if (irq_data->flags == FLAGS_RTC)
			i2c = chip->rtc;
		else if (irq_data->flags == FLAGS_ADC)
			i2c = chip->adc;
		else
			i2c = chip->i2c;
		if (read_reg != irq_data->reg) {
			read_reg = irq_data->reg;
			value = max8925_reg_read(i2c, irq_data->reg);
		}
		if (value & irq_data->enable)
			handle_nested_irq(chip->irq_base + i);
	}
	return IRQ_HANDLED;
}

static void max8925_irq_lock(unsigned int irq)
{
	struct max8925_chip *chip = get_irq_chip_data(irq);

	mutex_lock(&chip->irq_lock);
}

static void max8925_irq_sync_unlock(unsigned int irq)
{
	struct max8925_chip *chip = get_irq_chip_data(irq);
	struct max8925_irq_data *irq_data;
	static unsigned char cache_chg[2] = {0xff, 0xff};
	static unsigned char cache_on[2] = {0xff, 0xff};
	static unsigned char cache_rtc = 0xff, cache_tsc = 0xff;
	unsigned char irq_chg[2], irq_on[2];
	unsigned char irq_rtc, irq_tsc;
	int i;

	/* Load cached value. In initial, all IRQs are masked */
	irq_chg[0] = cache_chg[0];
	irq_chg[1] = cache_chg[1];
	irq_on[0] = cache_on[0];
	irq_on[1] = cache_on[1];
	irq_rtc = cache_rtc;
	irq_tsc = cache_tsc;
	for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
		irq_data = &max8925_irqs[i];
		/* 1 -- disable, 0 -- enable */
		switch (irq_data->mask_reg) {
		case MAX8925_CHG_IRQ1_MASK:
			irq_chg[0] &= ~irq_data->enable;
			break;
		case MAX8925_CHG_IRQ2_MASK:
			irq_chg[1] &= ~irq_data->enable;
			break;
		case MAX8925_ON_OFF_IRQ1_MASK:
			irq_on[0] &= ~irq_data->enable;
			break;
		case MAX8925_ON_OFF_IRQ2_MASK:
			irq_on[1] &= ~irq_data->enable;
			break;
		case MAX8925_RTC_IRQ_MASK:
			irq_rtc &= ~irq_data->enable;
			break;
		case MAX8925_TSC_IRQ_MASK:
			irq_tsc &= ~irq_data->enable;
			break;
		default:
			dev_err(chip->dev, "wrong IRQ\n");
			break;
		}
	}
	/* update mask into registers */
	if (cache_chg[0] != irq_chg[0]) {
		cache_chg[0] = irq_chg[0];
		max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK,
			irq_chg[0]);
	}
	if (cache_chg[1] != irq_chg[1]) {
		cache_chg[1] = irq_chg[1];
		max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK,
			irq_chg[1]);
	}
	if (cache_on[0] != irq_on[0]) {
		cache_on[0] = irq_on[0];
		max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK,
				irq_on[0]);
	}
	if (cache_on[1] != irq_on[1]) {
		cache_on[1] = irq_on[1];
		max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK,
				irq_on[1]);
	}
	if (cache_rtc != irq_rtc) {
		cache_rtc = irq_rtc;
		max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc);
	}
	if (cache_tsc != irq_tsc) {
		cache_tsc = irq_tsc;
		max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc);
	}

	mutex_unlock(&chip->irq_lock);
}

static void max8925_irq_enable(unsigned int irq)
{
	struct max8925_chip *chip = get_irq_chip_data(irq);
	max8925_irqs[irq - chip->irq_base].enable
		= max8925_irqs[irq - chip->irq_base].offs;
}

static void max8925_irq_disable(unsigned int irq)
{
	struct max8925_chip *chip = get_irq_chip_data(irq);
	max8925_irqs[irq - chip->irq_base].enable = 0;
}

static struct irq_chip max8925_irq_chip = {
	.name		= "max8925",
	.bus_lock	= max8925_irq_lock,
	.bus_sync_unlock = max8925_irq_sync_unlock,
	.enable		= max8925_irq_enable,
	.disable	= max8925_irq_disable,
};

static int max8925_irq_init(struct max8925_chip *chip, int irq,
			    struct max8925_platform_data *pdata)
{
	unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
	struct irq_desc *desc;
	int i, ret;
	int __irq;

	if (!pdata || !pdata->irq_base) {
		dev_warn(chip->dev, "No interrupt support on IRQ base\n");
		return -EINVAL;
	}
	/* clear all interrupts */
	max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1);
	max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2);
	max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1);
	max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2);
	max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ);
	max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
	/* mask all interrupts except for TSC */
	max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0);
	max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0);
	max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff);
	max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff);
	max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff);
	max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff);
	max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff);

	mutex_init(&chip->irq_lock);
	chip->core_irq = irq;
	chip->irq_base = pdata->irq_base;
	desc = irq_to_desc(chip->core_irq);

	/* register with genirq */
	for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
		__irq = i + chip->irq_base;
		set_irq_chip_data(__irq, chip);
		set_irq_chip_and_handler(__irq, &max8925_irq_chip,
					 handle_edge_irq);
		set_irq_nested_thread(__irq, 1);
#ifdef CONFIG_ARM
		set_irq_flags(__irq, IRQF_VALID);
#else
		set_irq_noprobe(__irq);
#endif
	}
	if (!irq) {
		dev_warn(chip->dev, "No interrupt support on core IRQ\n");
		goto tsc_irq;
	}

	ret = request_threaded_irq(irq, NULL, max8925_irq, flags,
				   "max8925", chip);
	if (ret) {
		dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
		chip->core_irq = 0;
	}

tsc_irq:
	/* mask TSC interrupt */
	max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0x0f);

	if (!pdata->tsc_irq) {
		dev_warn(chip->dev, "No interrupt support on TSC IRQ\n");
		return 0;
	}
	chip->tsc_irq = pdata->tsc_irq;

	ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq,
				   flags, "max8925-tsc", chip);
	if (ret) {
		dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret);
		chip->tsc_irq = 0;
	}
	return 0;
}

int __devinit max8925_device_init(struct max8925_chip *chip,
				  struct max8925_platform_data *pdata)
{
	int ret;

	max8925_irq_init(chip, chip->i2c->irq, pdata);

	if (pdata && (pdata->power || pdata->touch)) {
		/* enable ADC to control internal reference */
		max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1);
		/* enable internal reference for ADC */
		max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2);
		/* check for internal reference IRQ */
		do {
			ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
		} while (ret & MAX8925_NREF_OK);
		/* enaable ADC scheduler, interval is 1 second */
		max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2);
	}

	/* enable Momentary Power Loss */
	max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4);

	ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
			      ARRAY_SIZE(rtc_devs),
			      &rtc_resources[0], 0);
	if (ret < 0) {
		dev_err(chip->dev, "Failed to add rtc subdev\n");
		goto out;
	}

	ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
			      ARRAY_SIZE(onkey_devs),
			      &onkey_resources[0], 0);
	if (ret < 0) {
		dev_err(chip->dev, "Failed to add onkey subdev\n");
		goto out_dev;
	}

	if (pdata && pdata->regulator[0]) {
		ret = mfd_add_devices(chip->dev, 0, &regulator_devs[0],
				      ARRAY_SIZE(regulator_devs),
				      &regulator_resources[0], 0);
		if (ret < 0) {
			dev_err(chip->dev, "Failed to add regulator subdev\n");
			goto out_dev;
		}
	}

	if (pdata && pdata->backlight) {
		ret = mfd_add_devices(chip->dev, 0, &backlight_devs[0],
				      ARRAY_SIZE(backlight_devs),
				      &backlight_resources[0], 0);
		if (ret < 0) {
			dev_err(chip->dev, "Failed to add backlight subdev\n");
			goto out_dev;
		}
	}

	if (pdata && pdata->power) {
		ret = mfd_add_devices(chip->dev, 0, &power_devs[0],
					ARRAY_SIZE(power_devs),
					&power_supply_resources[0], 0);
		if (ret < 0) {
			dev_err(chip->dev, "Failed to add power supply "
				"subdev\n");
			goto out_dev;
		}
	}

	if (pdata && pdata->touch) {
		ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
				      ARRAY_SIZE(touch_devs),
				      &touch_resources[0], 0);
		if (ret < 0) {
			dev_err(chip->dev, "Failed to add touch subdev\n");
			goto out_dev;
		}
	}

	return 0;
out_dev:
	mfd_remove_devices(chip->dev);
out:
	return ret;
}

void __devexit max8925_device_exit(struct max8925_chip *chip)
{
	if (chip->core_irq)
		free_irq(chip->core_irq, chip);
	if (chip->tsc_irq)
		free_irq(chip->tsc_irq, chip);
	mfd_remove_devices(chip->dev);
}


MODULE_DESCRIPTION("PMIC Driver for Maxim MAX8925");
MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com");
MODULE_LICENSE("GPL");
Commit	Line	Data
d50f8f33 HZ	1	/*
	2	* Base driver for Maxim MAX8925
	3	*
1f1cf8f9	4	* Copyright (C) 2009-2010 Marvell International Ltd.
d50f8f33 HZ	5	* Haojian Zhuang <haojian.zhuang@marvell.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/i2c.h>
1f1cf8f9	15	#include <linux/irq.h>
d50f8f33 HZ	16	#include <linux/interrupt.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/mfd/core.h>
	19	#include <linux/mfd/max8925.h>
	20
1ad99893 HZ	21	static struct resource backlight_resources[] = {
	22	{
	23	.name = "max8925-backlight",
	24	.start = MAX8925_WLED_MODE_CNTL,
	25	.end = MAX8925_WLED_CNTL,
	26	.flags = IORESOURCE_IO,
	27	},
	28	};
	29
	30	static struct mfd_cell backlight_devs[] = {
	31	{
	32	.name = "max8925-backlight",
	33	.num_resources = 1,
	34	.resources = &backlight_resources[0],
	35	.id = -1,
	36	},
	37	};
	38
	39	static struct resource touch_resources[] = {
	40	{
	41	.name = "max8925-tsc",
	42	.start = MAX8925_TSC_IRQ,
	43	.end = MAX8925_ADC_RES_END,
	44	.flags = IORESOURCE_IO,
	45	},
	46	};
	47
	48	static struct mfd_cell touch_devs[] = {
	49	{
	50	.name = "max8925-touch",
	51	.num_resources = 1,
	52	.resources = &touch_resources[0],
	53	.id = -1,
	54	},
	55	};
	56
1f1cf8f9 HZ	57	static struct resource power_supply_resources[] = {
	58	{
	59	.name = "max8925-power",
	60	.start = MAX8925_CHG_IRQ1,
	61	.end = MAX8925_CHG_IRQ1_MASK,
	62	.flags = IORESOURCE_IO,
	63	},
	64	};
	65
	66	static struct mfd_cell power_devs[] = {
	67	{
	68	.name = "max8925-power",
	69	.num_resources = 1,
	70	.resources = &power_supply_resources[0],
	71	.id = -1,
	72	},
	73	};
	74
	75	static struct resource rtc_resources[] = {
	76	{
	77	.name = "max8925-rtc",
	78	.start = MAX8925_RTC_IRQ,
	79	.end = MAX8925_RTC_IRQ_MASK,
	80	.flags = IORESOURCE_IO,
	81	},
	82	};
	83
	84	static struct mfd_cell rtc_devs[] = {
	85	{
	86	.name = "max8925-rtc",
	87	.num_resources = 1,
	88	.resources = &rtc_resources[0],
	89	.id = -1,
	90	},
	91	};
	92
d0f7a6d6 HZ	93	static struct resource onkey_resources[] = {
	94	{
	95	.name = "max8925-onkey",
	96	.start = MAX8925_IRQ_GPM_SW_3SEC,
	97	.end = MAX8925_IRQ_GPM_SW_3SEC,
	98	.flags = IORESOURCE_IRQ,
	99	},
	100	};
	101
	102	static struct mfd_cell onkey_devs[] = {
	103	{
	104	.name = "max8925-onkey",
	105	.num_resources = 1,
	106	.resources = &onkey_resources[0],
	107	.id = -1,
	108	},
	109	};
	110
1ad99893 HZ	111	#define MAX8925_REG_RESOURCE(_start, _end) \
	112	{ \
	113	.start = MAX8925_##_start, \
	114	.end = MAX8925_##_end, \
	115	.flags = IORESOURCE_IO, \
	116	}
	117
	118	static struct resource regulator_resources[] = {
	119	MAX8925_REG_RESOURCE(SDCTL1, SDCTL1),
	120	MAX8925_REG_RESOURCE(SDCTL2, SDCTL2),
	121	MAX8925_REG_RESOURCE(SDCTL3, SDCTL3),
	122	MAX8925_REG_RESOURCE(LDOCTL1, LDOCTL1),
	123	MAX8925_REG_RESOURCE(LDOCTL2, LDOCTL2),
	124	MAX8925_REG_RESOURCE(LDOCTL3, LDOCTL3),
	125	MAX8925_REG_RESOURCE(LDOCTL4, LDOCTL4),
	126	MAX8925_REG_RESOURCE(LDOCTL5, LDOCTL5),
	127	MAX8925_REG_RESOURCE(LDOCTL6, LDOCTL6),
	128	MAX8925_REG_RESOURCE(LDOCTL7, LDOCTL7),
	129	MAX8925_REG_RESOURCE(LDOCTL8, LDOCTL8),
	130	MAX8925_REG_RESOURCE(LDOCTL9, LDOCTL9),
	131	MAX8925_REG_RESOURCE(LDOCTL10, LDOCTL10),
	132	MAX8925_REG_RESOURCE(LDOCTL11, LDOCTL11),
	133	MAX8925_REG_RESOURCE(LDOCTL12, LDOCTL12),
	134	MAX8925_REG_RESOURCE(LDOCTL13, LDOCTL13),
	135	MAX8925_REG_RESOURCE(LDOCTL14, LDOCTL14),
	136	MAX8925_REG_RESOURCE(LDOCTL15, LDOCTL15),
	137	MAX8925_REG_RESOURCE(LDOCTL16, LDOCTL16),
	138	MAX8925_REG_RESOURCE(LDOCTL17, LDOCTL17),
	139	MAX8925_REG_RESOURCE(LDOCTL18, LDOCTL18),
	140	MAX8925_REG_RESOURCE(LDOCTL19, LDOCTL19),
	141	MAX8925_REG_RESOURCE(LDOCTL20, LDOCTL20),
	142	};
	143
	144	#define MAX8925_REG_DEVS(_id) \
	145	{ \
	146	.name = "max8925-regulator", \
	147	.num_resources = 1, \
	148	.resources = &regulator_resources[MAX8925_ID_##_id], \
	149	.id = MAX8925_ID_##_id, \
	150	}
	151
	152	static struct mfd_cell regulator_devs[] = {
	153	MAX8925_REG_DEVS(SD1),
	154	MAX8925_REG_DEVS(SD2),
	155	MAX8925_REG_DEVS(SD3),
	156	MAX8925_REG_DEVS(LDO1),
	157	MAX8925_REG_DEVS(LDO2),
	158	MAX8925_REG_DEVS(LDO3),
	159	MAX8925_REG_DEVS(LDO4),
	160	MAX8925_REG_DEVS(LDO5),
	161	MAX8925_REG_DEVS(LDO6),
	162	MAX8925_REG_DEVS(LDO7),
	163	MAX8925_REG_DEVS(LDO8),
	164	MAX8925_REG_DEVS(LDO9),
	165	MAX8925_REG_DEVS(LDO10),
	166	MAX8925_REG_DEVS(LDO11),
	167	MAX8925_REG_DEVS(LDO12),
	168	MAX8925_REG_DEVS(LDO13),
	169	MAX8925_REG_DEVS(LDO14),
	170	MAX8925_REG_DEVS(LDO15),
	171	MAX8925_REG_DEVS(LDO16),
	172	MAX8925_REG_DEVS(LDO17),
	173	MAX8925_REG_DEVS(LDO18),
	174	MAX8925_REG_DEVS(LDO19),
175	MAX8925_REG_DEVS(LDO20),
176	};
177
1f1cf8f9 HZ	178	enum {
	179	FLAGS_ADC = 1, /* register in ADC component */
	180	FLAGS_RTC, /* register in RTC component */
	181	};
	182
	183	struct max8925_irq_data {
	184	int reg;
	185	int mask_reg;
	186	int enable; /* enable or not */
	187	int offs; /* bit offset in mask register */
	188	int flags;
	189	int tsc_irq;
	190	};
	191
	192	static struct max8925_irq_data max8925_irqs[] = {
	193	[MAX8925_IRQ_VCHG_DC_OVP] = {
	194	.reg = MAX8925_CHG_IRQ1,
	195	.mask_reg = MAX8925_CHG_IRQ1_MASK,
	196	.offs = 1 << 0,
	197	},
	198	[MAX8925_IRQ_VCHG_DC_F] = {
	199	.reg = MAX8925_CHG_IRQ1,
	200	.mask_reg = MAX8925_CHG_IRQ1_MASK,
	201	.offs = 1 << 1,
	202	},
	203	[MAX8925_IRQ_VCHG_DC_R] = {
	204	.reg = MAX8925_CHG_IRQ1,
	205	.mask_reg = MAX8925_CHG_IRQ1_MASK,
	206	.offs = 1 << 2,
	207	},
	208	[MAX8925_IRQ_VCHG_USB_OVP] = {
	209	.reg = MAX8925_CHG_IRQ1,
	210	.mask_reg = MAX8925_CHG_IRQ1_MASK,
	211	.offs = 1 << 3,
	212	},
	213	[MAX8925_IRQ_VCHG_USB_F] = {
	214	.reg = MAX8925_CHG_IRQ1,
	215	.mask_reg = MAX8925_CHG_IRQ1_MASK,
	216	.offs = 1 << 4,
	217	},
	218	[MAX8925_IRQ_VCHG_USB_R] = {
	219	.reg = MAX8925_CHG_IRQ1,
	220	.mask_reg = MAX8925_CHG_IRQ1_MASK,
	221	.offs = 1 << 5,
	222	},
	223	[MAX8925_IRQ_VCHG_THM_OK_R] = {
	224	.reg = MAX8925_CHG_IRQ2,
	225	.mask_reg = MAX8925_CHG_IRQ2_MASK,
	226	.offs = 1 << 0,
	227	},
	228	[MAX8925_IRQ_VCHG_THM_OK_F] = {
	229	.reg = MAX8925_CHG_IRQ2,
	230	.mask_reg = MAX8925_CHG_IRQ2_MASK,
	231	.offs = 1 << 1,
	232	},
	233	[MAX8925_IRQ_VCHG_SYSLOW_F] = {
	234	.reg = MAX8925_CHG_IRQ2,
	235	.mask_reg = MAX8925_CHG_IRQ2_MASK,
	236	.offs = 1 << 2,
	237	},
	238	[MAX8925_IRQ_VCHG_SYSLOW_R] = {
	239	.reg = MAX8925_CHG_IRQ2,
	240	.mask_reg = MAX8925_CHG_IRQ2_MASK,
	241	.offs = 1 << 3,
242	},
243	[MAX8925_IRQ_VCHG_RST] = {
244	.reg = MAX8925_CHG_IRQ2,
245	.mask_reg = MAX8925_CHG_IRQ2_MASK,
246	.offs = 1 << 4,
247	},
248	[MAX8925_IRQ_VCHG_DONE] = {
249	.reg = MAX8925_CHG_IRQ2,
250	.mask_reg = MAX8925_CHG_IRQ2_MASK,
251	.offs = 1 << 5,
252	},
253	[MAX8925_IRQ_VCHG_TOPOFF] = {
254	.reg = MAX8925_CHG_IRQ2,
255	.mask_reg = MAX8925_CHG_IRQ2_MASK,
256	.offs = 1 << 6,
257	},
258	[MAX8925_IRQ_VCHG_TMR_FAULT] = {
259	.reg = MAX8925_CHG_IRQ2,
260	.mask_reg = MAX8925_CHG_IRQ2_MASK,
261	.offs = 1 << 7,
262	},
263	[MAX8925_IRQ_GPM_RSTIN] = {
264	.reg = MAX8925_ON_OFF_IRQ1,
265	.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
266	.offs = 1 << 0,
267	},
268	[MAX8925_IRQ_GPM_MPL] = {
269	.reg = MAX8925_ON_OFF_IRQ1,
270	.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
271	.offs = 1 << 1,
272	},
273	[MAX8925_IRQ_GPM_SW_3SEC] = {
274	.reg = MAX8925_ON_OFF_IRQ1,
275	.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
276	.offs = 1 << 2,
277	},
278	[MAX8925_IRQ_GPM_EXTON_F] = {
279	.reg = MAX8925_ON_OFF_IRQ1,
280	.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
281	.offs = 1 << 3,
282	},
283	[MAX8925_IRQ_GPM_EXTON_R] = {
284	.reg = MAX8925_ON_OFF_IRQ1,
285	.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
286	.offs = 1 << 4,
287	},
288	[MAX8925_IRQ_GPM_SW_1SEC] = {
289	.reg = MAX8925_ON_OFF_IRQ1,
290	.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
291	.offs = 1 << 5,
292	},
293	[MAX8925_IRQ_GPM_SW_F] = {
294	.reg = MAX8925_ON_OFF_IRQ1,
295	.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
296	.offs = 1 << 6,
297	},
298	[MAX8925_IRQ_GPM_SW_R] = {
299	.reg = MAX8925_ON_OFF_IRQ1,
300	.mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
301	.offs = 1 << 7,
302	},
303	[MAX8925_IRQ_GPM_SYSCKEN_F] = {
304	.reg = MAX8925_ON_OFF_IRQ2,
305	.mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
306	.offs = 1 << 0,
307	},
308	[MAX8925_IRQ_GPM_SYSCKEN_R] = {
309	.reg = MAX8925_ON_OFF_IRQ2,
310	.mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
311	.offs = 1 << 1,
312	},
313	[MAX8925_IRQ_RTC_ALARM1] = {
314	.reg = MAX8925_RTC_IRQ,
315	.mask_reg = MAX8925_RTC_IRQ_MASK,
316	.offs = 1 << 2,
317	.flags = FLAGS_RTC,
318	},
319	[MAX8925_IRQ_RTC_ALARM0] = {
320	.reg = MAX8925_RTC_IRQ,
321	.mask_reg = MAX8925_RTC_IRQ_MASK,
322	.offs = 1 << 3,
323	.flags = FLAGS_RTC,
324	},
325	[MAX8925_IRQ_TSC_STICK] = {
326	.reg = MAX8925_TSC_IRQ,
327	.mask_reg = MAX8925_TSC_IRQ_MASK,
328	.offs = 1 << 0,
329	.flags = FLAGS_ADC,
330	.tsc_irq = 1,
331	},
332	[MAX8925_IRQ_TSC_NSTICK] = {
333	.reg = MAX8925_TSC_IRQ,
334	.mask_reg = MAX8925_TSC_IRQ_MASK,
335	.offs = 1 << 1,
336	.flags = FLAGS_ADC,
337	.tsc_irq = 1,
338	},
339	};
340
341	static inline struct max8925_irq_data irq_to_max8925(struct max8925_chip chip,
342	int irq)
d50f8f33	343	{
1f1cf8f9 HZ	344	return &max8925_irqs[irq - chip->irq_base];
1f1cf8f9 HZ	345	}
d50f8f33	346
1f1cf8f9 HZ	347	static irqreturn_t max8925_irq(int irq, void *data)
	348	{
	349	struct max8925_chip *chip = data;
	350	struct max8925_irq_data *irq_data;
	351	struct i2c_client *i2c;
	352	int read_reg = -1, value = 0;
	353	int i;
	354
	355	for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
	356	irq_data = &max8925_irqs[i];
	357	/* TSC IRQ should be serviced in max8925_tsc_irq() */
	358	if (irq_data->tsc_irq)
	359	continue;
	360	if (irq_data->flags == FLAGS_RTC)
	361	i2c = chip->rtc;
	362	else if (irq_data->flags == FLAGS_ADC)
	363	i2c = chip->adc;
	364	else
	365	i2c = chip->i2c;
	366	if (read_reg != irq_data->reg) {
	367	read_reg = irq_data->reg;
	368	value = max8925_reg_read(i2c, irq_data->reg);
d50f8f33	369	}
1f1cf8f9 HZ	370	if (value & irq_data->enable)
1f1cf8f9 HZ	371	handle_nested_irq(chip->irq_base + i);
d50f8f33	372	}
1f1cf8f9	373	return IRQ_HANDLED;
d50f8f33 HZ	374	}
d50f8f33 HZ	375
1f1cf8f9	376	static irqreturn_t max8925_tsc_irq(int irq, void *data)
d50f8f33	377	{
1f1cf8f9 HZ	378	struct max8925_chip *chip = data;
	379	struct max8925_irq_data *irq_data;
	380	struct i2c_client *i2c;
	381	int read_reg = -1, value = 0;
	382	int i;
	383
	384	for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
	385	irq_data = &max8925_irqs[i];
	386	/* non TSC IRQ should be serviced in max8925_irq() */
	387	if (!irq_data->tsc_irq)
	388	continue;
	389	if (irq_data->flags == FLAGS_RTC)
	390	i2c = chip->rtc;
	391	else if (irq_data->flags == FLAGS_ADC)
	392	i2c = chip->adc;
	393	else
	394	i2c = chip->i2c;
	395	if (read_reg != irq_data->reg) {
	396	read_reg = irq_data->reg;
	397	value = max8925_reg_read(i2c, irq_data->reg);
	398	}
	399	if (value & irq_data->enable)
	400	handle_nested_irq(chip->irq_base + i);
	401	}
	402	return IRQ_HANDLED;
d50f8f33 HZ	403	}
d50f8f33 HZ	404
1f1cf8f9	405	static void max8925_irq_lock(unsigned int irq)
d50f8f33	406	{
1f1cf8f9	407	struct max8925_chip *chip = get_irq_chip_data(irq);
d50f8f33	408
1f1cf8f9	409	mutex_lock(&chip->irq_lock);
d50f8f33 HZ	410	}
d50f8f33 HZ	411
1f1cf8f9	412	static void max8925_irq_sync_unlock(unsigned int irq)
d50f8f33	413	{
1f1cf8f9 HZ	414	struct max8925_chip *chip = get_irq_chip_data(irq);
	415	struct max8925_irq_data *irq_data;
	416	static unsigned char cache_chg[2] = {0xff, 0xff};
	417	static unsigned char cache_on[2] = {0xff, 0xff};
	418	static unsigned char cache_rtc = 0xff, cache_tsc = 0xff;
	419	unsigned char irq_chg[2], irq_on[2];
	420	unsigned char irq_rtc, irq_tsc;
	421	int i;
	422
	423	/* Load cached value. In initial, all IRQs are masked */
	424	irq_chg[0] = cache_chg[0];
	425	irq_chg[1] = cache_chg[1];
	426	irq_on[0] = cache_on[0];
	427	irq_on[1] = cache_on[1];
	428	irq_rtc = cache_rtc;
	429	irq_tsc = cache_tsc;
	430	for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
	431	irq_data = &max8925_irqs[i];
90182317	432	/* 1 -- disable, 0 -- enable */
1f1cf8f9 HZ	433	switch (irq_data->mask_reg) {
1f1cf8f9 HZ	434	case MAX8925_CHG_IRQ1_MASK:
90182317	435	irq_chg[0] &= ~irq_data->enable;
1f1cf8f9 HZ	436	break;
1f1cf8f9 HZ	437	case MAX8925_CHG_IRQ2_MASK:
90182317	438	irq_chg[1] &= ~irq_data->enable;
1f1cf8f9 HZ	439	break;
1f1cf8f9 HZ	440	case MAX8925_ON_OFF_IRQ1_MASK:
90182317	441	irq_on[0] &= ~irq_data->enable;
1f1cf8f9 HZ	442	break;
1f1cf8f9 HZ	443	case MAX8925_ON_OFF_IRQ2_MASK:
90182317	444	irq_on[1] &= ~irq_data->enable;
1f1cf8f9 HZ	445	break;
1f1cf8f9 HZ	446	case MAX8925_RTC_IRQ_MASK:
90182317	447	irq_rtc &= ~irq_data->enable;
1f1cf8f9 HZ	448	break;
1f1cf8f9 HZ	449	case MAX8925_TSC_IRQ_MASK:
90182317	450	irq_tsc &= ~irq_data->enable;
1f1cf8f9 HZ	451	break;
	452	default:
	453	dev_err(chip->dev, "wrong IRQ\n");
	454	break;
	455	}
	456	}
	457	/* update mask into registers */
	458	if (cache_chg[0] != irq_chg[0]) {
	459	cache_chg[0] = irq_chg[0];
	460	max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK,
	461	irq_chg[0]);
	462	}
	463	if (cache_chg[1] != irq_chg[1]) {
	464	cache_chg[1] = irq_chg[1];
	465	max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK,
	466	irq_chg[1]);
	467	}
	468	if (cache_on[0] != irq_on[0]) {
	469	cache_on[0] = irq_on[0];
	470	max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK,
	471	irq_on[0]);
	472	}
	473	if (cache_on[1] != irq_on[1]) {
	474	cache_on[1] = irq_on[1];
	475	max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK,
	476	irq_on[1]);
	477	}
	478	if (cache_rtc != irq_rtc) {
	479	cache_rtc = irq_rtc;
	480	max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc);
	481	}
	482	if (cache_tsc != irq_tsc) {
	483	cache_tsc = irq_tsc;
	484	max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc);
	485	}
d50f8f33	486
1f1cf8f9	487	mutex_unlock(&chip->irq_lock);
d50f8f33 HZ	488	}
d50f8f33 HZ	489
1f1cf8f9	490	static void max8925_irq_enable(unsigned int irq)
d50f8f33	491	{
1f1cf8f9 HZ	492	struct max8925_chip *chip = get_irq_chip_data(irq);
	493	max8925_irqs[irq - chip->irq_base].enable
	494	= max8925_irqs[irq - chip->irq_base].offs;
d50f8f33 HZ	495	}
d50f8f33 HZ	496
1f1cf8f9	497	static void max8925_irq_disable(unsigned int irq)
d50f8f33	498	{
1f1cf8f9 HZ	499	struct max8925_chip *chip = get_irq_chip_data(irq);
1f1cf8f9 HZ	500	max8925_irqs[irq - chip->irq_base].enable = 0;
d50f8f33	501	}
d50f8f33	502
1f1cf8f9 HZ	503	static struct irq_chip max8925_irq_chip = {
	504	.name = "max8925",
	505	.bus_lock = max8925_irq_lock,
	506	.bus_sync_unlock = max8925_irq_sync_unlock,
	507	.enable = max8925_irq_enable,
	508	.disable = max8925_irq_disable,
	509	};
	510
	511	static int max8925_irq_init(struct max8925_chip *chip, int irq,
	512	struct max8925_platform_data *pdata)
d50f8f33	513	{
1f1cf8f9 HZ	514	unsigned long flags = IRQF_TRIGGER_FALLING \| IRQF_ONESHOT;
	515	struct irq_desc *desc;
	516	int i, ret;
	517	int __irq;
	518
	519	if (!pdata \|\| !pdata->irq_base) {
	520	dev_warn(chip->dev, "No interrupt support on IRQ base\n");
d50f8f33	521	return -EINVAL;
1f1cf8f9 HZ	522	}
	523	/* clear all interrupts */
	524	max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1);
	525	max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2);
	526	max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1);
	527	max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2);
	528	max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ);
	529	max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
68e488d9	530	/* mask all interrupts except for TSC */
1f1cf8f9 HZ	531	max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0);
	532	max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0);
	533	max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff);
	534	max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff);
	535	max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff);
	536	max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff);
	537	max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff);
1f1cf8f9 HZ	538
	539	mutex_init(&chip->irq_lock);
	540	chip->core_irq = irq;
	541	chip->irq_base = pdata->irq_base;
	542	desc = irq_to_desc(chip->core_irq);
	543
	544	/* register with genirq */
	545	for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
	546	__irq = i + chip->irq_base;
	547	set_irq_chip_data(__irq, chip);
	548	set_irq_chip_and_handler(__irq, &max8925_irq_chip,
	549	handle_edge_irq);
	550	set_irq_nested_thread(__irq, 1);
	551	#ifdef CONFIG_ARM
	552	set_irq_flags(__irq, IRQF_VALID);
	553	#else
	554	set_irq_noprobe(__irq);
	555	#endif
	556	}
	557	if (!irq) {
	558	dev_warn(chip->dev, "No interrupt support on core IRQ\n");
	559	goto tsc_irq;
	560	}
d50f8f33	561
1f1cf8f9 HZ	562	ret = request_threaded_irq(irq, NULL, max8925_irq, flags,
	563	"max8925", chip);
	564	if (ret) {
	565	dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
	566	chip->core_irq = 0;
	567	}
68e488d9	568
1f1cf8f9	569	tsc_irq:
68e488d9 HZ	570	/* mask TSC interrupt */
	571	max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0x0f);
	572
1f1cf8f9 HZ	573	if (!pdata->tsc_irq) {
	574	dev_warn(chip->dev, "No interrupt support on TSC IRQ\n");
	575	return 0;
	576	}
	577	chip->tsc_irq = pdata->tsc_irq;
	578
	579	ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq,
	580	flags, "max8925-tsc", chip);
	581	if (ret) {
	582	dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret);
	583	chip->tsc_irq = 0;
	584	}
d50f8f33 HZ	585	return 0;
d50f8f33 HZ	586	}
d50f8f33	587
1f1cf8f9 HZ	588	int __devinit max8925_device_init(struct max8925_chip *chip,
1f1cf8f9 HZ	589	struct max8925_platform_data *pdata)
d50f8f33 HZ	590	{
	591	int ret;
	592
1f1cf8f9 HZ	593	max8925_irq_init(chip, chip->i2c->irq, pdata);
	594
	595	if (pdata && (pdata->power \|\| pdata->touch)) {
	596	/* enable ADC to control internal reference */
	597	max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1);
	598	/* enable internal reference for ADC */
	599	max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2);
	600	/* check for internal reference IRQ */
	601	do {
	602	ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
	603	} while (ret & MAX8925_NREF_OK);
	604	/* enaable ADC scheduler, interval is 1 second */
	605	max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2);
d50f8f33	606	}
d50f8f33	607
1f1cf8f9 HZ	608	/* enable Momentary Power Loss */
1f1cf8f9 HZ	609	max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4);
1ad99893	610
1f1cf8f9 HZ	611	ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
	612	ARRAY_SIZE(rtc_devs),
	613	&rtc_resources[0], 0);
1ad99893	614	if (ret < 0) {
1f1cf8f9 HZ	615	dev_err(chip->dev, "Failed to add rtc subdev\n");
	616	goto out;
	617	}
d0f7a6d6 HZ	618
	619	ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
	620	ARRAY_SIZE(onkey_devs),
	621	&onkey_resources[0], 0);
	622	if (ret < 0) {
	623	dev_err(chip->dev, "Failed to add onkey subdev\n");
	624	goto out_dev;
	625	}
	626
1f1cf8f9 HZ	627	if (pdata && pdata->regulator[0]) {
	628	ret = mfd_add_devices(chip->dev, 0, &regulator_devs[0],
	629	ARRAY_SIZE(regulator_devs),
	630	&regulator_resources[0], 0);
	631	if (ret < 0) {
	632	dev_err(chip->dev, "Failed to add regulator subdev\n");
	633	goto out_dev;
	634	}
1ad99893 HZ	635	}
	636
	637	if (pdata && pdata->backlight) {
	638	ret = mfd_add_devices(chip->dev, 0, &backlight_devs[0],
	639	ARRAY_SIZE(backlight_devs),
	640	&backlight_resources[0], 0);
	641	if (ret < 0) {
	642	dev_err(chip->dev, "Failed to add backlight subdev\n");
	643	goto out_dev;
	644	}
	645	}
d50f8f33	646
1f1cf8f9 HZ	647	if (pdata && pdata->power) {
	648	ret = mfd_add_devices(chip->dev, 0, &power_devs[0],
	649	ARRAY_SIZE(power_devs),
	650	&power_supply_resources[0], 0);
	651	if (ret < 0) {
	652	dev_err(chip->dev, "Failed to add power supply "
	653	"subdev\n");
	654	goto out_dev;
	655	}
d50f8f33	656	}
1ad99893 HZ	657
	658	if (pdata && pdata->touch) {
	659	ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
	660	ARRAY_SIZE(touch_devs),
	661	&touch_resources[0], 0);
	662	if (ret < 0) {
	663	dev_err(chip->dev, "Failed to add touch subdev\n");
1f1cf8f9	664	goto out_dev;
1ad99893 HZ	665	}
1ad99893 HZ	666	}
1f1cf8f9	667
1ad99893	668	return 0;
1f1cf8f9 HZ	669	out_dev:
1f1cf8f9 HZ	670	mfd_remove_devices(chip->dev);
d50f8f33 HZ	671	out:
	672	return ret;
	673	}
	674
1f1cf8f9	675	void __devexit max8925_device_exit(struct max8925_chip *chip)
d50f8f33	676	{
1f1cf8f9 HZ	677	if (chip->core_irq)
	678	free_irq(chip->core_irq, chip);
	679	if (chip->tsc_irq)
	680	free_irq(chip->tsc_irq, chip);
1ad99893	681	mfd_remove_devices(chip->dev);
d50f8f33 HZ	682	}
d50f8f33 HZ	683
1f1cf8f9	684
d50f8f33 HZ	685	MODULE_DESCRIPTION("PMIC Driver for Maxim MAX8925");
	686	MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com");
	687	MODULE_LICENSE("GPL");