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Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[net-next-2.6.git] / drivers / media / video / s5p-fimc / fimc-core.c
CommitLineData
5fd8f738
SN		 1/*
2 * S5P camera interface (video postprocessor) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics
5 *
6 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published
10 * by the Free Software Foundation, either version 2 of the License,
11 * or (at your option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/version.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/bug.h>
20#include <linux/interrupt.h>
21#include <linux/device.h>
22#include <linux/platform_device.h>
23#include <linux/list.h>
24#include <linux/io.h>
25#include <linux/slab.h>
26#include <linux/clk.h>
27#include <media/v4l2-ioctl.h>
28#include <media/videobuf-dma-contig.h>
29
30#include "fimc-core.h"
31
32static char *fimc_clock_name[NUM_FIMC_CLOCKS] = { "sclk_fimc", "fimc" };
33
34static struct fimc_fmt fimc_formats[] = {
35 {
36 .name = "RGB565",
37 .fourcc = V4L2_PIX_FMT_RGB565X,
38 .depth = 16,
39 .color = S5P_FIMC_RGB565,
40 .buff_cnt = 1,
41 .planes_cnt = 1
42 }, {
43 .name = "BGR666",
44 .fourcc = V4L2_PIX_FMT_BGR666,
45 .depth = 32,
46 .color = S5P_FIMC_RGB666,
47 .buff_cnt = 1,
48 .planes_cnt = 1
49 }, {
50 .name = "XRGB-8-8-8-8, 24 bpp",
51 .fourcc = V4L2_PIX_FMT_RGB24,
52 .depth = 32,
53 .color = S5P_FIMC_RGB888,
54 .buff_cnt = 1,
55 .planes_cnt = 1
56 }, {
57 .name = "YUV 4:2:2 packed, YCbYCr",
58 .fourcc = V4L2_PIX_FMT_YUYV,
59 .depth = 16,
60 .color = S5P_FIMC_YCBYCR422,
61 .buff_cnt = 1,
62 .planes_cnt = 1
63 }, {
64 .name = "YUV 4:2:2 packed, CbYCrY",
65 .fourcc = V4L2_PIX_FMT_UYVY,
66 .depth = 16,
67 .color = S5P_FIMC_CBYCRY422,
68 .buff_cnt = 1,
69 .planes_cnt = 1
70 }, {
71 .name = "YUV 4:2:2 packed, CrYCbY",
72 .fourcc = V4L2_PIX_FMT_VYUY,
73 .depth = 16,
74 .color = S5P_FIMC_CRYCBY422,
75 .buff_cnt = 1,
76 .planes_cnt = 1
77 }, {
78 .name = "YUV 4:2:2 packed, YCrYCb",
79 .fourcc = V4L2_PIX_FMT_YVYU,
80 .depth = 16,
81 .color = S5P_FIMC_YCRYCB422,
82 .buff_cnt = 1,
83 .planes_cnt = 1
84 }, {
85 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
86 .fourcc = V4L2_PIX_FMT_YUV422P,
87 .depth = 12,
88 .color = S5P_FIMC_YCBCR422,
89 .buff_cnt = 1,
90 .planes_cnt = 3
91 }, {
92 .name = "YUV 4:2:2 planar, Y/CbCr",
93 .fourcc = V4L2_PIX_FMT_NV16,
94 .depth = 16,
95 .color = S5P_FIMC_YCBCR422,
96 .buff_cnt = 1,
97 .planes_cnt = 2
98 }, {
99 .name = "YUV 4:2:2 planar, Y/CrCb",
100 .fourcc = V4L2_PIX_FMT_NV61,
101 .depth = 16,
102 .color = S5P_FIMC_RGB565,
103 .buff_cnt = 1,
104 .planes_cnt = 2
105 }, {
106 .name = "YUV 4:2:0 planar, YCbCr",
107 .fourcc = V4L2_PIX_FMT_YUV420,
108 .depth = 12,
109 .color = S5P_FIMC_YCBCR420,
110 .buff_cnt = 1,
111 .planes_cnt = 3
112 }, {
113 .name = "YUV 4:2:0 planar, Y/CbCr",
114 .fourcc = V4L2_PIX_FMT_NV12,
115 .depth = 12,
116 .color = S5P_FIMC_YCBCR420,
117 .buff_cnt = 1,
118 .planes_cnt = 2
119 }
120 };
121
122static struct v4l2_queryctrl fimc_ctrls[] = {
123 {
124 .id = V4L2_CID_HFLIP,
125 .type = V4L2_CTRL_TYPE_BOOLEAN,
126 .name = "Horizontal flip",
127 .minimum = 0,
128 .maximum = 1,
129 .default_value = 0,
130 },
131 {
132 .id = V4L2_CID_VFLIP,
133 .type = V4L2_CTRL_TYPE_BOOLEAN,
134 .name = "Vertical flip",
135 .minimum = 0,
136 .maximum = 1,
137 .default_value = 0,
138 },
139 {
140 .id = V4L2_CID_ROTATE,
141 .type = V4L2_CTRL_TYPE_INTEGER,
142 .name = "Rotation (CCW)",
143 .minimum = 0,
144 .maximum = 270,
145 .step = 90,
146 .default_value = 0,
147 },
148};
149
150
151static struct v4l2_queryctrl *get_ctrl(int id)
152{
153 int i;
154
155 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
156 if (id == fimc_ctrls[i].id)
157 return &fimc_ctrls[i];
158 return NULL;
159}
160
161static int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f)
162{
163 if (r->width > f->width) {
164 if (f->width > (r->width * SCALER_MAX_HRATIO))
165 return -EINVAL;
166 } else {
167 if ((f->width * SCALER_MAX_HRATIO) < r->width)
168 return -EINVAL;
169 }
170
171 if (r->height > f->height) {
172 if (f->height > (r->height * SCALER_MAX_VRATIO))
173 return -EINVAL;
174 } else {
175 if ((f->height * SCALER_MAX_VRATIO) < r->height)
176 return -EINVAL;
177 }
178
179 return 0;
180}
181
182static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
183{
184 if (src >= tar * 64) {
185 return -EINVAL;
186 } else if (src >= tar * 32) {
187 *ratio = 32;
188 *shift = 5;
189 } else if (src >= tar * 16) {
190 *ratio = 16;
191 *shift = 4;
192 } else if (src >= tar * 8) {
193 *ratio = 8;
194 *shift = 3;
195 } else if (src >= tar * 4) {
196 *ratio = 4;
197 *shift = 2;
198 } else if (src >= tar * 2) {
199 *ratio = 2;
200 *shift = 1;
201 } else {
202 *ratio = 1;
203 *shift = 0;
204 }
205
206 return 0;
207}
208
209static int fimc_set_scaler_info(struct fimc_ctx *ctx)
210{
211 struct fimc_scaler *sc = &ctx->scaler;
212 struct fimc_frame *s_frame = &ctx->s_frame;
213 struct fimc_frame *d_frame = &ctx->d_frame;
214 int tx, ty, sx, sy;
215 int ret;
216
217 tx = d_frame->width;
218 ty = d_frame->height;
219 if (tx <= 0 || ty <= 0) {
220 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
221 "invalid target size: %d x %d", tx, ty);
222 return -EINVAL;
223 }
224
225 sx = s_frame->width;
226 sy = s_frame->height;
227 if (sx <= 0 || sy <= 0) {
228 err("invalid source size: %d x %d", sx, sy);
229 return -EINVAL;
230 }
231
232 sc->real_width = sx;
233 sc->real_height = sy;
234 dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
235
236 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
237 if (ret)
238 return ret;
239
240 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
241 if (ret)
242 return ret;
243
244 sc->pre_dst_width = sx / sc->pre_hratio;
245 sc->pre_dst_height = sy / sc->pre_vratio;
246
247 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
248 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
249
250 sc->scaleup_h = (tx >= sx) ? 1 : 0;
251 sc->scaleup_v = (ty >= sy) ? 1 : 0;
252
253 /* check to see if input and output size/format differ */
254 if (s_frame->fmt->color == d_frame->fmt->color
255 && s_frame->width == d_frame->width
256 && s_frame->height == d_frame->height)
257 sc->copy_mode = 1;
258 else
259 sc->copy_mode = 0;
260
261 return 0;
262}
263
264
265static irqreturn_t fimc_isr(int irq, void *priv)
266{
267 struct fimc_vid_buffer *src_buf, *dst_buf;
268 struct fimc_dev *fimc = (struct fimc_dev *)priv;
269 struct fimc_ctx *ctx;
270
271 BUG_ON(!fimc);
272 fimc_hw_clear_irq(fimc);
273
274 spin_lock(&fimc->slock);
275
276 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
277 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
278 if (!ctx || !ctx->m2m_ctx)
279 goto isr_unlock;
280 src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
281 dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
282 if (src_buf && dst_buf) {
283 spin_lock(&fimc->irqlock);
284 src_buf->vb.state = dst_buf->vb.state = VIDEOBUF_DONE;
285 wake_up(&src_buf->vb.done);
286 wake_up(&dst_buf->vb.done);
287 spin_unlock(&fimc->irqlock);
288 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
289 }
290 }
291
292isr_unlock:
293 spin_unlock(&fimc->slock);
294 return IRQ_HANDLED;
295}
296
297/* The color format (planes_cnt, buff_cnt) must be already configured. */
298static int fimc_prepare_addr(struct fimc_ctx *ctx,
299 struct fimc_vid_buffer *buf, enum v4l2_buf_type type)
300{
301 struct fimc_frame *frame;
302 struct fimc_addr *paddr;
303 u32 pix_size;
304 int ret = 0;
305
03e30ca5
PO		 306 frame = ctx_m2m_get_frame(ctx, type);
307 if (IS_ERR(frame))
308 return PTR_ERR(frame);
5fd8f738
SN		 309 paddr = &frame->paddr;
310
311 if (!buf)
312 return -EINVAL;
313
314 pix_size = frame->width * frame->height;
315
316 dbg("buff_cnt= %d, planes_cnt= %d, frame->size= %d, pix_size= %d",
317 frame->fmt->buff_cnt, frame->fmt->planes_cnt,
318 frame->size, pix_size);
319
320 if (frame->fmt->buff_cnt == 1) {
321 paddr->y = videobuf_to_dma_contig(&buf->vb);
322 switch (frame->fmt->planes_cnt) {
323 case 1:
324 paddr->cb = 0;
325 paddr->cr = 0;
326 break;
327 case 2:
328 /* decompose Y into Y/Cb */
329 paddr->cb = (u32)(paddr->y + pix_size);
330 paddr->cr = 0;
331 break;
332 case 3:
333 paddr->cb = (u32)(paddr->y + pix_size);
334 /* decompose Y into Y/Cb/Cr */
335 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
336 paddr->cr = (u32)(paddr->cb
337 + (pix_size >> 2));
338 else /* 422 */
339 paddr->cr = (u32)(paddr->cb
340 + (pix_size >> 1));
341 break;
342 default:
343 return -EINVAL;
344 }
345 }
346
347 dbg("PHYS_ADDR: type= %d, y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
348 type, paddr->y, paddr->cb, paddr->cr, ret);
349
350 return ret;
351}
352
353/* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
354static void fimc_set_yuv_order(struct fimc_ctx *ctx)
355{
356 /* The one only mode supported in SoC. */
357 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
358 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
359
360 /* Set order for 1 plane input formats. */
361 switch (ctx->s_frame.fmt->color) {
362 case S5P_FIMC_YCRYCB422:
363 ctx->in_order_1p = S5P_FIMC_IN_YCRYCB;
364 break;
365 case S5P_FIMC_CBYCRY422:
366 ctx->in_order_1p = S5P_FIMC_IN_CBYCRY;
367 break;
368 case S5P_FIMC_CRYCBY422:
369 ctx->in_order_1p = S5P_FIMC_IN_CRYCBY;
370 break;
371 case S5P_FIMC_YCBYCR422:
372 default:
373 ctx->in_order_1p = S5P_FIMC_IN_YCBYCR;
374 break;
375 }
376 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
377
378 switch (ctx->d_frame.fmt->color) {
379 case S5P_FIMC_YCRYCB422:
380 ctx->out_order_1p = S5P_FIMC_OUT_YCRYCB;
381 break;
382 case S5P_FIMC_CBYCRY422:
383 ctx->out_order_1p = S5P_FIMC_OUT_CBYCRY;
384 break;
385 case S5P_FIMC_CRYCBY422:
386 ctx->out_order_1p = S5P_FIMC_OUT_CRYCBY;
387 break;
388 case S5P_FIMC_YCBYCR422:
389 default:
390 ctx->out_order_1p = S5P_FIMC_OUT_YCBYCR;
391 break;
392 }
393 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
394}
395
ddc79e0f
SN		 396static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
397{
398 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
399
400 f->dma_offset.y_h = f->offs_h;
401 if (!variant->pix_hoff)
402 f->dma_offset.y_h *= (f->fmt->depth >> 3);
403
404 f->dma_offset.y_v = f->offs_v;
405
406 f->dma_offset.cb_h = f->offs_h;
407 f->dma_offset.cb_v = f->offs_v;
408
409 f->dma_offset.cr_h = f->offs_h;
410 f->dma_offset.cr_v = f->offs_v;
411
412 if (!variant->pix_hoff) {
413 if (f->fmt->planes_cnt == 3) {
414 f->dma_offset.cb_h >>= 1;
415 f->dma_offset.cr_h >>= 1;
416 }
417 if (f->fmt->color == S5P_FIMC_YCBCR420) {
418 f->dma_offset.cb_v >>= 1;
419 f->dma_offset.cr_v >>= 1;
420 }
421 }
422
423 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
424 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
425}
426
5fd8f738
SN		 427/**
428 * fimc_prepare_config - check dimensions, operation and color mode
429 * and pre-calculate offset and the scaling coefficients.
430 *
431 * @ctx: hardware context information
432 * @flags: flags indicating which parameters to check/update
433 *
434 * Return: 0 if dimensions are valid or non zero otherwise.
435 */
436static int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
437{
438 struct fimc_frame *s_frame, *d_frame;
439 struct fimc_vid_buffer *buf = NULL;
5fd8f738
SN		 440 int ret = 0;
441
442 s_frame = &ctx->s_frame;
443 d_frame = &ctx->d_frame;
444
445 if (flags & FIMC_PARAMS) {
446 if ((ctx->out_path == FIMC_DMA) &&
447 (ctx->rotation == 90 || ctx->rotation == 270)) {
448 swap(d_frame->f_width, d_frame->f_height);
449 swap(d_frame->width, d_frame->height);
450 }
451
ddc79e0f
SN		 452 /* Prepare the DMA offset ratios for scaler. */
453 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
454 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
5fd8f738 455
5fd8f738
SN		 456 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
457 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
458 err("out of scaler range");
459 return -EINVAL;
460 }
ddc79e0f 461 fimc_set_yuv_order(ctx);
5fd8f738
SN		 462 }
463
464 /* Input DMA mode is not allowed when the scaler is disabled. */
465 ctx->scaler.enabled = 1;
466
467 if (flags & FIMC_SRC_ADDR) {
468 buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
469 ret = fimc_prepare_addr(ctx, buf,
470 V4L2_BUF_TYPE_VIDEO_OUTPUT);
471 if (ret)
472 return ret;
473 }
474
475 if (flags & FIMC_DST_ADDR) {
476 buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
477 ret = fimc_prepare_addr(ctx, buf,
478 V4L2_BUF_TYPE_VIDEO_CAPTURE);
479 }
480
481 return ret;
482}
483
484static void fimc_dma_run(void *priv)
485{
486 struct fimc_ctx *ctx = priv;
487 struct fimc_dev *fimc;
488 unsigned long flags;
489 u32 ret;
490
491 if (WARN(!ctx, "null hardware context"))
492 return;
493
494 fimc = ctx->fimc_dev;
495
496 spin_lock_irqsave(&ctx->slock, flags);
497 set_bit(ST_M2M_PEND, &fimc->state);
498
499 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
500 ret = fimc_prepare_config(ctx, ctx->state);
501 if (ret) {
502 err("general configuration error");
503 goto dma_unlock;
504 }
505
506 if (fimc->m2m.ctx != ctx)
507 ctx->state |= FIMC_PARAMS;
508
509 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
510
511 if (ctx->state & FIMC_PARAMS) {
512 fimc_hw_set_input_path(ctx);
513 fimc_hw_set_in_dma(ctx);
514 if (fimc_set_scaler_info(ctx)) {
515 err("scaler configuration error");
516 goto dma_unlock;
517 }
518 fimc_hw_set_prescaler(ctx);
519 fimc_hw_set_scaler(ctx);
520 fimc_hw_set_target_format(ctx);
521 fimc_hw_set_rotation(ctx);
522 fimc_hw_set_effect(ctx);
523 }
524
525 fimc_hw_set_output_path(ctx);
526 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
527 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr);
528
529 if (ctx->state & FIMC_PARAMS)
530 fimc_hw_set_out_dma(ctx);
531
532 if (ctx->scaler.enabled)
533 fimc_hw_start_scaler(fimc);
534 fimc_hw_en_capture(ctx);
535
536 ctx->state = 0;
537 fimc_hw_start_in_dma(fimc);
538
539 fimc->m2m.ctx = ctx;
540
541dma_unlock:
542 spin_unlock_irqrestore(&ctx->slock, flags);
543}
544
03e30ca5
PO		 545static void fimc_job_abort(void *priv)
546{
547 /* Nothing done in job_abort. */
548}
5fd8f738
SN		 549
550static void fimc_buf_release(struct videobuf_queue *vq,
551 struct videobuf_buffer *vb)
552{
553 videobuf_dma_contig_free(vq, vb);
554 vb->state = VIDEOBUF_NEEDS_INIT;
555}
556
557static int fimc_buf_setup(struct videobuf_queue *vq, unsigned int *count,
558 unsigned int *size)
559{
560 struct fimc_ctx *ctx = vq->priv_data;
561 struct fimc_frame *frame;
562
03e30ca5
PO		 563 frame = ctx_m2m_get_frame(ctx, vq->type);
564 if (IS_ERR(frame))
565 return PTR_ERR(frame);
5fd8f738
SN		 566
567 *size = (frame->width * frame->height * frame->fmt->depth) >> 3;
568 if (0 == *count)
569 *count = 1;
570 return 0;
571}
572
573static int fimc_buf_prepare(struct videobuf_queue *vq,
574 struct videobuf_buffer *vb, enum v4l2_field field)
575{
576 struct fimc_ctx *ctx = vq->priv_data;
577 struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
578 struct fimc_frame *frame;
579 int ret;
580
03e30ca5
PO		 581 frame = ctx_m2m_get_frame(ctx, vq->type);
582 if (IS_ERR(frame))
583 return PTR_ERR(frame);
5fd8f738
SN		 584
585 if (vb->baddr) {
586 if (vb->bsize < frame->size) {
587 v4l2_err(v4l2_dev,
588 "User-provided buffer too small (%d < %d)\n",
589 vb->bsize, frame->size);
590 WARN_ON(1);
591 return -EINVAL;
592 }
593 } else if (vb->state != VIDEOBUF_NEEDS_INIT
594 && vb->bsize < frame->size) {
595 return -EINVAL;
596 }
597
598 vb->width = frame->width;
599 vb->height = frame->height;
600 vb->bytesperline = (frame->width * frame->fmt->depth) >> 3;
601 vb->size = frame->size;
602 vb->field = field;
603
604 if (VIDEOBUF_NEEDS_INIT == vb->state) {
605 ret = videobuf_iolock(vq, vb, NULL);
606 if (ret) {
607 v4l2_err(v4l2_dev, "Iolock failed\n");
608 fimc_buf_release(vq, vb);
609 return ret;
610 }
611 }
612 vb->state = VIDEOBUF_PREPARED;
613
614 return 0;
615}
616
617static void fimc_buf_queue(struct videobuf_queue *vq,
618 struct videobuf_buffer *vb)
619{
620 struct fimc_ctx *ctx = vq->priv_data;
621 v4l2_m2m_buf_queue(ctx->m2m_ctx, vq, vb);
622}
623
03e30ca5 624static struct videobuf_queue_ops fimc_qops = {
5fd8f738
SN		 625 .buf_setup = fimc_buf_setup,
626 .buf_prepare = fimc_buf_prepare,
627 .buf_queue = fimc_buf_queue,
628 .buf_release = fimc_buf_release,
629};
630
631static int fimc_m2m_querycap(struct file *file, void *priv,
632 struct v4l2_capability *cap)
633{
634 struct fimc_ctx *ctx = file->private_data;
635 struct fimc_dev *fimc = ctx->fimc_dev;
636
637 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
638 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
639 cap->bus_info[0] = 0;
640 cap->version = KERNEL_VERSION(1, 0, 0);
641 cap->capabilities = V4L2_CAP_STREAMING |
642 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT;
643
644 return 0;
645}
646
647static int fimc_m2m_enum_fmt(struct file *file, void *priv,
648 struct v4l2_fmtdesc *f)
649{
650 struct fimc_fmt *fmt;
651
652 if (f->index >= ARRAY_SIZE(fimc_formats))
653 return -EINVAL;
654
655 fmt = &fimc_formats[f->index];
656 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
657 f->pixelformat = fmt->fourcc;
658 return 0;
659}
660
661static int fimc_m2m_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
662{
663 struct fimc_ctx *ctx = priv;
664 struct fimc_frame *frame;
665
03e30ca5
PO		 666 frame = ctx_m2m_get_frame(ctx, f->type);
667 if (IS_ERR(frame))
668 return PTR_ERR(frame);
5fd8f738
SN		 669
670 f->fmt.pix.width = frame->width;
671 f->fmt.pix.height = frame->height;
672 f->fmt.pix.field = V4L2_FIELD_NONE;
673 f->fmt.pix.pixelformat = frame->fmt->fourcc;
674
675 return 0;
676}
677
678static struct fimc_fmt *find_format(struct v4l2_format *f)
679{
680 struct fimc_fmt *fmt;
681 unsigned int i;
682
683 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
684 fmt = &fimc_formats[i];
685 if (fmt->fourcc == f->fmt.pix.pixelformat)
686 break;
687 }
688 if (i == ARRAY_SIZE(fimc_formats))
689 return NULL;
690
691 return fmt;
692}
693
694static int fimc_m2m_try_fmt(struct file *file, void *priv,
695 struct v4l2_format *f)
696{
697 struct fimc_fmt *fmt;
698 u32 max_width, max_height, mod_x, mod_y;
699 struct fimc_ctx *ctx = priv;
700 struct fimc_dev *fimc = ctx->fimc_dev;
701 struct v4l2_pix_format *pix = &f->fmt.pix;
702 struct samsung_fimc_variant *variant = fimc->variant;
703
704 fmt = find_format(f);
705 if (!fmt) {
706 v4l2_err(&fimc->m2m.v4l2_dev,
707 "Fourcc format (0x%X) invalid.\n", pix->pixelformat);
708 return -EINVAL;
709 }
710
711 if (pix->field == V4L2_FIELD_ANY)
712 pix->field = V4L2_FIELD_NONE;
713 else if (V4L2_FIELD_NONE != pix->field)
714 return -EINVAL;
715
716 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
717 max_width = variant->scaler_dis_w;
718 max_height = variant->scaler_dis_w;
719 mod_x = variant->min_inp_pixsize;
720 mod_y = variant->min_inp_pixsize;
721 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
722 max_width = variant->out_rot_dis_w;
723 max_height = variant->out_rot_dis_w;
724 mod_x = variant->min_out_pixsize;
725 mod_y = variant->min_out_pixsize;
726 } else {
727 err("Wrong stream type (%d)", f->type);
728 return -EINVAL;
729 }
730
731 dbg("max_w= %d, max_h= %d", max_width, max_height);
732
733 if (pix->height > max_height)
734 pix->height = max_height;
735 if (pix->width > max_width)
736 pix->width = max_width;
737
738 if (tiled_fmt(fmt)) {
739 mod_x = 64; /* 64x32 tile */
740 mod_y = 32;
741 }
742
743 dbg("mod_x= 0x%X, mod_y= 0x%X", mod_x, mod_y);
744
745 pix->width = (pix->width == 0) ? mod_x : ALIGN(pix->width, mod_x);
746 pix->height = (pix->height == 0) ? mod_y : ALIGN(pix->height, mod_y);
747
748 if (pix->bytesperline == 0 ||
749 pix->bytesperline * 8 / fmt->depth > pix->width)
750 pix->bytesperline = (pix->width * fmt->depth) >> 3;
751
752 if (pix->sizeimage == 0)
753 pix->sizeimage = pix->height * pix->bytesperline;
754
755 dbg("pix->bytesperline= %d, fmt->depth= %d",
756 pix->bytesperline, fmt->depth);
757
758 return 0;
759}
760
761
762static int fimc_m2m_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
763{
764 struct fimc_ctx *ctx = priv;
765 struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
766 struct videobuf_queue *src_vq, *dst_vq;
767 struct fimc_frame *frame;
768 struct v4l2_pix_format *pix;
769 unsigned long flags;
770 int ret = 0;
771
772 BUG_ON(!ctx);
773
774 ret = fimc_m2m_try_fmt(file, priv, f);
775 if (ret)
776 return ret;
777
778 mutex_lock(&ctx->fimc_dev->lock);
779
780 src_vq = v4l2_m2m_get_src_vq(ctx->m2m_ctx);
781 dst_vq = v4l2_m2m_get_dst_vq(ctx->m2m_ctx);
782
783 mutex_lock(&src_vq->vb_lock);
784 mutex_lock(&dst_vq->vb_lock);
785
786 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
787 if (videobuf_queue_is_busy(src_vq)) {
788 v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
789 ret = -EBUSY;
790 goto s_fmt_out;
791 }
792 frame = &ctx->s_frame;
793 spin_lock_irqsave(&ctx->slock, flags);
794 ctx->state |= FIMC_SRC_FMT;
795 spin_unlock_irqrestore(&ctx->slock, flags);
796
797 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
798 if (videobuf_queue_is_busy(dst_vq)) {
799 v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
800 ret = -EBUSY;
801 goto s_fmt_out;
802 }
803 frame = &ctx->d_frame;
804 spin_lock_irqsave(&ctx->slock, flags);
805 ctx->state |= FIMC_DST_FMT;
806 spin_unlock_irqrestore(&ctx->slock, flags);
807 } else {
808 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
809 "Wrong buffer/video queue type (%d)\n", f->type);
590a58d1
DC		 810 ret = -EINVAL;
811 goto s_fmt_out;
5fd8f738
SN		 812 }
813
814 pix = &f->fmt.pix;
815 frame->fmt = find_format(f);
816 if (!frame->fmt) {
817 ret = -EINVAL;
818 goto s_fmt_out;
819 }
820
821 frame->f_width = pix->bytesperline * 8 / frame->fmt->depth;
822 frame->f_height = pix->sizeimage/pix->bytesperline;
823 frame->width = pix->width;
824 frame->height = pix->height;
825 frame->o_width = pix->width;
826 frame->o_height = pix->height;
827 frame->offs_h = 0;
828 frame->offs_v = 0;
829 frame->size = (pix->width * pix->height * frame->fmt->depth) >> 3;
830 src_vq->field = dst_vq->field = pix->field;
831 spin_lock_irqsave(&ctx->slock, flags);
832 ctx->state |= FIMC_PARAMS;
833 spin_unlock_irqrestore(&ctx->slock, flags);
834
835 dbg("f_width= %d, f_height= %d", frame->f_width, frame->f_height);
836
837s_fmt_out:
838 mutex_unlock(&dst_vq->vb_lock);
839 mutex_unlock(&src_vq->vb_lock);
840 mutex_unlock(&ctx->fimc_dev->lock);
841 return ret;
842}
843
844static int fimc_m2m_reqbufs(struct file *file, void *priv,
845 struct v4l2_requestbuffers *reqbufs)
846{
847 struct fimc_ctx *ctx = priv;
848 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
849}
850
851static int fimc_m2m_querybuf(struct file *file, void *priv,
852 struct v4l2_buffer *buf)
853{
854 struct fimc_ctx *ctx = priv;
855 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
856}
857
858static int fimc_m2m_qbuf(struct file *file, void *priv,
859 struct v4l2_buffer *buf)
860{
861 struct fimc_ctx *ctx = priv;
862
863 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
864}
865
866static int fimc_m2m_dqbuf(struct file *file, void *priv,
867 struct v4l2_buffer *buf)
868{
869 struct fimc_ctx *ctx = priv;
870 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
871}
872
873static int fimc_m2m_streamon(struct file *file, void *priv,
874 enum v4l2_buf_type type)
875{
876 struct fimc_ctx *ctx = priv;
877 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
878}
879
880static int fimc_m2m_streamoff(struct file *file, void *priv,
881 enum v4l2_buf_type type)
882{
883 struct fimc_ctx *ctx = priv;
884 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
885}
886
887int fimc_m2m_queryctrl(struct file *file, void *priv,
888 struct v4l2_queryctrl *qc)
889{
890 struct v4l2_queryctrl *c;
891 c = get_ctrl(qc->id);
892 if (!c)
893 return -EINVAL;
894 *qc = *c;
895 return 0;
896}
897
898int fimc_m2m_g_ctrl(struct file *file, void *priv,
899 struct v4l2_control *ctrl)
900{
901 struct fimc_ctx *ctx = priv;
902
903 switch (ctrl->id) {
904 case V4L2_CID_HFLIP:
905 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
906 break;
907 case V4L2_CID_VFLIP:
908 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
909 break;
910 case V4L2_CID_ROTATE:
911 ctrl->value = ctx->rotation;
912 break;
913 default:
914 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, "Invalid control\n");
915 return -EINVAL;
916 }
917 dbg("ctrl->value= %d", ctrl->value);
918 return 0;
919}
920
921static int check_ctrl_val(struct fimc_ctx *ctx,
922 struct v4l2_control *ctrl)
923{
924 struct v4l2_queryctrl *c;
925 c = get_ctrl(ctrl->id);
926 if (!c)
927 return -EINVAL;
928
929 if (ctrl->value < c->minimum || ctrl->value > c->maximum
930 || (c->step != 0 && ctrl->value % c->step != 0)) {
931 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
932 "Invalid control value\n");
933 return -ERANGE;
934 }
935
936 return 0;
937}
938
939int fimc_m2m_s_ctrl(struct file *file, void *priv,
940 struct v4l2_control *ctrl)
941{
942 struct fimc_ctx *ctx = priv;
943 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
944 unsigned long flags;
945 int ret = 0;
946
947 ret = check_ctrl_val(ctx, ctrl);
948 if (ret)
949 return ret;
950
951 switch (ctrl->id) {
952 case V4L2_CID_HFLIP:
953 if (ctx->rotation != 0)
954 return 0;
955 if (ctrl->value)
956 ctx->flip |= FLIP_X_AXIS;
957 else
958 ctx->flip &= ~FLIP_X_AXIS;
959 break;
960
961 case V4L2_CID_VFLIP:
962 if (ctx->rotation != 0)
963 return 0;
964 if (ctrl->value)
965 ctx->flip |= FLIP_Y_AXIS;
966 else
967 ctx->flip &= ~FLIP_Y_AXIS;
968 break;
969
970 case V4L2_CID_ROTATE:
971 if (ctrl->value == 90 || ctrl->value == 270) {
972 if (ctx->out_path == FIMC_LCDFIFO &&
973 !variant->has_inp_rot) {
974 return -EINVAL;
975 } else if (ctx->in_path == FIMC_DMA &&
976 !variant->has_out_rot) {
977 return -EINVAL;
978 }
979 }
980 ctx->rotation = ctrl->value;
981 if (ctrl->value == 180)
982 ctx->flip = FLIP_XY_AXIS;
983 break;
984
985 default:
986 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, "Invalid control\n");
987 return -EINVAL;
988 }
989 spin_lock_irqsave(&ctx->slock, flags);
990 ctx->state |= FIMC_PARAMS;
991 spin_unlock_irqrestore(&ctx->slock, flags);
992 return 0;
993}
994
995
996static int fimc_m2m_cropcap(struct file *file, void *fh,
997 struct v4l2_cropcap *cr)
998{
999 struct fimc_frame *frame;
1000 struct fimc_ctx *ctx = fh;
1001
03e30ca5
PO		 1002 frame = ctx_m2m_get_frame(ctx, cr->type);
1003 if (IS_ERR(frame))
1004 return PTR_ERR(frame);
5fd8f738
SN		 1005
1006 cr->bounds.left = 0;
1007 cr->bounds.top = 0;
1008 cr->bounds.width = frame->f_width;
1009 cr->bounds.height = frame->f_height;
1010 cr->defrect.left = frame->offs_h;
1011 cr->defrect.top = frame->offs_v;
1012 cr->defrect.width = frame->o_width;
1013 cr->defrect.height = frame->o_height;
1014 return 0;
1015}
1016
1017static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1018{
1019 struct fimc_frame *frame;
1020 struct fimc_ctx *ctx = file->private_data;
1021
03e30ca5
PO		 1022 frame = ctx_m2m_get_frame(ctx, cr->type);
1023 if (IS_ERR(frame))
1024 return PTR_ERR(frame);
5fd8f738
SN		 1025
1026 cr->c.left = frame->offs_h;
1027 cr->c.top = frame->offs_v;
1028 cr->c.width = frame->width;
1029 cr->c.height = frame->height;
1030
1031 return 0;
1032}
1033
1034static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1035{
1036 struct fimc_ctx *ctx = file->private_data;
1037 struct fimc_dev *fimc = ctx->fimc_dev;
1038 unsigned long flags;
1039 struct fimc_frame *f;
1040 u32 min_size;
1041 int ret = 0;
1042
1043 if (cr->c.top < 0 || cr->c.left < 0) {
1044 v4l2_err(&fimc->m2m.v4l2_dev,
1045 "doesn't support negative values for top & left\n");
1046 return -EINVAL;
1047 }
1048
1049 if (cr->c.width <= 0 || cr->c.height <= 0) {
1050 v4l2_err(&fimc->m2m.v4l2_dev,
1051 "crop width and height must be greater than 0\n");
1052 return -EINVAL;
1053 }
1054
03e30ca5
PO		 1055 f = ctx_m2m_get_frame(ctx, cr->type);
1056 if (IS_ERR(f))
1057 return PTR_ERR(f);
5fd8f738
SN		 1058
1059 /* Adjust to required pixel boundary. */
1060 min_size = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) ?
1061 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1062
1063 cr->c.width = round_down(cr->c.width, min_size);
1064 cr->c.height = round_down(cr->c.height, min_size);
1065 cr->c.left = round_down(cr->c.left + 1, min_size);
1066 cr->c.top = round_down(cr->c.top + 1, min_size);
1067
1068 if ((cr->c.left + cr->c.width > f->o_width)
1069 || (cr->c.top + cr->c.height > f->o_height)) {
1070 v4l2_err(&fimc->m2m.v4l2_dev, "Error in S_CROP params\n");
1071 return -EINVAL;
1072 }
1073
1074 spin_lock_irqsave(&ctx->slock, flags);
1075 if ((ctx->state & FIMC_SRC_FMT) && (ctx->state & FIMC_DST_FMT)) {
1076 /* Check for the pixel scaling ratio when cropping input img. */
1077 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1078 ret = fimc_check_scaler_ratio(&cr->c, &ctx->d_frame);
1079 else if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1080 ret = fimc_check_scaler_ratio(&cr->c, &ctx->s_frame);
1081
1082 if (ret) {
1083 spin_unlock_irqrestore(&ctx->slock, flags);
1084 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range");
1085 return -EINVAL;
1086 }
1087 }
1088 ctx->state |= FIMC_PARAMS;
1089 spin_unlock_irqrestore(&ctx->slock, flags);
1090
1091 f->offs_h = cr->c.left;
1092 f->offs_v = cr->c.top;
1093 f->width = cr->c.width;
1094 f->height = cr->c.height;
1095 return 0;
1096}
1097
1098static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1099 .vidioc_querycap = fimc_m2m_querycap,
1100
1101 .vidioc_enum_fmt_vid_cap = fimc_m2m_enum_fmt,
1102 .vidioc_enum_fmt_vid_out = fimc_m2m_enum_fmt,
1103
1104 .vidioc_g_fmt_vid_cap = fimc_m2m_g_fmt,
1105 .vidioc_g_fmt_vid_out = fimc_m2m_g_fmt,
1106
1107 .vidioc_try_fmt_vid_cap = fimc_m2m_try_fmt,
1108 .vidioc_try_fmt_vid_out = fimc_m2m_try_fmt,
1109
1110 .vidioc_s_fmt_vid_cap = fimc_m2m_s_fmt,
1111 .vidioc_s_fmt_vid_out = fimc_m2m_s_fmt,
1112
1113 .vidioc_reqbufs = fimc_m2m_reqbufs,
1114 .vidioc_querybuf = fimc_m2m_querybuf,
1115
1116 .vidioc_qbuf = fimc_m2m_qbuf,
1117 .vidioc_dqbuf = fimc_m2m_dqbuf,
1118
1119 .vidioc_streamon = fimc_m2m_streamon,
1120 .vidioc_streamoff = fimc_m2m_streamoff,
1121
1122 .vidioc_queryctrl = fimc_m2m_queryctrl,
1123 .vidioc_g_ctrl = fimc_m2m_g_ctrl,
1124 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1125
1126 .vidioc_g_crop = fimc_m2m_g_crop,
1127 .vidioc_s_crop = fimc_m2m_s_crop,
1128 .vidioc_cropcap = fimc_m2m_cropcap
1129
1130};
1131
1132static void queue_init(void *priv, struct videobuf_queue *vq,
1133 enum v4l2_buf_type type)
1134{
1135 struct fimc_ctx *ctx = priv;
1136 struct fimc_dev *fimc = ctx->fimc_dev;
1137
1138 videobuf_queue_dma_contig_init(vq, &fimc_qops,
1139 fimc->m2m.v4l2_dev.dev,
1140 &fimc->irqlock, type, V4L2_FIELD_NONE,
1141 sizeof(struct fimc_vid_buffer), priv);
1142}
1143
1144static int fimc_m2m_open(struct file *file)
1145{
1146 struct fimc_dev *fimc = video_drvdata(file);
1147 struct fimc_ctx *ctx = NULL;
1148 int err = 0;
1149
1150 mutex_lock(&fimc->lock);
1151 fimc->m2m.refcnt++;
1152 set_bit(ST_OUTDMA_RUN, &fimc->state);
1153 mutex_unlock(&fimc->lock);
1154
1155
1156 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1157 if (!ctx)
1158 return -ENOMEM;
1159
1160 file->private_data = ctx;
1161 ctx->fimc_dev = fimc;
1162 /* default format */
1163 ctx->s_frame.fmt = &fimc_formats[0];
1164 ctx->d_frame.fmt = &fimc_formats[0];
1165 /* per user process device context initialization */
1166 ctx->state = 0;
1167 ctx->flags = 0;
1168 ctx->effect.type = S5P_FIMC_EFFECT_ORIGINAL;
1169 ctx->in_path = FIMC_DMA;
1170 ctx->out_path = FIMC_DMA;
1171 spin_lock_init(&ctx->slock);
1172
1173 ctx->m2m_ctx = v4l2_m2m_ctx_init(ctx, fimc->m2m.m2m_dev, queue_init);
1174 if (IS_ERR(ctx->m2m_ctx)) {
1175 err = PTR_ERR(ctx->m2m_ctx);
1176 kfree(ctx);
1177 }
1178 return err;
1179}
1180
1181static int fimc_m2m_release(struct file *file)
1182{
1183 struct fimc_ctx *ctx = file->private_data;
1184 struct fimc_dev *fimc = ctx->fimc_dev;
1185
1186 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1187 kfree(ctx);
1188 mutex_lock(&fimc->lock);
1189 if (--fimc->m2m.refcnt <= 0)
1190 clear_bit(ST_OUTDMA_RUN, &fimc->state);
1191 mutex_unlock(&fimc->lock);
1192 return 0;
1193}
1194
1195static unsigned int fimc_m2m_poll(struct file *file,
1196 struct poll_table_struct *wait)
1197{
1198 struct fimc_ctx *ctx = file->private_data;
1199 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1200}
1201
1202
1203static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1204{
1205 struct fimc_ctx *ctx = file->private_data;
1206 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1207}
1208
1209static const struct v4l2_file_operations fimc_m2m_fops = {
1210 .owner = THIS_MODULE,
1211 .open = fimc_m2m_open,
1212 .release = fimc_m2m_release,
1213 .poll = fimc_m2m_poll,
1214 .ioctl = video_ioctl2,
1215 .mmap = fimc_m2m_mmap,
1216};
1217
1218static struct v4l2_m2m_ops m2m_ops = {
1219 .device_run = fimc_dma_run,
1220 .job_abort = fimc_job_abort,
1221};
1222
1223
1224static int fimc_register_m2m_device(struct fimc_dev *fimc)
1225{
1226 struct video_device *vfd;
1227 struct platform_device *pdev;
1228 struct v4l2_device *v4l2_dev;
1229 int ret = 0;
1230
1231 if (!fimc)
1232 return -ENODEV;
1233
1234 pdev = fimc->pdev;
1235 v4l2_dev = &fimc->m2m.v4l2_dev;
1236
1237 /* set name if it is empty */
1238 if (!v4l2_dev->name[0])
1239 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1240 "%s.m2m", dev_name(&pdev->dev));
1241
1242 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1243 if (ret)
1244 return ret;;
1245
1246 vfd = video_device_alloc();
1247 if (!vfd) {
1248 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1249 goto err_m2m_r1;
1250 }
1251
1252 vfd->fops = &fimc_m2m_fops;
1253 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1254 vfd->minor = -1;
1255 vfd->release = video_device_release;
1256
1257 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1258
1259 video_set_drvdata(vfd, fimc);
1260 platform_set_drvdata(pdev, fimc);
1261
1262 fimc->m2m.vfd = vfd;
1263 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1264 if (IS_ERR(fimc->m2m.m2m_dev)) {
1265 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1266 ret = PTR_ERR(fimc->m2m.m2m_dev);
1267 goto err_m2m_r2;
1268 }
1269
1270 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1271 if (ret) {
1272 v4l2_err(v4l2_dev,
1273 "%s(): failed to register video device\n", __func__);
1274 goto err_m2m_r3;
1275 }
1276 v4l2_info(v4l2_dev,
1277 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1278
1279 return 0;
1280
1281err_m2m_r3:
1282 v4l2_m2m_release(fimc->m2m.m2m_dev);
1283err_m2m_r2:
1284 video_device_release(fimc->m2m.vfd);
1285err_m2m_r1:
1286 v4l2_device_unregister(v4l2_dev);
1287
1288 return ret;
1289}
1290
1291static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1292{
1293 if (fimc) {
1294 v4l2_m2m_release(fimc->m2m.m2m_dev);
1295 video_unregister_device(fimc->m2m.vfd);
1296 video_device_release(fimc->m2m.vfd);
1297 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1298 }
1299}
1300
1301static void fimc_clk_release(struct fimc_dev *fimc)
1302{
1303 int i;
1304 for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
1305 if (fimc->clock[i]) {
1306 clk_disable(fimc->clock[i]);
1307 clk_put(fimc->clock[i]);
1308 }
1309 }
1310}
1311
1312static int fimc_clk_get(struct fimc_dev *fimc)
1313{
1314 int i;
1315 for (i = 0; i < NUM_FIMC_CLOCKS; i++) {
1316 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clock_name[i]);
1317 if (IS_ERR(fimc->clock[i])) {
1318 dev_err(&fimc->pdev->dev,
1319 "failed to get fimc clock: %s\n",
1320 fimc_clock_name[i]);
1321 return -ENXIO;
1322 }
1323 clk_enable(fimc->clock[i]);
1324 }
1325 return 0;
1326}
1327
1328static int fimc_probe(struct platform_device *pdev)
1329{
1330 struct fimc_dev *fimc;
1331 struct resource *res;
1332 struct samsung_fimc_driverdata *drv_data;
1333 int ret = 0;
1334
1335 dev_dbg(&pdev->dev, "%s():\n", __func__);
1336
1337 drv_data = (struct samsung_fimc_driverdata *)
1338 platform_get_device_id(pdev)->driver_data;
1339
1340 if (pdev->id >= drv_data->devs_cnt) {
1341 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1342 pdev->id);
1343 return -EINVAL;
1344 }
1345
1346 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1347 if (!fimc)
1348 return -ENOMEM;
1349
1350 fimc->id = pdev->id;
1351 fimc->variant = drv_data->variant[fimc->id];
1352 fimc->pdev = pdev;
1353 fimc->state = ST_IDLE;
1354
1355 spin_lock_init(&fimc->irqlock);
1356 spin_lock_init(&fimc->slock);
1357
1358 mutex_init(&fimc->lock);
1359
1360 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1361 if (!res) {
1362 dev_err(&pdev->dev, "failed to find the registers\n");
1363 ret = -ENOENT;
1364 goto err_info;
1365 }
1366
1367 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1368 dev_name(&pdev->dev));
1369 if (!fimc->regs_res) {
1370 dev_err(&pdev->dev, "failed to obtain register region\n");
1371 ret = -ENOENT;
1372 goto err_info;
1373 }
1374
1375 fimc->regs = ioremap(res->start, resource_size(res));
1376 if (!fimc->regs) {
1377 dev_err(&pdev->dev, "failed to map registers\n");
1378 ret = -ENXIO;
1379 goto err_req_region;
1380 }
1381
1382 ret = fimc_clk_get(fimc);
1383 if (ret)
1384 goto err_regs_unmap;
1385
1386 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1387 if (!res) {
1388 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1389 ret = -ENXIO;
1390 goto err_clk;
1391 }
1392 fimc->irq = res->start;
1393
1394 fimc_hw_reset(fimc);
1395
1396 ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1397 if (ret) {
1398 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1399 goto err_clk;
1400 }
1401
1402 fimc->work_queue = create_workqueue(dev_name(&fimc->pdev->dev));
81c69fc2
PO		 1403 if (!fimc->work_queue) {
1404 ret = -ENOMEM;
5fd8f738 1405 goto err_irq;
81c69fc2 1406 }
5fd8f738
SN		 1407
1408 ret = fimc_register_m2m_device(fimc);
1409 if (ret)
1410 goto err_wq;
1411
1412 fimc_hw_en_lastirq(fimc, true);
1413
1414 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1415 __func__, fimc->id);
1416
1417 return 0;
1418
1419err_wq:
1420 destroy_workqueue(fimc->work_queue);
1421err_irq:
1422 free_irq(fimc->irq, fimc);
1423err_clk:
1424 fimc_clk_release(fimc);
1425err_regs_unmap:
1426 iounmap(fimc->regs);
1427err_req_region:
1428 release_resource(fimc->regs_res);
1429 kfree(fimc->regs_res);
1430err_info:
1431 kfree(fimc);
1432 dev_err(&pdev->dev, "failed to install\n");
1433 return ret;
1434}
1435
1436static int __devexit fimc_remove(struct platform_device *pdev)
1437{
1438 struct fimc_dev *fimc =
1439 (struct fimc_dev *)platform_get_drvdata(pdev);
1440
1441 v4l2_info(&fimc->m2m.v4l2_dev, "Removing %s\n", pdev->name);
1442
1443 free_irq(fimc->irq, fimc);
1444
1445 fimc_hw_reset(fimc);
1446
1447 fimc_unregister_m2m_device(fimc);
1448 fimc_clk_release(fimc);
1449 iounmap(fimc->regs);
1450 release_resource(fimc->regs_res);
1451 kfree(fimc->regs_res);
1452 kfree(fimc);
1453 return 0;
1454}
1455
1456static struct samsung_fimc_variant fimc01_variant_s5p = {
1457 .has_inp_rot = 1,
1458 .has_out_rot = 1,
1459 .min_inp_pixsize = 16,
1460 .min_out_pixsize = 16,
1461
1462 .scaler_en_w = 3264,
1463 .scaler_dis_w = 8192,
1464 .in_rot_en_h = 1920,
1465 .in_rot_dis_w = 8192,
1466 .out_rot_en_w = 1920,
1467 .out_rot_dis_w = 4224,
1468};
1469
1470static struct samsung_fimc_variant fimc2_variant_s5p = {
1471 .min_inp_pixsize = 16,
1472 .min_out_pixsize = 16,
1473
1474 .scaler_en_w = 4224,
1475 .scaler_dis_w = 8192,
1476 .in_rot_en_h = 1920,
1477 .in_rot_dis_w = 8192,
1478 .out_rot_en_w = 1920,
1479 .out_rot_dis_w = 4224,
1480};
1481
1482static struct samsung_fimc_variant fimc01_variant_s5pv210 = {
ddc79e0f 1483 .pix_hoff = 1,
5fd8f738
SN		 1484 .has_inp_rot = 1,
1485 .has_out_rot = 1,
1486 .min_inp_pixsize = 16,
1487 .min_out_pixsize = 32,
1488
1489 .scaler_en_w = 4224,
1490 .scaler_dis_w = 8192,
1491 .in_rot_en_h = 1920,
1492 .in_rot_dis_w = 8192,
1493 .out_rot_en_w = 1920,
1494 .out_rot_dis_w = 4224,
1495};
1496
1497static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
ddc79e0f 1498 .pix_hoff = 1,
5fd8f738
SN		 1499 .min_inp_pixsize = 16,
1500 .min_out_pixsize = 32,
1501
1502 .scaler_en_w = 1920,
1503 .scaler_dis_w = 8192,
1504 .in_rot_en_h = 1280,
1505 .in_rot_dis_w = 8192,
1506 .out_rot_en_w = 1280,
1507 .out_rot_dis_w = 1920,
1508};
1509
1510static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1511 .variant = {
1512 [0] = &fimc01_variant_s5p,
1513 [1] = &fimc01_variant_s5p,
1514 [2] = &fimc2_variant_s5p,
1515 },
1516 .devs_cnt = 3
1517};
1518
1519static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1520 .variant = {
1521 [0] = &fimc01_variant_s5pv210,
1522 [1] = &fimc01_variant_s5pv210,
1523 [2] = &fimc2_variant_s5pv210,
1524 },
1525 .devs_cnt = 3
1526};
1527
1528static struct platform_device_id fimc_driver_ids[] = {
1529 {
1530 .name = "s5p-fimc",
1531 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1532 }, {
1533 .name = "s5pv210-fimc",
1534 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
1535 },
1536 {},
1537};
1538MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1539
1540static struct platform_driver fimc_driver = {
1541 .probe = fimc_probe,
1542 .remove = __devexit_p(fimc_remove),
1543 .id_table = fimc_driver_ids,
1544 .driver = {
1545 .name = MODULE_NAME,
1546 .owner = THIS_MODULE,
1547 }
1548};
1549
1550static char banner[] __initdata = KERN_INFO
1551 "S5PC Camera Interface V4L2 Driver, (c) 2010 Samsung Electronics\n";
1552
1553static int __init fimc_init(void)
1554{
1555 u32 ret;
1556 printk(banner);
1557
1558 ret = platform_driver_register(&fimc_driver);
1559 if (ret) {
1560 printk(KERN_ERR "FIMC platform driver register failed\n");
1561 return -1;
1562 }
1563 return 0;
1564}
1565
1566static void __exit fimc_exit(void)
1567{
1568 platform_driver_unregister(&fimc_driver);
1569}
1570
1571module_init(fimc_init);
1572module_exit(fimc_exit);
1573
1574MODULE_AUTHOR("Sylwester Nawrocki, s.nawrocki@samsung.com");
1575MODULE_DESCRIPTION("S3C/S5P FIMC (video postprocessor) driver");
1576MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree