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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
d855497e
MI		 33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
5f6dae80 38#include "pvrusb2-wm8775.h"
6f956512 39#include "pvrusb2-video-v4l.h"
634ba268 40#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 41#include "pvrusb2-cs53l32a.h"
76891d65 42#include "pvrusb2-audio.h"
d855497e 43
1bde0289
MI		 44#define TV_MIN_FREQ 55250000L
45#define TV_MAX_FREQ 850000000L
25d8527a 46
83ce57aa
MI		 47/* This defines a minimum interval that the decoder must remain quiet
48 before we are allowed to start it running. */
49#define TIME_MSEC_DECODER_WAIT 50
50
6e931375
MI		 51/* This defines a minimum interval that the decoder must be allowed to run
52 before we can safely begin using its streaming output. */
53#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
54
83ce57aa 55/* This defines a minimum interval that the encoder must remain quiet
91b5b489
MI		 56 before we are allowed to configure it. */
57#define TIME_MSEC_ENCODER_WAIT 50
83ce57aa
MI		 58
59/* This defines the minimum interval that the encoder must successfully run
60 before we consider that the encoder has run at least once since its
61 firmware has been loaded. This measurement is in important for cases
62 where we can't do something until we know that the encoder has been run
63 at least once. */
64#define TIME_MSEC_ENCODER_OK 250
65
a0fd1cb1 66static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 67static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 68
ff699e6b 69static int ctlchg;
ff699e6b 70static int procreload;
d855497e
MI		 71static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
72static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
73static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 74static int init_pause_msec;
d855497e
MI		 75
76module_param(ctlchg, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
78module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 80module_param(procreload, int, S_IRUGO|S_IWUSR);
81MODULE_PARM_DESC(procreload,
82 "Attempt init failure recovery with firmware reload");
83module_param_array(tuner, int, NULL, 0444);
84MODULE_PARM_DESC(tuner,"specify installed tuner type");
85module_param_array(video_std, int, NULL, 0444);
86MODULE_PARM_DESC(video_std,"specify initial video standard");
87module_param_array(tolerance, int, NULL, 0444);
88MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
89
6f441ed7
MI		 90/* US Broadcast channel 3 (61.25 MHz), to help with testing */
91static int default_tv_freq = 61250000L;
5a4f5da6
MK		 92/* 104.3 MHz, a usable FM station for my area */
93static int default_radio_freq = 104300000L;
94
95module_param_named(tv_freq, default_tv_freq, int, 0444);
96MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
97module_param_named(radio_freq, default_radio_freq, int, 0444);
98MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
99
d855497e
MI		 100#define PVR2_CTL_WRITE_ENDPOINT 0x01
101#define PVR2_CTL_READ_ENDPOINT 0x81
102
103#define PVR2_GPIO_IN 0x9008
104#define PVR2_GPIO_OUT 0x900c
105#define PVR2_GPIO_DIR 0x9020
106
107#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
108
109#define PVR2_FIRMWARE_ENDPOINT 0x02
110
111/* size of a firmware chunk */
112#define FIRMWARE_CHUNK_SIZE 0x2000
113
edb9dcb8
MI		 114typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
115 struct v4l2_subdev *);
116
117static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 118 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 119 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 120 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 121 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 122 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 123};
124
e9c64a78
MI		 125static const char *module_names[] = {
126 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
127 [PVR2_CLIENT_ID_CX25840] = "cx25840",
128 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
129 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 130 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 131 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 132 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 133};
134
135
136static const unsigned char *module_i2c_addresses[] = {
137 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 138 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 139 [PVR2_CLIENT_ID_MSP3400] = "\x40",
140 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 141 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 142 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 143 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 144};
145
146
27eab384
MI		 147static const char *ir_scheme_names[] = {
148 [PVR2_IR_SCHEME_NONE] = "none",
149 [PVR2_IR_SCHEME_29XXX] = "29xxx",
150 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
151 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
152 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
153};
154
155
b30d2441
MI		 156/* Define the list of additional controls we'll dynamically construct based
157 on query of the cx2341x module. */
158struct pvr2_mpeg_ids {
159 const char *strid;
160 int id;
161};
162static const struct pvr2_mpeg_ids mpeg_ids[] = {
163 {
164 .strid = "audio_layer",
165 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
166 },{
167 .strid = "audio_bitrate",
168 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
169 },{
170 /* Already using audio_mode elsewhere :-( */
171 .strid = "mpeg_audio_mode",
172 .id = V4L2_CID_MPEG_AUDIO_MODE,
173 },{
174 .strid = "mpeg_audio_mode_extension",
175 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
176 },{
177 .strid = "audio_emphasis",
178 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
179 },{
180 .strid = "audio_crc",
181 .id = V4L2_CID_MPEG_AUDIO_CRC,
182 },{
183 .strid = "video_aspect",
184 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
185 },{
186 .strid = "video_b_frames",
187 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
188 },{
189 .strid = "video_gop_size",
190 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
191 },{
192 .strid = "video_gop_closure",
193 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 194 },{
195 .strid = "video_bitrate_mode",
196 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
197 },{
198 .strid = "video_bitrate",
199 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
200 },{
201 .strid = "video_bitrate_peak",
202 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
203 },{
204 .strid = "video_temporal_decimation",
205 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
206 },{
207 .strid = "stream_type",
208 .id = V4L2_CID_MPEG_STREAM_TYPE,
209 },{
210 .strid = "video_spatial_filter_mode",
211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
212 },{
213 .strid = "video_spatial_filter",
214 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
215 },{
216 .strid = "video_luma_spatial_filter_type",
217 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
218 },{
219 .strid = "video_chroma_spatial_filter_type",
220 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
221 },{
222 .strid = "video_temporal_filter_mode",
223 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
224 },{
225 .strid = "video_temporal_filter",
226 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
227 },{
228 .strid = "video_median_filter_type",
229 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
230 },{
231 .strid = "video_luma_median_filter_top",
232 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
233 },{
234 .strid = "video_luma_median_filter_bottom",
235 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
236 },{
237 .strid = "video_chroma_median_filter_top",
238 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
239 },{
240 .strid = "video_chroma_median_filter_bottom",
241 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
242 }
243};
eca8ebfc 244#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 245
434449f4 246
d855497e 247static const char *control_values_srate[] = {
434449f4
MI		 248 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 251};
252
253
d855497e 254
d855497e
MI		 255static const char *control_values_input[] = {
256 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 257 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 258 [PVR2_CVAL_INPUT_RADIO] = "radio",
259 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
260 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
261};
262
263
264static const char *control_values_audiomode[] = {
265 [V4L2_TUNER_MODE_MONO] = "Mono",
266 [V4L2_TUNER_MODE_STEREO] = "Stereo",
267 [V4L2_TUNER_MODE_LANG1] = "Lang1",
268 [V4L2_TUNER_MODE_LANG2] = "Lang2",
269 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
270};
271
272
273static const char *control_values_hsm[] = {
274 [PVR2_CVAL_HSM_FAIL] = "Fail",
275 [PVR2_CVAL_HSM_HIGH] = "High",
276 [PVR2_CVAL_HSM_FULL] = "Full",
277};
278
279
681c7399
MI		 280static const char *pvr2_state_names[] = {
281 [PVR2_STATE_NONE] = "none",
282 [PVR2_STATE_DEAD] = "dead",
283 [PVR2_STATE_COLD] = "cold",
284 [PVR2_STATE_WARM] = "warm",
285 [PVR2_STATE_ERROR] = "error",
286 [PVR2_STATE_READY] = "ready",
287 [PVR2_STATE_RUN] = "run",
d855497e
MI		 288};
289
681c7399 290
694dca2b 291struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 292 unsigned char id;
293 unsigned char *desc;
294};
295
694dca2b 296static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 297 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
298 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 299 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 300 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
301 {FX2CMD_REG_WRITE, "write encoder register"},
302 {FX2CMD_REG_READ, "read encoder register"},
303 {FX2CMD_MEMSEL, "encoder memsel"},
304 {FX2CMD_I2C_WRITE, "i2c write"},
305 {FX2CMD_I2C_READ, "i2c read"},
306 {FX2CMD_GET_USB_SPEED, "get USB speed"},
307 {FX2CMD_STREAMING_ON, "stream on"},
308 {FX2CMD_STREAMING_OFF, "stream off"},
309 {FX2CMD_FWPOST1, "fwpost1"},
310 {FX2CMD_POWER_OFF, "power off"},
311 {FX2CMD_POWER_ON, "power on"},
312 {FX2CMD_DEEP_RESET, "deep reset"},
313 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
314 {FX2CMD_GET_IR_CODE, "get IR code"},
315 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
316 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
317 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
318 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
319 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
320 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
321 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
322};
323
324
1cb03b76 325static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 326static void pvr2_hdw_state_sched(struct pvr2_hdw *);
327static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 328static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 329static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 330static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
331static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
332static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 333static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 334static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 335static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 336static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
337static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399 338static void pvr2_hdw_quiescent_timeout(unsigned long);
6e931375 339static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
681c7399 340static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 341static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 342static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 343static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
344 unsigned int timeout,int probe_fl,
345 void *write_data,unsigned int write_len,
346 void *read_data,unsigned int read_len);
432907f7 347static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 348
681c7399
MI		 349
350static void trace_stbit(const char *name,int val)
351{
352 pvr2_trace(PVR2_TRACE_STBITS,
353 "State bit %s <-- %s",
354 name,(val ? "true" : "false"));
355}
356
d855497e
MI		 357static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
358{
359 struct pvr2_hdw *hdw = cptr->hdw;
360 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
361 *vp = hdw->freqTable[hdw->freqProgSlot-1];
362 } else {
363 *vp = 0;
364 }
365 return 0;
366}
367
368static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
369{
370 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 371 unsigned int slotId = hdw->freqProgSlot;
372 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
373 hdw->freqTable[slotId-1] = v;
374 /* Handle side effects correctly - if we're tuned to this
375 slot, then forgot the slot id relation since the stored
376 frequency has been changed. */
377 if (hdw->freqSelector) {
378 if (hdw->freqSlotRadio == slotId) {
379 hdw->freqSlotRadio = 0;
380 }
381 } else {
382 if (hdw->freqSlotTelevision == slotId) {
383 hdw->freqSlotTelevision = 0;
384 }
385 }
d855497e
MI		 386 }
387 return 0;
388}
389
390static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
391{
392 *vp = cptr->hdw->freqProgSlot;
393 return 0;
394}
395
396static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
397{
398 struct pvr2_hdw *hdw = cptr->hdw;
399 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
400 hdw->freqProgSlot = v;
401 }
402 return 0;
403}
404
405static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
406{
1bde0289
MI		 407 struct pvr2_hdw *hdw = cptr->hdw;
408 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 409 return 0;
410}
411
1bde0289 412static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 413{
414 unsigned freq = 0;
415 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 416 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
417 if (slotId > 0) {
418 freq = hdw->freqTable[slotId-1];
419 if (!freq) return 0;
420 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 421 }
1bde0289
MI		 422 if (hdw->freqSelector) {
423 hdw->freqSlotRadio = slotId;
424 } else {
425 hdw->freqSlotTelevision = slotId;
d855497e
MI		 426 }
427 return 0;
428}
429
430static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
431{
1bde0289 432 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 433 return 0;
434}
435
436static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
437{
438 return cptr->hdw->freqDirty != 0;
439}
440
441static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
442{
443 cptr->hdw->freqDirty = 0;
444}
445
446static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
447{
1bde0289 448 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 449 return 0;
450}
451
e784bfb9 452static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
453{
432907f7
MI		 454 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
455 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
456 if (stat != 0) {
432907f7 457 return stat;
e784bfb9 458 }
432907f7 459 *left = cap->bounds.left;
e784bfb9 460 return 0;
461}
462
463static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
464{
432907f7
MI		 465 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
466 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
467 if (stat != 0) {
432907f7
MI		 468 return stat;
469 }
470 *left = cap->bounds.left;
471 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 472 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 473 }
474 return 0;
475}
476
477static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
478{
432907f7
MI		 479 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
480 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
481 if (stat != 0) {
432907f7 482 return stat;
e784bfb9 483 }
432907f7 484 *top = cap->bounds.top;
e784bfb9 485 return 0;
486}
487
432907f7 488static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 489{
432907f7
MI		 490 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
491 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
492 if (stat != 0) {
432907f7
MI		 493 return stat;
494 }
495 *top = cap->bounds.top;
496 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 497 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 498 }
499 return 0;
500}
501
432907f7
MI		 502static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
503{
504 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
505 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
506 if (stat != 0) {
432907f7
MI		 507 return stat;
508 }
509 *val = 0;
510 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 511 *val = cap->bounds.width - cptr->hdw->cropl_val;
512 }
513 return 0;
514}
515
516static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
517{
518 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
519 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
520 if (stat != 0) {
432907f7
MI		 521 return stat;
522 }
523 *val = 0;
524 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 525 *val = cap->bounds.height - cptr->hdw->cropt_val;
526 }
527 return 0;
528}
529
530static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
531{
532 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
533 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
534 if (stat != 0) {
432907f7
MI		 535 return stat;
536 }
537 *val = cap->bounds.left;
538 return 0;
539}
540
541static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
542{
543 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
544 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
545 if (stat != 0) {
432907f7
MI		 546 return stat;
547 }
548 *val = cap->bounds.top;
549 return 0;
550}
551
552static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
553{
554 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
555 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
556 if (stat != 0) {
432907f7
MI		 557 return stat;
558 }
559 *val = cap->bounds.width;
560 return 0;
561}
562
563static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
564{
565 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
566 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
567 if (stat != 0) {
432907f7
MI		 568 return stat;
569 }
570 *val = cap->bounds.height;
571 return 0;
572}
573
574static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
575{
576 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
577 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
578 if (stat != 0) {
432907f7
MI		 579 return stat;
580 }
581 *val = cap->defrect.left;
582 return 0;
583}
584
585static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
586{
587 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
588 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
589 if (stat != 0) {
432907f7
MI		 590 return stat;
591 }
592 *val = cap->defrect.top;
593 return 0;
594}
595
596static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
597{
598 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
599 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
600 if (stat != 0) {
432907f7
MI		 601 return stat;
602 }
603 *val = cap->defrect.width;
604 return 0;
605}
606
607static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
608{
609 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
610 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
611 if (stat != 0) {
432907f7
MI		 612 return stat;
613 }
614 *val = cap->defrect.height;
615 return 0;
616}
617
618static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
619{
620 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
621 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
622 if (stat != 0) {
432907f7
MI		 623 return stat;
624 }
625 *val = cap->pixelaspect.numerator;
626 return 0;
627}
628
629static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
630{
631 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
632 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
633 if (stat != 0) {
432907f7
MI		 634 return stat;
635 }
636 *val = cap->pixelaspect.denominator;
637 return 0;
638}
639
640static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 641{
432907f7
MI		 642 /* Actual maximum depends on the video standard in effect. */
643 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
644 *vp = 480;
e784bfb9 645 } else {
432907f7 646 *vp = 576;
e784bfb9 647 }
648 return 0;
649}
650
3ad9fc37
MI		 651static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
652{
989eb154
MI		 653 /* Actual minimum depends on device digitizer type. */
654 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 655 *vp = 75;
656 } else {
657 *vp = 17;
658 }
659 return 0;
660}
661
1bde0289 662static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 663{
1bde0289
MI		 664 *vp = cptr->hdw->input_val;
665 return 0;
666}
667
29bf5b1d
MI		 668static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
669{
1cb03b76 670 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 671}
672
1bde0289
MI		 673static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
674{
1cb03b76 675 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 676}
677
678static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
679{
680 return cptr->hdw->input_dirty != 0;
681}
682
683static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
684{
685 cptr->hdw->input_dirty = 0;
686}
687
5549f54f 688
25d8527a
PK		 689static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
690{
644afdb9
MI		 691 unsigned long fv;
692 struct pvr2_hdw *hdw = cptr->hdw;
693 if (hdw->tuner_signal_stale) {
a51f5000 694 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 695 }
696 fv = hdw->tuner_signal_info.rangehigh;
697 if (!fv) {
698 /* Safety fallback */
25d8527a 699 *vp = TV_MAX_FREQ;
644afdb9 700 return 0;
25d8527a 701 }
644afdb9
MI		 702 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
703 fv = (fv * 125) / 2;
704 } else {
705 fv = fv * 62500;
706 }
707 *vp = fv;
25d8527a
PK		 708 return 0;
709}
710
711static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
712{
644afdb9
MI		 713 unsigned long fv;
714 struct pvr2_hdw *hdw = cptr->hdw;
715 if (hdw->tuner_signal_stale) {
a51f5000 716 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 717 }
718 fv = hdw->tuner_signal_info.rangelow;
719 if (!fv) {
720 /* Safety fallback */
25d8527a 721 *vp = TV_MIN_FREQ;
644afdb9
MI		 722 return 0;
723 }
724 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
725 fv = (fv * 125) / 2;
726 } else {
727 fv = fv * 62500;
25d8527a 728 }
644afdb9 729 *vp = fv;
25d8527a
PK		 730 return 0;
731}
732
b30d2441
MI		 733static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
734{
735 return cptr->hdw->enc_stale != 0;
736}
737
738static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
739{
740 cptr->hdw->enc_stale = 0;
681c7399 741 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 742}
743
744static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
745{
746 int ret;
747 struct v4l2_ext_controls cs;
748 struct v4l2_ext_control c1;
749 memset(&cs,0,sizeof(cs));
750 memset(&c1,0,sizeof(c1));
751 cs.controls = &c1;
752 cs.count = 1;
753 c1.id = cptr->info->v4l_id;
01f1e44f 754 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 755 VIDIOC_G_EXT_CTRLS);
756 if (ret) return ret;
757 *vp = c1.value;
758 return 0;
759}
760
761static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
762{
763 int ret;
681c7399 764 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 765 struct v4l2_ext_controls cs;
766 struct v4l2_ext_control c1;
767 memset(&cs,0,sizeof(cs));
768 memset(&c1,0,sizeof(c1));
769 cs.controls = &c1;
770 cs.count = 1;
771 c1.id = cptr->info->v4l_id;
772 c1.value = v;
681c7399
MI		 773 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
774 hdw->state_encoder_run, &cs,
b30d2441 775 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 776 if (ret == -EBUSY) {
777 /* Oops. cx2341x is telling us it's not safe to change
778 this control while we're capturing. Make a note of this
779 fact so that the pipeline will be stopped the next time
780 controls are committed. Then go on ahead and store this
781 change anyway. */
782 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
783 0, &cs,
784 VIDIOC_S_EXT_CTRLS);
785 if (!ret) hdw->enc_unsafe_stale = !0;
786 }
b30d2441 787 if (ret) return ret;
681c7399 788 hdw->enc_stale = !0;
b30d2441
MI		 789 return 0;
790}
791
792static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
793{
794 struct v4l2_queryctrl qctrl;
795 struct pvr2_ctl_info *info;
796 qctrl.id = cptr->info->v4l_id;
797 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
798 /* Strip out the const so we can adjust a function pointer. It's
799 OK to do this here because we know this is a dynamically created
800 control, so the underlying storage for the info pointer is (a)
801 private to us, and (b) not in read-only storage. Either we do
802 this or we significantly complicate the underlying control
803 implementation. */
804 info = (struct pvr2_ctl_info *)(cptr->info);
805 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
806 if (info->set_value) {
a0fd1cb1 807 info->set_value = NULL;
b30d2441
MI		 808 }
809 } else {
810 if (!(info->set_value)) {
811 info->set_value = ctrl_cx2341x_set;
812 }
813 }
814 return qctrl.flags;
815}
816
d855497e
MI		 817static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
818{
681c7399
MI		 819 *vp = cptr->hdw->state_pipeline_req;
820 return 0;
821}
822
823static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
824{
825 *vp = cptr->hdw->master_state;
d855497e
MI		 826 return 0;
827}
828
829static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
830{
831 int result = pvr2_hdw_is_hsm(cptr->hdw);
832 *vp = PVR2_CVAL_HSM_FULL;
833 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
834 if (result) *vp = PVR2_CVAL_HSM_HIGH;
835 return 0;
836}
837
838static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
839{
840 *vp = cptr->hdw->std_mask_avail;
841 return 0;
842}
843
844static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
845{
846 struct pvr2_hdw *hdw = cptr->hdw;
847 v4l2_std_id ns;
848 ns = hdw->std_mask_avail;
849 ns = (ns & ~m) | (v & m);
850 if (ns == hdw->std_mask_avail) return 0;
851 hdw->std_mask_avail = ns;
852 pvr2_hdw_internal_set_std_avail(hdw);
853 pvr2_hdw_internal_find_stdenum(hdw);
854 return 0;
855}
856
857static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
858 char *bufPtr,unsigned int bufSize,
859 unsigned int *len)
860{
861 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
862 return 0;
863}
864
865static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
866 const char *bufPtr,unsigned int bufSize,
867 int *mskp,int *valp)
868{
869 int ret;
870 v4l2_std_id id;
871 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
872 if (ret < 0) return ret;
873 if (mskp) *mskp = id;
874 if (valp) *valp = id;
875 return 0;
876}
877
878static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
879{
880 *vp = cptr->hdw->std_mask_cur;
881 return 0;
882}
883
884static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
885{
886 struct pvr2_hdw *hdw = cptr->hdw;
887 v4l2_std_id ns;
888 ns = hdw->std_mask_cur;
889 ns = (ns & ~m) | (v & m);
890 if (ns == hdw->std_mask_cur) return 0;
891 hdw->std_mask_cur = ns;
892 hdw->std_dirty = !0;
893 pvr2_hdw_internal_find_stdenum(hdw);
894 return 0;
895}
896
897static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
898{
899 return cptr->hdw->std_dirty != 0;
900}
901
902static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
903{
904 cptr->hdw->std_dirty = 0;
905}
906
907static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
908{
18103c57 909 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 910 pvr2_hdw_status_poll(hdw);
18103c57
MI		 911 *vp = hdw->tuner_signal_info.signal;
912 return 0;
913}
914
915static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
916{
917 int val = 0;
918 unsigned int subchan;
919 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 920 pvr2_hdw_status_poll(hdw);
18103c57
MI		 921 subchan = hdw->tuner_signal_info.rxsubchans;
922 if (subchan & V4L2_TUNER_SUB_MONO) {
923 val |= (1 << V4L2_TUNER_MODE_MONO);
924 }
925 if (subchan & V4L2_TUNER_SUB_STEREO) {
926 val |= (1 << V4L2_TUNER_MODE_STEREO);
927 }
928 if (subchan & V4L2_TUNER_SUB_LANG1) {
929 val |= (1 << V4L2_TUNER_MODE_LANG1);
930 }
931 if (subchan & V4L2_TUNER_SUB_LANG2) {
932 val |= (1 << V4L2_TUNER_MODE_LANG2);
933 }
934 *vp = val;
d855497e
MI		 935 return 0;
936}
937
d855497e
MI		 938
939static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
940{
941 struct pvr2_hdw *hdw = cptr->hdw;
942 if (v < 0) return -EINVAL;
943 if (v > hdw->std_enum_cnt) return -EINVAL;
944 hdw->std_enum_cur = v;
945 if (!v) return 0;
946 v--;
947 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
948 hdw->std_mask_cur = hdw->std_defs[v].id;
949 hdw->std_dirty = !0;
950 return 0;
951}
952
953
954static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
955{
956 *vp = cptr->hdw->std_enum_cur;
957 return 0;
958}
959
960
961static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
962{
963 return cptr->hdw->std_dirty != 0;
964}
965
966
967static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
968{
969 cptr->hdw->std_dirty = 0;
970}
971
972
973#define DEFINT(vmin,vmax) \
974 .type = pvr2_ctl_int, \
975 .def.type_int.min_value = vmin, \
976 .def.type_int.max_value = vmax
977
978#define DEFENUM(tab) \
979 .type = pvr2_ctl_enum, \
27c7b710 980 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 981 .def.type_enum.value_names = tab
982
33213963
MI		 983#define DEFBOOL \
984 .type = pvr2_ctl_bool
985
d855497e
MI		 986#define DEFMASK(msk,tab) \
987 .type = pvr2_ctl_bitmask, \
988 .def.type_bitmask.valid_bits = msk, \
989 .def.type_bitmask.bit_names = tab
990
991#define DEFREF(vname) \
992 .set_value = ctrl_set_##vname, \
993 .get_value = ctrl_get_##vname, \
994 .is_dirty = ctrl_isdirty_##vname, \
995 .clear_dirty = ctrl_cleardirty_##vname
996
997
998#define VCREATE_FUNCS(vname) \
999static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1000{*vp = cptr->hdw->vname##_val; return 0;} \
1001static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1002{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1003static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1004{return cptr->hdw->vname##_dirty != 0;} \
1005static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1006{cptr->hdw->vname##_dirty = 0;}
1007
1008VCREATE_FUNCS(brightness)
1009VCREATE_FUNCS(contrast)
1010VCREATE_FUNCS(saturation)
1011VCREATE_FUNCS(hue)
1012VCREATE_FUNCS(volume)
1013VCREATE_FUNCS(balance)
1014VCREATE_FUNCS(bass)
1015VCREATE_FUNCS(treble)
1016VCREATE_FUNCS(mute)
e784bfb9 1017VCREATE_FUNCS(cropl)
1018VCREATE_FUNCS(cropt)
1019VCREATE_FUNCS(cropw)
1020VCREATE_FUNCS(croph)
c05c0462
MI		 1021VCREATE_FUNCS(audiomode)
1022VCREATE_FUNCS(res_hor)
1023VCREATE_FUNCS(res_ver)
d855497e 1024VCREATE_FUNCS(srate)
d855497e 1025
d855497e
MI		 1026/* Table definition of all controls which can be manipulated */
1027static const struct pvr2_ctl_info control_defs[] = {
1028 {
1029 .v4l_id = V4L2_CID_BRIGHTNESS,
1030 .desc = "Brightness",
1031 .name = "brightness",
1032 .default_value = 128,
1033 DEFREF(brightness),
1034 DEFINT(0,255),
1035 },{
1036 .v4l_id = V4L2_CID_CONTRAST,
1037 .desc = "Contrast",
1038 .name = "contrast",
1039 .default_value = 68,
1040 DEFREF(contrast),
1041 DEFINT(0,127),
1042 },{
1043 .v4l_id = V4L2_CID_SATURATION,
1044 .desc = "Saturation",
1045 .name = "saturation",
1046 .default_value = 64,
1047 DEFREF(saturation),
1048 DEFINT(0,127),
1049 },{
1050 .v4l_id = V4L2_CID_HUE,
1051 .desc = "Hue",
1052 .name = "hue",
1053 .default_value = 0,
1054 DEFREF(hue),
1055 DEFINT(-128,127),
1056 },{
1057 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1058 .desc = "Volume",
1059 .name = "volume",
139eecf9 1060 .default_value = 62000,
d855497e
MI		 1061 DEFREF(volume),
1062 DEFINT(0,65535),
1063 },{
1064 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1065 .desc = "Balance",
1066 .name = "balance",
1067 .default_value = 0,
1068 DEFREF(balance),
1069 DEFINT(-32768,32767),
1070 },{
1071 .v4l_id = V4L2_CID_AUDIO_BASS,
1072 .desc = "Bass",
1073 .name = "bass",
1074 .default_value = 0,
1075 DEFREF(bass),
1076 DEFINT(-32768,32767),
1077 },{
1078 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1079 .desc = "Treble",
1080 .name = "treble",
1081 .default_value = 0,
1082 DEFREF(treble),
1083 DEFINT(-32768,32767),
1084 },{
1085 .v4l_id = V4L2_CID_AUDIO_MUTE,
1086 .desc = "Mute",
1087 .name = "mute",
1088 .default_value = 0,
1089 DEFREF(mute),
33213963 1090 DEFBOOL,
e784bfb9 1091 }, {
432907f7 1092 .desc = "Capture crop left margin",
e784bfb9 1093 .name = "crop_left",
1094 .internal_id = PVR2_CID_CROPL,
1095 .default_value = 0,
1096 DEFREF(cropl),
1097 DEFINT(-129, 340),
1098 .get_min_value = ctrl_cropl_min_get,
1099 .get_max_value = ctrl_cropl_max_get,
432907f7 1100 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1101 }, {
432907f7 1102 .desc = "Capture crop top margin",
e784bfb9 1103 .name = "crop_top",
1104 .internal_id = PVR2_CID_CROPT,
1105 .default_value = 0,
1106 DEFREF(cropt),
1107 DEFINT(-35, 544),
1108 .get_min_value = ctrl_cropt_min_get,
1109 .get_max_value = ctrl_cropt_max_get,
432907f7 1110 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1111 }, {
432907f7 1112 .desc = "Capture crop width",
e784bfb9 1113 .name = "crop_width",
1114 .internal_id = PVR2_CID_CROPW,
1115 .default_value = 720,
1116 DEFREF(cropw),
432907f7
MI		 1117 .get_max_value = ctrl_cropw_max_get,
1118 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1119 }, {
432907f7 1120 .desc = "Capture crop height",
e784bfb9 1121 .name = "crop_height",
1122 .internal_id = PVR2_CID_CROPH,
1123 .default_value = 480,
1124 DEFREF(croph),
432907f7
MI		 1125 .get_max_value = ctrl_croph_max_get,
1126 .get_def_value = ctrl_get_cropcapdh,
1127 }, {
1128 .desc = "Capture capability pixel aspect numerator",
1129 .name = "cropcap_pixel_numerator",
1130 .internal_id = PVR2_CID_CROPCAPPAN,
1131 .get_value = ctrl_get_cropcappan,
1132 }, {
1133 .desc = "Capture capability pixel aspect denominator",
1134 .name = "cropcap_pixel_denominator",
1135 .internal_id = PVR2_CID_CROPCAPPAD,
1136 .get_value = ctrl_get_cropcappad,
1137 }, {
1138 .desc = "Capture capability bounds top",
1139 .name = "cropcap_bounds_top",
1140 .internal_id = PVR2_CID_CROPCAPBT,
1141 .get_value = ctrl_get_cropcapbt,
1142 }, {
1143 .desc = "Capture capability bounds left",
1144 .name = "cropcap_bounds_left",
1145 .internal_id = PVR2_CID_CROPCAPBL,
1146 .get_value = ctrl_get_cropcapbl,
1147 }, {
1148 .desc = "Capture capability bounds width",
1149 .name = "cropcap_bounds_width",
1150 .internal_id = PVR2_CID_CROPCAPBW,
1151 .get_value = ctrl_get_cropcapbw,
1152 }, {
1153 .desc = "Capture capability bounds height",
1154 .name = "cropcap_bounds_height",
1155 .internal_id = PVR2_CID_CROPCAPBH,
1156 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1157 },{
1158 .desc = "Video Source",
1159 .name = "input",
1160 .internal_id = PVR2_CID_INPUT,
1161 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1162 .check_value = ctrl_check_input,
c05c0462
MI		 1163 DEFREF(input),
1164 DEFENUM(control_values_input),
1165 },{
1166 .desc = "Audio Mode",
1167 .name = "audio_mode",
1168 .internal_id = PVR2_CID_AUDIOMODE,
1169 .default_value = V4L2_TUNER_MODE_STEREO,
1170 DEFREF(audiomode),
1171 DEFENUM(control_values_audiomode),
1172 },{
1173 .desc = "Horizontal capture resolution",
1174 .name = "resolution_hor",
1175 .internal_id = PVR2_CID_HRES,
1176 .default_value = 720,
1177 DEFREF(res_hor),
3ad9fc37 1178 DEFINT(19,720),
c05c0462
MI		 1179 },{
1180 .desc = "Vertical capture resolution",
1181 .name = "resolution_ver",
1182 .internal_id = PVR2_CID_VRES,
1183 .default_value = 480,
1184 DEFREF(res_ver),
3ad9fc37
MI		 1185 DEFINT(17,576),
1186 /* Hook in check for video standard and adjust maximum
1187 depending on the standard. */
1188 .get_max_value = ctrl_vres_max_get,
1189 .get_min_value = ctrl_vres_min_get,
d855497e 1190 },{
b30d2441 1191 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1192 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1193 .desc = "Audio Sampling Frequency",
d855497e 1194 .name = "srate",
d855497e
MI		 1195 DEFREF(srate),
1196 DEFENUM(control_values_srate),
d855497e
MI		 1197 },{
1198 .desc = "Tuner Frequency (Hz)",
1199 .name = "frequency",
1200 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1201 .default_value = 0,
d855497e
MI		 1202 .set_value = ctrl_freq_set,
1203 .get_value = ctrl_freq_get,
1204 .is_dirty = ctrl_freq_is_dirty,
1205 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1206 DEFINT(0,0),
25d8527a
PK		 1207 /* Hook in check for input value (tv/radio) and adjust
1208 max/min values accordingly */
1209 .get_max_value = ctrl_freq_max_get,
1210 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1211 },{
1212 .desc = "Channel",
1213 .name = "channel",
1214 .set_value = ctrl_channel_set,
1215 .get_value = ctrl_channel_get,
1216 DEFINT(0,FREQTABLE_SIZE),
1217 },{
1218 .desc = "Channel Program Frequency",
1219 .name = "freq_table_value",
1220 .set_value = ctrl_channelfreq_set,
1221 .get_value = ctrl_channelfreq_get,
644afdb9 1222 DEFINT(0,0),
1bde0289
MI		 1223 /* Hook in check for input value (tv/radio) and adjust
1224 max/min values accordingly */
1bde0289
MI		 1225 .get_max_value = ctrl_freq_max_get,
1226 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1227 },{
1228 .desc = "Channel Program ID",
1229 .name = "freq_table_channel",
1230 .set_value = ctrl_channelprog_set,
1231 .get_value = ctrl_channelprog_get,
1232 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1233 },{
1234 .desc = "Streaming Enabled",
1235 .name = "streaming_enabled",
1236 .get_value = ctrl_streamingenabled_get,
33213963 1237 DEFBOOL,
d855497e
MI		 1238 },{
1239 .desc = "USB Speed",
1240 .name = "usb_speed",
1241 .get_value = ctrl_hsm_get,
1242 DEFENUM(control_values_hsm),
681c7399
MI		 1243 },{
1244 .desc = "Master State",
1245 .name = "master_state",
1246 .get_value = ctrl_masterstate_get,
1247 DEFENUM(pvr2_state_names),
d855497e
MI		 1248 },{
1249 .desc = "Signal Present",
1250 .name = "signal_present",
1251 .get_value = ctrl_signal_get,
18103c57
MI		 1252 DEFINT(0,65535),
1253 },{
1254 .desc = "Audio Modes Present",
1255 .name = "audio_modes_present",
1256 .get_value = ctrl_audio_modes_present_get,
1257 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1258 v4l. Nothing outside of this module cares about this,
1259 but I reuse it in order to also reuse the
1260 control_values_audiomode string table. */
1261 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1262 (1 << V4L2_TUNER_MODE_STEREO)|
1263 (1 << V4L2_TUNER_MODE_LANG1)|
1264 (1 << V4L2_TUNER_MODE_LANG2)),
1265 control_values_audiomode),
d855497e
MI		 1266 },{
1267 .desc = "Video Standards Available Mask",
1268 .name = "video_standard_mask_available",
1269 .internal_id = PVR2_CID_STDAVAIL,
1270 .skip_init = !0,
1271 .get_value = ctrl_stdavail_get,
1272 .set_value = ctrl_stdavail_set,
1273 .val_to_sym = ctrl_std_val_to_sym,
1274 .sym_to_val = ctrl_std_sym_to_val,
1275 .type = pvr2_ctl_bitmask,
1276 },{
1277 .desc = "Video Standards In Use Mask",
1278 .name = "video_standard_mask_active",
1279 .internal_id = PVR2_CID_STDCUR,
1280 .skip_init = !0,
1281 .get_value = ctrl_stdcur_get,
1282 .set_value = ctrl_stdcur_set,
1283 .is_dirty = ctrl_stdcur_is_dirty,
1284 .clear_dirty = ctrl_stdcur_clear_dirty,
1285 .val_to_sym = ctrl_std_val_to_sym,
1286 .sym_to_val = ctrl_std_sym_to_val,
1287 .type = pvr2_ctl_bitmask,
d855497e
MI		 1288 },{
1289 .desc = "Video Standard Name",
1290 .name = "video_standard",
1291 .internal_id = PVR2_CID_STDENUM,
1292 .skip_init = !0,
1293 .get_value = ctrl_stdenumcur_get,
1294 .set_value = ctrl_stdenumcur_set,
1295 .is_dirty = ctrl_stdenumcur_is_dirty,
1296 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1297 .type = pvr2_ctl_enum,
1298 }
1299};
1300
eca8ebfc 1301#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1302
1303
1304const char *pvr2_config_get_name(enum pvr2_config cfg)
1305{
1306 switch (cfg) {
1307 case pvr2_config_empty: return "empty";
1308 case pvr2_config_mpeg: return "mpeg";
1309 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1310 case pvr2_config_pcm: return "pcm";
1311 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1312 }
1313 return "<unknown>";
1314}
1315
1316
1317struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1318{
1319 return hdw->usb_dev;
1320}
1321
1322
1323unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1324{
1325 return hdw->serial_number;
1326}
1327
31a18547
MI		 1328
1329const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1330{
1331 return hdw->bus_info;
1332}
1333
1334
13a88797
MI		 1335const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1336{
1337 return hdw->identifier;
1338}
1339
1340
1bde0289
MI		 1341unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1342{
1343 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1344}
1345
1346/* Set the currently tuned frequency and account for all possible
1347 driver-core side effects of this action. */
f55a8712 1348static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1349{
7c74e57e 1350 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1351 if (hdw->freqSelector) {
1352 /* Swing over to radio frequency selection */
1353 hdw->freqSelector = 0;
1354 hdw->freqDirty = !0;
1355 }
1bde0289
MI		 1356 if (hdw->freqValRadio != val) {
1357 hdw->freqValRadio = val;
1358 hdw->freqSlotRadio = 0;
7c74e57e 1359 hdw->freqDirty = !0;
1bde0289 1360 }
7c74e57e 1361 } else {
1bde0289
MI		 1362 if (!(hdw->freqSelector)) {
1363 /* Swing over to television frequency selection */
1364 hdw->freqSelector = 1;
1365 hdw->freqDirty = !0;
1366 }
1bde0289
MI		 1367 if (hdw->freqValTelevision != val) {
1368 hdw->freqValTelevision = val;
1369 hdw->freqSlotTelevision = 0;
7c74e57e 1370 hdw->freqDirty = !0;
1bde0289 1371 }
1bde0289
MI		 1372 }
1373}
1374
d855497e
MI		 1375int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1376{
1377 return hdw->unit_number;
1378}
1379
1380
1381/* Attempt to locate one of the given set of files. Messages are logged
1382 appropriate to what has been found. The return value will be 0 or
1383 greater on success (it will be the index of the file name found) and
1384 fw_entry will be filled in. Otherwise a negative error is returned on
1385 failure. If the return value is -ENOENT then no viable firmware file
1386 could be located. */
1387static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1388 const struct firmware **fw_entry,
1389 const char *fwtypename,
1390 unsigned int fwcount,
1391 const char *fwnames[])
1392{
1393 unsigned int idx;
1394 int ret = -EINVAL;
1395 for (idx = 0; idx < fwcount; idx++) {
1396 ret = request_firmware(fw_entry,
1397 fwnames[idx],
1398 &hdw->usb_dev->dev);
1399 if (!ret) {
1400 trace_firmware("Located %s firmware: %s;"
1401 " uploading...",
1402 fwtypename,
1403 fwnames[idx]);
1404 return idx;
1405 }
1406 if (ret == -ENOENT) continue;
1407 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1408 "request_firmware fatal error with code=%d",ret);
1409 return ret;
1410 }
1411 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1412 "***WARNING***"
1413 " Device %s firmware"
1414 " seems to be missing.",
1415 fwtypename);
1416 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1417 "Did you install the pvrusb2 firmware files"
1418 " in their proper location?");
1419 if (fwcount == 1) {
1420 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1421 "request_firmware unable to locate %s file %s",
1422 fwtypename,fwnames[0]);
1423 } else {
1424 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425 "request_firmware unable to locate"
1426 " one of the following %s files:",
1427 fwtypename);
1428 for (idx = 0; idx < fwcount; idx++) {
1429 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1430 "request_firmware: Failed to find %s",
1431 fwnames[idx]);
1432 }
1433 }
1434 return ret;
1435}
1436
1437
1438/*
1439 * pvr2_upload_firmware1().
1440 *
1441 * Send the 8051 firmware to the device. After the upload, arrange for
1442 * device to re-enumerate.
1443 *
1444 * NOTE : the pointer to the firmware data given by request_firmware()
1445 * is not suitable for an usb transaction.
1446 *
1447 */
07e337ee 1448static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1449{
a0fd1cb1 1450 const struct firmware *fw_entry = NULL;
d855497e
MI		 1451 void *fw_ptr;
1452 unsigned int pipe;
9081d901 1453 unsigned int fwsize;
d855497e
MI		 1454 int ret;
1455 u16 address;
1d643a37 1456
989eb154 1457 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1458 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1459 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1460 "Connected device type defines"
1461 " no firmware to upload; ignoring firmware");
1462 return -ENOTTY;
1d643a37
MI		 1463 }
1464
d855497e
MI		 1465 hdw->fw1_state = FW1_STATE_FAILED; // default result
1466
1467 trace_firmware("pvr2_upload_firmware1");
1468
1469 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1470 hdw->hdw_desc->fx2_firmware.cnt,
1471 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1472 if (ret < 0) {
1473 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1474 return ret;
1475 }
1476
d855497e
MI		 1477 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1478
1479 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
9081d901 1480 fwsize = fw_entry->size;
d855497e 1481
9081d901
MI		 1482 if ((fwsize != 0x2000) &&
1483 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
c21c2db4
MI		 1484 if (hdw->hdw_desc->flag_fx2_16kb) {
1485 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1486 "Wrong fx2 firmware size"
1487 " (expected 8192 or 16384, got %u)",
9081d901 1488 fwsize);
c21c2db4
MI		 1489 } else {
1490 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1491 "Wrong fx2 firmware size"
1492 " (expected 8192, got %u)",
9081d901 1493 fwsize);
c21c2db4 1494 }
d855497e
MI		 1495 release_firmware(fw_entry);
1496 return -ENOMEM;
1497 }
1498
1499 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1500 if (fw_ptr == NULL){
1501 release_firmware(fw_entry);
1502 return -ENOMEM;
1503 }
1504
1505 /* We have to hold the CPU during firmware upload. */
1506 pvr2_hdw_cpureset_assert(hdw,1);
1507
1508 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1509 chunk. */
1510
1511 ret = 0;
9081d901 1512 for (address = 0; address < fwsize; address += 0x800) {
d855497e
MI		 1513 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1514 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1515 0, fw_ptr, 0x800, HZ);
1516 }
1517
1518 trace_firmware("Upload done, releasing device's CPU");
1519
1520 /* Now release the CPU. It will disconnect and reconnect later. */
1521 pvr2_hdw_cpureset_assert(hdw,0);
1522
1523 kfree(fw_ptr);
1524 release_firmware(fw_entry);
1525
1526 trace_firmware("Upload done (%d bytes sent)",ret);
1527
75727460
GF		 1528 /* We should have written fwsize bytes */
1529 if (ret == fwsize) {
d855497e
MI		 1530 hdw->fw1_state = FW1_STATE_RELOAD;
1531 return 0;
1532 }
1533
1534 return -EIO;
1535}
1536
1537
1538/*
1539 * pvr2_upload_firmware2()
1540 *
1541 * This uploads encoder firmware on endpoint 2.
1542 *
1543 */
1544
1545int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1546{
a0fd1cb1 1547 const struct firmware *fw_entry = NULL;
d855497e 1548 void *fw_ptr;
90060d32 1549 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1550 int actual_length;
1551 int ret = 0;
1552 int fwidx;
1553 static const char *fw_files[] = {
1554 CX2341X_FIRM_ENC_FILENAME,
1555 };
1556
989eb154 1557 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1558 return 0;
1559 }
1560
d855497e
MI		 1561 trace_firmware("pvr2_upload_firmware2");
1562
1563 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1564 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1565 if (ret < 0) return ret;
1566 fwidx = ret;
1567 ret = 0;
b30d2441
MI		 1568 /* Since we're about to completely reinitialize the encoder,
1569 invalidate our cached copy of its configuration state. Next
1570 time we configure the encoder, then we'll fully configure it. */
1571 hdw->enc_cur_valid = 0;
d855497e 1572
d913d630
MI		 1573 /* Encoder is about to be reset so note that as far as we're
1574 concerned now, the encoder has never been run. */
1575 del_timer_sync(&hdw->encoder_run_timer);
1576 if (hdw->state_encoder_runok) {
1577 hdw->state_encoder_runok = 0;
1578 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1579 }
1580
d855497e
MI		 1581 /* First prepare firmware loading */
1582 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1583 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1584 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1585 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1586 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1587 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1588 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1589 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1590 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1591 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1592 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1593 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1594 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1595 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1596 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1597 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1598 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1599 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1600
1601 if (ret) {
1602 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1603 "firmware2 upload prep failed, ret=%d",ret);
1604 release_firmware(fw_entry);
21684ba9 1605 goto done;
d855497e
MI		 1606 }
1607
1608 /* Now send firmware */
1609
1610 fw_len = fw_entry->size;
1611
90060d32 1612 if (fw_len % sizeof(u32)) {
d855497e
MI		 1613 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1614 "size of %s firmware"
48dc30a1 1615 " must be a multiple of %zu bytes",
90060d32 1616 fw_files[fwidx],sizeof(u32));
d855497e 1617 release_firmware(fw_entry);
21684ba9
MI		 1618 ret = -EINVAL;
1619 goto done;
d855497e
MI		 1620 }
1621
1622 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1623 if (fw_ptr == NULL){
1624 release_firmware(fw_entry);
1625 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1626 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1627 ret = -ENOMEM;
1628 goto done;
d855497e
MI		 1629 }
1630
1631 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1632
90060d32
MI		 1633 fw_done = 0;
1634 for (fw_done = 0; fw_done < fw_len;) {
1635 bcnt = fw_len - fw_done;
1636 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1637 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1638 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1639 /* Some background info: The data being swapped here is a
1640 firmware image destined for the mpeg encoder chip that
1641 lives at the other end of a USB endpoint. The encoder
1642 chip always talks in 32 bit chunks and its storage is
1643 organized into 32 bit words. However from the file
1644 system to the encoder chip everything is purely a byte
1645 stream. The firmware file's contents are always 32 bit
1646 swapped from what the encoder expects. Thus the need
1647 always exists to swap the bytes regardless of the endian
1648 type of the host processor and therefore swab32() makes
1649 the most sense. */
90060d32 1650 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1651 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1652
1653 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1654 &actual_length, HZ);
90060d32
MI		 1655 ret |= (actual_length != bcnt);
1656 if (ret) break;
1657 fw_done += bcnt;
d855497e
MI		 1658 }
1659
1660 trace_firmware("upload of %s : %i / %i ",
1661 fw_files[fwidx],fw_done,fw_len);
1662
1663 kfree(fw_ptr);
1664 release_firmware(fw_entry);
1665
1666 if (ret) {
1667 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1668 "firmware2 upload transfer failure");
21684ba9 1669 goto done;
d855497e
MI		 1670 }
1671
1672 /* Finish upload */
1673
1674 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1675 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1676 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1677
1678 if (ret) {
1679 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1680 "firmware2 upload post-proc failure");
d855497e 1681 }
21684ba9
MI		 1682
1683 done:
1df59f0b
MI		 1684 if (hdw->hdw_desc->signal_routing_scheme ==
1685 PVR2_ROUTING_SCHEME_GOTVIEW) {
1686 /* Ensure that GPIO 11 is set to output for GOTVIEW
1687 hardware. */
1688 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1689 }
d855497e
MI		 1690 return ret;
1691}
1692
1693
681c7399
MI		 1694static const char *pvr2_get_state_name(unsigned int st)
1695{
1696 if (st < ARRAY_SIZE(pvr2_state_names)) {
1697 return pvr2_state_names[st];
d855497e 1698 }
681c7399 1699 return "???";
d855497e
MI		 1700}
1701
681c7399 1702static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1703{
af78e16b
MI		 1704 /* Even though we really only care about the video decoder chip at
1705 this point, we'll broadcast stream on/off to all sub-devices
1706 anyway, just in case somebody else wants to hear the
1707 command... */
e260508d
MI		 1708 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1709 (enablefl ? "on" : "off"));
af78e16b 1710 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
3ccc646b 1711 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
af78e16b
MI		 1712 if (hdw->decoder_client_id) {
1713 /* We get here if the encoder has been noticed. Otherwise
1714 we'll issue a warning to the user (which should
1715 normally never happen). */
1716 return 0;
1717 }
1718 if (!hdw->flag_decoder_missed) {
1719 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1720 "WARNING: No decoder present");
1721 hdw->flag_decoder_missed = !0;
1722 trace_stbit("flag_decoder_missed",
1723 hdw->flag_decoder_missed);
1724 }
1725 return -EIO;
d855497e
MI		 1726}
1727
1728
681c7399 1729int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1730{
681c7399 1731 return hdw->master_state;
d855497e
MI		 1732}
1733
1734
681c7399 1735static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1736{
681c7399
MI		 1737 if (!hdw->flag_tripped) return 0;
1738 hdw->flag_tripped = 0;
1739 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1740 "Clearing driver error statuss");
1741 return !0;
d855497e
MI		 1742}
1743
1744
681c7399 1745int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1746{
681c7399 1747 int fl;
d855497e 1748 LOCK_TAKE(hdw->big_lock); do {
681c7399 1749 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1750 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1751 if (fl) pvr2_hdw_state_sched(hdw);
1752 return 0;
d855497e
MI		 1753}
1754
1755
d855497e
MI		 1756
1757
1758int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1759{
681c7399 1760 return hdw->state_pipeline_req != 0;
d855497e
MI		 1761}
1762
1763
1764int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1765{
681c7399 1766 int ret,st;
d855497e 1767 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1768 pvr2_hdw_untrip_unlocked(hdw);
1769 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1770 hdw->state_pipeline_req = enable_flag != 0;
1771 pvr2_trace(PVR2_TRACE_START_STOP,
1772 "/*--TRACE_STREAM--*/ %s",
1773 enable_flag ? "enable" : "disable");
1774 }
1775 pvr2_hdw_state_sched(hdw);
d855497e 1776 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1777 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1778 if (enable_flag) {
1779 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1780 if (st != PVR2_STATE_READY) return -EIO;
1781 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1782 }
1783 }
d855497e
MI		 1784 return 0;
1785}
1786
1787
1788int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1789{
681c7399 1790 int fl;
d855497e 1791 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1792 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1793 hdw->desired_stream_type = config;
1794 hdw->state_pipeline_config = 0;
1795 trace_stbit("state_pipeline_config",
1796 hdw->state_pipeline_config);
1797 pvr2_hdw_state_sched(hdw);
1798 }
d855497e 1799 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1800 if (fl) return 0;
1801 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1802}
1803
1804
1805static int get_default_tuner_type(struct pvr2_hdw *hdw)
1806{
1807 int unit_number = hdw->unit_number;
1808 int tp = -1;
1809 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1810 tp = tuner[unit_number];
1811 }
1812 if (tp < 0) return -EINVAL;
1813 hdw->tuner_type = tp;
aaf7884d 1814 hdw->tuner_updated = !0;
d855497e
MI		 1815 return 0;
1816}
1817
1818
1819static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1820{
1821 int unit_number = hdw->unit_number;
1822 int tp = 0;
1823 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1824 tp = video_std[unit_number];
6a540254 1825 if (tp) return tp;
d855497e 1826 }
6a540254 1827 return 0;
d855497e
MI		 1828}
1829
1830
1831static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1832{
1833 int unit_number = hdw->unit_number;
1834 int tp = 0;
1835 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1836 tp = tolerance[unit_number];
1837 }
1838 return tp;
1839}
1840
1841
1842static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1843{
1844 /* Try a harmless request to fetch the eeprom's address over
1845 endpoint 1. See what happens. Only the full FX2 image can
1846 respond to this. If this probe fails then likely the FX2
1847 firmware needs be loaded. */
1848 int result;
1849 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1850 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1851 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1852 hdw->cmd_buffer,1,
1853 hdw->cmd_buffer,1);
1854 if (result < 0) break;
1855 } while(0); LOCK_GIVE(hdw->ctl_lock);
1856 if (result) {
1857 pvr2_trace(PVR2_TRACE_INIT,
1858 "Probe of device endpoint 1 result status %d",
1859 result);
1860 } else {
1861 pvr2_trace(PVR2_TRACE_INIT,
1862 "Probe of device endpoint 1 succeeded");
1863 }
1864 return result == 0;
1865}
1866
9f66d4ea
MI		 1867struct pvr2_std_hack {
1868 v4l2_std_id pat; /* Pattern to match */
1869 v4l2_std_id msk; /* Which bits we care about */
1870 v4l2_std_id std; /* What additional standards or default to set */
1871};
1872
1873/* This data structure labels specific combinations of standards from
1874 tveeprom that we'll try to recognize. If we recognize one, then assume
1875 a specified default standard to use. This is here because tveeprom only
1876 tells us about available standards not the intended default standard (if
1877 any) for the device in question. We guess the default based on what has
1878 been reported as available. Note that this is only for guessing a
1879 default - which can always be overridden explicitly - and if the user
1880 has otherwise named a default then that default will always be used in
1881 place of this table. */
ebff0330 1882static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1883 { /* PAL(B/G) */
1884 .pat = V4L2_STD_B|V4L2_STD_GH,
1885 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1886 },
1887 { /* NTSC(M) */
1888 .pat = V4L2_STD_MN,
1889 .std = V4L2_STD_NTSC_M,
1890 },
1891 { /* PAL(I) */
1892 .pat = V4L2_STD_PAL_I,
1893 .std = V4L2_STD_PAL_I,
1894 },
1895 { /* SECAM(L/L') */
1896 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1897 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1898 },
1899 { /* PAL(D/D1/K) */
1900 .pat = V4L2_STD_DK,
ea2562d9 1901 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1902 },
1903};
1904
d855497e
MI		 1905static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1906{
1907 char buf[40];
1908 unsigned int bcnt;
3d290bdb 1909 v4l2_std_id std1,std2,std3;
d855497e
MI		 1910
1911 std1 = get_default_standard(hdw);
3d290bdb 1912 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1913
1914 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1915 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1916 "Supported video standard(s) reported available"
1917 " in hardware: %.*s",
d855497e
MI		 1918 bcnt,buf);
1919
1920 hdw->std_mask_avail = hdw->std_mask_eeprom;
1921
3d290bdb 1922 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1923 if (std2) {
1924 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1925 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1926 "Expanding supported video standards"
1927 " to include: %.*s",
1928 bcnt,buf);
1929 hdw->std_mask_avail |= std2;
1930 }
1931
1932 pvr2_hdw_internal_set_std_avail(hdw);
1933
1934 if (std1) {
1935 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1936 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1937 "Initial video standard forced to %.*s",
1938 bcnt,buf);
1939 hdw->std_mask_cur = std1;
1940 hdw->std_dirty = !0;
1941 pvr2_hdw_internal_find_stdenum(hdw);
1942 return;
1943 }
3d290bdb
MI		 1944 if (std3) {
1945 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1946 pvr2_trace(PVR2_TRACE_STD,
1947 "Initial video standard"
1948 " (determined by device type): %.*s",bcnt,buf);
1949 hdw->std_mask_cur = std3;
1950 hdw->std_dirty = !0;
1951 pvr2_hdw_internal_find_stdenum(hdw);
1952 return;
1953 }
d855497e 1954
9f66d4ea
MI		 1955 {
1956 unsigned int idx;
1957 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1958 if (std_eeprom_maps[idx].msk ?
1959 ((std_eeprom_maps[idx].pat ^
1960 hdw->std_mask_eeprom) &
1961 std_eeprom_maps[idx].msk) :
1962 (std_eeprom_maps[idx].pat !=
1963 hdw->std_mask_eeprom)) continue;
1964 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1965 std_eeprom_maps[idx].std);
56585386 1966 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1967 "Initial video standard guessed as %.*s",
1968 bcnt,buf);
1969 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1970 hdw->std_dirty = !0;
1971 pvr2_hdw_internal_find_stdenum(hdw);
1972 return;
1973 }
1974 }
1975
d855497e
MI		 1976 if (hdw->std_enum_cnt > 1) {
1977 // Autoselect the first listed standard
1978 hdw->std_enum_cur = 1;
1979 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1980 hdw->std_dirty = !0;
56585386 1981 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1982 "Initial video standard auto-selected to %s",
1983 hdw->std_defs[hdw->std_enum_cur-1].name);
1984 return;
1985 }
1986
0885ba1d 1987 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1988 "Unable to select a viable initial video standard");
1989}
1990
1991
e9c64a78
MI		 1992static unsigned int pvr2_copy_i2c_addr_list(
1993 unsigned short *dst, const unsigned char *src,
1994 unsigned int dst_max)
1995{
3ab8d295 1996 unsigned int cnt = 0;
e9c64a78
MI		 1997 if (!src) return 0;
1998 while (src[cnt] && (cnt + 1) < dst_max) {
1999 dst[cnt] = src[cnt];
2000 cnt++;
2001 }
2002 dst[cnt] = I2C_CLIENT_END;
2003 return cnt;
2004}
2005
2006
e17d787c
MI		 2007static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2008{
2009 /*
2010 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2011 for cx25840 causes that module to correctly set up its video
2012 scaling. This is really a problem in the cx25840 module itself,
2013 but we work around it here. The problem has not been seen in
2014 ivtv because there VBI is supported and set up. We don't do VBI
2015 here (at least not yet) and thus we never attempted to even set
2016 it up.
2017 */
2018 struct v4l2_format fmt;
2019 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2020 /* We're not using a cx25840 so don't enable the hack */
2021 return;
2022 }
2023
2024 pvr2_trace(PVR2_TRACE_INIT,
2025 "Module ID %u:"
2026 " Executing cx25840 VBI hack",
2027 hdw->decoder_client_id);
2028 memset(&fmt, 0, sizeof(fmt));
2029 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2030 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
09419af3 2031 vbi, s_sliced_fmt, &fmt.fmt.sliced);
e17d787c
MI		 2032}
2033
2034
1ab5e74f
MI		 2035static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2036 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 2037{
2038 const char *fname;
2039 unsigned char mid;
2040 struct v4l2_subdev *sd;
2041 unsigned int i2ccnt;
2042 const unsigned char *p;
2043 /* Arbitrary count - max # i2c addresses we will probe */
2044 unsigned short i2caddr[25];
2045
2046 mid = cd->module_id;
2047 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2048 if (!fname) {
2049 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2050 "Module ID %u for device %s has no name?"
2051 " The driver might have a configuration problem.",
e9c64a78
MI		 2052 mid,
2053 hdw->hdw_desc->description);
1ab5e74f 2054 return -EINVAL;
e9c64a78 2055 }
bd14d4f8
MI		 2056 pvr2_trace(PVR2_TRACE_INIT,
2057 "Module ID %u (%s) for device %s being loaded...",
2058 mid, fname,
2059 hdw->hdw_desc->description);
e9c64a78
MI		 2060
2061 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2062 ARRAY_SIZE(i2caddr));
2063 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2064 module_i2c_addresses[mid] : NULL) != NULL)) {
2065 /* Second chance: Try default i2c address list */
2066 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2067 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2068 if (i2ccnt) {
2069 pvr2_trace(PVR2_TRACE_INIT,
2070 "Module ID %u:"
2071 " Using default i2c address list",
2072 mid);
2073 }
e9c64a78
MI		 2074 }
2075
2076 if (!i2ccnt) {
2077 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2078 "Module ID %u (%s) for device %s:"
27108147
MI		 2079 " No i2c addresses."
2080 " The driver might have a configuration problem.",
1ab5e74f
MI		 2081 mid, fname, hdw->hdw_desc->description);
2082 return -EINVAL;
e9c64a78
MI		 2083 }
2084
53dacb15
HV		 2085 /* Note how the 2nd and 3rd arguments are the same for
2086 * v4l2_i2c_new_subdev(). Why?
e9c64a78
MI		 2087 * Well the 2nd argument is the module name to load, while the 3rd
2088 * argument is documented in the framework as being the "chipid" -
2089 * and every other place where I can find examples of this, the
2090 * "chipid" appears to just be the module name again. So here we
2091 * just do the same thing. */
2092 if (i2ccnt == 1) {
bd14d4f8
MI		 2093 pvr2_trace(PVR2_TRACE_INIT,
2094 "Module ID %u:"
2095 " Setting up with specified i2c address 0x%x",
2096 mid, i2caddr[0]);
e6574f2f 2097 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78 2098 fname, fname,
53dacb15 2099 i2caddr[0], NULL);
e9c64a78 2100 } else {
bd14d4f8
MI		 2101 pvr2_trace(PVR2_TRACE_INIT,
2102 "Module ID %u:"
2103 " Setting up with address probe list",
2104 mid);
53dacb15 2105 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
e9c64a78 2106 fname, fname,
53dacb15 2107 0, i2caddr);
e9c64a78
MI		 2108 }
2109
446dfdc6
MI		 2110 if (!sd) {
2111 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2112 "Module ID %u (%s) for device %s failed to load."
2113 " Possible missing sub-device kernel module or"
2114 " initialization failure within module.",
1ab5e74f
MI		 2115 mid, fname, hdw->hdw_desc->description);
2116 return -EIO;
446dfdc6
MI		 2117 }
2118
2119 /* Tag this sub-device instance with the module ID we know about.
2120 In other places we'll use that tag to determine if the instance
2121 requires special handling. */
2122 sd->grp_id = mid;
2123
bd14d4f8 2124 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2125
e9c64a78 2126
00e5f736
MI		 2127 /* client-specific setup... */
2128 switch (mid) {
2129 case PVR2_CLIENT_ID_CX25840:
00e5f736
MI		 2130 case PVR2_CLIENT_ID_SAA7115:
2131 hdw->decoder_client_id = mid;
2132 break;
2133 default: break;
2134 }
1ab5e74f
MI		 2135
2136 return 0;
e9c64a78
MI		 2137}
2138
2139
2140static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2141{
2142 unsigned int idx;
2143 const struct pvr2_string_table *cm;
2144 const struct pvr2_device_client_table *ct;
1ab5e74f 2145 int okFl = !0;
e9c64a78
MI		 2146
2147 cm = &hdw->hdw_desc->client_modules;
2148 for (idx = 0; idx < cm->cnt; idx++) {
2149 request_module(cm->lst[idx]);
2150 }
2151
2152 ct = &hdw->hdw_desc->client_table;
2153 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2154 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2155 }
27108147
MI		 2156 if (!okFl) {
2157 hdw->flag_modulefail = !0;
2158 pvr2_hdw_render_useless(hdw);
2159 }
e9c64a78
MI		 2160}
2161
2162
d855497e
MI		 2163static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2164{
2165 int ret;
2166 unsigned int idx;
2167 struct pvr2_ctrl *cptr;
2168 int reloadFl = 0;
989eb154 2169 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2170 if (!reloadFl) {
2171 reloadFl =
2172 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2173 == 0);
2174 if (reloadFl) {
2175 pvr2_trace(PVR2_TRACE_INIT,
2176 "USB endpoint config looks strange"
2177 "; possibly firmware needs to be"
2178 " loaded");
2179 }
d855497e 2180 }
1d643a37
MI		 2181 if (!reloadFl) {
2182 reloadFl = !pvr2_hdw_check_firmware(hdw);
2183 if (reloadFl) {
2184 pvr2_trace(PVR2_TRACE_INIT,
2185 "Check for FX2 firmware failed"
2186 "; possibly firmware needs to be"
2187 " loaded");
2188 }
d855497e 2189 }
1d643a37
MI		 2190 if (reloadFl) {
2191 if (pvr2_upload_firmware1(hdw) != 0) {
2192 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2193 "Failure uploading firmware1");
2194 }
2195 return;
d855497e 2196 }
d855497e
MI		 2197 }
2198 hdw->fw1_state = FW1_STATE_OK;
2199
d855497e
MI		 2200 if (!pvr2_hdw_dev_ok(hdw)) return;
2201
27764726
MI		 2202 hdw->force_dirty = !0;
2203
989eb154 2204 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2205 pvr2_hdw_cmd_powerup(hdw);
2206 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2207 }
2208
31335b13 2209 /* Take the IR chip out of reset, if appropriate */
27eab384 2210 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
31335b13
MI		 2211 pvr2_issue_simple_cmd(hdw,
2212 FX2CMD_HCW_ZILOG_RESET |
2213 (1 << 8) |
2214 ((0) << 16));
2215 }
2216
d855497e
MI		 2217 // This step MUST happen after the earlier powerup step.
2218 pvr2_i2c_core_init(hdw);
2219 if (!pvr2_hdw_dev_ok(hdw)) return;
2220
e9c64a78 2221 pvr2_hdw_load_modules(hdw);
1ab5e74f 2222 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2223
cc26b076 2224 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2225
c05c0462 2226 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2227 cptr = hdw->controls + idx;
2228 if (cptr->info->skip_init) continue;
2229 if (!cptr->info->set_value) continue;
2230 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2231 }
2232
e17d787c
MI		 2233 pvr2_hdw_cx25840_vbi_hack(hdw);
2234
1bde0289
MI		 2235 /* Set up special default values for the television and radio
2236 frequencies here. It's not really important what these defaults
2237 are, but I set them to something usable in the Chicago area just
2238 to make driver testing a little easier. */
2239
5a4f5da6
MK		 2240 hdw->freqValTelevision = default_tv_freq;
2241 hdw->freqValRadio = default_radio_freq;
1bde0289 2242
d855497e
MI		 2243 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2244 // thread-safe against the normal pvr2_send_request() mechanism.
2245 // (We should make it thread safe).
2246
aaf7884d
MI		 2247 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2248 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2249 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2250 if (ret < 0) {
2251 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2252 "Unable to determine location of eeprom,"
2253 " skipping");
2254 } else {
2255 hdw->eeprom_addr = ret;
2256 pvr2_eeprom_analyze(hdw);
2257 if (!pvr2_hdw_dev_ok(hdw)) return;
2258 }
2259 } else {
2260 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2261 hdw->tuner_updated = !0;
2262 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2263 }
2264
13a88797
MI		 2265 if (hdw->serial_number) {
2266 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2267 "sn-%lu", hdw->serial_number);
2268 } else if (hdw->unit_number >= 0) {
2269 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2270 "unit-%c",
2271 hdw->unit_number + 'a');
2272 } else {
2273 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2274 "unit-??");
2275 }
2276 hdw->identifier[idx] = 0;
2277
d855497e
MI		 2278 pvr2_hdw_setup_std(hdw);
2279
2280 if (!get_default_tuner_type(hdw)) {
2281 pvr2_trace(PVR2_TRACE_INIT,
2282 "pvr2_hdw_setup: Tuner type overridden to %d",
2283 hdw->tuner_type);
2284 }
2285
d855497e
MI		 2286
2287 if (!pvr2_hdw_dev_ok(hdw)) return;
2288
1df59f0b
MI		 2289 if (hdw->hdw_desc->signal_routing_scheme ==
2290 PVR2_ROUTING_SCHEME_GOTVIEW) {
2291 /* Ensure that GPIO 11 is set to output for GOTVIEW
2292 hardware. */
2293 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2294 }
2295
681c7399 2296 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2297
2298 hdw->vid_stream = pvr2_stream_create();
2299 if (!pvr2_hdw_dev_ok(hdw)) return;
2300 pvr2_trace(PVR2_TRACE_INIT,
2301 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2302 if (hdw->vid_stream) {
2303 idx = get_default_error_tolerance(hdw);
2304 if (idx) {
2305 pvr2_trace(PVR2_TRACE_INIT,
2306 "pvr2_hdw_setup: video stream %p"
2307 " setting tolerance %u",
2308 hdw->vid_stream,idx);
2309 }
2310 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2311 PVR2_VID_ENDPOINT,idx);
2312 }
2313
2314 if (!pvr2_hdw_dev_ok(hdw)) return;
2315
d855497e 2316 hdw->flag_init_ok = !0;
681c7399
MI		 2317
2318 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2319}
2320
2321
681c7399
MI		 2322/* Set up the structure and attempt to put the device into a usable state.
2323 This can be a time-consuming operation, which is why it is not done
2324 internally as part of the create() step. */
2325static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2326{
2327 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2328 do {
d855497e
MI		 2329 pvr2_hdw_setup_low(hdw);
2330 pvr2_trace(PVR2_TRACE_INIT,
2331 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2332 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2333 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2334 if (hdw->flag_init_ok) {
d855497e
MI		 2335 pvr2_trace(
2336 PVR2_TRACE_INFO,
2337 "Device initialization"
2338 " completed successfully.");
2339 break;
2340 }
2341 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2342 pvr2_trace(
2343 PVR2_TRACE_INFO,
2344 "Device microcontroller firmware"
2345 " (re)loaded; it should now reset"
2346 " and reconnect.");
2347 break;
2348 }
2349 pvr2_trace(
2350 PVR2_TRACE_ERROR_LEGS,
2351 "Device initialization was not successful.");
2352 if (hdw->fw1_state == FW1_STATE_MISSING) {
2353 pvr2_trace(
2354 PVR2_TRACE_ERROR_LEGS,
2355 "Giving up since device"
2356 " microcontroller firmware"
2357 " appears to be missing.");
2358 break;
2359 }
2360 }
27108147
MI		 2361 if (hdw->flag_modulefail) {
2362 pvr2_trace(
2363 PVR2_TRACE_ERROR_LEGS,
2364 "***WARNING*** pvrusb2 driver initialization"
2365 " failed due to the failure of one or more"
2366 " sub-device kernel modules.");
2367 pvr2_trace(
2368 PVR2_TRACE_ERROR_LEGS,
2369 "You need to resolve the failing condition"
2370 " before this driver can function. There"
2371 " should be some earlier messages giving more"
2372 " information about the problem.");
515ebf79 2373 break;
27108147 2374 }
d855497e
MI		 2375 if (procreload) {
2376 pvr2_trace(
2377 PVR2_TRACE_ERROR_LEGS,
2378 "Attempting pvrusb2 recovery by reloading"
2379 " primary firmware.");
2380 pvr2_trace(
2381 PVR2_TRACE_ERROR_LEGS,
2382 "If this works, device should disconnect"
2383 " and reconnect in a sane state.");
2384 hdw->fw1_state = FW1_STATE_UNKNOWN;
2385 pvr2_upload_firmware1(hdw);
2386 } else {
2387 pvr2_trace(
2388 PVR2_TRACE_ERROR_LEGS,
2389 "***WARNING*** pvrusb2 device hardware"
2390 " appears to be jammed"
2391 " and I can't clear it.");
2392 pvr2_trace(
2393 PVR2_TRACE_ERROR_LEGS,
2394 "You might need to power cycle"
2395 " the pvrusb2 device"
2396 " in order to recover.");
2397 }
681c7399 2398 } while (0);
d855497e 2399 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2400}
2401
2402
c4a8828d
MI		 2403/* Perform second stage initialization. Set callback pointer first so that
2404 we can avoid a possible initialization race (if the kernel thread runs
2405 before the callback has been set). */
794b1607
MI		 2406int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2407 void (*callback_func)(void *),
2408 void *callback_data)
c4a8828d
MI		 2409{
2410 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2411 if (hdw->flag_disconnected) {
2412 /* Handle a race here: If we're already
2413 disconnected by this point, then give up. If we
2414 get past this then we'll remain connected for
2415 the duration of initialization since the entire
2416 initialization sequence is now protected by the
2417 big_lock. */
2418 break;
2419 }
c4a8828d
MI		 2420 hdw->state_data = callback_data;
2421 hdw->state_func = callback_func;
97f26ff6 2422 pvr2_hdw_setup(hdw);
c4a8828d 2423 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2424 return hdw->flag_init_ok;
c4a8828d
MI		 2425}
2426
2427
2428/* Create, set up, and return a structure for interacting with the
2429 underlying hardware. */
d855497e
MI		 2430struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2431 const struct usb_device_id *devid)
2432{
7fb20fa3 2433 unsigned int idx,cnt1,cnt2,m;
fe15f136 2434 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2435 int valid_std_mask;
2436 struct pvr2_ctrl *cptr;
b72b7bf5 2437 struct usb_device *usb_dev;
989eb154 2438 const struct pvr2_device_desc *hdw_desc;
d855497e 2439 __u8 ifnum;
b30d2441
MI		 2440 struct v4l2_queryctrl qctrl;
2441 struct pvr2_ctl_info *ciptr;
d855497e 2442
b72b7bf5
MI		 2443 usb_dev = interface_to_usbdev(intf);
2444
d130fa8a 2445 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2446
fe15f136
MI		 2447 if (hdw_desc == NULL) {
2448 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2449 " No device description pointer,"
2450 " unable to continue.");
2451 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2452 " please contact Mike Isely <isely@pobox.com>"
2453 " to get it included in the driver\n");
2454 goto fail;
2455 }
2456
ca545f7c 2457 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2458 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2459 hdw,hdw_desc->description);
e67e376b 2460 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
00970beb 2461 hdw_desc->description);
8fd04448
MI		 2462 if (hdw_desc->flag_is_experimental) {
2463 pvr2_trace(PVR2_TRACE_INFO, "**********");
2464 pvr2_trace(PVR2_TRACE_INFO,
2465 "WARNING: Support for this device (%s) is"
2466 " experimental.", hdw_desc->description);
2467 pvr2_trace(PVR2_TRACE_INFO,
2468 "Important functionality might not be"
2469 " entirely working.");
2470 pvr2_trace(PVR2_TRACE_INFO,
2471 "Please consider contacting the driver author to"
2472 " help with further stabilization of the driver.");
2473 pvr2_trace(PVR2_TRACE_INFO, "**********");
2474 }
d855497e 2475 if (!hdw) goto fail;
681c7399
MI		 2476
2477 init_timer(&hdw->quiescent_timer);
2478 hdw->quiescent_timer.data = (unsigned long)hdw;
2479 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2480
6e931375
MI		 2481 init_timer(&hdw->decoder_stabilization_timer);
2482 hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2483 hdw->decoder_stabilization_timer.function =
2484 pvr2_hdw_decoder_stabilization_timeout;
2485
681c7399
MI		 2486 init_timer(&hdw->encoder_wait_timer);
2487 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2488 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2489
d913d630
MI		 2490 init_timer(&hdw->encoder_run_timer);
2491 hdw->encoder_run_timer.data = (unsigned long)hdw;
2492 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2493
681c7399
MI		 2494 hdw->master_state = PVR2_STATE_DEAD;
2495
2496 init_waitqueue_head(&hdw->state_wait_data);
2497
18103c57 2498 hdw->tuner_signal_stale = !0;
b30d2441 2499 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2500
7fb20fa3
MI		 2501 /* Calculate which inputs are OK */
2502 m = 0;
2503 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2504 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2505 m |= 1 << PVR2_CVAL_INPUT_DTV;
2506 }
7fb20fa3
MI		 2507 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2508 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2509 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2510 hdw->input_avail_mask = m;
1cb03b76 2511 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2512
62433e31
MI		 2513 /* If not a hybrid device, pathway_state never changes. So
2514 initialize it here to what it should forever be. */
2515 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2516 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2517 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2518 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2519 }
2520
c05c0462 2521 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2522 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2523 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2524 GFP_KERNEL);
2525 if (!hdw->controls) goto fail;
989eb154 2526 hdw->hdw_desc = hdw_desc;
27eab384 2527 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
c05c0462
MI		 2528 for (idx = 0; idx < hdw->control_cnt; idx++) {
2529 cptr = hdw->controls + idx;
2530 cptr->hdw = hdw;
2531 }
d855497e
MI		 2532 for (idx = 0; idx < 32; idx++) {
2533 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2534 }
c05c0462 2535 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2536 cptr = hdw->controls + idx;
d855497e
MI		 2537 cptr->info = control_defs+idx;
2538 }
dbc40a0e
MI		 2539
2540 /* Ensure that default input choice is a valid one. */
2541 m = hdw->input_avail_mask;
2542 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2543 if (!((1 << idx) & m)) continue;
2544 hdw->input_val = idx;
2545 break;
2546 }
2547
b30d2441 2548 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2549 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2550 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2551 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2552 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2553 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2554 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2555 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2556 ciptr->name = mpeg_ids[idx].strid;
2557 ciptr->v4l_id = mpeg_ids[idx].id;
2558 ciptr->skip_init = !0;
2559 ciptr->get_value = ctrl_cx2341x_get;
2560 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2561 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2562 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2563 qctrl.id = ciptr->v4l_id;
2564 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2565 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2566 ciptr->set_value = ctrl_cx2341x_set;
2567 }
2568 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2569 PVR2_CTLD_INFO_DESC_SIZE);
2570 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2571 ciptr->default_value = qctrl.default_value;
2572 switch (qctrl.type) {
2573 default:
2574 case V4L2_CTRL_TYPE_INTEGER:
2575 ciptr->type = pvr2_ctl_int;
2576 ciptr->def.type_int.min_value = qctrl.minimum;
2577 ciptr->def.type_int.max_value = qctrl.maximum;
2578 break;
2579 case V4L2_CTRL_TYPE_BOOLEAN:
2580 ciptr->type = pvr2_ctl_bool;
2581 break;
2582 case V4L2_CTRL_TYPE_MENU:
2583 ciptr->type = pvr2_ctl_enum;
2584 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2585 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2586 ciptr->v4l_id);
b30d2441
MI		 2587 for (cnt1 = 0;
2588 ciptr->def.type_enum.value_names[cnt1] != NULL;
2589 cnt1++) { }
2590 ciptr->def.type_enum.count = cnt1;
2591 break;
2592 }
2593 cptr->info = ciptr;
2594 }
d855497e
MI		 2595
2596 // Initialize video standard enum dynamic control
2597 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2598 if (cptr) {
2599 memcpy(&hdw->std_info_enum,cptr->info,
2600 sizeof(hdw->std_info_enum));
2601 cptr->info = &hdw->std_info_enum;
2602
2603 }
2604 // Initialize control data regarding video standard masks
2605 valid_std_mask = pvr2_std_get_usable();
2606 for (idx = 0; idx < 32; idx++) {
2607 if (!(valid_std_mask & (1 << idx))) continue;
2608 cnt1 = pvr2_std_id_to_str(
2609 hdw->std_mask_names[idx],
2610 sizeof(hdw->std_mask_names[idx])-1,
2611 1 << idx);
2612 hdw->std_mask_names[idx][cnt1] = 0;
2613 }
2614 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2615 if (cptr) {
2616 memcpy(&hdw->std_info_avail,cptr->info,
2617 sizeof(hdw->std_info_avail));
2618 cptr->info = &hdw->std_info_avail;
2619 hdw->std_info_avail.def.type_bitmask.bit_names =
2620 hdw->std_mask_ptrs;
2621 hdw->std_info_avail.def.type_bitmask.valid_bits =
2622 valid_std_mask;
2623 }
2624 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2625 if (cptr) {
2626 memcpy(&hdw->std_info_cur,cptr->info,
2627 sizeof(hdw->std_info_cur));
2628 cptr->info = &hdw->std_info_cur;
2629 hdw->std_info_cur.def.type_bitmask.bit_names =
2630 hdw->std_mask_ptrs;
2631 hdw->std_info_avail.def.type_bitmask.valid_bits =
2632 valid_std_mask;
2633 }
2634
432907f7 2635 hdw->cropcap_stale = !0;
d855497e
MI		 2636 hdw->eeprom_addr = -1;
2637 hdw->unit_number = -1;
8079384e
MI		 2638 hdw->v4l_minor_number_video = -1;
2639 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2640 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2641 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2642 if (!hdw->ctl_write_buffer) goto fail;
2643 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2644 if (!hdw->ctl_read_buffer) goto fail;
2645 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2646 if (!hdw->ctl_write_urb) goto fail;
2647 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2648 if (!hdw->ctl_read_urb) goto fail;
2649
70ad6383 2650 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2651 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2652 "Error registering with v4l core, giving up");
2653 goto fail;
2654 }
8df0c87c 2655 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2656 for (idx = 0; idx < PVR_NUM; idx++) {
2657 if (unit_pointers[idx]) continue;
2658 hdw->unit_number = idx;
2659 unit_pointers[idx] = hdw;
2660 break;
2661 }
8df0c87c 2662 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2663
2664 cnt1 = 0;
2665 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2666 cnt1 += cnt2;
2667 if (hdw->unit_number >= 0) {
2668 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2669 ('a' + hdw->unit_number));
2670 cnt1 += cnt2;
2671 }
2672 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2673 hdw->name[cnt1] = 0;
2674
681c7399
MI		 2675 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2676 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2677
d855497e
MI		 2678 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2679 hdw->unit_number,hdw->name);
2680
2681 hdw->tuner_type = -1;
2682 hdw->flag_ok = !0;
d855497e
MI		 2683
2684 hdw->usb_intf = intf;
b72b7bf5 2685 hdw->usb_dev = usb_dev;
d855497e 2686
87e3495c 2687 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2688
d855497e
MI		 2689 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2690 usb_set_interface(hdw->usb_dev,ifnum,0);
2691
2692 mutex_init(&hdw->ctl_lock_mutex);
2693 mutex_init(&hdw->big_lock_mutex);
2694
2695 return hdw;
2696 fail:
2697 if (hdw) {
681c7399 2698 del_timer_sync(&hdw->quiescent_timer);
6e931375 2699 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2700 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2701 del_timer_sync(&hdw->encoder_wait_timer);
2702 if (hdw->workqueue) {
2703 flush_workqueue(hdw->workqueue);
2704 destroy_workqueue(hdw->workqueue);
2705 hdw->workqueue = NULL;
2706 }
5e55d2ce
MK		 2707 usb_free_urb(hdw->ctl_read_urb);
2708 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2709 kfree(hdw->ctl_read_buffer);
2710 kfree(hdw->ctl_write_buffer);
2711 kfree(hdw->controls);
2712 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2713 kfree(hdw->std_defs);
2714 kfree(hdw->std_enum_names);
d855497e
MI		 2715 kfree(hdw);
2716 }
a0fd1cb1 2717 return NULL;
d855497e
MI		 2718}
2719
2720
2721/* Remove _all_ associations between this driver and the underlying USB
2722 layer. */
07e337ee 2723static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2724{
2725 if (hdw->flag_disconnected) return;
2726 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2727 if (hdw->ctl_read_urb) {
2728 usb_kill_urb(hdw->ctl_read_urb);
2729 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2730 hdw->ctl_read_urb = NULL;
d855497e
MI		 2731 }
2732 if (hdw->ctl_write_urb) {
2733 usb_kill_urb(hdw->ctl_write_urb);
2734 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2735 hdw->ctl_write_urb = NULL;
d855497e
MI		 2736 }
2737 if (hdw->ctl_read_buffer) {
2738 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2739 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2740 }
2741 if (hdw->ctl_write_buffer) {
2742 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2743 hdw->ctl_write_buffer = NULL;
d855497e 2744 }
d855497e 2745 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2746 /* If we don't do this, then there will be a dangling struct device
2747 reference to our disappearing device persisting inside the V4L
2748 core... */
dc070bcc 2749 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2750 hdw->usb_dev = NULL;
2751 hdw->usb_intf = NULL;
681c7399 2752 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2753}
2754
2755
2756/* Destroy hardware interaction structure */
2757void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2758{
401c27ce 2759 if (!hdw) return;
d855497e 2760 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2761 if (hdw->workqueue) {
2762 flush_workqueue(hdw->workqueue);
2763 destroy_workqueue(hdw->workqueue);
2764 hdw->workqueue = NULL;
2765 }
8f59100a 2766 del_timer_sync(&hdw->quiescent_timer);
6e931375 2767 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2768 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2769 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2770 if (hdw->fw_buffer) {
2771 kfree(hdw->fw_buffer);
a0fd1cb1 2772 hdw->fw_buffer = NULL;
d855497e
MI		 2773 }
2774 if (hdw->vid_stream) {
2775 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2776 hdw->vid_stream = NULL;
d855497e 2777 }
d855497e 2778 pvr2_i2c_core_done(hdw);
b72b7bf5 2779 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2780 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2781 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2782 if ((hdw->unit_number >= 0) &&
2783 (hdw->unit_number < PVR_NUM) &&
2784 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2785 unit_pointers[hdw->unit_number] = NULL;
d855497e 2786 }
8df0c87c 2787 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2788 kfree(hdw->controls);
2789 kfree(hdw->mpeg_ctrl_info);
2790 kfree(hdw->std_defs);
2791 kfree(hdw->std_enum_names);
d855497e
MI		 2792 kfree(hdw);
2793}
2794
2795
d855497e
MI		 2796int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2797{
2798 return (hdw && hdw->flag_ok);
2799}
2800
2801
2802/* Called when hardware has been unplugged */
2803void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2804{
2805 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2806 LOCK_TAKE(hdw->big_lock);
2807 LOCK_TAKE(hdw->ctl_lock);
2808 pvr2_hdw_remove_usb_stuff(hdw);
2809 LOCK_GIVE(hdw->ctl_lock);
2810 LOCK_GIVE(hdw->big_lock);
2811}
2812
2813
2814// Attempt to autoselect an appropriate value for std_enum_cur given
2815// whatever is currently in std_mask_cur
07e337ee 2816static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2817{
2818 unsigned int idx;
2819 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2820 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2821 hdw->std_enum_cur = idx;
2822 return;
2823 }
2824 }
2825 hdw->std_enum_cur = 0;
2826}
2827
2828
2829// Calculate correct set of enumerated standards based on currently known
2830// set of available standards bits.
07e337ee 2831static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2832{
2833 struct v4l2_standard *newstd;
2834 unsigned int std_cnt;
2835 unsigned int idx;
2836
2837 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2838
2839 if (hdw->std_defs) {
2840 kfree(hdw->std_defs);
a0fd1cb1 2841 hdw->std_defs = NULL;
d855497e
MI		 2842 }
2843 hdw->std_enum_cnt = 0;
2844 if (hdw->std_enum_names) {
2845 kfree(hdw->std_enum_names);
a0fd1cb1 2846 hdw->std_enum_names = NULL;
d855497e
MI		 2847 }
2848
2849 if (!std_cnt) {
2850 pvr2_trace(
2851 PVR2_TRACE_ERROR_LEGS,
2852 "WARNING: Failed to identify any viable standards");
2853 }
2854 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2855 hdw->std_enum_names[0] = "none";
2856 for (idx = 0; idx < std_cnt; idx++) {
2857 hdw->std_enum_names[idx+1] =
2858 newstd[idx].name;
2859 }
2860 // Set up the dynamic control for this standard
2861 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2862 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2863 hdw->std_defs = newstd;
2864 hdw->std_enum_cnt = std_cnt+1;
2865 hdw->std_enum_cur = 0;
2866 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2867}
2868
2869
2870int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2871 struct v4l2_standard *std,
2872 unsigned int idx)
2873{
2874 int ret = -EINVAL;
2875 if (!idx) return ret;
2876 LOCK_TAKE(hdw->big_lock); do {
2877 if (idx >= hdw->std_enum_cnt) break;
2878 idx--;
2879 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2880 ret = 0;
2881 } while (0); LOCK_GIVE(hdw->big_lock);
2882 return ret;
2883}
2884
2885
2886/* Get the number of defined controls */
2887unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2888{
c05c0462 2889 return hdw->control_cnt;
d855497e
MI		 2890}
2891
2892
2893/* Retrieve a control handle given its index (0..count-1) */
2894struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2895 unsigned int idx)
2896{
a0fd1cb1 2897 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2898 return hdw->controls + idx;
2899}
2900
2901
2902/* Retrieve a control handle given its index (0..count-1) */
2903struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2904 unsigned int ctl_id)
2905{
2906 struct pvr2_ctrl *cptr;
2907 unsigned int idx;
2908 int i;
2909
2910 /* This could be made a lot more efficient, but for now... */
c05c0462 2911 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2912 cptr = hdw->controls + idx;
2913 i = cptr->info->internal_id;
2914 if (i && (i == ctl_id)) return cptr;
2915 }
a0fd1cb1 2916 return NULL;
d855497e
MI		 2917}
2918
2919
a761f431 2920/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2921struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2922{
2923 struct pvr2_ctrl *cptr;
2924 unsigned int idx;
2925 int i;
2926
2927 /* This could be made a lot more efficient, but for now... */
c05c0462 2928 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2929 cptr = hdw->controls + idx;
2930 i = cptr->info->v4l_id;
2931 if (i && (i == ctl_id)) return cptr;
2932 }
a0fd1cb1 2933 return NULL;
d855497e
MI		 2934}
2935
2936
a761f431
MI		 2937/* Given a V4L ID for its immediate predecessor, retrieve the control
2938 structure associated with it. */
2939struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2940 unsigned int ctl_id)
2941{
2942 struct pvr2_ctrl *cptr,*cp2;
2943 unsigned int idx;
2944 int i;
2945
2946 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2947 cp2 = NULL;
a761f431
MI		 2948 for (idx = 0; idx < hdw->control_cnt; idx++) {
2949 cptr = hdw->controls + idx;
2950 i = cptr->info->v4l_id;
2951 if (!i) continue;
2952 if (i <= ctl_id) continue;
2953 if (cp2 && (cp2->info->v4l_id < i)) continue;
2954 cp2 = cptr;
2955 }
2956 return cp2;
a0fd1cb1 2957 return NULL;
a761f431
MI		 2958}
2959
2960
d855497e
MI		 2961static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2962{
2963 switch (tp) {
2964 case pvr2_ctl_int: return "integer";
2965 case pvr2_ctl_enum: return "enum";
33213963 2966 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2967 case pvr2_ctl_bitmask: return "bitmask";
2968 }
2969 return "";
2970}
2971
2972
2641df36
MI		 2973static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2974 const char *name, int val)
2975{
2976 struct v4l2_control ctrl;
2977 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2978 memset(&ctrl, 0, sizeof(ctrl));
2979 ctrl.id = id;
2980 ctrl.value = val;
2981 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2982}
2983
2984#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2985 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2986 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2987 }
2988
5ceaad14 2989/* Execute whatever commands are required to update the state of all the
2641df36 2990 sub-devices so that they match our current control values. */
5ceaad14
MI		 2991static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2992{
edb9dcb8
MI		 2993 struct v4l2_subdev *sd;
2994 unsigned int id;
2995 pvr2_subdev_update_func fp;
2996
75212a02
MI		 2997 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2998
27764726 2999 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 3000 struct tuner_setup setup;
3001 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
3002 hdw->tuner_type);
3003 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 3004 memset(&setup, 0, sizeof(setup));
75212a02
MI		 3005 setup.addr = ADDR_UNSET;
3006 setup.type = hdw->tuner_type;
3007 setup.mode_mask = T_RADIO | T_ANALOG_TV;
3008 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3009 tuner, s_type_addr, &setup);
3010 }
3011 }
3012
27764726 3013 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 3014 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 3015 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3016 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3017 tuner, s_radio);
3018 } else {
3019 v4l2_std_id vs;
3020 vs = hdw->std_mask_cur;
3021 v4l2_device_call_all(&hdw->v4l2_dev, 0,
f41737ec 3022 core, s_std, vs);
a6862da2 3023 pvr2_hdw_cx25840_vbi_hack(hdw);
2641df36
MI		 3024 }
3025 hdw->tuner_signal_stale = !0;
3026 hdw->cropcap_stale = !0;
3027 }
3028
3029 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3030 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3031 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3032 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3033 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3034 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3035 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3036 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3037 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3038
27764726 3039 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 3040 struct v4l2_tuner vt;
3041 memset(&vt, 0, sizeof(vt));
3042 vt.audmode = hdw->audiomode_val;
3043 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3044 }
3045
27764726 3046 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 3047 unsigned long fv;
3048 struct v4l2_frequency freq;
3049 fv = pvr2_hdw_get_cur_freq(hdw);
3050 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3051 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3052 memset(&freq, 0, sizeof(freq));
3053 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3054 /* ((fv * 1000) / 62500) */
3055 freq.frequency = (fv * 2) / 125;
3056 } else {
3057 freq.frequency = fv / 62500;
3058 }
3059 /* tuner-core currently doesn't seem to care about this, but
3060 let's set it anyway for completeness. */
3061 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3062 freq.type = V4L2_TUNER_RADIO;
3063 } else {
3064 freq.type = V4L2_TUNER_ANALOG_TV;
3065 }
3066 freq.tuner = 0;
3067 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3068 s_frequency, &freq);
3069 }
3070
27764726 3071 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
fa190ee9 3072 struct v4l2_mbus_framefmt fmt;
2641df36 3073 memset(&fmt, 0, sizeof(fmt));
fa190ee9
HV		 3074 fmt.width = hdw->res_hor_val;
3075 fmt.height = hdw->res_ver_val;
3076 fmt.code = V4L2_MBUS_FMT_FIXED;
7dfdf1ee 3077 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
fa190ee9
HV		 3078 fmt.width, fmt.height);
3079 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_mbus_fmt, &fmt);
2641df36
MI		 3080 }
3081
27764726 3082 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3083 u32 val;
3084 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3085 hdw->srate_val);
3086 switch (hdw->srate_val) {
3087 default:
3088 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3089 val = 48000;
3090 break;
3091 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3092 val = 44100;
3093 break;
3094 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3095 val = 32000;
3096 break;
3097 }
3098 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3099 audio, s_clock_freq, val);
3100 }
3101
2641df36
MI		 3102 /* Unable to set crop parameters; there is apparently no equivalent
3103 for VIDIOC_S_CROP */
3104
edb9dcb8
MI		 3105 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3106 id = sd->grp_id;
3107 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3108 fp = pvr2_module_update_functions[id];
3109 if (!fp) continue;
3110 (*fp)(hdw, sd);
3111 }
2641df36 3112
27764726 3113 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3114 pvr2_hdw_status_poll(hdw);
3115 }
5ceaad14
MI		 3116}
3117
3118
681c7399
MI		 3119/* Figure out if we need to commit control changes. If so, mark internal
3120 state flags to indicate this fact and return true. Otherwise do nothing
3121 else and return false. */
3122static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3123{
d855497e
MI		 3124 unsigned int idx;
3125 struct pvr2_ctrl *cptr;
3126 int value;
27764726 3127 int commit_flag = hdw->force_dirty;
d855497e
MI		 3128 char buf[100];
3129 unsigned int bcnt,ccnt;
3130
c05c0462 3131 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3132 cptr = hdw->controls + idx;
5fa1247a 3133 if (!cptr->info->is_dirty) continue;
d855497e 3134 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3135 commit_flag = !0;
d855497e 3136
fe23a280 3137 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3138 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3139 cptr->info->name);
3140 value = 0;
3141 cptr->info->get_value(cptr,&value);
3142 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3143 buf+bcnt,
3144 sizeof(buf)-bcnt,&ccnt);
3145 bcnt += ccnt;
3146 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3147 get_ctrl_typename(cptr->info->type));
3148 pvr2_trace(PVR2_TRACE_CTL,
3149 "/*--TRACE_COMMIT--*/ %.*s",
3150 bcnt,buf);
3151 }
3152
3153 if (!commit_flag) {
3154 /* Nothing has changed */
3155 return 0;
3156 }
3157
681c7399
MI		 3158 hdw->state_pipeline_config = 0;
3159 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3160 pvr2_hdw_state_sched(hdw);
3161
3162 return !0;
3163}
3164
3165
3166/* Perform all operations needed to commit all control changes. This must
3167 be performed in synchronization with the pipeline state and is thus
3168 expected to be called as part of the driver's worker thread. Return
3169 true if commit successful, otherwise return false to indicate that
3170 commit isn't possible at this time. */
3171static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3172{
3173 unsigned int idx;
3174 struct pvr2_ctrl *cptr;
3175 int disruptive_change;
3176
ab062fe3
MI		 3177 /* Handle some required side effects when the video standard is
3178 changed.... */
d855497e 3179 if (hdw->std_dirty) {
d855497e 3180 int nvres;
00528d9c 3181 int gop_size;
d855497e
MI		 3182 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3183 nvres = 480;
00528d9c 3184 gop_size = 15;
d855497e
MI		 3185 } else {
3186 nvres = 576;
00528d9c 3187 gop_size = 12;
d855497e 3188 }
00528d9c
MI		 3189 /* Rewrite the vertical resolution to be appropriate to the
3190 video standard that has been selected. */
d855497e
MI		 3191 if (nvres != hdw->res_ver_val) {
3192 hdw->res_ver_val = nvres;
3193 hdw->res_ver_dirty = !0;
3194 }
00528d9c
MI		 3195 /* Rewrite the GOP size to be appropriate to the video
3196 standard that has been selected. */
3197 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3198 struct v4l2_ext_controls cs;
3199 struct v4l2_ext_control c1;
3200 memset(&cs, 0, sizeof(cs));
3201 memset(&c1, 0, sizeof(c1));
3202 cs.controls = &c1;
3203 cs.count = 1;
3204 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3205 c1.value = gop_size;
3206 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3207 VIDIOC_S_EXT_CTRLS);
3208 }
d855497e
MI		 3209 }
3210
38d9a2cf 3211 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3212 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3213 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3214 hdw->pathway_state)) {
3215 /* Change of mode being asked for... */
3216 hdw->state_pathway_ok = 0;
e9db1ff2 3217 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3218 }
3219 if (!hdw->state_pathway_ok) {
3220 /* Can't commit anything until pathway is ok. */
3221 return 0;
3222 }
e784bfb9 3223 /* The broadcast decoder can only scale down, so if
3224 * res_*_dirty && crop window < output format ==> enlarge crop.
3225 *
3226 * The mpeg encoder receives fields of res_hor_val dots and
3227 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3228 */
3229 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3230 hdw->cropw_val = hdw->res_hor_val;
3231 hdw->cropw_dirty = !0;
3232 } else if (hdw->cropw_dirty) {
3233 hdw->res_hor_dirty = !0; /* must rescale */
3234 hdw->res_hor_val = min(720, hdw->cropw_val);
3235 }
3236 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3237 hdw->croph_val = hdw->res_ver_val;
3238 hdw->croph_dirty = !0;
3239 } else if (hdw->croph_dirty) {
3240 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3241 hdw->res_ver_dirty = !0;
3242 hdw->res_ver_val = min(nvres, hdw->croph_val);
3243 }
3244
681c7399
MI		 3245 /* If any of the below has changed, then we can't do the update
3246 while the pipeline is running. Pipeline must be paused first
3247 and decoder -> encoder connection be made quiescent before we
3248 can proceed. */
3249 disruptive_change =
3250 (hdw->std_dirty ||
3251 hdw->enc_unsafe_stale ||
3252 hdw->srate_dirty ||
3253 hdw->res_ver_dirty ||
3254 hdw->res_hor_dirty ||
755879c6
MI		 3255 hdw->cropw_dirty ||
3256 hdw->croph_dirty ||
681c7399
MI		 3257 hdw->input_dirty ||
3258 (hdw->active_stream_type != hdw->desired_stream_type));
3259 if (disruptive_change && !hdw->state_pipeline_idle) {
3260 /* Pipeline is not idle; we can't proceed. Arrange to
3261 cause pipeline to stop so that we can try this again
3262 later.... */
3263 hdw->state_pipeline_pause = !0;
3264 return 0;
275b2e28
PK		 3265 }
3266
b30d2441
MI		 3267 if (hdw->srate_dirty) {
3268 /* Write new sample rate into control structure since
3269 * the master copy is stale. We must track srate
3270 * separate from the mpeg control structure because
3271 * other logic also uses this value. */
3272 struct v4l2_ext_controls cs;
3273 struct v4l2_ext_control c1;
3274 memset(&cs,0,sizeof(cs));
3275 memset(&c1,0,sizeof(c1));
3276 cs.controls = &c1;
3277 cs.count = 1;
3278 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3279 c1.value = hdw->srate_val;
01f1e44f 3280 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3281 }
c05c0462 3282
681c7399
MI		 3283 if (hdw->active_stream_type != hdw->desired_stream_type) {
3284 /* Handle any side effects of stream config here */
3285 hdw->active_stream_type = hdw->desired_stream_type;
3286 }
3287
1df59f0b
MI		 3288 if (hdw->hdw_desc->signal_routing_scheme ==
3289 PVR2_ROUTING_SCHEME_GOTVIEW) {
3290 u32 b;
3291 /* Handle GOTVIEW audio switching */
3292 pvr2_hdw_gpio_get_out(hdw,&b);
3293 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3294 /* Set GPIO 11 */
3295 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3296 } else {
3297 /* Clear GPIO 11 */
3298 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3299 }
3300 }
3301
e68a619a
MI		 3302 /* Check and update state for all sub-devices. */
3303 pvr2_subdev_update(hdw);
3304
75212a02 3305 hdw->tuner_updated = 0;
27764726 3306 hdw->force_dirty = 0;
5ceaad14
MI		 3307 for (idx = 0; idx < hdw->control_cnt; idx++) {
3308 cptr = hdw->controls + idx;
3309 if (!cptr->info->clear_dirty) continue;
3310 cptr->info->clear_dirty(cptr);
3311 }
3312
62433e31
MI		 3313 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3314 hdw->state_encoder_run) {
3315 /* If encoder isn't running or it can't be touched, then
3316 this will get worked out later when we start the
3317 encoder. */
681c7399
MI		 3318 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3319 }
d855497e 3320
681c7399 3321 hdw->state_pipeline_config = !0;
432907f7
MI		 3322 /* Hardware state may have changed in a way to cause the cropping
3323 capabilities to have changed. So mark it stale, which will
3324 cause a later re-fetch. */
681c7399
MI		 3325 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3326 return !0;
d855497e
MI		 3327}
3328
3329
3330int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3331{
681c7399
MI		 3332 int fl;
3333 LOCK_TAKE(hdw->big_lock);
3334 fl = pvr2_hdw_commit_setup(hdw);
3335 LOCK_GIVE(hdw->big_lock);
3336 if (!fl) return 0;
3337 return pvr2_hdw_wait(hdw,0);
3338}
3339
3340
681c7399 3341static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3342{
681c7399
MI		 3343 int fl = 0;
3344 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3345 LOCK_TAKE(hdw->big_lock); do {
681c7399 3346 fl = pvr2_hdw_state_eval(hdw);
d855497e 3347 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3348 if (fl && hdw->state_func) {
3349 hdw->state_func(hdw->state_data);
3350 }
d855497e
MI		 3351}
3352
3353
681c7399 3354static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3355{
681c7399
MI		 3356 return wait_event_interruptible(
3357 hdw->state_wait_data,
3358 (hdw->state_stale == 0) &&
3359 (!state || (hdw->master_state != state)));
3360}
3361
3362
d855497e
MI		 3363/* Return name for this driver instance */
3364const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3365{
3366 return hdw->name;
3367}
3368
3369
78a47101
MI		 3370const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3371{
3372 return hdw->hdw_desc->description;
3373}
3374
3375
3376const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3377{
3378 return hdw->hdw_desc->shortname;
3379}
3380
3381
d855497e
MI		 3382int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3383{
3384 int result;
3385 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3386 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3387 result = pvr2_send_request(hdw,
3388 hdw->cmd_buffer,1,
3389 hdw->cmd_buffer,1);
3390 if (result < 0) break;
3391 result = (hdw->cmd_buffer[0] != 0);
3392 } while(0); LOCK_GIVE(hdw->ctl_lock);
3393 return result;
3394}
3395
3396
18103c57
MI		 3397/* Execute poll of tuner status */
3398void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3399{
d855497e 3400 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3401 pvr2_hdw_status_poll(hdw);
d855497e 3402 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3403}
3404
3405
432907f7
MI		 3406static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3407{
3408 if (!hdw->cropcap_stale) {
432907f7
MI		 3409 return 0;
3410 }
a51f5000 3411 pvr2_hdw_status_poll(hdw);
432907f7 3412 if (hdw->cropcap_stale) {
432907f7
MI		 3413 return -EIO;
3414 }
3415 return 0;
3416}
3417
3418
3419/* Return information about cropping capabilities */
3420int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3421{
3422 int stat = 0;
3423 LOCK_TAKE(hdw->big_lock);
3424 stat = pvr2_hdw_check_cropcap(hdw);
3425 if (!stat) {
432907f7
MI		 3426 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3427 }
3428 LOCK_GIVE(hdw->big_lock);
3429 return stat;
3430}
3431
3432
18103c57
MI		 3433/* Return information about the tuner */
3434int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3435{
3436 LOCK_TAKE(hdw->big_lock); do {
3437 if (hdw->tuner_signal_stale) {
a51f5000 3438 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3439 }
3440 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3441 } while (0); LOCK_GIVE(hdw->big_lock);
3442 return 0;
d855497e
MI		 3443}
3444
3445
3446/* Get handle to video output stream */
3447struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3448{
3449 return hp->vid_stream;
3450}
3451
3452
3453void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3454{
4f1a3e5b 3455 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3456 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3457 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3458 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3459 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3460 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3461 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3462 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3463 } while (0); LOCK_GIVE(hdw->big_lock);
3464}
3465
4db666cc
MI		 3466
3467/* Grab EEPROM contents, needed for direct method. */
3468#define EEPROM_SIZE 8192
3469#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3470static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3471{
3472 struct i2c_msg msg[2];
3473 u8 *eeprom;
3474 u8 iadd[2];
3475 u8 addr;
3476 u16 eepromSize;
3477 unsigned int offs;
3478 int ret;
3479 int mode16 = 0;
3480 unsigned pcnt,tcnt;
3481 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3482 if (!eeprom) {
3483 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3484 "Failed to allocate memory"
3485 " required to read eeprom");
3486 return NULL;
3487 }
3488
3489 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3490 hdw->eeprom_addr);
3491 addr = hdw->eeprom_addr;
3492 /* Seems that if the high bit is set, then the *real* eeprom
3493 address is shifted right now bit position (noticed this in
3494 newer PVR USB2 hardware) */
3495 if (addr & 0x80) addr >>= 1;
3496
3497 /* FX2 documentation states that a 16bit-addressed eeprom is
3498 expected if the I2C address is an odd number (yeah, this is
3499 strange but it's what they do) */
3500 mode16 = (addr & 1);
3501 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3502 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3503 " using %d bit addressing",eepromSize,addr,
3504 mode16 ? 16 : 8);
3505
3506 msg[0].addr = addr;
3507 msg[0].flags = 0;
3508 msg[0].len = mode16 ? 2 : 1;
3509 msg[0].buf = iadd;
3510 msg[1].addr = addr;
3511 msg[1].flags = I2C_M_RD;
3512
3513 /* We have to do the actual eeprom data fetch ourselves, because
3514 (1) we're only fetching part of the eeprom, and (2) if we were
3515 getting the whole thing our I2C driver can't grab it in one
3516 pass - which is what tveeprom is otherwise going to attempt */
3517 memset(eeprom,0,EEPROM_SIZE);
3518 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3519 pcnt = 16;
3520 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3521 offs = tcnt + (eepromSize - EEPROM_SIZE);
3522 if (mode16) {
3523 iadd[0] = offs >> 8;
3524 iadd[1] = offs;
3525 } else {
3526 iadd[0] = offs;
3527 }
3528 msg[1].len = pcnt;
3529 msg[1].buf = eeprom+tcnt;
3530 if ((ret = i2c_transfer(&hdw->i2c_adap,
3531 msg,ARRAY_SIZE(msg))) != 2) {
3532 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3533 "eeprom fetch set offs err=%d",ret);
3534 kfree(eeprom);
3535 return NULL;
3536 }
3537 }
3538 return eeprom;
3539}
3540
3541
3542void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
568efaa2 3543 int mode,
4db666cc 3544 int enable_flag)
d855497e
MI		 3545{
3546 int ret;
3547 u16 address;
3548 unsigned int pipe;
3549 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3550 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3551
3552 if (!enable_flag) {
3553 pvr2_trace(PVR2_TRACE_FIRMWARE,
3554 "Cleaning up after CPU firmware fetch");
3555 kfree(hdw->fw_buffer);
a0fd1cb1 3556 hdw->fw_buffer = NULL;
d855497e 3557 hdw->fw_size = 0;
4db666cc
MI		 3558 if (hdw->fw_cpu_flag) {
3559 /* Now release the CPU. It will disconnect
3560 and reconnect later. */
3561 pvr2_hdw_cpureset_assert(hdw,0);
3562 }
d855497e
MI		 3563 break;
3564 }
3565
568efaa2 3566 hdw->fw_cpu_flag = (mode != 2);
4db666cc 3567 if (hdw->fw_cpu_flag) {
568efaa2 3568 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
4db666cc 3569 pvr2_trace(PVR2_TRACE_FIRMWARE,
568efaa2
MI		 3570 "Preparing to suck out CPU firmware"
3571 " (size=%u)", hdw->fw_size);
4db666cc
MI		 3572 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3573 if (!hdw->fw_buffer) {
3574 hdw->fw_size = 0;
3575 break;
3576 }
d855497e 3577
4db666cc
MI		 3578 /* We have to hold the CPU during firmware upload. */
3579 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3580
4db666cc
MI		 3581 /* download the firmware from address 0000-1fff in 2048
3582 (=0x800) bytes chunk. */
d855497e 3583
4db666cc
MI		 3584 pvr2_trace(PVR2_TRACE_FIRMWARE,
3585 "Grabbing CPU firmware");
3586 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3587 for(address = 0; address < hdw->fw_size;
3588 address += 0x800) {
3589 ret = usb_control_msg(hdw->usb_dev,pipe,
3590 0xa0,0xc0,
3591 address,0,
3592 hdw->fw_buffer+address,
3593 0x800,HZ);
3594 if (ret < 0) break;
3595 }
d855497e 3596
4db666cc
MI		 3597 pvr2_trace(PVR2_TRACE_FIRMWARE,
3598 "Done grabbing CPU firmware");
3599 } else {
3600 pvr2_trace(PVR2_TRACE_FIRMWARE,
3601 "Sucking down EEPROM contents");
3602 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3603 if (!hdw->fw_buffer) {
3604 pvr2_trace(PVR2_TRACE_FIRMWARE,
3605 "EEPROM content suck failed.");
3606 break;
3607 }
3608 hdw->fw_size = EEPROM_SIZE;
3609 pvr2_trace(PVR2_TRACE_FIRMWARE,
3610 "Done sucking down EEPROM contents");
3611 }
d855497e
MI		 3612
3613 } while (0); LOCK_GIVE(hdw->big_lock);
3614}
3615
3616
3617/* Return true if we're in a mode for retrieval CPU firmware */
3618int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3619{
5fa1247a 3620 return hdw->fw_buffer != NULL;
d855497e
MI		 3621}
3622
3623
3624int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3625 char *buf,unsigned int cnt)
3626{
3627 int ret = -EINVAL;
3628 LOCK_TAKE(hdw->big_lock); do {
3629 if (!buf) break;
3630 if (!cnt) break;
3631
3632 if (!hdw->fw_buffer) {
3633 ret = -EIO;
3634 break;
3635 }
3636
3637 if (offs >= hdw->fw_size) {
3638 pvr2_trace(PVR2_TRACE_FIRMWARE,
3639 "Read firmware data offs=%d EOF",
3640 offs);
3641 ret = 0;
3642 break;
3643 }
3644
3645 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3646
3647 memcpy(buf,hdw->fw_buffer+offs,cnt);
3648
3649 pvr2_trace(PVR2_TRACE_FIRMWARE,
3650 "Read firmware data offs=%d cnt=%d",
3651 offs,cnt);
3652 ret = cnt;
3653 } while (0); LOCK_GIVE(hdw->big_lock);
3654
3655 return ret;
3656}
3657
3658
fd5a75fe 3659int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3660 enum pvr2_v4l_type index)
d855497e 3661{
fd5a75fe 3662 switch (index) {
8079384e
MI		 3663 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3664 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3665 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3666 default: return -1;
3667 }
d855497e
MI		 3668}
3669
3670
2fdf3d9c 3671/* Store a v4l minor device number */
fd5a75fe 3672void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3673 enum pvr2_v4l_type index,int v)
d855497e 3674{
fd5a75fe 3675 switch (index) {
8079384e
MI		 3676 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3677 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3678 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3679 default: break;
3680 }
d855497e
MI		 3681}
3682
3683
7d12e780 3684static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3685{
3686 struct pvr2_hdw *hdw = urb->context;
3687 hdw->ctl_write_pend_flag = 0;
3688 if (hdw->ctl_read_pend_flag) return;
3689 complete(&hdw->ctl_done);
3690}
3691
3692
7d12e780 3693static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3694{
3695 struct pvr2_hdw *hdw = urb->context;
3696 hdw->ctl_read_pend_flag = 0;
3697 if (hdw->ctl_write_pend_flag) return;
3698 complete(&hdw->ctl_done);
3699}
3700
3701
3702static void pvr2_ctl_timeout(unsigned long data)
3703{
3704 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3705 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3706 hdw->ctl_timeout_flag = !0;
5e55d2ce 3707 if (hdw->ctl_write_pend_flag)
d855497e 3708 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3709 if (hdw->ctl_read_pend_flag)
d855497e 3710 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3711 }
3712}
3713
3714
e61b6fc5
MI		 3715/* Issue a command and get a response from the device. This extended
3716 version includes a probe flag (which if set means that device errors
3717 should not be logged or treated as fatal) and a timeout in jiffies.
3718 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3719static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3720 unsigned int timeout,int probe_fl,
3721 void *write_data,unsigned int write_len,
3722 void *read_data,unsigned int read_len)
d855497e
MI		 3723{
3724 unsigned int idx;
3725 int status = 0;
3726 struct timer_list timer;
3727 if (!hdw->ctl_lock_held) {
3728 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3729 "Attempted to execute control transfer"
3730 " without lock!!");
3731 return -EDEADLK;
3732 }
681c7399 3733 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3734 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3735 "Attempted to execute control transfer"
3736 " when device not ok");
3737 return -EIO;
3738 }
3739 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3740 if (!probe_fl) {
3741 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3742 "Attempted to execute control transfer"
3743 " when USB is disconnected");
3744 }
3745 return -ENOTTY;
3746 }
3747
3748 /* Ensure that we have sane parameters */
3749 if (!write_data) write_len = 0;
3750 if (!read_data) read_len = 0;
3751 if (write_len > PVR2_CTL_BUFFSIZE) {
3752 pvr2_trace(
3753 PVR2_TRACE_ERROR_LEGS,
3754 "Attempted to execute %d byte"
3755 " control-write transfer (limit=%d)",
3756 write_len,PVR2_CTL_BUFFSIZE);
3757 return -EINVAL;
3758 }
3759 if (read_len > PVR2_CTL_BUFFSIZE) {
3760 pvr2_trace(
3761 PVR2_TRACE_ERROR_LEGS,
3762 "Attempted to execute %d byte"
3763 " control-read transfer (limit=%d)",
3764 write_len,PVR2_CTL_BUFFSIZE);
3765 return -EINVAL;
3766 }
3767 if ((!write_len) && (!read_len)) {
3768 pvr2_trace(
3769 PVR2_TRACE_ERROR_LEGS,
3770 "Attempted to execute null control transfer?");
3771 return -EINVAL;
3772 }
3773
3774
3775 hdw->cmd_debug_state = 1;
3776 if (write_len) {
3777 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3778 } else {
3779 hdw->cmd_debug_code = 0;
3780 }
3781 hdw->cmd_debug_write_len = write_len;
3782 hdw->cmd_debug_read_len = read_len;
3783
3784 /* Initialize common stuff */
3785 init_completion(&hdw->ctl_done);
3786 hdw->ctl_timeout_flag = 0;
3787 hdw->ctl_write_pend_flag = 0;
3788 hdw->ctl_read_pend_flag = 0;
3789 init_timer(&timer);
3790 timer.expires = jiffies + timeout;
3791 timer.data = (unsigned long)hdw;
3792 timer.function = pvr2_ctl_timeout;
3793
3794 if (write_len) {
3795 hdw->cmd_debug_state = 2;
3796 /* Transfer write data to internal buffer */
3797 for (idx = 0; idx < write_len; idx++) {
3798 hdw->ctl_write_buffer[idx] =
3799 ((unsigned char *)write_data)[idx];
3800 }
3801 /* Initiate a write request */
3802 usb_fill_bulk_urb(hdw->ctl_write_urb,
3803 hdw->usb_dev,
3804 usb_sndbulkpipe(hdw->usb_dev,
3805 PVR2_CTL_WRITE_ENDPOINT),
3806 hdw->ctl_write_buffer,
3807 write_len,
3808 pvr2_ctl_write_complete,
3809 hdw);
3810 hdw->ctl_write_urb->actual_length = 0;
3811 hdw->ctl_write_pend_flag = !0;
3812 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3813 if (status < 0) {
3814 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3815 "Failed to submit write-control"
3816 " URB status=%d",status);
3817 hdw->ctl_write_pend_flag = 0;
3818 goto done;
3819 }
3820 }
3821
3822 if (read_len) {
3823 hdw->cmd_debug_state = 3;
3824 memset(hdw->ctl_read_buffer,0x43,read_len);
3825 /* Initiate a read request */
3826 usb_fill_bulk_urb(hdw->ctl_read_urb,
3827 hdw->usb_dev,
3828 usb_rcvbulkpipe(hdw->usb_dev,
3829 PVR2_CTL_READ_ENDPOINT),
3830 hdw->ctl_read_buffer,
3831 read_len,
3832 pvr2_ctl_read_complete,
3833 hdw);
3834 hdw->ctl_read_urb->actual_length = 0;
3835 hdw->ctl_read_pend_flag = !0;
3836 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3837 if (status < 0) {
3838 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3839 "Failed to submit read-control"
3840 " URB status=%d",status);
3841 hdw->ctl_read_pend_flag = 0;
3842 goto done;
3843 }
3844 }
3845
3846 /* Start timer */
3847 add_timer(&timer);
3848
3849 /* Now wait for all I/O to complete */
3850 hdw->cmd_debug_state = 4;
3851 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3852 wait_for_completion(&hdw->ctl_done);
3853 }
3854 hdw->cmd_debug_state = 5;
3855
3856 /* Stop timer */
3857 del_timer_sync(&timer);
3858
3859 hdw->cmd_debug_state = 6;
3860 status = 0;
3861
3862 if (hdw->ctl_timeout_flag) {
3863 status = -ETIMEDOUT;
3864 if (!probe_fl) {
3865 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3866 "Timed out control-write");
3867 }
3868 goto done;
3869 }
3870
3871 if (write_len) {
3872 /* Validate results of write request */
3873 if ((hdw->ctl_write_urb->status != 0) &&
3874 (hdw->ctl_write_urb->status != -ENOENT) &&
3875 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3876 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3877 /* USB subsystem is reporting some kind of failure
3878 on the write */
3879 status = hdw->ctl_write_urb->status;
3880 if (!probe_fl) {
3881 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3882 "control-write URB failure,"
3883 " status=%d",
3884 status);
3885 }
3886 goto done;
3887 }
3888 if (hdw->ctl_write_urb->actual_length < write_len) {
3889 /* Failed to write enough data */
3890 status = -EIO;
3891 if (!probe_fl) {
3892 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3893 "control-write URB short,"
3894 " expected=%d got=%d",
3895 write_len,
3896 hdw->ctl_write_urb->actual_length);
3897 }
3898 goto done;
3899 }
3900 }
3901 if (read_len) {
3902 /* Validate results of read request */
3903 if ((hdw->ctl_read_urb->status != 0) &&
3904 (hdw->ctl_read_urb->status != -ENOENT) &&
3905 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3906 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3907 /* USB subsystem is reporting some kind of failure
3908 on the read */
3909 status = hdw->ctl_read_urb->status;
3910 if (!probe_fl) {
3911 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3912 "control-read URB failure,"
3913 " status=%d",
3914 status);
3915 }
3916 goto done;
3917 }
3918 if (hdw->ctl_read_urb->actual_length < read_len) {
3919 /* Failed to read enough data */
3920 status = -EIO;
3921 if (!probe_fl) {
3922 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3923 "control-read URB short,"
3924 " expected=%d got=%d",
3925 read_len,
3926 hdw->ctl_read_urb->actual_length);
3927 }
3928 goto done;
3929 }
3930 /* Transfer retrieved data out from internal buffer */
3931 for (idx = 0; idx < read_len; idx++) {
3932 ((unsigned char *)read_data)[idx] =
3933 hdw->ctl_read_buffer[idx];
3934 }
3935 }
3936
3937 done:
3938
3939 hdw->cmd_debug_state = 0;
3940 if ((status < 0) && (!probe_fl)) {
681c7399 3941 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3942 }
3943 return status;
3944}
3945
3946
3947int pvr2_send_request(struct pvr2_hdw *hdw,
3948 void *write_data,unsigned int write_len,
3949 void *read_data,unsigned int read_len)
3950{
3951 return pvr2_send_request_ex(hdw,HZ*4,0,
3952 write_data,write_len,
3953 read_data,read_len);
3954}
3955
1c9d10d4
MI		 3956
3957static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3958{
3959 int ret;
3960 unsigned int cnt = 1;
3961 unsigned int args = 0;
3962 LOCK_TAKE(hdw->ctl_lock);
3963 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3964 args = (cmdcode >> 8) & 0xffu;
3965 args = (args > 2) ? 2 : args;
3966 if (args) {
3967 cnt += args;
3968 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3969 if (args > 1) {
3970 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3971 }
3972 }
3973 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3974 unsigned int idx;
3975 unsigned int ccnt,bcnt;
3976 char tbuf[50];
3977 cmdcode &= 0xffu;
3978 bcnt = 0;
3979 ccnt = scnprintf(tbuf+bcnt,
3980 sizeof(tbuf)-bcnt,
3981 "Sending FX2 command 0x%x",cmdcode);
3982 bcnt += ccnt;
3983 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3984 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3985 ccnt = scnprintf(tbuf+bcnt,
3986 sizeof(tbuf)-bcnt,
3987 " \"%s\"",
3988 pvr2_fx2cmd_desc[idx].desc);
3989 bcnt += ccnt;
3990 break;
3991 }
3992 }
3993 if (args) {
3994 ccnt = scnprintf(tbuf+bcnt,
3995 sizeof(tbuf)-bcnt,
3996 " (%u",hdw->cmd_buffer[1]);
3997 bcnt += ccnt;
3998 if (args > 1) {
3999 ccnt = scnprintf(tbuf+bcnt,
4000 sizeof(tbuf)-bcnt,
4001 ",%u",hdw->cmd_buffer[2]);
4002 bcnt += ccnt;
4003 }
4004 ccnt = scnprintf(tbuf+bcnt,
4005 sizeof(tbuf)-bcnt,
4006 ")");
4007 bcnt += ccnt;
4008 }
4009 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
4010 }
4011 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
4012 LOCK_GIVE(hdw->ctl_lock);
4013 return ret;
4014}
4015
4016
d855497e
MI		 4017int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
4018{
4019 int ret;
4020
4021 LOCK_TAKE(hdw->ctl_lock);
4022
8d364363 4023 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 4024 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4025 hdw->cmd_buffer[5] = 0;
4026 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4027 hdw->cmd_buffer[7] = reg & 0xff;
4028
4029
4030 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4031
4032 LOCK_GIVE(hdw->ctl_lock);
4033
4034 return ret;
4035}
4036
4037
07e337ee 4038static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 4039{
4040 int ret = 0;
4041
4042 LOCK_TAKE(hdw->ctl_lock);
4043
8d364363 4044 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 4045 hdw->cmd_buffer[1] = 0;
4046 hdw->cmd_buffer[2] = 0;
4047 hdw->cmd_buffer[3] = 0;
4048 hdw->cmd_buffer[4] = 0;
4049 hdw->cmd_buffer[5] = 0;
4050 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4051 hdw->cmd_buffer[7] = reg & 0xff;
4052
4053 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4054 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4055
4056 LOCK_GIVE(hdw->ctl_lock);
4057
4058 return ret;
4059}
4060
4061
681c7399 4062void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4063{
4064 if (!hdw->flag_ok) return;
681c7399
MI		 4065 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4066 "Device being rendered inoperable");
d855497e 4067 if (hdw->vid_stream) {
a0fd1cb1 4068 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4069 }
681c7399
MI		 4070 hdw->flag_ok = 0;
4071 trace_stbit("flag_ok",hdw->flag_ok);
4072 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4073}
4074
4075
4076void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4077{
4078 int ret;
4079 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4080 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4081 if (ret == 0) {
d855497e
MI		 4082 ret = usb_reset_device(hdw->usb_dev);
4083 usb_unlock_device(hdw->usb_dev);
4084 } else {
4085 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4086 "Failed to lock USB device ret=%d",ret);
4087 }
4088 if (init_pause_msec) {
4089 pvr2_trace(PVR2_TRACE_INFO,
4090 "Waiting %u msec for hardware to settle",
4091 init_pause_msec);
4092 msleep(init_pause_msec);
4093 }
4094
4095}
4096
4097
4098void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4099{
6861800c 4100 char *da;
d855497e
MI		 4101 unsigned int pipe;
4102 int ret;
4103
4104 if (!hdw->usb_dev) return;
4105
6861800c
MI		 4106 da = kmalloc(16, GFP_KERNEL);
4107
4108 if (da == NULL) {
4109 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4110 "Unable to allocate memory to control CPU reset");
4111 return;
4112 }
4113
d855497e
MI		 4114 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4115
4116 da[0] = val ? 0x01 : 0x00;
4117
4118 /* Write the CPUCS register on the 8051. The lsb of the register
4119 is the reset bit; a 1 asserts reset while a 0 clears it. */
4120 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4121 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4122 if (ret < 0) {
4123 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4124 "cpureset_assert(%d) error=%d",val,ret);
4125 pvr2_hdw_render_useless(hdw);
4126 }
6861800c
MI		 4127
4128 kfree(da);
d855497e
MI		 4129}
4130
4131
4132int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4133{
1c9d10d4 4134 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4135}
4136
4137
e1edb19a
MK		 4138int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4139{
1c9d10d4 4140 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4141}
4142
1c9d10d4 4143
e1edb19a
MK		 4144int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4145{
1c9d10d4 4146 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4147}
4148
d855497e
MI		 4149
4150int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4151{
af78e16b
MI		 4152 pvr2_trace(PVR2_TRACE_INIT,
4153 "Requesting decoder reset");
af78e16b
MI		 4154 if (hdw->decoder_client_id) {
4155 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4156 core, reset, 0);
e17d787c 4157 pvr2_hdw_cx25840_vbi_hack(hdw);
af78e16b 4158 return 0;
d855497e 4159 }
d855497e 4160 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4161 "Unable to reset decoder: nothing attached");
4162 return -ENOTTY;
d855497e
MI		 4163}
4164
4165
62433e31 4166static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4167{
1c9d10d4
MI		 4168 hdw->flag_ok = !0;
4169 return pvr2_issue_simple_cmd(hdw,
4170 FX2CMD_HCW_DEMOD_RESETIN |
4171 (1 << 8) |
4172 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4173}
4174
84147f3d 4175
62433e31 4176static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4177{
1c9d10d4
MI		 4178 hdw->flag_ok = !0;
4179 return pvr2_issue_simple_cmd(hdw,(onoff ?
4180 FX2CMD_ONAIR_DTV_POWER_ON :
4181 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4182}
4183
62433e31
MI		 4184
4185static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4186 int onoff)
84147f3d 4187{
1c9d10d4
MI		 4188 return pvr2_issue_simple_cmd(hdw,(onoff ?
4189 FX2CMD_ONAIR_DTV_STREAMING_ON :
4190 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4191}
4192
62433e31
MI		 4193
4194static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4195{
4196 int cmode;
4197 /* Compare digital/analog desired setting with current setting. If
4198 they don't match, fix it... */
4199 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4200 if (cmode == hdw->pathway_state) {
4201 /* They match; nothing to do */
4202 return;
4203 }
4204
4205 switch (hdw->hdw_desc->digital_control_scheme) {
4206 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4207 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4208 if (cmode == PVR2_PATHWAY_ANALOG) {
4209 /* If moving to analog mode, also force the decoder
4210 to reset. If no decoder is attached, then it's
4211 ok to ignore this because if/when the decoder
4212 attaches, it will reset itself at that time. */
4213 pvr2_hdw_cmd_decoder_reset(hdw);
4214 }
4215 break;
4216 case PVR2_DIGITAL_SCHEME_ONAIR:
4217 /* Supposedly we should always have the power on whether in
4218 digital or analog mode. But for now do what appears to
4219 work... */
bb0c2fe0 4220 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4221 break;
4222 default: break;
4223 }
4224
1b9c18c5 4225 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4226 hdw->pathway_state = cmode;
4227}
4228
4229
e9b59f6e 4230static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4231{
4232 /* change some GPIO data
4233 *
4234 * note: bit d7 of dir appears to control the LED,
4235 * so we shut it off here.
4236 *
c55a97d7 4237 */
40381cb0 4238 if (onoff) {
c55a97d7 4239 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4240 } else {
c55a97d7 4241 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4242 }
c55a97d7 4243 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4244}
c55a97d7 4245
40381cb0
MI		 4246
4247typedef void (*led_method_func)(struct pvr2_hdw *,int);
4248
4249static led_method_func led_methods[] = {
4250 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4251};
4252
4253
4254/* Toggle LED */
4255static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4256{
4257 unsigned int scheme_id;
4258 led_method_func fp;
4259
4260 if ((!onoff) == (!hdw->led_on)) return;
4261
4262 hdw->led_on = onoff != 0;
4263
4264 scheme_id = hdw->hdw_desc->led_scheme;
4265 if (scheme_id < ARRAY_SIZE(led_methods)) {
4266 fp = led_methods[scheme_id];
4267 } else {
4268 fp = NULL;
4269 }
4270
4271 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4272}
4273
4274
e61b6fc5 4275/* Stop / start video stream transport */
07e337ee 4276static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4277{
bb0c2fe0
MI		 4278 int ret;
4279
4280 /* If we're in analog mode, then just issue the usual analog
4281 command. */
4282 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4283 return pvr2_issue_simple_cmd(hdw,
4284 (runFl ?
4285 FX2CMD_STREAMING_ON :
4286 FX2CMD_STREAMING_OFF));
4287 /*Note: Not reached */
4288 }
4289
4290 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4291 /* Whoops, we don't know what mode we're in... */
4292 return -EINVAL;
4293 }
4294
4295 /* To get here we have to be in digital mode. The mechanism here
4296 is unfortunately different for different vendors. So we switch
4297 on the device's digital scheme attribute in order to figure out
4298 what to do. */
4299 switch (hdw->hdw_desc->digital_control_scheme) {
4300 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4301 return pvr2_issue_simple_cmd(hdw,
4302 (runFl ?
4303 FX2CMD_HCW_DTV_STREAMING_ON :
4304 FX2CMD_HCW_DTV_STREAMING_OFF));
4305 case PVR2_DIGITAL_SCHEME_ONAIR:
4306 ret = pvr2_issue_simple_cmd(hdw,
4307 (runFl ?
4308 FX2CMD_STREAMING_ON :
4309 FX2CMD_STREAMING_OFF));
4310 if (ret) return ret;
4311 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4312 default:
4313 return -EINVAL;
62433e31 4314 }
d855497e
MI		 4315}
4316
4317
62433e31
MI		 4318/* Evaluate whether or not state_pathway_ok can change */
4319static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4320{
4321 if (hdw->state_pathway_ok) {
4322 /* Nothing to do if pathway is already ok */
4323 return 0;
4324 }
4325 if (!hdw->state_pipeline_idle) {
4326 /* Not allowed to change anything if pipeline is not idle */
4327 return 0;
4328 }
4329 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4330 hdw->state_pathway_ok = !0;
e9db1ff2 4331 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4332 return !0;
4333}
4334
4335
681c7399
MI		 4336/* Evaluate whether or not state_encoder_ok can change */
4337static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4338{
4339 if (hdw->state_encoder_ok) return 0;
4340 if (hdw->flag_tripped) return 0;
4341 if (hdw->state_encoder_run) return 0;
4342 if (hdw->state_encoder_config) return 0;
4343 if (hdw->state_decoder_run) return 0;
4344 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4345 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4346 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4347 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4348 return 0;
4349 }
4350
681c7399
MI		 4351 if (pvr2_upload_firmware2(hdw) < 0) {
4352 hdw->flag_tripped = !0;
4353 trace_stbit("flag_tripped",hdw->flag_tripped);
4354 return !0;
4355 }
4356 hdw->state_encoder_ok = !0;
4357 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4358 return !0;
4359}
4360
4361
4362/* Evaluate whether or not state_encoder_config can change */
4363static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4364{
4365 if (hdw->state_encoder_config) {
4366 if (hdw->state_encoder_ok) {
4367 if (hdw->state_pipeline_req &&
4368 !hdw->state_pipeline_pause) return 0;
4369 }
4370 hdw->state_encoder_config = 0;
4371 hdw->state_encoder_waitok = 0;
4372 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4373 /* paranoia - solve race if timer just completed */
4374 del_timer_sync(&hdw->encoder_wait_timer);
4375 } else {
62433e31
MI		 4376 if (!hdw->state_pathway_ok ||
4377 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4378 !hdw->state_encoder_ok ||
681c7399
MI		 4379 !hdw->state_pipeline_idle ||
4380 hdw->state_pipeline_pause ||
4381 !hdw->state_pipeline_req ||
4382 !hdw->state_pipeline_config) {
4383 /* We must reset the enforced wait interval if
4384 anything has happened that might have disturbed
4385 the encoder. This should be a rare case. */
4386 if (timer_pending(&hdw->encoder_wait_timer)) {
4387 del_timer_sync(&hdw->encoder_wait_timer);
4388 }
4389 if (hdw->state_encoder_waitok) {
4390 /* Must clear the state - therefore we did
4391 something to a state bit and must also
4392 return true. */
4393 hdw->state_encoder_waitok = 0;
4394 trace_stbit("state_encoder_waitok",
4395 hdw->state_encoder_waitok);
4396 return !0;
4397 }
4398 return 0;
4399 }
4400 if (!hdw->state_encoder_waitok) {
4401 if (!timer_pending(&hdw->encoder_wait_timer)) {
4402 /* waitok flag wasn't set and timer isn't
4403 running. Check flag once more to avoid
4404 a race then start the timer. This is
4405 the point when we measure out a minimal
4406 quiet interval before doing something to
4407 the encoder. */
4408 if (!hdw->state_encoder_waitok) {
4409 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4410 jiffies +
4411 (HZ * TIME_MSEC_ENCODER_WAIT
4412 / 1000);
681c7399
MI		 4413 add_timer(&hdw->encoder_wait_timer);
4414 }
4415 }
4416 /* We can't continue until we know we have been
4417 quiet for the interval measured by this
4418 timer. */
4419 return 0;
4420 }
4421 pvr2_encoder_configure(hdw);
4422 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4423 }
4424 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4425 return !0;
4426}
4427
4428
d913d630
MI		 4429/* Return true if the encoder should not be running. */
4430static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4431{
4432 if (!hdw->state_encoder_ok) {
4433 /* Encoder isn't healthy at the moment, so stop it. */
4434 return !0;
4435 }
4436 if (!hdw->state_pathway_ok) {
4437 /* Mode is not understood at the moment (i.e. it wants to
4438 change), so encoder must be stopped. */
4439 return !0;
4440 }
4441
4442 switch (hdw->pathway_state) {
4443 case PVR2_PATHWAY_ANALOG:
4444 if (!hdw->state_decoder_run) {
4445 /* We're in analog mode and the decoder is not
4446 running; thus the encoder should be stopped as
4447 well. */
4448 return !0;
4449 }
4450 break;
4451 case PVR2_PATHWAY_DIGITAL:
4452 if (hdw->state_encoder_runok) {
4453 /* This is a funny case. We're in digital mode so
4454 really the encoder should be stopped. However
4455 if it really is running, only kill it after
4456 runok has been set. This gives a chance for the
4457 onair quirk to function (encoder must run
4458 briefly first, at least once, before onair
4459 digital streaming can work). */
4460 return !0;
4461 }
4462 break;
4463 default:
4464 /* Unknown mode; so encoder should be stopped. */
4465 return !0;
4466 }
4467
4468 /* If we get here, we haven't found a reason to stop the
4469 encoder. */
4470 return 0;
4471}
4472
4473
4474/* Return true if the encoder should be running. */
4475static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4476{
4477 if (!hdw->state_encoder_ok) {
4478 /* Don't run the encoder if it isn't healthy... */
4479 return 0;
4480 }
4481 if (!hdw->state_pathway_ok) {
4482 /* Don't run the encoder if we don't (yet) know what mode
4483 we need to be in... */
4484 return 0;
4485 }
4486
4487 switch (hdw->pathway_state) {
4488 case PVR2_PATHWAY_ANALOG:
6e931375 4489 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
d913d630
MI		 4490 /* In analog mode, if the decoder is running, then
4491 run the encoder. */
4492 return !0;
4493 }
4494 break;
4495 case PVR2_PATHWAY_DIGITAL:
4496 if ((hdw->hdw_desc->digital_control_scheme ==
4497 PVR2_DIGITAL_SCHEME_ONAIR) &&
4498 !hdw->state_encoder_runok) {
4499 /* This is a quirk. OnAir hardware won't stream
4500 digital until the encoder has been run at least
4501 once, for a minimal period of time (empiricially
4502 measured to be 1/4 second). So if we're on
4503 OnAir hardware and the encoder has never been
4504 run at all, then start the encoder. Normal
4505 state machine logic in the driver will
4506 automatically handle the remaining bits. */
4507 return !0;
4508 }
4509 break;
4510 default:
4511 /* For completeness (unknown mode; encoder won't run ever) */
4512 break;
4513 }
4514 /* If we get here, then we haven't found any reason to run the
4515 encoder, so don't run it. */
4516 return 0;
4517}
4518
4519
681c7399
MI		 4520/* Evaluate whether or not state_encoder_run can change */
4521static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4522{
4523 if (hdw->state_encoder_run) {
d913d630 4524 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4525 if (hdw->state_encoder_ok) {
d913d630 4526 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4527 if (pvr2_encoder_stop(hdw) < 0) return !0;
4528 }
4529 hdw->state_encoder_run = 0;
4530 } else {
d913d630 4531 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4532 if (pvr2_encoder_start(hdw) < 0) return !0;
4533 hdw->state_encoder_run = !0;
d913d630
MI		 4534 if (!hdw->state_encoder_runok) {
4535 hdw->encoder_run_timer.expires =
83ce57aa 4536 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4537 add_timer(&hdw->encoder_run_timer);
4538 }
681c7399
MI		 4539 }
4540 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4541 return !0;
4542}
4543
4544
4545/* Timeout function for quiescent timer. */
4546static void pvr2_hdw_quiescent_timeout(unsigned long data)
4547{
4548 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4549 hdw->state_decoder_quiescent = !0;
4550 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4551 hdw->state_stale = !0;
4552 queue_work(hdw->workqueue,&hdw->workpoll);
4553}
4554
4555
6e931375
MI		 4556/* Timeout function for decoder stabilization timer. */
4557static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4558{
4559 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4560 hdw->state_decoder_ready = !0;
4561 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4562 hdw->state_stale = !0;
4563 queue_work(hdw->workqueue, &hdw->workpoll);
4564}
4565
4566
681c7399
MI		 4567/* Timeout function for encoder wait timer. */
4568static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4569{
4570 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4571 hdw->state_encoder_waitok = !0;
4572 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4573 hdw->state_stale = !0;
4574 queue_work(hdw->workqueue,&hdw->workpoll);
4575}
4576
4577
d913d630
MI		 4578/* Timeout function for encoder run timer. */
4579static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4580{
4581 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4582 if (!hdw->state_encoder_runok) {
4583 hdw->state_encoder_runok = !0;
4584 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4585 hdw->state_stale = !0;
4586 queue_work(hdw->workqueue,&hdw->workpoll);
4587 }
4588}
4589
4590
681c7399
MI		 4591/* Evaluate whether or not state_decoder_run can change */
4592static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4593{
4594 if (hdw->state_decoder_run) {
4595 if (hdw->state_encoder_ok) {
4596 if (hdw->state_pipeline_req &&
62433e31
MI		 4597 !hdw->state_pipeline_pause &&
4598 hdw->state_pathway_ok) return 0;
681c7399
MI		 4599 }
4600 if (!hdw->flag_decoder_missed) {
4601 pvr2_decoder_enable(hdw,0);
4602 }
4603 hdw->state_decoder_quiescent = 0;
4604 hdw->state_decoder_run = 0;
6e931375 4605 /* paranoia - solve race if timer(s) just completed */
681c7399 4606 del_timer_sync(&hdw->quiescent_timer);
6e931375
MI		 4607 /* Kill the stabilization timer, in case we're killing the
4608 encoder before the previous stabilization interval has
4609 been properly timed. */
4610 del_timer_sync(&hdw->decoder_stabilization_timer);
4611 hdw->state_decoder_ready = 0;
681c7399
MI		 4612 } else {
4613 if (!hdw->state_decoder_quiescent) {
4614 if (!timer_pending(&hdw->quiescent_timer)) {
4615 /* We don't do something about the
4616 quiescent timer until right here because
4617 we also want to catch cases where the
4618 decoder was already not running (like
4619 after initialization) as opposed to
4620 knowing that we had just stopped it.
4621 The second flag check is here to cover a
4622 race - the timer could have run and set
4623 this flag just after the previous check
4624 but before we did the pending check. */
4625 if (!hdw->state_decoder_quiescent) {
4626 hdw->quiescent_timer.expires =
83ce57aa
MI		 4627 jiffies +
4628 (HZ * TIME_MSEC_DECODER_WAIT
4629 / 1000);
681c7399
MI		 4630 add_timer(&hdw->quiescent_timer);
4631 }
4632 }
4633 /* Don't allow decoder to start again until it has
4634 been quiesced first. This little detail should
4635 hopefully further stabilize the encoder. */
4636 return 0;
4637 }
62433e31
MI		 4638 if (!hdw->state_pathway_ok ||
4639 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4640 !hdw->state_pipeline_req ||
681c7399
MI		 4641 hdw->state_pipeline_pause ||
4642 !hdw->state_pipeline_config ||
4643 !hdw->state_encoder_config ||
4644 !hdw->state_encoder_ok) return 0;
4645 del_timer_sync(&hdw->quiescent_timer);
4646 if (hdw->flag_decoder_missed) return 0;
4647 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4648 hdw->state_decoder_quiescent = 0;
6e931375 4649 hdw->state_decoder_ready = 0;
681c7399 4650 hdw->state_decoder_run = !0;
fb640224
MI		 4651 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4652 hdw->decoder_stabilization_timer.expires =
4653 jiffies +
4654 (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
4655 1000);
4656 add_timer(&hdw->decoder_stabilization_timer);
4657 } else {
4658 hdw->state_decoder_ready = !0;
4659 }
681c7399
MI		 4660 }
4661 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4662 trace_stbit("state_decoder_run",hdw->state_decoder_run);
6e931375 4663 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
681c7399
MI		 4664 return !0;
4665}
4666
4667
4668/* Evaluate whether or not state_usbstream_run can change */
4669static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4670{
4671 if (hdw->state_usbstream_run) {
72998b71 4672 int fl = !0;
62433e31 4673 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4674 fl = (hdw->state_encoder_ok &&
4675 hdw->state_encoder_run);
4676 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4677 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4678 fl = hdw->state_encoder_ok;
4679 }
4680 if (fl &&
4681 hdw->state_pipeline_req &&
4682 !hdw->state_pipeline_pause &&
4683 hdw->state_pathway_ok) {
4684 return 0;
681c7399
MI		 4685 }
4686 pvr2_hdw_cmd_usbstream(hdw,0);
4687 hdw->state_usbstream_run = 0;
4688 } else {
62433e31
MI		 4689 if (!hdw->state_pipeline_req ||
4690 hdw->state_pipeline_pause ||
4691 !hdw->state_pathway_ok) return 0;
4692 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4693 if (!hdw->state_encoder_ok ||
4694 !hdw->state_encoder_run) return 0;
72998b71
MI		 4695 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4696 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4697 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4698 if (hdw->state_encoder_run) return 0;
4699 if (hdw->hdw_desc->digital_control_scheme ==
4700 PVR2_DIGITAL_SCHEME_ONAIR) {
4701 /* OnAir digital receivers won't stream
4702 unless the analog encoder has run first.
4703 Why? I have no idea. But don't even
4704 try until we know the analog side is
4705 known to have run. */
4706 if (!hdw->state_encoder_runok) return 0;
4707 }
62433e31 4708 }
681c7399
MI		 4709 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4710 hdw->state_usbstream_run = !0;
4711 }
4712 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4713 return !0;
4714}
4715
4716
4717/* Attempt to configure pipeline, if needed */
4718static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4719{
4720 if (hdw->state_pipeline_config ||
4721 hdw->state_pipeline_pause) return 0;
4722 pvr2_hdw_commit_execute(hdw);
4723 return !0;
4724}
4725
4726
4727/* Update pipeline idle and pipeline pause tracking states based on other
4728 inputs. This must be called whenever the other relevant inputs have
4729 changed. */
4730static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4731{
4732 unsigned int st;
4733 int updatedFl = 0;
4734 /* Update pipeline state */
4735 st = !(hdw->state_encoder_run ||
4736 hdw->state_decoder_run ||
4737 hdw->state_usbstream_run ||
4738 (!hdw->state_decoder_quiescent));
4739 if (!st != !hdw->state_pipeline_idle) {
4740 hdw->state_pipeline_idle = st;
4741 updatedFl = !0;
4742 }
4743 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4744 hdw->state_pipeline_pause = 0;
4745 updatedFl = !0;
4746 }
4747 return updatedFl;
4748}
4749
4750
4751typedef int (*state_eval_func)(struct pvr2_hdw *);
4752
4753/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4754static const state_eval_func eval_funcs[] = {
62433e31 4755 state_eval_pathway_ok,
681c7399
MI		 4756 state_eval_pipeline_config,
4757 state_eval_encoder_ok,
4758 state_eval_encoder_config,
4759 state_eval_decoder_run,
4760 state_eval_encoder_run,
4761 state_eval_usbstream_run,
4762};
4763
4764
4765/* Process various states and return true if we did anything interesting. */
4766static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4767{
4768 unsigned int i;
4769 int state_updated = 0;
4770 int check_flag;
4771
4772 if (!hdw->state_stale) return 0;
4773 if ((hdw->fw1_state != FW1_STATE_OK) ||
4774 !hdw->flag_ok) {
4775 hdw->state_stale = 0;
4776 return !0;
4777 }
4778 /* This loop is the heart of the entire driver. It keeps trying to
4779 evaluate various bits of driver state until nothing changes for
4780 one full iteration. Each "bit of state" tracks some global
4781 aspect of the driver, e.g. whether decoder should run, if
4782 pipeline is configured, usb streaming is on, etc. We separately
4783 evaluate each of those questions based on other driver state to
4784 arrive at the correct running configuration. */
4785 do {
4786 check_flag = 0;
4787 state_update_pipeline_state(hdw);
4788 /* Iterate over each bit of state */
4789 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4790 if ((*eval_funcs[i])(hdw)) {
4791 check_flag = !0;
4792 state_updated = !0;
4793 state_update_pipeline_state(hdw);
4794 }
4795 }
4796 } while (check_flag && hdw->flag_ok);
4797 hdw->state_stale = 0;
4798 trace_stbit("state_stale",hdw->state_stale);
4799 return state_updated;
4800}
4801
4802
1cb03b76
MI		 4803static unsigned int print_input_mask(unsigned int msk,
4804 char *buf,unsigned int acnt)
4805{
4806 unsigned int idx,ccnt;
4807 unsigned int tcnt = 0;
4808 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4809 if (!((1 << idx) & msk)) continue;
4810 ccnt = scnprintf(buf+tcnt,
4811 acnt-tcnt,
4812 "%s%s",
4813 (tcnt ? ", " : ""),
4814 control_values_input[idx]);
4815 tcnt += ccnt;
4816 }
4817 return tcnt;
4818}
4819
4820
62433e31
MI		 4821static const char *pvr2_pathway_state_name(int id)
4822{
4823 switch (id) {
4824 case PVR2_PATHWAY_ANALOG: return "analog";
4825 case PVR2_PATHWAY_DIGITAL: return "digital";
4826 default: return "unknown";
4827 }
4828}
4829
4830
681c7399
MI		 4831static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4832 char *buf,unsigned int acnt)
4833{
4834 switch (which) {
4835 case 0:
4836 return scnprintf(
4837 buf,acnt,
e9db1ff2 4838 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4839 (hdw->flag_ok ? " <ok>" : " <fail>"),
4840 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4841 (hdw->flag_disconnected ? " <disconnected>" :
4842 " <connected>"),
4843 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4844 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4845 pvr2_pathway_state_name(hdw->pathway_state));
4846
681c7399
MI		 4847 case 1:
4848 return scnprintf(
4849 buf,acnt,
4850 "pipeline:%s%s%s%s",
4851 (hdw->state_pipeline_idle ? " <idle>" : ""),
4852 (hdw->state_pipeline_config ?
4853 " <configok>" : " <stale>"),
4854 (hdw->state_pipeline_req ? " <req>" : ""),
4855 (hdw->state_pipeline_pause ? " <pause>" : ""));
4856 case 2:
4857 return scnprintf(
4858 buf,acnt,
62433e31 4859 "worker:%s%s%s%s%s%s%s",
681c7399 4860 (hdw->state_decoder_run ?
6e931375
MI		 4861 (hdw->state_decoder_ready ?
4862 "<decode:run>" : " <decode:start>") :
681c7399
MI		 4863 (hdw->state_decoder_quiescent ?
4864 "" : " <decode:stop>")),
4865 (hdw->state_decoder_quiescent ?
4866 " <decode:quiescent>" : ""),
4867 (hdw->state_encoder_ok ?
4868 "" : " <encode:init>"),
4869 (hdw->state_encoder_run ?
d913d630
MI		 4870 (hdw->state_encoder_runok ?
4871 " <encode:run>" :
4872 " <encode:firstrun>") :
4873 (hdw->state_encoder_runok ?
4874 " <encode:stop>" :
4875 " <encode:virgin>")),
681c7399
MI		 4876 (hdw->state_encoder_config ?
4877 " <encode:configok>" :
4878 (hdw->state_encoder_waitok ?
b9a37d91 4879 "" : " <encode:waitok>")),
681c7399 4880 (hdw->state_usbstream_run ?
62433e31
MI		 4881 " <usb:run>" : " <usb:stop>"),
4882 (hdw->state_pathway_ok ?
e9db1ff2 4883 " <pathway:ok>" : ""));
681c7399
MI		 4884 case 3:
4885 return scnprintf(
4886 buf,acnt,
4887 "state: %s",
4888 pvr2_get_state_name(hdw->master_state));
ad0992e9 4889 case 4: {
1cb03b76
MI		 4890 unsigned int tcnt = 0;
4891 unsigned int ccnt;
4892
4893 ccnt = scnprintf(buf,
4894 acnt,
4895 "Hardware supported inputs: ");
4896 tcnt += ccnt;
4897 tcnt += print_input_mask(hdw->input_avail_mask,
4898 buf+tcnt,
4899 acnt-tcnt);
4900 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4901 ccnt = scnprintf(buf+tcnt,
4902 acnt-tcnt,
4903 "; allowed inputs: ");
4904 tcnt += ccnt;
4905 tcnt += print_input_mask(hdw->input_allowed_mask,
4906 buf+tcnt,
4907 acnt-tcnt);
4908 }
4909 return tcnt;
4910 }
4911 case 5: {
ad0992e9
MI		 4912 struct pvr2_stream_stats stats;
4913 if (!hdw->vid_stream) break;
4914 pvr2_stream_get_stats(hdw->vid_stream,
4915 &stats,
4916 0);
4917 return scnprintf(
4918 buf,acnt,
4919 "Bytes streamed=%u"
4920 " URBs: queued=%u idle=%u ready=%u"
4921 " processed=%u failed=%u",
4922 stats.bytes_processed,
4923 stats.buffers_in_queue,
4924 stats.buffers_in_idle,
4925 stats.buffers_in_ready,
4926 stats.buffers_processed,
4927 stats.buffers_failed);
4928 }
27eab384
MI		 4929 case 6: {
4930 unsigned int id = hdw->ir_scheme_active;
4931 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4932 (id >= ARRAY_SIZE(ir_scheme_names) ?
4933 "?" : ir_scheme_names[id]));
4934 }
2eb563b7
MI		 4935 default: break;
4936 }
4937 return 0;
4938}
4939
4940
4941/* Generate report containing info about attached sub-devices and attached
4942 i2c clients, including an indication of which attached i2c clients are
4943 actually sub-devices. */
4944static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4945 char *buf, unsigned int acnt)
4946{
4947 struct v4l2_subdev *sd;
4948 unsigned int tcnt = 0;
4949 unsigned int ccnt;
4950 struct i2c_client *client;
2eb563b7
MI		 4951 const char *p;
4952 unsigned int id;
4953
fa7ce764 4954 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
2eb563b7
MI		 4955 tcnt += ccnt;
4956 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4957 id = sd->grp_id;
4958 p = NULL;
4959 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4960 if (p) {
fa7ce764 4961 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
2eb563b7
MI		 4962 tcnt += ccnt;
4963 } else {
4964 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
fa7ce764 4965 " (unknown id=%u):", id);
2eb563b7
MI		 4966 tcnt += ccnt;
4967 }
fa7ce764
JD		 4968 client = v4l2_get_subdevdata(sd);
4969 if (client) {
4970 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4971 " %s @ %02x\n", client->name,
4972 client->addr);
4973 tcnt += ccnt;
4974 } else {
4975 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4976 " no i2c client\n");
4977 tcnt += ccnt;
858f910e 4978 }
681c7399 4979 }
2eb563b7 4980 return tcnt;
681c7399
MI		 4981}
4982
4983
4984unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4985 char *buf,unsigned int acnt)
4986{
4987 unsigned int bcnt,ccnt,idx;
4988 bcnt = 0;
4989 LOCK_TAKE(hdw->big_lock);
4990 for (idx = 0; ; idx++) {
4991 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4992 if (!ccnt) break;
4993 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4994 if (!acnt) break;
4995 buf[0] = '\n'; ccnt = 1;
4996 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4997 }
2eb563b7
MI		 4998 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4999 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 5000 LOCK_GIVE(hdw->big_lock);
5001 return bcnt;
5002}
5003
5004
5005static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
5006{
2eb563b7
MI		 5007 char buf[256];
5008 unsigned int idx, ccnt;
5009 unsigned int lcnt, ucnt;
681c7399
MI		 5010
5011 for (idx = 0; ; idx++) {
5012 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
5013 if (!ccnt) break;
5014 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
5015 }
2eb563b7
MI		 5016 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
5017 ucnt = 0;
5018 while (ucnt < ccnt) {
5019 lcnt = 0;
5020 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
5021 lcnt++;
5022 }
5023 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
5024 ucnt += lcnt + 1;
5025 }
681c7399
MI		 5026}
5027
5028
5029/* Evaluate and update the driver's current state, taking various actions
5030 as appropriate for the update. */
5031static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
5032{
5033 unsigned int st;
5034 int state_updated = 0;
5035 int callback_flag = 0;
1b9c18c5 5036 int analog_mode;
681c7399
MI		 5037
5038 pvr2_trace(PVR2_TRACE_STBITS,
5039 "Drive state check START");
5040 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5041 pvr2_hdw_state_log_state(hdw);
5042 }
5043
5044 /* Process all state and get back over disposition */
5045 state_updated = pvr2_hdw_state_update(hdw);
5046
1b9c18c5
MI		 5047 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
5048
681c7399
MI		 5049 /* Update master state based upon all other states. */
5050 if (!hdw->flag_ok) {
5051 st = PVR2_STATE_DEAD;
5052 } else if (hdw->fw1_state != FW1_STATE_OK) {
5053 st = PVR2_STATE_COLD;
72998b71
MI		 5054 } else if ((analog_mode ||
5055 hdw->hdw_desc->flag_digital_requires_cx23416) &&
5056 !hdw->state_encoder_ok) {
681c7399 5057 st = PVR2_STATE_WARM;
1b9c18c5
MI		 5058 } else if (hdw->flag_tripped ||
5059 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 5060 st = PVR2_STATE_ERROR;
62433e31 5061 } else if (hdw->state_usbstream_run &&
1b9c18c5 5062 (!analog_mode ||
62433e31 5063 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 5064 st = PVR2_STATE_RUN;
5065 } else {
5066 st = PVR2_STATE_READY;
5067 }
5068 if (hdw->master_state != st) {
5069 pvr2_trace(PVR2_TRACE_STATE,
5070 "Device state change from %s to %s",
5071 pvr2_get_state_name(hdw->master_state),
5072 pvr2_get_state_name(st));
40381cb0 5073 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 5074 hdw->master_state = st;
5075 state_updated = !0;
5076 callback_flag = !0;
5077 }
5078 if (state_updated) {
5079 /* Trigger anyone waiting on any state changes here. */
5080 wake_up(&hdw->state_wait_data);
5081 }
5082
5083 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5084 pvr2_hdw_state_log_state(hdw);
5085 }
5086 pvr2_trace(PVR2_TRACE_STBITS,
5087 "Drive state check DONE callback=%d",callback_flag);
5088
5089 return callback_flag;
5090}
5091
5092
5093/* Cause kernel thread to check / update driver state */
5094static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5095{
5096 if (hdw->state_stale) return;
5097 hdw->state_stale = !0;
5098 trace_stbit("state_stale",hdw->state_stale);
5099 queue_work(hdw->workqueue,&hdw->workpoll);
5100}
5101
5102
d855497e
MI		 5103int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5104{
5105 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5106}
5107
5108
5109int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5110{
5111 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5112}
5113
5114
5115int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5116{
5117 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5118}
5119
5120
5121int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5122{
5123 u32 cval,nval;
5124 int ret;
5125 if (~msk) {
5126 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5127 if (ret) return ret;
5128 nval = (cval & ~msk) | (val & msk);
5129 pvr2_trace(PVR2_TRACE_GPIO,
5130 "GPIO direction changing 0x%x:0x%x"
5131 " from 0x%x to 0x%x",
5132 msk,val,cval,nval);
5133 } else {
5134 nval = val;
5135 pvr2_trace(PVR2_TRACE_GPIO,
5136 "GPIO direction changing to 0x%x",nval);
5137 }
5138 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5139}
5140
5141
5142int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5143{
5144 u32 cval,nval;
5145 int ret;
5146 if (~msk) {
5147 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5148 if (ret) return ret;
5149 nval = (cval & ~msk) | (val & msk);
5150 pvr2_trace(PVR2_TRACE_GPIO,
5151 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5152 msk,val,cval,nval);
5153 } else {
5154 nval = val;
5155 pvr2_trace(PVR2_TRACE_GPIO,
5156 "GPIO output changing to 0x%x",nval);
5157 }
5158 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5159}
5160
5161
a51f5000
MI		 5162void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5163{
40f07111
MI		 5164 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5165 memset(vtp, 0, sizeof(*vtp));
2641df36 5166 hdw->tuner_signal_stale = 0;
40f07111
MI		 5167 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5168 using v4l2-subdev - therefore we can't support that AT ALL right
5169 now. (Of course, no sub-drivers seem to implement it either.
5170 But now it's a a chicken and egg problem...) */
5171 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5172 &hdw->tuner_signal_info);
2641df36 5173 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5174 " type=%u strength=%u audio=0x%x cap=0x%x"
5175 " low=%u hi=%u",
5176 vtp->type,
5177 vtp->signal, vtp->rxsubchans, vtp->capability,
5178 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5179
5180 /* We have to do this to avoid getting into constant polling if
5181 there's nobody to answer a poll of cropcap info. */
5182 hdw->cropcap_stale = 0;
a51f5000
MI		 5183}
5184
5185
7fb20fa3
MI		 5186unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5187{
5188 return hdw->input_avail_mask;
5189}
5190
5191
1cb03b76
MI		 5192unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5193{
5194 return hdw->input_allowed_mask;
5195}
5196
5197
5198static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5199{
5200 if (hdw->input_val != v) {
5201 hdw->input_val = v;
5202 hdw->input_dirty = !0;
5203 }
5204
5205 /* Handle side effects - if we switch to a mode that needs the RF
5206 tuner, then select the right frequency choice as well and mark
5207 it dirty. */
5208 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5209 hdw->freqSelector = 0;
5210 hdw->freqDirty = !0;
5211 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5212 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5213 hdw->freqSelector = 1;
5214 hdw->freqDirty = !0;
5215 }
5216 return 0;
5217}
5218
5219
5220int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5221 unsigned int change_mask,
5222 unsigned int change_val)
5223{
5224 int ret = 0;
5225 unsigned int nv,m,idx;
5226 LOCK_TAKE(hdw->big_lock);
5227 do {
5228 nv = hdw->input_allowed_mask & ~change_mask;
5229 nv |= (change_val & change_mask);
5230 nv &= hdw->input_avail_mask;
5231 if (!nv) {
5232 /* No legal modes left; return error instead. */
5233 ret = -EPERM;
5234 break;
5235 }
5236 hdw->input_allowed_mask = nv;
5237 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5238 /* Current mode is still in the allowed mask, so
5239 we're done. */
5240 break;
5241 }
5242 /* Select and switch to a mode that is still in the allowed
5243 mask */
5244 if (!hdw->input_allowed_mask) {
5245 /* Nothing legal; give up */
5246 break;
5247 }
5248 m = hdw->input_allowed_mask;
5249 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5250 if (!((1 << idx) & m)) continue;
5251 pvr2_hdw_set_input(hdw,idx);
5252 break;
5253 }
5254 } while (0);
5255 LOCK_GIVE(hdw->big_lock);
5256 return ret;
5257}
5258
5259
e61b6fc5 5260/* Find I2C address of eeprom */
07e337ee 5261static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5262{
5263 int result;
5264 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5265 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5266 result = pvr2_send_request(hdw,
5267 hdw->cmd_buffer,1,
5268 hdw->cmd_buffer,1);
5269 if (result < 0) break;
5270 result = hdw->cmd_buffer[0];
5271 } while(0); LOCK_GIVE(hdw->ctl_lock);
5272 return result;
5273}
5274
5275
32ffa9ae 5276int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5277 struct v4l2_dbg_match *match, u64 reg_id,
5278 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5279{
5280#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5281 struct v4l2_dbg_register req;
6d98816f
MI		 5282 int stat = 0;
5283 int okFl = 0;
32ffa9ae 5284
201f5c9c
MI		 5285 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5286
aecde8b5 5287 req.match = *match;
32ffa9ae
MI		 5288 req.reg = reg_id;
5289 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5290 /* It would be nice to know if a sub-device answered the request */
5291 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5292 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5293 if (okFl) {
5294 return stat;
5295 }
32ffa9ae
MI		 5296 return -EINVAL;
5297#else
5298 return -ENOSYS;
5299#endif
5300}
5301
5302
d855497e
MI		 5303/*
5304 Stuff for Emacs to see, in order to encourage consistent editing style:
5305 *** Local Variables: ***
5306 *** mode: c ***
5307 *** fill-column: 75 ***
5308 *** tab-width: 8 ***
5309 *** c-basic-offset: 8 ***
5310 *** End: ***
5311 */
Clone of davem's net-next-2.6 tree