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V4L/DVB (13090): cx25840: Init PLLs properly for CX2388[578] A/V cores
[net-next-2.6.git] / drivers / media / video / cx25840 / cx25840-core.c
CommitLineData
bd985160
HV		 1/* cx25840 - Conexant CX25840 audio/video decoder driver
2 *
3 * Copyright (C) 2004 Ulf Eklund
4 *
5 * Based on the saa7115 driver and on the first verison of Chris Kennedy's
6 * cx25840 driver.
7 *
8 * Changes by Tyler Trafford <tatrafford@comcast.net>
9 * - cleanup/rewrite for V4L2 API (2005)
10 *
11 * VBI support by Hans Verkuil <hverkuil@xs4all.nl>.
12 *
3e3bf277
CN		 13 * NTSC sliced VBI support by Christopher Neufeld <television@cneufeld.ca>
14 * with additional fixes by Hans Verkuil <hverkuil@xs4all.nl>.
15 *
6d897616 16 * CX23885 support by Steven Toth <stoth@linuxtv.org>.
f234081b 17 *
bd985160
HV		 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
31 */
32
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/slab.h>
37#include <linux/videodev2.h>
38#include <linux/i2c.h>
f61b48f7 39#include <linux/delay.h>
bd985160 40#include <media/v4l2-common.h>
3434eb7e 41#include <media/v4l2-chip-ident.h>
b6198ade 42#include <media/v4l2-i2c-drv.h>
31bc09b5 43#include <media/cx25840.h>
bd985160 44
31bc09b5 45#include "cx25840-core.h"
bd985160
HV		 46
47MODULE_DESCRIPTION("Conexant CX25840 audio/video decoder driver");
1f4b3365 48MODULE_AUTHOR("Ulf Eklund, Chris Kennedy, Hans Verkuil, Tyler Trafford");
bd985160
HV		 49MODULE_LICENSE("GPL");
50
fe0d3dff 51static int cx25840_debug;
bd985160 52
b5fc7144 53module_param_named(debug,cx25840_debug, int, 0644);
bd985160 54
fac9e899 55MODULE_PARM_DESC(debug, "Debugging messages [0=Off (default) 1=On]");
bd985160 56
bd985160
HV		 57
58/* ----------------------------------------------------------------------- */
59
60int cx25840_write(struct i2c_client *client, u16 addr, u8 value)
61{
62 u8 buffer[3];
63 buffer[0] = addr >> 8;
64 buffer[1] = addr & 0xff;
65 buffer[2] = value;
66 return i2c_master_send(client, buffer, 3);
67}
68
69int cx25840_write4(struct i2c_client *client, u16 addr, u32 value)
70{
71 u8 buffer[6];
72 buffer[0] = addr >> 8;
73 buffer[1] = addr & 0xff;
4a56eb3f
HV		 74 buffer[2] = value & 0xff;
75 buffer[3] = (value >> 8) & 0xff;
76 buffer[4] = (value >> 16) & 0xff;
77 buffer[5] = value >> 24;
bd985160
HV		 78 return i2c_master_send(client, buffer, 6);
79}
80
81u8 cx25840_read(struct i2c_client * client, u16 addr)
82{
83 u8 buffer[2];
84 buffer[0] = addr >> 8;
85 buffer[1] = addr & 0xff;
86
87 if (i2c_master_send(client, buffer, 2) < 2)
88 return 0;
89
90 if (i2c_master_recv(client, buffer, 1) < 1)
91 return 0;
92
93 return buffer[0];
94}
95
96u32 cx25840_read4(struct i2c_client * client, u16 addr)
97{
98 u8 buffer[4];
99 buffer[0] = addr >> 8;
100 buffer[1] = addr & 0xff;
101
102 if (i2c_master_send(client, buffer, 2) < 2)
103 return 0;
104
105 if (i2c_master_recv(client, buffer, 4) < 4)
106 return 0;
107
17531c16
HV		 108 return (buffer[3] << 24) | (buffer[2] << 16) |
109 (buffer[1] << 8) | buffer[0];
bd985160
HV		 110}
111
e2b8cf4c 112int cx25840_and_or(struct i2c_client *client, u16 addr, unsigned and_mask,
bd985160
HV		 113 u8 or_value)
114{
115 return cx25840_write(client, addr,
116 (cx25840_read(client, addr) & and_mask) |
117 or_value);
118}
119
120/* ----------------------------------------------------------------------- */
121
a8bbf12a
HV		 122static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
123 enum cx25840_audio_input aud_input);
bd985160
HV		 124
125/* ----------------------------------------------------------------------- */
126
d92c20e0 127static void init_dll1(struct i2c_client *client)
bd985160
HV		 128{
129 /* This is the Hauppauge sequence used to
130 * initialize the Delay Lock Loop 1 (ADC DLL). */
131 cx25840_write(client, 0x159, 0x23);
132 cx25840_write(client, 0x15a, 0x87);
133 cx25840_write(client, 0x15b, 0x06);
38051450 134 udelay(10);
bd985160 135 cx25840_write(client, 0x159, 0xe1);
38051450 136 udelay(10);
bd985160
HV		 137 cx25840_write(client, 0x15a, 0x86);
138 cx25840_write(client, 0x159, 0xe0);
139 cx25840_write(client, 0x159, 0xe1);
140 cx25840_write(client, 0x15b, 0x10);
141}
142
d92c20e0 143static void init_dll2(struct i2c_client *client)
bd985160
HV		 144{
145 /* This is the Hauppauge sequence used to
146 * initialize the Delay Lock Loop 2 (ADC DLL). */
147 cx25840_write(client, 0x15d, 0xe3);
148 cx25840_write(client, 0x15e, 0x86);
149 cx25840_write(client, 0x15f, 0x06);
38051450 150 udelay(10);
bd985160
HV		 151 cx25840_write(client, 0x15d, 0xe1);
152 cx25840_write(client, 0x15d, 0xe0);
153 cx25840_write(client, 0x15d, 0xe1);
154}
155
e2b8cf4c
HV		 156static void cx25836_initialize(struct i2c_client *client)
157{
158 /* reset configuration is described on page 3-77 of the CX25836 datasheet */
159 /* 2. */
160 cx25840_and_or(client, 0x000, ~0x01, 0x01);
161 cx25840_and_or(client, 0x000, ~0x01, 0x00);
162 /* 3a. */
163 cx25840_and_or(client, 0x15a, ~0x70, 0x00);
164 /* 3b. */
165 cx25840_and_or(client, 0x15b, ~0x1e, 0x06);
166 /* 3c. */
167 cx25840_and_or(client, 0x159, ~0x02, 0x02);
168 /* 3d. */
38051450 169 udelay(10);
e2b8cf4c
HV		 170 /* 3e. */
171 cx25840_and_or(client, 0x159, ~0x02, 0x00);
172 /* 3f. */
173 cx25840_and_or(client, 0x159, ~0xc0, 0xc0);
174 /* 3g. */
175 cx25840_and_or(client, 0x159, ~0x01, 0x00);
176 cx25840_and_or(client, 0x159, ~0x01, 0x01);
177 /* 3h. */
178 cx25840_and_or(client, 0x15b, ~0x1e, 0x10);
179}
180
21340ae0
HV		 181static void cx25840_work_handler(struct work_struct *work)
182{
183 struct cx25840_state *state = container_of(work, struct cx25840_state, fw_work);
184 cx25840_loadfw(state->c);
185 wake_up(&state->fw_wait);
186}
187
89fc4eb9 188static void cx25840_initialize(struct i2c_client *client)
bd985160 189{
21340ae0 190 DEFINE_WAIT(wait);
9357b31c 191 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
21340ae0 192 struct workqueue_struct *q;
bd985160
HV		 193
194 /* datasheet startup in numbered steps, refer to page 3-77 */
195 /* 2. */
196 cx25840_and_or(client, 0x803, ~0x10, 0x00);
197 /* The default of this register should be 4, but I get 0 instead.
198 * Set this register to 4 manually. */
199 cx25840_write(client, 0x000, 0x04);
200 /* 3. */
201 init_dll1(client);
202 init_dll2(client);
203 cx25840_write(client, 0x136, 0x0a);
204 /* 4. */
205 cx25840_write(client, 0x13c, 0x01);
206 cx25840_write(client, 0x13c, 0x00);
207 /* 5. */
21340ae0
HV		 208 /* Do the firmware load in a work handler to prevent.
209 Otherwise the kernel is blocked waiting for the
210 bit-banging i2c interface to finish uploading the
211 firmware. */
212 INIT_WORK(&state->fw_work, cx25840_work_handler);
213 init_waitqueue_head(&state->fw_wait);
214 q = create_singlethread_workqueue("cx25840_fw");
215 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
216 queue_work(q, &state->fw_work);
217 schedule();
218 finish_wait(&state->fw_wait, &wait);
219 destroy_workqueue(q);
220
bd985160
HV		 221 /* 6. */
222 cx25840_write(client, 0x115, 0x8c);
223 cx25840_write(client, 0x116, 0x07);
224 cx25840_write(client, 0x118, 0x02);
225 /* 7. */
226 cx25840_write(client, 0x4a5, 0x80);
227 cx25840_write(client, 0x4a5, 0x00);
228 cx25840_write(client, 0x402, 0x00);
229 /* 8. */
73dcddc5
HV		 230 cx25840_and_or(client, 0x401, ~0x18, 0);
231 cx25840_and_or(client, 0x4a2, ~0x10, 0x10);
232 /* steps 8c and 8d are done in change_input() */
bd985160
HV		 233 /* 10. */
234 cx25840_write(client, 0x8d3, 0x1f);
235 cx25840_write(client, 0x8e3, 0x03);
236
cb5aa1c6 237 cx25840_std_setup(client);
bd985160
HV		 238
239 /* trial and error says these are needed to get audio */
240 cx25840_write(client, 0x914, 0xa0);
241 cx25840_write(client, 0x918, 0xa0);
242 cx25840_write(client, 0x919, 0x01);
243
244 /* stereo prefered */
245 cx25840_write(client, 0x809, 0x04);
246 /* AC97 shift */
247 cx25840_write(client, 0x8cf, 0x0f);
248
a8bbf12a
HV		 249 /* (re)set input */
250 set_input(client, state->vid_input, state->aud_input);
bd985160
HV		 251
252 /* start microcontroller */
253 cx25840_and_or(client, 0x803, ~0x10, 0x10);
254}
255
f234081b
ST		 256static void cx23885_initialize(struct i2c_client *client)
257{
258 DEFINE_WAIT(wait);
9357b31c 259 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
f234081b
ST		 260 struct workqueue_struct *q;
261
e283d780
AW		 262 /*
263 * Come out of digital power down
264 * The CX23888, at least, needs this, otherwise registers aside from
265 * 0x0-0x2 can't be read or written.
266 */
267 cx25840_write(client, 0x000, 0);
268
f234081b
ST		 269 /* Internal Reset */
270 cx25840_and_or(client, 0x102, ~0x01, 0x01);
271 cx25840_and_or(client, 0x102, ~0x01, 0x00);
272
273 /* Stop microcontroller */
274 cx25840_and_or(client, 0x803, ~0x10, 0x00);
275
276 /* DIF in reset? */
277 cx25840_write(client, 0x398, 0);
278
e283d780
AW		 279 /*
280 * Trust the default xtal, no division
281 * '885: 28.636363... MHz
282 * '887: 25.000000 MHz
283 * '888: 50.000000 MHz
284 */
f234081b
ST		 285 cx25840_write(client, 0x2, 0x76);
286
e283d780 287 /* Power up all the PLL's and DLL */
f234081b
ST		 288 cx25840_write(client, 0x1, 0x40);
289
e283d780
AW		 290 /* Sys PLL */
291 switch (state->id) {
292 case V4L2_IDENT_CX23888_AV:
293 /*
294 * 50.0 MHz * (0xb + 0xe8ba26/0x2000000)/4 = 5 * 28.636363 MHz
295 * 572.73 MHz before post divide
296 */
297 cx25840_write4(client, 0x11c, 0x00e8ba26);
298 cx25840_write4(client, 0x118, 0x0000040b);
299 break;
300 case V4L2_IDENT_CX23887_AV:
301 /*
302 * 25.0 MHz * (0x16 + 0x1d1744c/0x2000000)/4 = 5 * 28.636363 MHz
303 * 572.73 MHz before post divide
304 */
305 cx25840_write4(client, 0x11c, 0x01d1744c);
306 cx25840_write4(client, 0x118, 0x00000416);
307 break;
308 case V4L2_IDENT_CX23885_AV:
309 default:
310 /*
311 * 28.636363 MHz * (0x14 + 0x0/0x2000000)/4 = 5 * 28.636363 MHz
312 * 572.73 MHz before post divide
313 */
314 cx25840_write4(client, 0x11c, 0x00000000);
315 cx25840_write4(client, 0x118, 0x00000414);
316 break;
317 }
f234081b
ST		 318
319 /* Disable DIF bypass */
320 cx25840_write4(client, 0x33c, 0x00000001);
321
322 /* DIF Src phase inc */
323 cx25840_write4(client, 0x340, 0x0df7df83);
324
e283d780
AW		 325 /*
326 * Vid PLL
327 * Setup for a BT.656 pixel clock of 13.5 Mpixels/second
328 *
329 * 28.636363 MHz * (0xf + 0x02be2c9/0x2000000)/4 = 8 * 13.5 MHz
330 * 432.0 MHz before post divide
331 */
332 cx25840_write4(client, 0x10c, 0x002be2c9);
333 cx25840_write4(client, 0x108, 0x0000040f);
f234081b
ST		 334
335 /* Luma */
336 cx25840_write4(client, 0x414, 0x00107d12);
337
338 /* Chroma */
339 cx25840_write4(client, 0x420, 0x3d008282);
340
e283d780
AW		 341 /*
342 * Aux PLL
343 * Initial setup for audio sample clock:
344 * 48 ksps, 16 bits/sample, x160 multiplier = 122.88 MHz
345 * Intial I2S output/master clock(?):
346 * 48 ksps, 16 bits/sample, x16 multiplier = 12.288 MHz
347 */
348 switch (state->id) {
349 case V4L2_IDENT_CX23888_AV:
350 /*
351 * 50.0 MHz * (0x7 + 0x0bedfa4/0x2000000)/3 = 122.88 MHz
352 * 368.64 MHz before post divide
353 * 122.88 MHz / 0xa = 12.288 MHz
354 */
355 cx25840_write4(client, 0x114, 0x00bedfa4);
356 cx25840_write4(client, 0x110, 0x000a0307);
357 break;
358 case V4L2_IDENT_CX23887_AV:
359 /*
360 * 25.0 MHz * (0xe + 0x17dbf48/0x2000000)/3 = 122.88 MHz
361 * 368.64 MHz before post divide
362 * 122.88 MHz / 0xa = 12.288 MHz
363 */
364 cx25840_write4(client, 0x114, 0x017dbf48);
365 cx25840_write4(client, 0x110, 0x000a030e);
366 break;
367 case V4L2_IDENT_CX23885_AV:
368 default:
369 /*
370 * 28.636363 MHz * (0xc + 0x1bf0c9e/0x2000000)/3 = 122.88 MHz
371 * 368.64 MHz before post divide
372 * 122.88 MHz / 0xa = 12.288 MHz
373 */
374 cx25840_write4(client, 0x114, 0x01bf0c9e);
375 cx25840_write4(client, 0x110, 0x000a030c);
376 break;
377 };
f234081b
ST		 378
379 /* ADC2 input select */
380 cx25840_write(client, 0x102, 0x10);
381
382 /* VIN1 & VIN5 */
383 cx25840_write(client, 0x103, 0x11);
384
385 /* Enable format auto detect */
386 cx25840_write(client, 0x400, 0);
387 /* Fast subchroma lock */
388 /* White crush, Chroma AGC & Chroma Killer enabled */
389 cx25840_write(client, 0x401, 0xe8);
390
391 /* Select AFE clock pad output source */
392 cx25840_write(client, 0x144, 0x05);
393
f3d6f633
ST		 394 /* Drive GPIO2 direction and values for HVR1700
395 * where an onboard mux selects the output of demodulator
396 * vs the 417. Failure to set this results in no DTV.
397 * It's safe to set this across all Hauppauge boards
398 * currently, regardless of the board type.
399 */
400 cx25840_write(client, 0x160, 0x1d);
401 cx25840_write(client, 0x164, 0x00);
402
f234081b
ST		 403 /* Do the firmware load in a work handler to prevent.
404 Otherwise the kernel is blocked waiting for the
405 bit-banging i2c interface to finish uploading the
406 firmware. */
407 INIT_WORK(&state->fw_work, cx25840_work_handler);
408 init_waitqueue_head(&state->fw_wait);
409 q = create_singlethread_workqueue("cx25840_fw");
410 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
411 queue_work(q, &state->fw_work);
412 schedule();
413 finish_wait(&state->fw_wait, &wait);
414 destroy_workqueue(q);
415
cb5aa1c6 416 cx25840_std_setup(client);
f234081b
ST		 417
418 /* (re)set input */
419 set_input(client, state->vid_input, state->aud_input);
420
421 /* start microcontroller */
422 cx25840_and_or(client, 0x803, ~0x10, 0x10);
423}
424
bd985160
HV		 425/* ----------------------------------------------------------------------- */
426
149783b5
SD		 427static void cx231xx_initialize(struct i2c_client *client)
428{
429 DEFINE_WAIT(wait);
430 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
431 struct workqueue_struct *q;
432
433 /* Internal Reset */
434 cx25840_and_or(client, 0x102, ~0x01, 0x01);
435 cx25840_and_or(client, 0x102, ~0x01, 0x00);
436
437 /* Stop microcontroller */
438 cx25840_and_or(client, 0x803, ~0x10, 0x00);
439
440 /* DIF in reset? */
441 cx25840_write(client, 0x398, 0);
442
443 /* Trust the default xtal, no division */
444 /* This changes for the cx23888 products */
445 cx25840_write(client, 0x2, 0x76);
446
447 /* Bring down the regulator for AUX clk */
448 cx25840_write(client, 0x1, 0x40);
449
450 /* Disable DIF bypass */
451 cx25840_write4(client, 0x33c, 0x00000001);
452
453 /* DIF Src phase inc */
454 cx25840_write4(client, 0x340, 0x0df7df83);
455
149783b5
SD		 456 /* Luma */
457 cx25840_write4(client, 0x414, 0x00107d12);
458
459 /* Chroma */
460 cx25840_write4(client, 0x420, 0x3d008282);
461
149783b5
SD		 462 /* ADC2 input select */
463 cx25840_write(client, 0x102, 0x10);
464
465 /* VIN1 & VIN5 */
466 cx25840_write(client, 0x103, 0x11);
467
468 /* Enable format auto detect */
469 cx25840_write(client, 0x400, 0);
470 /* Fast subchroma lock */
471 /* White crush, Chroma AGC & Chroma Killer enabled */
472 cx25840_write(client, 0x401, 0xe8);
473
149783b5
SD		 474 /* Do the firmware load in a work handler to prevent.
475 Otherwise the kernel is blocked waiting for the
476 bit-banging i2c interface to finish uploading the
477 firmware. */
478 INIT_WORK(&state->fw_work, cx25840_work_handler);
479 init_waitqueue_head(&state->fw_wait);
480 q = create_singlethread_workqueue("cx25840_fw");
481 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
482 queue_work(q, &state->fw_work);
483 schedule();
484 finish_wait(&state->fw_wait, &wait);
485 destroy_workqueue(q);
486
487 cx25840_std_setup(client);
488
489 /* (re)set input */
490 set_input(client, state->vid_input, state->aud_input);
491
492 /* start microcontroller */
493 cx25840_and_or(client, 0x803, ~0x10, 0x10);
494}
495
496/* ----------------------------------------------------------------------- */
497
cb5aa1c6
HV		 498void cx25840_std_setup(struct i2c_client *client)
499{
9357b31c 500 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
cb5aa1c6
HV		 501 v4l2_std_id std = state->std;
502 int hblank, hactive, burst, vblank, vactive, sc;
503 int vblank656, src_decimation;
504 int luma_lpf, uv_lpf, comb;
505 u32 pll_int, pll_frac, pll_post;
506
507 /* datasheet startup, step 8d */
508 if (std & ~V4L2_STD_NTSC)
509 cx25840_write(client, 0x49f, 0x11);
510 else
511 cx25840_write(client, 0x49f, 0x14);
512
513 if (std & V4L2_STD_625_50) {
514 hblank = 132;
515 hactive = 720;
516 burst = 93;
517 vblank = 36;
518 vactive = 580;
519 vblank656 = 40;
520 src_decimation = 0x21f;
521 luma_lpf = 2;
522
523 if (std & V4L2_STD_SECAM) {
524 uv_lpf = 0;
525 comb = 0;
526 sc = 0x0a425f;
527 } else if (std == V4L2_STD_PAL_Nc) {
528 uv_lpf = 1;
529 comb = 0x20;
530 sc = 556453;
531 } else {
532 uv_lpf = 1;
533 comb = 0x20;
534 sc = 688739;
535 }
536 } else {
537 hactive = 720;
538 hblank = 122;
539 vactive = 487;
540 luma_lpf = 1;
541 uv_lpf = 1;
542
543 src_decimation = 0x21f;
544 if (std == V4L2_STD_PAL_60) {
545 vblank = 26;
546 vblank656 = 26;
547 burst = 0x5b;
548 luma_lpf = 2;
549 comb = 0x20;
550 sc = 688739;
551 } else if (std == V4L2_STD_PAL_M) {
552 vblank = 20;
553 vblank656 = 24;
554 burst = 0x61;
555 comb = 0x20;
556 sc = 555452;
557 } else {
558 vblank = 26;
559 vblank656 = 26;
560 burst = 0x5b;
561 comb = 0x66;
562 sc = 556063;
563 }
564 }
565
566 /* DEBUG: Displays configured PLL frequency */
2a03f034 567 if (!is_cx231xx(state)) {
95b14fb2
MCC		 568 pll_int = cx25840_read(client, 0x108);
569 pll_frac = cx25840_read4(client, 0x10c) & 0x1ffffff;
570 pll_post = cx25840_read(client, 0x109);
cb5aa1c6 571 v4l_dbg(1, cx25840_debug, client,
95b14fb2
MCC		 572 "PLL regs = int: %u, frac: %u, post: %u\n",
573 pll_int, pll_frac, pll_post);
574
575 if (pll_post) {
576 int fin, fsc;
577 int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L;
578
579 pll /= pll_post;
580 v4l_dbg(1, cx25840_debug, client, "PLL = %d.%06d MHz\n",
581 pll / 1000000, pll % 1000000);
582 v4l_dbg(1, cx25840_debug, client, "PLL/8 = %d.%06d MHz\n",
583 pll / 8000000, (pll / 8) % 1000000);
584
585 fin = ((u64)src_decimation * pll) >> 12;
586 v4l_dbg(1, cx25840_debug, client,
587 "ADC Sampling freq = %d.%06d MHz\n",
588 fin / 1000000, fin % 1000000);
589
590 fsc = (((u64)sc) * pll) >> 24L;
591 v4l_dbg(1, cx25840_debug, client,
592 "Chroma sub-carrier freq = %d.%06d MHz\n",
593 fsc / 1000000, fsc % 1000000);
594
595 v4l_dbg(1, cx25840_debug, client, "hblank %i, hactive %i, "
596 "vblank %i, vactive %i, vblank656 %i, src_dec %i, "
597 "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, "
598 "sc 0x%06x\n",
599 hblank, hactive, vblank, vactive, vblank656,
600 src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
601 }
cb5aa1c6
HV		 602 }
603
604 /* Sets horizontal blanking delay and active lines */
605 cx25840_write(client, 0x470, hblank);
606 cx25840_write(client, 0x471,
607 0xff & (((hblank >> 8) & 0x3) | (hactive << 4)));
608 cx25840_write(client, 0x472, hactive >> 4);
609
610 /* Sets burst gate delay */
611 cx25840_write(client, 0x473, burst);
612
613 /* Sets vertical blanking delay and active duration */
614 cx25840_write(client, 0x474, vblank);
615 cx25840_write(client, 0x475,
616 0xff & (((vblank >> 8) & 0x3) | (vactive << 4)));
617 cx25840_write(client, 0x476, vactive >> 4);
618 cx25840_write(client, 0x477, vblank656);
619
620 /* Sets src decimation rate */
621 cx25840_write(client, 0x478, 0xff & src_decimation);
622 cx25840_write(client, 0x479, 0xff & (src_decimation >> 8));
623
624 /* Sets Luma and UV Low pass filters */
625 cx25840_write(client, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
626
627 /* Enables comb filters */
628 cx25840_write(client, 0x47b, comb);
629
630 /* Sets SC Step*/
631 cx25840_write(client, 0x47c, sc);
632 cx25840_write(client, 0x47d, 0xff & sc >> 8);
633 cx25840_write(client, 0x47e, 0xff & sc >> 16);
634
635 /* Sets VBI parameters */
636 if (std & V4L2_STD_625_50) {
637 cx25840_write(client, 0x47f, 0x01);
638 state->vbi_line_offset = 5;
639 } else {
640 cx25840_write(client, 0x47f, 0x00);
641 state->vbi_line_offset = 8;
642 }
643}
644
645/* ----------------------------------------------------------------------- */
646
bd985160
HV		 647static void input_change(struct i2c_client *client)
648{
9357b31c 649 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
081b496a 650 v4l2_std_id std = state->std;
bd985160 651
73dcddc5
HV		 652 /* Follow step 8c and 8d of section 3.16 in the cx25840 datasheet */
653 if (std & V4L2_STD_SECAM) {
654 cx25840_write(client, 0x402, 0);
655 }
656 else {
657 cx25840_write(client, 0x402, 0x04);
658 cx25840_write(client, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
659 }
660 cx25840_and_or(client, 0x401, ~0x60, 0);
661 cx25840_and_or(client, 0x401, ~0x60, 0x60);
82677618 662 cx25840_and_or(client, 0x810, ~0x01, 1);
73dcddc5 663
39c4ad6a
HV		 664 if (state->radio) {
665 cx25840_write(client, 0x808, 0xf9);
666 cx25840_write(client, 0x80b, 0x00);
667 }
668 else if (std & V4L2_STD_525_60) {
d97a11e0
HV		 669 /* Certain Hauppauge PVR150 models have a hardware bug
670 that causes audio to drop out. For these models the
671 audio standard must be set explicitly.
672 To be precise: it affects cards with tuner models
673 85, 99 and 112 (model numbers from tveeprom). */
674 int hw_fix = state->pvr150_workaround;
675
676 if (std == V4L2_STD_NTSC_M_JP) {
f95006f8 677 /* Japan uses EIAJ audio standard */
d97a11e0
HV		 678 cx25840_write(client, 0x808, hw_fix ? 0x2f : 0xf7);
679 } else if (std == V4L2_STD_NTSC_M_KR) {
680 /* South Korea uses A2 audio standard */
681 cx25840_write(client, 0x808, hw_fix ? 0x3f : 0xf8);
f95006f8
HV		 682 } else {
683 /* Others use the BTSC audio standard */
d97a11e0 684 cx25840_write(client, 0x808, hw_fix ? 0x1f : 0xf6);
f95006f8 685 }
bd985160 686 cx25840_write(client, 0x80b, 0x00);
839e4a4a
MCC		 687 } else if (std & V4L2_STD_PAL) {
688 /* Follow tuner change procedure for PAL */
689 cx25840_write(client, 0x808, 0xff);
690 cx25840_write(client, 0x80b, 0x10);
691 } else if (std & V4L2_STD_SECAM) {
692 /* Select autodetect for SECAM */
693 cx25840_write(client, 0x808, 0xff);
694 cx25840_write(client, 0x80b, 0x10);
bd985160
HV		 695 }
696
82677618 697 cx25840_and_or(client, 0x810, ~0x01, 0);
bd985160
HV		 698}
699
a8bbf12a
HV		 700static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
701 enum cx25840_audio_input aud_input)
bd985160 702{
9357b31c 703 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
a8bbf12a
HV		 704 u8 is_composite = (vid_input >= CX25840_COMPOSITE1 &&
705 vid_input <= CX25840_COMPOSITE8);
706 u8 reg;
bd985160 707
f234081b
ST		 708 v4l_dbg(1, cx25840_debug, client,
709 "decoder set video input %d, audio input %d\n",
710 vid_input, aud_input);
bd985160 711
f234081b
ST		 712 if (vid_input >= CX25840_VIN1_CH1) {
713 v4l_dbg(1, cx25840_debug, client, "vid_input 0x%x\n",
714 vid_input);
715 reg = vid_input & 0xff;
716 if ((vid_input & CX25840_SVIDEO_ON) == CX25840_SVIDEO_ON)
717 is_composite = 0;
718 else
719 is_composite = 1;
720
721 v4l_dbg(1, cx25840_debug, client, "mux cfg 0x%x comp=%d\n",
722 reg, is_composite);
723 } else
a8bbf12a
HV		 724 if (is_composite) {
725 reg = 0xf0 + (vid_input - CX25840_COMPOSITE1);
726 } else {
727 int luma = vid_input & 0xf0;
728 int chroma = vid_input & 0xf00;
bd985160 729
a8bbf12a 730 if ((vid_input & ~0xff0) ||
45270a15 731 luma < CX25840_SVIDEO_LUMA1 || luma > CX25840_SVIDEO_LUMA8 ||
a8bbf12a 732 chroma < CX25840_SVIDEO_CHROMA4 || chroma > CX25840_SVIDEO_CHROMA8) {
f234081b
ST		 733 v4l_err(client, "0x%04x is not a valid video input!\n",
734 vid_input);
a8bbf12a 735 return -EINVAL;
bd985160 736 }
a8bbf12a
HV		 737 reg = 0xf0 + ((luma - CX25840_SVIDEO_LUMA1) >> 4);
738 if (chroma >= CX25840_SVIDEO_CHROMA7) {
739 reg &= 0x3f;
740 reg |= (chroma - CX25840_SVIDEO_CHROMA7) >> 2;
bd985160 741 } else {
a8bbf12a
HV		 742 reg &= 0xcf;
743 reg |= (chroma - CX25840_SVIDEO_CHROMA4) >> 4;
bd985160 744 }
a8bbf12a 745 }
bd985160 746
f234081b
ST		 747 /* The caller has previously prepared the correct routing
748 * configuration in reg (for the cx23885) so we have no
749 * need to attempt to flip bits for earlier av decoders.
750 */
2a03f034 751 if (!is_cx2388x(state) && !is_cx231xx(state)) {
f234081b
ST		 752 switch (aud_input) {
753 case CX25840_AUDIO_SERIAL:
754 /* do nothing, use serial audio input */
755 break;
756 case CX25840_AUDIO4: reg &= ~0x30; break;
757 case CX25840_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
758 case CX25840_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
759 case CX25840_AUDIO7: reg &= ~0xc0; break;
760 case CX25840_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
bd985160 761
f234081b
ST		 762 default:
763 v4l_err(client, "0x%04x is not a valid audio input!\n",
764 aud_input);
765 return -EINVAL;
766 }
bd985160
HV		 767 }
768
a8bbf12a 769 cx25840_write(client, 0x103, reg);
f234081b 770
a8bbf12a
HV		 771 /* Set INPUT_MODE to Composite (0) or S-Video (1) */
772 cx25840_and_or(client, 0x401, ~0x6, is_composite ? 0 : 0x02);
f234081b 773
2a03f034 774 if (!is_cx2388x(state) && !is_cx231xx(state)) {
f234081b
ST		 775 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
776 cx25840_and_or(client, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0);
777 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2&CH3 */
778 if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
779 cx25840_and_or(client, 0x102, ~0x4, 4);
780 else
781 cx25840_and_or(client, 0x102, ~0x4, 0);
782 } else {
783 if (is_composite)
784 /* ADC2 input select channel 2 */
785 cx25840_and_or(client, 0x102, ~0x2, 0);
786 else
787 /* ADC2 input select channel 3 */
788 cx25840_and_or(client, 0x102, ~0x2, 2);
789 }
a8bbf12a
HV		 790
791 state->vid_input = vid_input;
792 state->aud_input = aud_input;
2a03f034 793 if (!is_cx2583x(state)) {
e2b8cf4c
HV		 794 cx25840_audio_set_path(client);
795 input_change(client);
796 }
f234081b 797
2a03f034 798 if (is_cx2388x(state)) {
f234081b
ST		 799 /* Audio channel 1 src : Parallel 1 */
800 cx25840_write(client, 0x124, 0x03);
801
802 /* Select AFE clock pad output source */
803 cx25840_write(client, 0x144, 0x05);
804
805 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
806 cx25840_write(client, 0x914, 0xa0);
807
149783b5
SD		 808 /* I2S_OUT_CTL:
809 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
810 * I2S_OUT_MASTER_MODE = Master
811 */
812 cx25840_write(client, 0x918, 0xa0);
813 cx25840_write(client, 0x919, 0x01);
2a03f034 814 } else if (is_cx231xx(state)) {
149783b5
SD		 815 /* Audio channel 1 src : Parallel 1 */
816 cx25840_write(client, 0x124, 0x03);
817
818 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
819 cx25840_write(client, 0x914, 0xa0);
820
f234081b
ST		 821 /* I2S_OUT_CTL:
822 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
823 * I2S_OUT_MASTER_MODE = Master
824 */
825 cx25840_write(client, 0x918, 0xa0);
826 cx25840_write(client, 0x919, 0x01);
827 }
828
bd985160
HV		 829 return 0;
830}
831
832/* ----------------------------------------------------------------------- */
833
081b496a 834static int set_v4lstd(struct i2c_client *client)
bd985160 835{
9357b31c 836 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
081b496a
HV		 837 u8 fmt = 0; /* zero is autodetect */
838 u8 pal_m = 0;
468a0a54
MCC		 839
840 /* First tests should be against specific std */
081b496a
HV		 841 if (state->std == V4L2_STD_NTSC_M_JP) {
842 fmt = 0x2;
843 } else if (state->std == V4L2_STD_NTSC_443) {
844 fmt = 0x3;
845 } else if (state->std == V4L2_STD_PAL_M) {
846 pal_m = 1;
847 fmt = 0x5;
848 } else if (state->std == V4L2_STD_PAL_N) {
849 fmt = 0x6;
850 } else if (state->std == V4L2_STD_PAL_Nc) {
851 fmt = 0x7;
852 } else if (state->std == V4L2_STD_PAL_60) {
853 fmt = 0x8;
468a0a54
MCC		 854 } else {
855 /* Then, test against generic ones */
081b496a
HV		 856 if (state->std & V4L2_STD_NTSC)
857 fmt = 0x1;
858 else if (state->std & V4L2_STD_PAL)
859 fmt = 0x4;
860 else if (state->std & V4L2_STD_SECAM)
861 fmt = 0xc;
bd985160
HV		 862 }
863
839e4a4a
MCC		 864 v4l_dbg(1, cx25840_debug, client, "changing video std to fmt %i\n",fmt);
865
73dcddc5
HV		 866 /* Follow step 9 of section 3.16 in the cx25840 datasheet.
867 Without this PAL may display a vertical ghosting effect.
868 This happens for example with the Yuan MPC622. */
869 if (fmt >= 4 && fmt < 8) {
870 /* Set format to NTSC-M */
871 cx25840_and_or(client, 0x400, ~0xf, 1);
872 /* Turn off LCOMB */
873 cx25840_and_or(client, 0x47b, ~6, 0);
874 }
bd985160 875 cx25840_and_or(client, 0x400, ~0xf, fmt);
081b496a 876 cx25840_and_or(client, 0x403, ~0x3, pal_m);
cb5aa1c6 877 cx25840_std_setup(client);
2a03f034 878 if (!is_cx2583x(state))
081b496a 879 input_change(client);
bd985160
HV		 880 return 0;
881}
882
bd985160
HV		 883/* ----------------------------------------------------------------------- */
884
9357b31c 885static int cx25840_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
bd985160 886{
95b14fb2 887 struct cx25840_state *state = to_state(sd);
9357b31c 888 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160
HV		 889
890 switch (ctrl->id) {
a8bbf12a
HV		 891 case CX25840_CID_ENABLE_PVR150_WORKAROUND:
892 state->pvr150_workaround = ctrl->value;
893 set_input(client, state->vid_input, state->aud_input);
bd985160
HV		 894 break;
895
896 case V4L2_CID_BRIGHTNESS:
897 if (ctrl->value < 0 || ctrl->value > 255) {
fac9e899 898 v4l_err(client, "invalid brightness setting %d\n",
bd985160
HV		 899 ctrl->value);
900 return -ERANGE;
901 }
902
903 cx25840_write(client, 0x414, ctrl->value - 128);
904 break;
905
906 case V4L2_CID_CONTRAST:
907 if (ctrl->value < 0 || ctrl->value > 127) {
fac9e899 908 v4l_err(client, "invalid contrast setting %d\n",
bd985160
HV		 909 ctrl->value);
910 return -ERANGE;
911 }
912
913 cx25840_write(client, 0x415, ctrl->value << 1);
914 break;
915
916 case V4L2_CID_SATURATION:
917 if (ctrl->value < 0 || ctrl->value > 127) {
fac9e899 918 v4l_err(client, "invalid saturation setting %d\n",
bd985160
HV		 919 ctrl->value);
920 return -ERANGE;
921 }
922
923 cx25840_write(client, 0x420, ctrl->value << 1);
924 cx25840_write(client, 0x421, ctrl->value << 1);
925 break;
926
927 case V4L2_CID_HUE:
de6476f5 928 if (ctrl->value < -128 || ctrl->value > 127) {
fac9e899 929 v4l_err(client, "invalid hue setting %d\n", ctrl->value);
bd985160
HV		 930 return -ERANGE;
931 }
932
933 cx25840_write(client, 0x422, ctrl->value);
934 break;
935
936 case V4L2_CID_AUDIO_VOLUME:
937 case V4L2_CID_AUDIO_BASS:
938 case V4L2_CID_AUDIO_TREBLE:
939 case V4L2_CID_AUDIO_BALANCE:
940 case V4L2_CID_AUDIO_MUTE:
2a03f034 941 if (is_cx2583x(state))
e2b8cf4c 942 return -EINVAL;
df1d5ed8 943 return cx25840_audio_s_ctrl(sd, ctrl);
3faeeae4
HV		 944
945 default:
946 return -EINVAL;
bd985160
HV		 947 }
948
949 return 0;
950}
951
9357b31c 952static int cx25840_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
bd985160 953{
95b14fb2 954 struct cx25840_state *state = to_state(sd);
9357b31c 955 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160
HV		 956
957 switch (ctrl->id) {
a8bbf12a
HV		 958 case CX25840_CID_ENABLE_PVR150_WORKAROUND:
959 ctrl->value = state->pvr150_workaround;
bd985160
HV		 960 break;
961 case V4L2_CID_BRIGHTNESS:
0de71224 962 ctrl->value = (s8)cx25840_read(client, 0x414) + 128;
bd985160
HV		 963 break;
964 case V4L2_CID_CONTRAST:
965 ctrl->value = cx25840_read(client, 0x415) >> 1;
966 break;
967 case V4L2_CID_SATURATION:
968 ctrl->value = cx25840_read(client, 0x420) >> 1;
969 break;
970 case V4L2_CID_HUE:
c5099a64 971 ctrl->value = (s8)cx25840_read(client, 0x422);
bd985160
HV		 972 break;
973 case V4L2_CID_AUDIO_VOLUME:
974 case V4L2_CID_AUDIO_BASS:
975 case V4L2_CID_AUDIO_TREBLE:
976 case V4L2_CID_AUDIO_BALANCE:
977 case V4L2_CID_AUDIO_MUTE:
2a03f034 978 if (is_cx2583x(state))
e2b8cf4c 979 return -EINVAL;
df1d5ed8 980 return cx25840_audio_g_ctrl(sd, ctrl);
bd985160
HV		 981 default:
982 return -EINVAL;
983 }
984
985 return 0;
986}
987
988/* ----------------------------------------------------------------------- */
989
9357b31c 990static int cx25840_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
bd985160
HV		 991{
992 switch (fmt->type) {
993 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
df1d5ed8 994 return cx25840_vbi_g_fmt(sd, fmt);
bd985160
HV		 995 default:
996 return -EINVAL;
997 }
bd985160
HV		 998 return 0;
999}
1000
9357b31c 1001static int cx25840_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
bd985160 1002{
9357b31c
HV		 1003 struct cx25840_state *state = to_state(sd);
1004 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160
HV		 1005 struct v4l2_pix_format *pix;
1006 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
081b496a 1007 int is_50Hz = !(state->std & V4L2_STD_525_60);
bd985160
HV		 1008
1009 switch (fmt->type) {
1010 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
1011 pix = &(fmt->fmt.pix);
1012
1013 Vsrc = (cx25840_read(client, 0x476) & 0x3f) << 4;
1014 Vsrc |= (cx25840_read(client, 0x475) & 0xf0) >> 4;
1015
1016 Hsrc = (cx25840_read(client, 0x472) & 0x3f) << 4;
1017 Hsrc |= (cx25840_read(client, 0x471) & 0xf0) >> 4;
1018
ba70d59b 1019 Vlines = pix->height + (is_50Hz ? 4 : 7);
bd985160
HV		 1020
1021 if ((pix->width * 16 < Hsrc) || (Hsrc < pix->width) ||
1022 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
fac9e899 1023 v4l_err(client, "%dx%d is not a valid size!\n",
bd985160
HV		 1024 pix->width, pix->height);
1025 return -ERANGE;
1026 }
1027
1028 HSC = (Hsrc * (1 << 20)) / pix->width - (1 << 20);
1029 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
1030 VSC &= 0x1fff;
1031
1032 if (pix->width >= 385)
1033 filter = 0;
1034 else if (pix->width > 192)
1035 filter = 1;
1036 else if (pix->width > 96)
1037 filter = 2;
1038 else
1039 filter = 3;
1040
b5fc7144 1041 v4l_dbg(1, cx25840_debug, client, "decoder set size %dx%d -> scale %ux%u\n",
bd985160
HV		 1042 pix->width, pix->height, HSC, VSC);
1043
1044 /* HSCALE=HSC */
1045 cx25840_write(client, 0x418, HSC & 0xff);
1046 cx25840_write(client, 0x419, (HSC >> 8) & 0xff);
1047 cx25840_write(client, 0x41a, HSC >> 16);
1048 /* VSCALE=VSC */
1049 cx25840_write(client, 0x41c, VSC & 0xff);
1050 cx25840_write(client, 0x41d, VSC >> 8);
1051 /* VS_INTRLACE=1 VFILT=filter */
1052 cx25840_write(client, 0x41e, 0x8 | filter);
1053 break;
1054
1055 case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
df1d5ed8 1056 return cx25840_vbi_s_fmt(sd, fmt);
bd985160
HV		 1057
1058 case V4L2_BUF_TYPE_VBI_CAPTURE:
df1d5ed8 1059 return cx25840_vbi_s_fmt(sd, fmt);
bd985160
HV		 1060
1061 default:
1062 return -EINVAL;
1063 }
1064
1065 return 0;
1066}
1067
1068/* ----------------------------------------------------------------------- */
1069
1a39275a
HV		 1070static void log_video_status(struct i2c_client *client)
1071{
1072 static const char *const fmt_strs[] = {
1073 "0x0",
1074 "NTSC-M", "NTSC-J", "NTSC-4.43",
1075 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1076 "0x9", "0xA", "0xB",
1077 "SECAM",
1078 "0xD", "0xE", "0xF"
1079 };
1080
9357b31c 1081 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1a39275a
HV		 1082 u8 vidfmt_sel = cx25840_read(client, 0x400) & 0xf;
1083 u8 gen_stat1 = cx25840_read(client, 0x40d);
1084 u8 gen_stat2 = cx25840_read(client, 0x40e);
1085 int vid_input = state->vid_input;
1086
1087 v4l_info(client, "Video signal: %spresent\n",
1088 (gen_stat2 & 0x20) ? "" : "not ");
1089 v4l_info(client, "Detected format: %s\n",
1090 fmt_strs[gen_stat1 & 0xf]);
1091
1092 v4l_info(client, "Specified standard: %s\n",
1093 vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection");
1094
1095 if (vid_input >= CX25840_COMPOSITE1 &&
1096 vid_input <= CX25840_COMPOSITE8) {
1097 v4l_info(client, "Specified video input: Composite %d\n",
1098 vid_input - CX25840_COMPOSITE1 + 1);
1099 } else {
1100 v4l_info(client, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
1101 (vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8);
1102 }
1103
1104 v4l_info(client, "Specified audioclock freq: %d Hz\n", state->audclk_freq);
1105}
1106
1107/* ----------------------------------------------------------------------- */
1108
1109static void log_audio_status(struct i2c_client *client)
1110{
9357b31c 1111 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1a39275a
HV		 1112 u8 download_ctl = cx25840_read(client, 0x803);
1113 u8 mod_det_stat0 = cx25840_read(client, 0x804);
1114 u8 mod_det_stat1 = cx25840_read(client, 0x805);
1115 u8 audio_config = cx25840_read(client, 0x808);
1116 u8 pref_mode = cx25840_read(client, 0x809);
1117 u8 afc0 = cx25840_read(client, 0x80b);
1118 u8 mute_ctl = cx25840_read(client, 0x8d3);
1119 int aud_input = state->aud_input;
1120 char *p;
1121
1122 switch (mod_det_stat0) {
1123 case 0x00: p = "mono"; break;
1124 case 0x01: p = "stereo"; break;
1125 case 0x02: p = "dual"; break;
1126 case 0x04: p = "tri"; break;
1127 case 0x10: p = "mono with SAP"; break;
1128 case 0x11: p = "stereo with SAP"; break;
1129 case 0x12: p = "dual with SAP"; break;
1130 case 0x14: p = "tri with SAP"; break;
1131 case 0xfe: p = "forced mode"; break;
1132 default: p = "not defined";
1133 }
1134 v4l_info(client, "Detected audio mode: %s\n", p);
1135
1136 switch (mod_det_stat1) {
1137 case 0x00: p = "not defined"; break;
1138 case 0x01: p = "EIAJ"; break;
1139 case 0x02: p = "A2-M"; break;
1140 case 0x03: p = "A2-BG"; break;
1141 case 0x04: p = "A2-DK1"; break;
1142 case 0x05: p = "A2-DK2"; break;
1143 case 0x06: p = "A2-DK3"; break;
1144 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1145 case 0x08: p = "AM-L"; break;
1146 case 0x09: p = "NICAM-BG"; break;
1147 case 0x0a: p = "NICAM-DK"; break;
1148 case 0x0b: p = "NICAM-I"; break;
1149 case 0x0c: p = "NICAM-L"; break;
1150 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1151 case 0x0e: p = "IF FM Radio"; break;
1152 case 0x0f: p = "BTSC"; break;
1153 case 0x10: p = "high-deviation FM"; break;
1154 case 0x11: p = "very high-deviation FM"; break;
1155 case 0xfd: p = "unknown audio standard"; break;
1156 case 0xfe: p = "forced audio standard"; break;
1157 case 0xff: p = "no detected audio standard"; break;
1158 default: p = "not defined";
1159 }
1160 v4l_info(client, "Detected audio standard: %s\n", p);
1161 v4l_info(client, "Audio muted: %s\n",
1162 (state->unmute_volume >= 0) ? "yes" : "no");
1163 v4l_info(client, "Audio microcontroller: %s\n",
1164 (download_ctl & 0x10) ?
1165 ((mute_ctl & 0x2) ? "detecting" : "running") : "stopped");
1166
1167 switch (audio_config >> 4) {
1168 case 0x00: p = "undefined"; break;
1169 case 0x01: p = "BTSC"; break;
1170 case 0x02: p = "EIAJ"; break;
1171 case 0x03: p = "A2-M"; break;
1172 case 0x04: p = "A2-BG"; break;
1173 case 0x05: p = "A2-DK1"; break;
1174 case 0x06: p = "A2-DK2"; break;
1175 case 0x07: p = "A2-DK3"; break;
1176 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1177 case 0x09: p = "AM-L"; break;
1178 case 0x0a: p = "NICAM-BG"; break;
1179 case 0x0b: p = "NICAM-DK"; break;
1180 case 0x0c: p = "NICAM-I"; break;
1181 case 0x0d: p = "NICAM-L"; break;
1182 case 0x0e: p = "FM radio"; break;
1183 case 0x0f: p = "automatic detection"; break;
1184 default: p = "undefined";
1185 }
1186 v4l_info(client, "Configured audio standard: %s\n", p);
1187
1188 if ((audio_config >> 4) < 0xF) {
1189 switch (audio_config & 0xF) {
1190 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1191 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1192 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1193 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1194 case 0x04: p = "STEREO"; break;
1195 case 0x05: p = "DUAL1 (AB)"; break;
1196 case 0x06: p = "DUAL2 (AC) (FM)"; break;
1197 case 0x07: p = "DUAL3 (BC) (FM)"; break;
1198 case 0x08: p = "DUAL4 (AC) (AM)"; break;
1199 case 0x09: p = "DUAL5 (BC) (AM)"; break;
1200 case 0x0a: p = "SAP"; break;
1201 default: p = "undefined";
1202 }
1203 v4l_info(client, "Configured audio mode: %s\n", p);
1204 } else {
1205 switch (audio_config & 0xF) {
1206 case 0x00: p = "BG"; break;
1207 case 0x01: p = "DK1"; break;
1208 case 0x02: p = "DK2"; break;
1209 case 0x03: p = "DK3"; break;
1210 case 0x04: p = "I"; break;
1211 case 0x05: p = "L"; break;
1212 case 0x06: p = "BTSC"; break;
1213 case 0x07: p = "EIAJ"; break;
1214 case 0x08: p = "A2-M"; break;
1215 case 0x09: p = "FM Radio"; break;
1216 case 0x0f: p = "automatic standard and mode detection"; break;
1217 default: p = "undefined";
1218 }
1219 v4l_info(client, "Configured audio system: %s\n", p);
1220 }
1221
1222 if (aud_input) {
1223 v4l_info(client, "Specified audio input: Tuner (In%d)\n", aud_input);
1224 } else {
1225 v4l_info(client, "Specified audio input: External\n");
1226 }
1227
1228 switch (pref_mode & 0xf) {
1229 case 0: p = "mono/language A"; break;
1230 case 1: p = "language B"; break;
1231 case 2: p = "language C"; break;
1232 case 3: p = "analog fallback"; break;
1233 case 4: p = "stereo"; break;
1234 case 5: p = "language AC"; break;
1235 case 6: p = "language BC"; break;
1236 case 7: p = "language AB"; break;
1237 default: p = "undefined";
1238 }
1239 v4l_info(client, "Preferred audio mode: %s\n", p);
1240
1241 if ((audio_config & 0xf) == 0xf) {
1242 switch ((afc0 >> 3) & 0x3) {
1243 case 0: p = "system DK"; break;
1244 case 1: p = "system L"; break;
1245 case 2: p = "autodetect"; break;
1246 default: p = "undefined";
1247 }
1248 v4l_info(client, "Selected 65 MHz format: %s\n", p);
1249
1250 switch (afc0 & 0x7) {
1251 case 0: p = "chroma"; break;
1252 case 1: p = "BTSC"; break;
1253 case 2: p = "EIAJ"; break;
1254 case 3: p = "A2-M"; break;
1255 case 4: p = "autodetect"; break;
1256 default: p = "undefined";
1257 }
1258 v4l_info(client, "Selected 45 MHz format: %s\n", p);
1259 }
1260}
1261
1262/* ----------------------------------------------------------------------- */
1263
cc26b076 1264/* This load_fw operation must be called to load the driver's firmware.
6ca187ab
HV		 1265 Without this the audio standard detection will fail and you will
1266 only get mono.
1267
1268 Since loading the firmware is often problematic when the driver is
1269 compiled into the kernel I recommend postponing calling this function
1270 until the first open of the video device. Another reason for
1271 postponing it is that loading this firmware takes a long time (seconds)
1272 due to the slow i2c bus speed. So it will speed up the boot process if
1273 you can avoid loading the fw as long as the video device isn't used. */
cc26b076 1274static int cx25840_load_fw(struct v4l2_subdev *sd)
bd985160 1275{
9357b31c
HV		 1276 struct cx25840_state *state = to_state(sd);
1277 struct i2c_client *client = v4l2_get_subdevdata(sd);
c976bc82
HV		 1278
1279 if (!state->is_initialized) {
cc26b076 1280 /* initialize and load firmware */
c976bc82 1281 state->is_initialized = 1;
2a03f034 1282 if (is_cx2583x(state))
c976bc82 1283 cx25836_initialize(client);
2a03f034 1284 else if (is_cx2388x(state))
f234081b 1285 cx23885_initialize(client);
2a03f034 1286 else if (is_cx231xx(state))
149783b5 1287 cx231xx_initialize(client);
c976bc82 1288 else
89fc4eb9 1289 cx25840_initialize(client);
c976bc82 1290 }
9357b31c
HV		 1291 return 0;
1292}
c976bc82 1293
bd985160 1294#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 1295static int cx25840_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
9357b31c
HV		 1296{
1297 struct i2c_client *client = v4l2_get_subdevdata(sd);
f234081b 1298
aecde8b5 1299 if (!v4l2_chip_match_i2c_client(client, &reg->match))
9357b31c
HV		 1300 return -EINVAL;
1301 if (!capable(CAP_SYS_ADMIN))
1302 return -EPERM;
aecde8b5 1303 reg->size = 1;
9357b31c
HV		 1304 reg->val = cx25840_read(client, reg->reg & 0x0fff);
1305 return 0;
1306}
1307
aecde8b5 1308static int cx25840_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
9357b31c
HV		 1309{
1310 struct i2c_client *client = v4l2_get_subdevdata(sd);
1311
aecde8b5 1312 if (!v4l2_chip_match_i2c_client(client, &reg->match))
9357b31c
HV		 1313 return -EINVAL;
1314 if (!capable(CAP_SYS_ADMIN))
1315 return -EPERM;
1316 cx25840_write(client, reg->reg & 0x0fff, reg->val & 0xff);
1317 return 0;
1318}
bd985160
HV		 1319#endif
1320
9357b31c
HV		 1321static int cx25840_s_stream(struct v4l2_subdev *sd, int enable)
1322{
1323 struct cx25840_state *state = to_state(sd);
1324 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1325
9357b31c
HV		 1326 v4l_dbg(1, cx25840_debug, client, "%s output\n",
1327 enable ? "enable" : "disable");
1328 if (enable) {
2a03f034 1329 if (is_cx2388x(state) || is_cx231xx(state)) {
f234081b
ST		 1330 u8 v = (cx25840_read(client, 0x421) | 0x0b);
1331 cx25840_write(client, 0x421, v);
1332 } else {
1333 cx25840_write(client, 0x115,
2a03f034 1334 is_cx2583x(state) ? 0x0c : 0x8c);
f234081b 1335 cx25840_write(client, 0x116,
2a03f034 1336 is_cx2583x(state) ? 0x04 : 0x07);
f234081b 1337 }
9357b31c 1338 } else {
2a03f034 1339 if (is_cx2388x(state) || is_cx231xx(state)) {
f234081b
ST		 1340 u8 v = cx25840_read(client, 0x421) & ~(0x0b);
1341 cx25840_write(client, 0x421, v);
1342 } else {
1343 cx25840_write(client, 0x115, 0x00);
1344 cx25840_write(client, 0x116, 0x00);
1345 }
9357b31c
HV		 1346 }
1347 return 0;
1348}
bd985160 1349
9357b31c
HV		 1350static int cx25840_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
1351{
1352 struct cx25840_state *state = to_state(sd);
bd985160 1353
9357b31c
HV		 1354 switch (qc->id) {
1355 case V4L2_CID_BRIGHTNESS:
10afbef1 1356 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
9357b31c
HV		 1357 case V4L2_CID_CONTRAST:
1358 case V4L2_CID_SATURATION:
10afbef1 1359 return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64);
9357b31c 1360 case V4L2_CID_HUE:
10afbef1 1361 return v4l2_ctrl_query_fill(qc, -128, 127, 1, 0);
9357b31c
HV		 1362 default:
1363 break;
1364 }
2a03f034 1365 if (is_cx2583x(state))
9357b31c 1366 return -EINVAL;
bd985160 1367
9357b31c
HV		 1368 switch (qc->id) {
1369 case V4L2_CID_AUDIO_VOLUME:
1370 return v4l2_ctrl_query_fill(qc, 0, 65535,
1371 65535 / 100, state->default_volume);
1372 case V4L2_CID_AUDIO_MUTE:
10afbef1 1373 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
9357b31c
HV		 1374 case V4L2_CID_AUDIO_BALANCE:
1375 case V4L2_CID_AUDIO_BASS:
1376 case V4L2_CID_AUDIO_TREBLE:
10afbef1 1377 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
9357b31c
HV		 1378 default:
1379 return -EINVAL;
1380 }
1381 return -EINVAL;
1382}
bd985160 1383
9357b31c
HV		 1384static int cx25840_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1385{
1386 struct cx25840_state *state = to_state(sd);
1387 struct i2c_client *client = v4l2_get_subdevdata(sd);
d92c20e0 1388
9357b31c
HV		 1389 if (state->radio == 0 && state->std == std)
1390 return 0;
1391 state->radio = 0;
1392 state->std = std;
1393 return set_v4lstd(client);
1394}
e2b8cf4c 1395
9357b31c
HV		 1396static int cx25840_s_radio(struct v4l2_subdev *sd)
1397{
1398 struct cx25840_state *state = to_state(sd);
d92c20e0 1399
9357b31c
HV		 1400 state->radio = 1;
1401 return 0;
1402}
bd985160 1403
5325b427
HV		 1404static int cx25840_s_video_routing(struct v4l2_subdev *sd,
1405 u32 input, u32 output, u32 config)
9357b31c
HV		 1406{
1407 struct cx25840_state *state = to_state(sd);
1408 struct i2c_client *client = v4l2_get_subdevdata(sd);
3faeeae4 1409
5325b427 1410 return set_input(client, input, state->aud_input);
9357b31c 1411}
bd985160 1412
5325b427
HV		 1413static int cx25840_s_audio_routing(struct v4l2_subdev *sd,
1414 u32 input, u32 output, u32 config)
9357b31c
HV		 1415{
1416 struct cx25840_state *state = to_state(sd);
1417 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1418
2a03f034 1419 if (is_cx2583x(state))
9357b31c 1420 return -EINVAL;
5325b427 1421 return set_input(client, state->vid_input, input);
9357b31c 1422}
bd985160 1423
9357b31c
HV		 1424static int cx25840_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1425{
1426 struct cx25840_state *state = to_state(sd);
1427 struct i2c_client *client = v4l2_get_subdevdata(sd);
a8bbf12a 1428
2a03f034 1429 if (!is_cx2583x(state))
9357b31c
HV		 1430 input_change(client);
1431 return 0;
1432}
a8bbf12a 1433
9357b31c
HV		 1434static int cx25840_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1435{
1436 struct cx25840_state *state = to_state(sd);
1437 struct i2c_client *client = v4l2_get_subdevdata(sd);
1438 u8 vpres = cx25840_read(client, 0x40e) & 0x20;
1439 u8 mode;
1440 int val = 0;
bd985160 1441
9357b31c
HV		 1442 if (state->radio)
1443 return 0;
bd985160 1444
9357b31c 1445 vt->signal = vpres ? 0xffff : 0x0;
2a03f034 1446 if (is_cx2583x(state))
9357b31c 1447 return 0;
3faeeae4 1448
9357b31c
HV		 1449 vt->capability |=
1450 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
1451 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
e2b8cf4c 1452
9357b31c 1453 mode = cx25840_read(client, 0x804);
bd985160 1454
9357b31c
HV		 1455 /* get rxsubchans and audmode */
1456 if ((mode & 0xf) == 1)
1457 val |= V4L2_TUNER_SUB_STEREO;
1458 else
1459 val |= V4L2_TUNER_SUB_MONO;
bd985160 1460
9357b31c
HV		 1461 if (mode == 2 || mode == 4)
1462 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
bd985160 1463
9357b31c
HV		 1464 if (mode & 0x10)
1465 val |= V4L2_TUNER_SUB_SAP;
bd985160 1466
9357b31c
HV		 1467 vt->rxsubchans = val;
1468 vt->audmode = state->audmode;
1469 return 0;
1470}
bd985160 1471
9357b31c
HV		 1472static int cx25840_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1473{
1474 struct cx25840_state *state = to_state(sd);
1475 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1476
2a03f034 1477 if (state->radio || is_cx2583x(state))
9357b31c 1478 return 0;
8a4b275f 1479
9357b31c 1480 switch (vt->audmode) {
bd985160 1481 case V4L2_TUNER_MODE_MONO:
8a4b275f
HV		 1482 /* mono -> mono
1483 stereo -> mono
1484 bilingual -> lang1 */
bd985160
HV		 1485 cx25840_and_or(client, 0x809, ~0xf, 0x00);
1486 break;
301e22d6 1487 case V4L2_TUNER_MODE_STEREO:
8a4b275f
HV		 1488 case V4L2_TUNER_MODE_LANG1:
1489 /* mono -> mono
1490 stereo -> stereo
1491 bilingual -> lang1 */
bd985160
HV		 1492 cx25840_and_or(client, 0x809, ~0xf, 0x04);
1493 break;
301e22d6 1494 case V4L2_TUNER_MODE_LANG1_LANG2:
8a4b275f
HV		 1495 /* mono -> mono
1496 stereo -> stereo
1497 bilingual -> lang1/lang2 */
1498 cx25840_and_or(client, 0x809, ~0xf, 0x07);
1499 break;
bd985160 1500 case V4L2_TUNER_MODE_LANG2:
8a4b275f 1501 /* mono -> mono
301e22d6 1502 stereo -> stereo
8a4b275f 1503 bilingual -> lang2 */
bd985160
HV		 1504 cx25840_and_or(client, 0x809, ~0xf, 0x01);
1505 break;
8a4b275f
HV		 1506 default:
1507 return -EINVAL;
9357b31c
HV		 1508 }
1509 state->audmode = vt->audmode;
1510 return 0;
1511}
bd985160 1512
9357b31c
HV		 1513static int cx25840_reset(struct v4l2_subdev *sd, u32 val)
1514{
1515 struct cx25840_state *state = to_state(sd);
1516 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1517
2a03f034 1518 if (is_cx2583x(state))
9357b31c 1519 cx25836_initialize(client);
2a03f034 1520 else if (is_cx2388x(state))
9357b31c 1521 cx23885_initialize(client);
2a03f034 1522 else if (is_cx231xx(state))
149783b5 1523 cx231xx_initialize(client);
9357b31c
HV		 1524 else
1525 cx25840_initialize(client);
1526 return 0;
1527}
bd985160 1528
aecde8b5 1529static int cx25840_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
9357b31c
HV		 1530{
1531 struct cx25840_state *state = to_state(sd);
1532 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1533
9357b31c
HV		 1534 return v4l2_chip_ident_i2c_client(client, chip, state->id, state->rev);
1535}
bd985160 1536
9357b31c
HV		 1537static int cx25840_log_status(struct v4l2_subdev *sd)
1538{
1539 struct cx25840_state *state = to_state(sd);
1540 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1541
9357b31c 1542 log_video_status(client);
2a03f034 1543 if (!is_cx2583x(state))
9357b31c 1544 log_audio_status(client);
3faeeae4 1545 return 0;
bd985160
HV		 1546}
1547
9357b31c
HV		 1548/* ----------------------------------------------------------------------- */
1549
1550static const struct v4l2_subdev_core_ops cx25840_core_ops = {
1551 .log_status = cx25840_log_status,
1552 .g_chip_ident = cx25840_g_chip_ident,
1553 .g_ctrl = cx25840_g_ctrl,
1554 .s_ctrl = cx25840_s_ctrl,
1555 .queryctrl = cx25840_queryctrl,
f41737ec 1556 .s_std = cx25840_s_std,
9357b31c 1557 .reset = cx25840_reset,
cc26b076 1558 .load_fw = cx25840_load_fw,
9357b31c
HV		 1559#ifdef CONFIG_VIDEO_ADV_DEBUG
1560 .g_register = cx25840_g_register,
1561 .s_register = cx25840_s_register,
1562#endif
1563};
1564
1565static const struct v4l2_subdev_tuner_ops cx25840_tuner_ops = {
1566 .s_frequency = cx25840_s_frequency,
9357b31c
HV		 1567 .s_radio = cx25840_s_radio,
1568 .g_tuner = cx25840_g_tuner,
1569 .s_tuner = cx25840_s_tuner,
1570};
1571
1572static const struct v4l2_subdev_audio_ops cx25840_audio_ops = {
1573 .s_clock_freq = cx25840_s_clock_freq,
1574 .s_routing = cx25840_s_audio_routing,
1575};
1576
1577static const struct v4l2_subdev_video_ops cx25840_video_ops = {
1578 .s_routing = cx25840_s_video_routing,
1579 .g_fmt = cx25840_g_fmt,
1580 .s_fmt = cx25840_s_fmt,
1581 .decode_vbi_line = cx25840_decode_vbi_line,
1582 .s_stream = cx25840_s_stream,
1583};
1584
1585static const struct v4l2_subdev_ops cx25840_ops = {
1586 .core = &cx25840_core_ops,
1587 .tuner = &cx25840_tuner_ops,
1588 .audio = &cx25840_audio_ops,
1589 .video = &cx25840_video_ops,
1590};
1591
bd985160
HV		 1592/* ----------------------------------------------------------------------- */
1593
c7dd1ecd
AW		 1594static u32 get_cx2388x_ident(struct i2c_client *client)
1595{
1596 u32 ret;
1597
1598 /* Come out of digital power down */
1599 cx25840_write(client, 0x000, 0);
1600
1601 if (cx25840_read4(client, 0x204) & 0xffff) {
1602 /* IR Tx Clk Divider register exists; chip must be a CX23885 */
1603 ret = V4L2_IDENT_CX23885_AV;
1604 } else if (cx25840_read4(client, 0x300) & 0x0fffffff) {
1605 /* DIF PLL Freq Word reg exists; chip must be a CX23888 */
1606 ret = V4L2_IDENT_CX23888_AV;
1607 } else {
1608 /* A CX23887 A/V core has neither IR nor DIF */
1609 ret = V4L2_IDENT_CX23887_AV;
1610 }
1611
1612 /* Back into digital power down */
1613 cx25840_write(client, 0x000, 2);
1614 return ret;
1615}
1616
d2653e92
JD		 1617static int cx25840_probe(struct i2c_client *client,
1618 const struct i2c_device_id *did)
bd985160 1619{
bd985160 1620 struct cx25840_state *state;
9357b31c 1621 struct v4l2_subdev *sd;
c7dd1ecd 1622 u32 id = V4L2_IDENT_NONE;
bd985160
HV		 1623 u16 device_id;
1624
188f3457
HV		 1625 /* Check if the adapter supports the needed features */
1626 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1627 return -EIO;
1628
21340ae0 1629 v4l_dbg(1, cx25840_debug, client, "detecting cx25840 client on address 0x%x\n", client->addr << 1);
bd985160
HV		 1630
1631 device_id = cx25840_read(client, 0x101) << 8;
1632 device_id |= cx25840_read(client, 0x100);
f234081b 1633 v4l_dbg(1, cx25840_debug, client, "device_id = 0x%04x\n", device_id);
bd985160
HV		 1634
1635 /* The high byte of the device ID should be
e2b8cf4c
HV		 1636 * 0x83 for the cx2583x and 0x84 for the cx2584x */
1637 if ((device_id & 0xff00) == 0x8300) {
1638 id = V4L2_IDENT_CX25836 + ((device_id >> 4) & 0xf) - 6;
c7dd1ecd 1639 } else if ((device_id & 0xff00) == 0x8400) {
e2b8cf4c 1640 id = V4L2_IDENT_CX25840 + ((device_id >> 4) & 0xf);
00ca7324 1641 } else if (device_id == 0x0000) {
c7dd1ecd 1642 id = get_cx2388x_ident(client);
149783b5 1643 } else if ((device_id & 0xfff0) == 0x5A30) {
c7dd1ecd
AW		 1644 /* The CX23100 (0x5A3C = 23100) doesn't have an A/V decoder */
1645 id = V4L2_IDENT_CX2310X_AV;
1646 } else if ((device_id & 0xff) == (device_id >> 8)) {
1647 v4l_err(client,
1648 "likely a confused/unresponsive cx2388[578] A/V decoder"
1649 " found @ 0x%x (%s)\n",
1650 client->addr << 1, client->adapter->name);
1651 v4l_err(client, "A method to reset it from the cx25840 driver"
1652 " software is not known at this time\n");
1653 return -ENODEV;
1654 } else {
b5fc7144 1655 v4l_dbg(1, cx25840_debug, client, "cx25840 not found\n");
188f3457 1656 return -ENODEV;
bd985160
HV		 1657 }
1658
21340ae0 1659 state = kzalloc(sizeof(struct cx25840_state), GFP_KERNEL);
9357b31c 1660 if (state == NULL)
21340ae0 1661 return -ENOMEM;
21340ae0 1662
9357b31c
HV		 1663 sd = &state->sd;
1664 v4l2_i2c_subdev_init(sd, client, &cx25840_ops);
c7dd1ecd
AW		 1665 switch (id) {
1666 case V4L2_IDENT_CX23885_AV:
c7dd1ecd
AW		 1667 v4l_info(client, "cx23885 A/V decoder found @ 0x%x (%s)\n",
1668 client->addr << 1, client->adapter->name);
1669 break;
1670 case V4L2_IDENT_CX23887_AV:
c7dd1ecd
AW		 1671 v4l_info(client, "cx23887 A/V decoder found @ 0x%x (%s)\n",
1672 client->addr << 1, client->adapter->name);
1673 break;
1674 case V4L2_IDENT_CX23888_AV:
c7dd1ecd
AW		 1675 v4l_info(client, "cx23888 A/V decoder found @ 0x%x (%s)\n",
1676 client->addr << 1, client->adapter->name);
1677 break;
1678 case V4L2_IDENT_CX2310X_AV:
c7dd1ecd
AW		 1679 v4l_info(client, "cx%d A/V decoder found @ 0x%x (%s)\n",
1680 device_id, client->addr << 1, client->adapter->name);
1681 break;
1682 case V4L2_IDENT_CX25840:
1683 case V4L2_IDENT_CX25841:
1684 case V4L2_IDENT_CX25842:
1685 case V4L2_IDENT_CX25843:
1686 /* Note: revision '(device_id & 0x0f) == 2' was never built. The
1687 marking skips from 0x1 == 22 to 0x3 == 23. */
1688 v4l_info(client, "cx25%3x-2%x found @ 0x%x (%s)\n",
1689 (device_id & 0xfff0) >> 4,
1690 (device_id & 0x0f) < 3 ? (device_id & 0x0f) + 1
1691 : (device_id & 0x0f),
1692 client->addr << 1, client->adapter->name);
1693 break;
1694 case V4L2_IDENT_CX25836:
1695 case V4L2_IDENT_CX25837:
c7dd1ecd
AW		 1696 default:
1697 v4l_info(client, "cx25%3x-%x found @ 0x%x (%s)\n",
1698 (device_id & 0xfff0) >> 4, device_id & 0x0f,
1699 client->addr << 1, client->adapter->name);
1700 break;
1701 }
bd985160 1702
21340ae0 1703 state->c = client;
a8bbf12a
HV		 1704 state->vid_input = CX25840_COMPOSITE7;
1705 state->aud_input = CX25840_AUDIO8;
3578d3dd 1706 state->audclk_freq = 48000;
a8bbf12a 1707 state->pvr150_workaround = 0;
8a4b275f 1708 state->audmode = V4L2_TUNER_MODE_LANG1;
87410dab 1709 state->unmute_volume = -1;
ca130eef
HV		 1710 state->default_volume = 228 - cx25840_read(client, 0x8d4);
1711 state->default_volume = ((state->default_volume / 2) + 23) << 9;
3e3bf277 1712 state->vbi_line_offset = 8;
e2b8cf4c 1713 state->id = id;
3434eb7e 1714 state->rev = device_id;
f234081b 1715
bd985160
HV		 1716 return 0;
1717}
1718
1a39275a 1719static int cx25840_remove(struct i2c_client *client)
bd985160 1720{
9357b31c
HV		 1721 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1722
1723 v4l2_device_unregister_subdev(sd);
1724 kfree(to_state(sd));
bd985160
HV		 1725 return 0;
1726}
1727
af294867
JD		 1728static const struct i2c_device_id cx25840_id[] = {
1729 { "cx25840", 0 },
1730 { }
1731};
1732MODULE_DEVICE_TABLE(i2c, cx25840_id);
1733
1a39275a
HV		 1734static struct v4l2_i2c_driver_data v4l2_i2c_data = {
1735 .name = "cx25840",
1a39275a
HV		 1736 .probe = cx25840_probe,
1737 .remove = cx25840_remove,
af294867 1738 .id_table = cx25840_id,
bd985160 1739};
Clone of davem's net-next-2.6 tree