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Merge branch 'for-2.6.36' of git://linux-nfs.org/~bfields/linux
[net-next-2.6.git] / drivers / media / video / cx25840 / cx25840-core.c
CommitLineData
bd985160
HV		 1/* cx25840 - Conexant CX25840 audio/video decoder driver
2 *
3 * Copyright (C) 2004 Ulf Eklund
4 *
5 * Based on the saa7115 driver and on the first verison of Chris Kennedy's
6 * cx25840 driver.
7 *
8 * Changes by Tyler Trafford <tatrafford@comcast.net>
9 * - cleanup/rewrite for V4L2 API (2005)
10 *
11 * VBI support by Hans Verkuil <hverkuil@xs4all.nl>.
12 *
3e3bf277
CN		 13 * NTSC sliced VBI support by Christopher Neufeld <television@cneufeld.ca>
14 * with additional fixes by Hans Verkuil <hverkuil@xs4all.nl>.
15 *
6d897616 16 * CX23885 support by Steven Toth <stoth@linuxtv.org>.
f234081b 17 *
52fd3dda
AW		 18 * CX2388[578] IRQ handling, IO Pin mux configuration and other small fixes are
19 * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
20 *
bd985160
HV		 21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License
23 * as published by the Free Software Foundation; either version 2
24 * of the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
34 */
35
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/videodev2.h>
41#include <linux/i2c.h>
f61b48f7 42#include <linux/delay.h>
bd985160 43#include <media/v4l2-common.h>
3434eb7e 44#include <media/v4l2-chip-ident.h>
b6198ade 45#include <media/v4l2-i2c-drv.h>
31bc09b5 46#include <media/cx25840.h>
bd985160 47
31bc09b5 48#include "cx25840-core.h"
bd985160
HV		 49
50MODULE_DESCRIPTION("Conexant CX25840 audio/video decoder driver");
1f4b3365 51MODULE_AUTHOR("Ulf Eklund, Chris Kennedy, Hans Verkuil, Tyler Trafford");
bd985160
HV		 52MODULE_LICENSE("GPL");
53
52fd3dda
AW		 54#define CX25840_VID_INT_STAT_REG 0x410
55#define CX25840_VID_INT_STAT_BITS 0x0000ffff
56#define CX25840_VID_INT_MASK_BITS 0xffff0000
57#define CX25840_VID_INT_MASK_SHFT 16
58#define CX25840_VID_INT_MASK_REG 0x412
59
60#define CX23885_AUD_MC_INT_MASK_REG 0x80c
61#define CX23885_AUD_MC_INT_STAT_BITS 0xffff0000
62#define CX23885_AUD_MC_INT_CTRL_BITS 0x0000ffff
63#define CX23885_AUD_MC_INT_STAT_SHFT 16
64
65#define CX25840_AUD_INT_CTRL_REG 0x812
66#define CX25840_AUD_INT_STAT_REG 0x813
67
68#define CX23885_PIN_CTRL_IRQ_REG 0x123
69#define CX23885_PIN_CTRL_IRQ_IR_STAT 0x40
70#define CX23885_PIN_CTRL_IRQ_AUD_STAT 0x20
71#define CX23885_PIN_CTRL_IRQ_VID_STAT 0x10
72
73#define CX25840_IR_STATS_REG 0x210
74#define CX25840_IR_IRQEN_REG 0x214
75
fe0d3dff 76static int cx25840_debug;
bd985160 77
b5fc7144 78module_param_named(debug,cx25840_debug, int, 0644);
bd985160 79
fac9e899 80MODULE_PARM_DESC(debug, "Debugging messages [0=Off (default) 1=On]");
bd985160 81
bd985160
HV		 82
83/* ----------------------------------------------------------------------- */
84
85int cx25840_write(struct i2c_client *client, u16 addr, u8 value)
86{
87 u8 buffer[3];
88 buffer[0] = addr >> 8;
89 buffer[1] = addr & 0xff;
90 buffer[2] = value;
91 return i2c_master_send(client, buffer, 3);
92}
93
94int cx25840_write4(struct i2c_client *client, u16 addr, u32 value)
95{
96 u8 buffer[6];
97 buffer[0] = addr >> 8;
98 buffer[1] = addr & 0xff;
4a56eb3f
HV		 99 buffer[2] = value & 0xff;
100 buffer[3] = (value >> 8) & 0xff;
101 buffer[4] = (value >> 16) & 0xff;
102 buffer[5] = value >> 24;
bd985160
HV		 103 return i2c_master_send(client, buffer, 6);
104}
105
106u8 cx25840_read(struct i2c_client * client, u16 addr)
107{
5f272644
AW		 108 struct i2c_msg msgs[2];
109 u8 tx_buf[2], rx_buf[1];
110
111 /* Write register address */
112 tx_buf[0] = addr >> 8;
113 tx_buf[1] = addr & 0xff;
114 msgs[0].addr = client->addr;
115 msgs[0].flags = 0;
116 msgs[0].len = 2;
117 msgs[0].buf = (char *) tx_buf;
118
119 /* Read data from register */
120 msgs[1].addr = client->addr;
121 msgs[1].flags = I2C_M_RD;
122 msgs[1].len = 1;
123 msgs[1].buf = (char *) rx_buf;
124
125 if (i2c_transfer(client->adapter, msgs, 2) < 2)
bd985160
HV		 126 return 0;
127
5f272644 128 return rx_buf[0];
bd985160
HV		 129}
130
131u32 cx25840_read4(struct i2c_client * client, u16 addr)
132{
5f272644
AW		 133 struct i2c_msg msgs[2];
134 u8 tx_buf[2], rx_buf[4];
135
136 /* Write register address */
137 tx_buf[0] = addr >> 8;
138 tx_buf[1] = addr & 0xff;
139 msgs[0].addr = client->addr;
140 msgs[0].flags = 0;
141 msgs[0].len = 2;
142 msgs[0].buf = (char *) tx_buf;
143
144 /* Read data from registers */
145 msgs[1].addr = client->addr;
146 msgs[1].flags = I2C_M_RD;
147 msgs[1].len = 4;
148 msgs[1].buf = (char *) rx_buf;
149
150 if (i2c_transfer(client->adapter, msgs, 2) < 2)
bd985160
HV		 151 return 0;
152
5f272644
AW		 153 return (rx_buf[3] << 24) | (rx_buf[2] << 16) | (rx_buf[1] << 8) |
154 rx_buf[0];
bd985160
HV		 155}
156
e2b8cf4c 157int cx25840_and_or(struct i2c_client *client, u16 addr, unsigned and_mask,
bd985160
HV		 158 u8 or_value)
159{
160 return cx25840_write(client, addr,
161 (cx25840_read(client, addr) & and_mask) |
162 or_value);
163}
164
52fd3dda
AW		 165int cx25840_and_or4(struct i2c_client *client, u16 addr, u32 and_mask,
166 u32 or_value)
167{
168 return cx25840_write4(client, addr,
169 (cx25840_read4(client, addr) & and_mask) |
170 or_value);
171}
172
bd985160
HV		 173/* ----------------------------------------------------------------------- */
174
a8bbf12a
HV		 175static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
176 enum cx25840_audio_input aud_input);
bd985160
HV		 177
178/* ----------------------------------------------------------------------- */
179
d06d5777
AW		 180static int cx23885_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
181 struct v4l2_subdev_io_pin_config *p)
182{
183 struct i2c_client *client = v4l2_get_subdevdata(sd);
184 int i;
185 u32 pin_ctrl;
186 u8 gpio_oe, gpio_data, strength;
187
188 pin_ctrl = cx25840_read4(client, 0x120);
189 gpio_oe = cx25840_read(client, 0x160);
190 gpio_data = cx25840_read(client, 0x164);
191
192 for (i = 0; i < n; i++) {
193 strength = p[i].strength;
194 if (strength > CX25840_PIN_DRIVE_FAST)
195 strength = CX25840_PIN_DRIVE_FAST;
196
197 switch (p[i].pin) {
198 case CX23885_PIN_IRQ_N_GPIO16:
199 if (p[i].function != CX23885_PAD_IRQ_N) {
200 /* GPIO16 */
201 pin_ctrl &= ~(0x1 << 25);
202 } else {
203 /* IRQ_N */
204 if (p[i].flags &
205 (V4L2_SUBDEV_IO_PIN_DISABLE |
206 V4L2_SUBDEV_IO_PIN_INPUT)) {
207 pin_ctrl &= ~(0x1 << 25);
208 } else {
209 pin_ctrl |= (0x1 << 25);
210 }
211 if (p[i].flags &
212 V4L2_SUBDEV_IO_PIN_ACTIVE_LOW) {
213 pin_ctrl &= ~(0x1 << 24);
214 } else {
215 pin_ctrl |= (0x1 << 24);
216 }
217 }
218 break;
219 case CX23885_PIN_IR_RX_GPIO19:
220 if (p[i].function != CX23885_PAD_GPIO19) {
221 /* IR_RX */
222 gpio_oe |= (0x1 << 0);
223 pin_ctrl &= ~(0x3 << 18);
224 pin_ctrl |= (strength << 18);
225 } else {
226 /* GPIO19 */
227 gpio_oe &= ~(0x1 << 0);
228 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
229 gpio_data &= ~(0x1 << 0);
230 gpio_data |= ((p[i].value & 0x1) << 0);
231 }
232 pin_ctrl &= ~(0x3 << 12);
233 pin_ctrl |= (strength << 12);
234 }
235 break;
236 case CX23885_PIN_IR_TX_GPIO20:
237 if (p[i].function != CX23885_PAD_GPIO20) {
238 /* IR_TX */
239 gpio_oe |= (0x1 << 1);
240 if (p[i].flags & V4L2_SUBDEV_IO_PIN_DISABLE)
241 pin_ctrl &= ~(0x1 << 10);
242 else
243 pin_ctrl |= (0x1 << 10);
244 pin_ctrl &= ~(0x3 << 18);
245 pin_ctrl |= (strength << 18);
246 } else {
247 /* GPIO20 */
248 gpio_oe &= ~(0x1 << 1);
249 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
250 gpio_data &= ~(0x1 << 1);
251 gpio_data |= ((p[i].value & 0x1) << 1);
252 }
253 pin_ctrl &= ~(0x3 << 12);
254 pin_ctrl |= (strength << 12);
255 }
256 break;
257 case CX23885_PIN_I2S_SDAT_GPIO21:
258 if (p[i].function != CX23885_PAD_GPIO21) {
259 /* I2S_SDAT */
260 /* TODO: Input or Output config */
261 gpio_oe |= (0x1 << 2);
262 pin_ctrl &= ~(0x3 << 22);
263 pin_ctrl |= (strength << 22);
264 } else {
265 /* GPIO21 */
266 gpio_oe &= ~(0x1 << 2);
267 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
268 gpio_data &= ~(0x1 << 2);
269 gpio_data |= ((p[i].value & 0x1) << 2);
270 }
271 pin_ctrl &= ~(0x3 << 12);
272 pin_ctrl |= (strength << 12);
273 }
274 break;
275 case CX23885_PIN_I2S_WCLK_GPIO22:
276 if (p[i].function != CX23885_PAD_GPIO22) {
277 /* I2S_WCLK */
278 /* TODO: Input or Output config */
279 gpio_oe |= (0x1 << 3);
280 pin_ctrl &= ~(0x3 << 22);
281 pin_ctrl |= (strength << 22);
282 } else {
283 /* GPIO22 */
284 gpio_oe &= ~(0x1 << 3);
285 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
286 gpio_data &= ~(0x1 << 3);
287 gpio_data |= ((p[i].value & 0x1) << 3);
288 }
289 pin_ctrl &= ~(0x3 << 12);
290 pin_ctrl |= (strength << 12);
291 }
292 break;
293 case CX23885_PIN_I2S_BCLK_GPIO23:
294 if (p[i].function != CX23885_PAD_GPIO23) {
295 /* I2S_BCLK */
296 /* TODO: Input or Output config */
297 gpio_oe |= (0x1 << 4);
298 pin_ctrl &= ~(0x3 << 22);
299 pin_ctrl |= (strength << 22);
300 } else {
301 /* GPIO23 */
302 gpio_oe &= ~(0x1 << 4);
303 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
304 gpio_data &= ~(0x1 << 4);
305 gpio_data |= ((p[i].value & 0x1) << 4);
306 }
307 pin_ctrl &= ~(0x3 << 12);
308 pin_ctrl |= (strength << 12);
309 }
310 break;
311 }
312 }
313
314 cx25840_write(client, 0x164, gpio_data);
315 cx25840_write(client, 0x160, gpio_oe);
316 cx25840_write4(client, 0x120, pin_ctrl);
317 return 0;
318}
319
320static int common_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
321 struct v4l2_subdev_io_pin_config *pincfg)
322{
323 struct cx25840_state *state = to_state(sd);
324
325 if (is_cx2388x(state))
326 return cx23885_s_io_pin_config(sd, n, pincfg);
327 return 0;
328}
329
330/* ----------------------------------------------------------------------- */
331
d92c20e0 332static void init_dll1(struct i2c_client *client)
bd985160
HV		 333{
334 /* This is the Hauppauge sequence used to
335 * initialize the Delay Lock Loop 1 (ADC DLL). */
336 cx25840_write(client, 0x159, 0x23);
337 cx25840_write(client, 0x15a, 0x87);
338 cx25840_write(client, 0x15b, 0x06);
38051450 339 udelay(10);
bd985160 340 cx25840_write(client, 0x159, 0xe1);
38051450 341 udelay(10);
bd985160
HV		 342 cx25840_write(client, 0x15a, 0x86);
343 cx25840_write(client, 0x159, 0xe0);
344 cx25840_write(client, 0x159, 0xe1);
345 cx25840_write(client, 0x15b, 0x10);
346}
347
d92c20e0 348static void init_dll2(struct i2c_client *client)
bd985160
HV		 349{
350 /* This is the Hauppauge sequence used to
351 * initialize the Delay Lock Loop 2 (ADC DLL). */
352 cx25840_write(client, 0x15d, 0xe3);
353 cx25840_write(client, 0x15e, 0x86);
354 cx25840_write(client, 0x15f, 0x06);
38051450 355 udelay(10);
bd985160
HV		 356 cx25840_write(client, 0x15d, 0xe1);
357 cx25840_write(client, 0x15d, 0xe0);
358 cx25840_write(client, 0x15d, 0xe1);
359}
360
e2b8cf4c
HV		 361static void cx25836_initialize(struct i2c_client *client)
362{
363 /* reset configuration is described on page 3-77 of the CX25836 datasheet */
364 /* 2. */
365 cx25840_and_or(client, 0x000, ~0x01, 0x01);
366 cx25840_and_or(client, 0x000, ~0x01, 0x00);
367 /* 3a. */
368 cx25840_and_or(client, 0x15a, ~0x70, 0x00);
369 /* 3b. */
370 cx25840_and_or(client, 0x15b, ~0x1e, 0x06);
371 /* 3c. */
372 cx25840_and_or(client, 0x159, ~0x02, 0x02);
373 /* 3d. */
38051450 374 udelay(10);
e2b8cf4c
HV		 375 /* 3e. */
376 cx25840_and_or(client, 0x159, ~0x02, 0x00);
377 /* 3f. */
378 cx25840_and_or(client, 0x159, ~0xc0, 0xc0);
379 /* 3g. */
380 cx25840_and_or(client, 0x159, ~0x01, 0x00);
381 cx25840_and_or(client, 0x159, ~0x01, 0x01);
382 /* 3h. */
383 cx25840_and_or(client, 0x15b, ~0x1e, 0x10);
384}
385
21340ae0
HV		 386static void cx25840_work_handler(struct work_struct *work)
387{
388 struct cx25840_state *state = container_of(work, struct cx25840_state, fw_work);
389 cx25840_loadfw(state->c);
390 wake_up(&state->fw_wait);
391}
392
89fc4eb9 393static void cx25840_initialize(struct i2c_client *client)
bd985160 394{
21340ae0 395 DEFINE_WAIT(wait);
9357b31c 396 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
21340ae0 397 struct workqueue_struct *q;
bd985160
HV		 398
399 /* datasheet startup in numbered steps, refer to page 3-77 */
400 /* 2. */
401 cx25840_and_or(client, 0x803, ~0x10, 0x00);
402 /* The default of this register should be 4, but I get 0 instead.
403 * Set this register to 4 manually. */
404 cx25840_write(client, 0x000, 0x04);
405 /* 3. */
406 init_dll1(client);
407 init_dll2(client);
408 cx25840_write(client, 0x136, 0x0a);
409 /* 4. */
410 cx25840_write(client, 0x13c, 0x01);
411 cx25840_write(client, 0x13c, 0x00);
412 /* 5. */
21340ae0
HV		 413 /* Do the firmware load in a work handler to prevent.
414 Otherwise the kernel is blocked waiting for the
415 bit-banging i2c interface to finish uploading the
416 firmware. */
417 INIT_WORK(&state->fw_work, cx25840_work_handler);
418 init_waitqueue_head(&state->fw_wait);
419 q = create_singlethread_workqueue("cx25840_fw");
420 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
421 queue_work(q, &state->fw_work);
422 schedule();
423 finish_wait(&state->fw_wait, &wait);
424 destroy_workqueue(q);
425
bd985160
HV		 426 /* 6. */
427 cx25840_write(client, 0x115, 0x8c);
428 cx25840_write(client, 0x116, 0x07);
429 cx25840_write(client, 0x118, 0x02);
430 /* 7. */
431 cx25840_write(client, 0x4a5, 0x80);
432 cx25840_write(client, 0x4a5, 0x00);
433 cx25840_write(client, 0x402, 0x00);
434 /* 8. */
73dcddc5
HV		 435 cx25840_and_or(client, 0x401, ~0x18, 0);
436 cx25840_and_or(client, 0x4a2, ~0x10, 0x10);
437 /* steps 8c and 8d are done in change_input() */
bd985160
HV		 438 /* 10. */
439 cx25840_write(client, 0x8d3, 0x1f);
440 cx25840_write(client, 0x8e3, 0x03);
441
cb5aa1c6 442 cx25840_std_setup(client);
bd985160
HV		 443
444 /* trial and error says these are needed to get audio */
445 cx25840_write(client, 0x914, 0xa0);
446 cx25840_write(client, 0x918, 0xa0);
447 cx25840_write(client, 0x919, 0x01);
448
449 /* stereo prefered */
450 cx25840_write(client, 0x809, 0x04);
451 /* AC97 shift */
452 cx25840_write(client, 0x8cf, 0x0f);
453
a8bbf12a
HV		 454 /* (re)set input */
455 set_input(client, state->vid_input, state->aud_input);
bd985160
HV		 456
457 /* start microcontroller */
458 cx25840_and_or(client, 0x803, ~0x10, 0x10);
459}
460
f234081b
ST		 461static void cx23885_initialize(struct i2c_client *client)
462{
463 DEFINE_WAIT(wait);
9357b31c 464 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
f234081b
ST		 465 struct workqueue_struct *q;
466
e283d780
AW		 467 /*
468 * Come out of digital power down
469 * The CX23888, at least, needs this, otherwise registers aside from
470 * 0x0-0x2 can't be read or written.
471 */
472 cx25840_write(client, 0x000, 0);
473
f234081b
ST		 474 /* Internal Reset */
475 cx25840_and_or(client, 0x102, ~0x01, 0x01);
476 cx25840_and_or(client, 0x102, ~0x01, 0x00);
477
478 /* Stop microcontroller */
479 cx25840_and_or(client, 0x803, ~0x10, 0x00);
480
481 /* DIF in reset? */
482 cx25840_write(client, 0x398, 0);
483
e283d780
AW		 484 /*
485 * Trust the default xtal, no division
486 * '885: 28.636363... MHz
487 * '887: 25.000000 MHz
488 * '888: 50.000000 MHz
489 */
f234081b
ST		 490 cx25840_write(client, 0x2, 0x76);
491
e283d780 492 /* Power up all the PLL's and DLL */
f234081b
ST		 493 cx25840_write(client, 0x1, 0x40);
494
e283d780
AW		 495 /* Sys PLL */
496 switch (state->id) {
497 case V4L2_IDENT_CX23888_AV:
498 /*
499 * 50.0 MHz * (0xb + 0xe8ba26/0x2000000)/4 = 5 * 28.636363 MHz
500 * 572.73 MHz before post divide
501 */
502 cx25840_write4(client, 0x11c, 0x00e8ba26);
503 cx25840_write4(client, 0x118, 0x0000040b);
504 break;
505 case V4L2_IDENT_CX23887_AV:
506 /*
507 * 25.0 MHz * (0x16 + 0x1d1744c/0x2000000)/4 = 5 * 28.636363 MHz
508 * 572.73 MHz before post divide
509 */
510 cx25840_write4(client, 0x11c, 0x01d1744c);
511 cx25840_write4(client, 0x118, 0x00000416);
512 break;
513 case V4L2_IDENT_CX23885_AV:
514 default:
515 /*
516 * 28.636363 MHz * (0x14 + 0x0/0x2000000)/4 = 5 * 28.636363 MHz
517 * 572.73 MHz before post divide
518 */
519 cx25840_write4(client, 0x11c, 0x00000000);
520 cx25840_write4(client, 0x118, 0x00000414);
521 break;
522 }
f234081b
ST		 523
524 /* Disable DIF bypass */
525 cx25840_write4(client, 0x33c, 0x00000001);
526
527 /* DIF Src phase inc */
528 cx25840_write4(client, 0x340, 0x0df7df83);
529
e283d780
AW		 530 /*
531 * Vid PLL
532 * Setup for a BT.656 pixel clock of 13.5 Mpixels/second
533 *
534 * 28.636363 MHz * (0xf + 0x02be2c9/0x2000000)/4 = 8 * 13.5 MHz
535 * 432.0 MHz before post divide
536 */
537 cx25840_write4(client, 0x10c, 0x002be2c9);
538 cx25840_write4(client, 0x108, 0x0000040f);
f234081b
ST		 539
540 /* Luma */
541 cx25840_write4(client, 0x414, 0x00107d12);
542
543 /* Chroma */
544 cx25840_write4(client, 0x420, 0x3d008282);
545
e283d780
AW		 546 /*
547 * Aux PLL
548 * Initial setup for audio sample clock:
549 * 48 ksps, 16 bits/sample, x160 multiplier = 122.88 MHz
550 * Intial I2S output/master clock(?):
551 * 48 ksps, 16 bits/sample, x16 multiplier = 12.288 MHz
552 */
553 switch (state->id) {
554 case V4L2_IDENT_CX23888_AV:
555 /*
556 * 50.0 MHz * (0x7 + 0x0bedfa4/0x2000000)/3 = 122.88 MHz
557 * 368.64 MHz before post divide
558 * 122.88 MHz / 0xa = 12.288 MHz
559 */
560 cx25840_write4(client, 0x114, 0x00bedfa4);
561 cx25840_write4(client, 0x110, 0x000a0307);
562 break;
563 case V4L2_IDENT_CX23887_AV:
564 /*
565 * 25.0 MHz * (0xe + 0x17dbf48/0x2000000)/3 = 122.88 MHz
566 * 368.64 MHz before post divide
567 * 122.88 MHz / 0xa = 12.288 MHz
568 */
569 cx25840_write4(client, 0x114, 0x017dbf48);
570 cx25840_write4(client, 0x110, 0x000a030e);
571 break;
572 case V4L2_IDENT_CX23885_AV:
573 default:
574 /*
575 * 28.636363 MHz * (0xc + 0x1bf0c9e/0x2000000)/3 = 122.88 MHz
576 * 368.64 MHz before post divide
577 * 122.88 MHz / 0xa = 12.288 MHz
578 */
579 cx25840_write4(client, 0x114, 0x01bf0c9e);
580 cx25840_write4(client, 0x110, 0x000a030c);
581 break;
582 };
f234081b
ST		 583
584 /* ADC2 input select */
585 cx25840_write(client, 0x102, 0x10);
586
587 /* VIN1 & VIN5 */
588 cx25840_write(client, 0x103, 0x11);
589
590 /* Enable format auto detect */
591 cx25840_write(client, 0x400, 0);
592 /* Fast subchroma lock */
593 /* White crush, Chroma AGC & Chroma Killer enabled */
594 cx25840_write(client, 0x401, 0xe8);
595
596 /* Select AFE clock pad output source */
597 cx25840_write(client, 0x144, 0x05);
598
f3d6f633
ST		 599 /* Drive GPIO2 direction and values for HVR1700
600 * where an onboard mux selects the output of demodulator
601 * vs the 417. Failure to set this results in no DTV.
602 * It's safe to set this across all Hauppauge boards
603 * currently, regardless of the board type.
604 */
605 cx25840_write(client, 0x160, 0x1d);
606 cx25840_write(client, 0x164, 0x00);
607
f234081b
ST		 608 /* Do the firmware load in a work handler to prevent.
609 Otherwise the kernel is blocked waiting for the
610 bit-banging i2c interface to finish uploading the
611 firmware. */
612 INIT_WORK(&state->fw_work, cx25840_work_handler);
613 init_waitqueue_head(&state->fw_wait);
614 q = create_singlethread_workqueue("cx25840_fw");
615 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
616 queue_work(q, &state->fw_work);
617 schedule();
618 finish_wait(&state->fw_wait, &wait);
619 destroy_workqueue(q);
620
cb5aa1c6 621 cx25840_std_setup(client);
f234081b
ST		 622
623 /* (re)set input */
624 set_input(client, state->vid_input, state->aud_input);
625
626 /* start microcontroller */
627 cx25840_and_or(client, 0x803, ~0x10, 0x10);
52fd3dda
AW		 628
629 /* Disable and clear video interrupts - we don't use them */
630 cx25840_write4(client, CX25840_VID_INT_STAT_REG, 0xffffffff);
631
632 /* Disable and clear audio interrupts - we don't use them */
633 cx25840_write(client, CX25840_AUD_INT_CTRL_REG, 0xff);
634 cx25840_write(client, CX25840_AUD_INT_STAT_REG, 0xff);
f234081b
ST		 635}
636
bd985160
HV		 637/* ----------------------------------------------------------------------- */
638
149783b5
SD		 639static void cx231xx_initialize(struct i2c_client *client)
640{
641 DEFINE_WAIT(wait);
642 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
643 struct workqueue_struct *q;
644
645 /* Internal Reset */
646 cx25840_and_or(client, 0x102, ~0x01, 0x01);
647 cx25840_and_or(client, 0x102, ~0x01, 0x00);
648
649 /* Stop microcontroller */
650 cx25840_and_or(client, 0x803, ~0x10, 0x00);
651
652 /* DIF in reset? */
653 cx25840_write(client, 0x398, 0);
654
655 /* Trust the default xtal, no division */
656 /* This changes for the cx23888 products */
657 cx25840_write(client, 0x2, 0x76);
658
659 /* Bring down the regulator for AUX clk */
660 cx25840_write(client, 0x1, 0x40);
661
662 /* Disable DIF bypass */
663 cx25840_write4(client, 0x33c, 0x00000001);
664
665 /* DIF Src phase inc */
666 cx25840_write4(client, 0x340, 0x0df7df83);
667
149783b5
SD		 668 /* Luma */
669 cx25840_write4(client, 0x414, 0x00107d12);
670
671 /* Chroma */
672 cx25840_write4(client, 0x420, 0x3d008282);
673
149783b5
SD		 674 /* ADC2 input select */
675 cx25840_write(client, 0x102, 0x10);
676
677 /* VIN1 & VIN5 */
678 cx25840_write(client, 0x103, 0x11);
679
680 /* Enable format auto detect */
681 cx25840_write(client, 0x400, 0);
682 /* Fast subchroma lock */
683 /* White crush, Chroma AGC & Chroma Killer enabled */
684 cx25840_write(client, 0x401, 0xe8);
685
149783b5
SD		 686 /* Do the firmware load in a work handler to prevent.
687 Otherwise the kernel is blocked waiting for the
688 bit-banging i2c interface to finish uploading the
689 firmware. */
690 INIT_WORK(&state->fw_work, cx25840_work_handler);
691 init_waitqueue_head(&state->fw_wait);
692 q = create_singlethread_workqueue("cx25840_fw");
693 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
694 queue_work(q, &state->fw_work);
695 schedule();
696 finish_wait(&state->fw_wait, &wait);
697 destroy_workqueue(q);
698
699 cx25840_std_setup(client);
700
701 /* (re)set input */
702 set_input(client, state->vid_input, state->aud_input);
703
704 /* start microcontroller */
705 cx25840_and_or(client, 0x803, ~0x10, 0x10);
706}
707
708/* ----------------------------------------------------------------------- */
709
cb5aa1c6
HV		 710void cx25840_std_setup(struct i2c_client *client)
711{
9357b31c 712 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
cb5aa1c6
HV		 713 v4l2_std_id std = state->std;
714 int hblank, hactive, burst, vblank, vactive, sc;
715 int vblank656, src_decimation;
716 int luma_lpf, uv_lpf, comb;
717 u32 pll_int, pll_frac, pll_post;
718
719 /* datasheet startup, step 8d */
720 if (std & ~V4L2_STD_NTSC)
721 cx25840_write(client, 0x49f, 0x11);
722 else
723 cx25840_write(client, 0x49f, 0x14);
724
725 if (std & V4L2_STD_625_50) {
726 hblank = 132;
727 hactive = 720;
728 burst = 93;
729 vblank = 36;
730 vactive = 580;
731 vblank656 = 40;
732 src_decimation = 0x21f;
733 luma_lpf = 2;
734
735 if (std & V4L2_STD_SECAM) {
736 uv_lpf = 0;
737 comb = 0;
738 sc = 0x0a425f;
739 } else if (std == V4L2_STD_PAL_Nc) {
740 uv_lpf = 1;
741 comb = 0x20;
742 sc = 556453;
743 } else {
744 uv_lpf = 1;
745 comb = 0x20;
746 sc = 688739;
747 }
748 } else {
749 hactive = 720;
750 hblank = 122;
751 vactive = 487;
752 luma_lpf = 1;
753 uv_lpf = 1;
754
755 src_decimation = 0x21f;
756 if (std == V4L2_STD_PAL_60) {
757 vblank = 26;
758 vblank656 = 26;
759 burst = 0x5b;
760 luma_lpf = 2;
761 comb = 0x20;
762 sc = 688739;
763 } else if (std == V4L2_STD_PAL_M) {
764 vblank = 20;
765 vblank656 = 24;
766 burst = 0x61;
767 comb = 0x20;
768 sc = 555452;
769 } else {
770 vblank = 26;
771 vblank656 = 26;
772 burst = 0x5b;
773 comb = 0x66;
774 sc = 556063;
775 }
776 }
777
778 /* DEBUG: Displays configured PLL frequency */
2a03f034 779 if (!is_cx231xx(state)) {
95b14fb2
MCC		 780 pll_int = cx25840_read(client, 0x108);
781 pll_frac = cx25840_read4(client, 0x10c) & 0x1ffffff;
782 pll_post = cx25840_read(client, 0x109);
cb5aa1c6 783 v4l_dbg(1, cx25840_debug, client,
95b14fb2
MCC		 784 "PLL regs = int: %u, frac: %u, post: %u\n",
785 pll_int, pll_frac, pll_post);
786
787 if (pll_post) {
788 int fin, fsc;
789 int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L;
790
791 pll /= pll_post;
792 v4l_dbg(1, cx25840_debug, client, "PLL = %d.%06d MHz\n",
793 pll / 1000000, pll % 1000000);
794 v4l_dbg(1, cx25840_debug, client, "PLL/8 = %d.%06d MHz\n",
795 pll / 8000000, (pll / 8) % 1000000);
796
797 fin = ((u64)src_decimation * pll) >> 12;
798 v4l_dbg(1, cx25840_debug, client,
799 "ADC Sampling freq = %d.%06d MHz\n",
800 fin / 1000000, fin % 1000000);
801
802 fsc = (((u64)sc) * pll) >> 24L;
803 v4l_dbg(1, cx25840_debug, client,
804 "Chroma sub-carrier freq = %d.%06d MHz\n",
805 fsc / 1000000, fsc % 1000000);
806
807 v4l_dbg(1, cx25840_debug, client, "hblank %i, hactive %i, "
808 "vblank %i, vactive %i, vblank656 %i, src_dec %i, "
809 "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, "
810 "sc 0x%06x\n",
811 hblank, hactive, vblank, vactive, vblank656,
812 src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
813 }
cb5aa1c6
HV		 814 }
815
816 /* Sets horizontal blanking delay and active lines */
817 cx25840_write(client, 0x470, hblank);
818 cx25840_write(client, 0x471,
819 0xff & (((hblank >> 8) & 0x3) | (hactive << 4)));
820 cx25840_write(client, 0x472, hactive >> 4);
821
822 /* Sets burst gate delay */
823 cx25840_write(client, 0x473, burst);
824
825 /* Sets vertical blanking delay and active duration */
826 cx25840_write(client, 0x474, vblank);
827 cx25840_write(client, 0x475,
828 0xff & (((vblank >> 8) & 0x3) | (vactive << 4)));
829 cx25840_write(client, 0x476, vactive >> 4);
830 cx25840_write(client, 0x477, vblank656);
831
832 /* Sets src decimation rate */
833 cx25840_write(client, 0x478, 0xff & src_decimation);
834 cx25840_write(client, 0x479, 0xff & (src_decimation >> 8));
835
836 /* Sets Luma and UV Low pass filters */
837 cx25840_write(client, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
838
839 /* Enables comb filters */
840 cx25840_write(client, 0x47b, comb);
841
842 /* Sets SC Step*/
843 cx25840_write(client, 0x47c, sc);
844 cx25840_write(client, 0x47d, 0xff & sc >> 8);
845 cx25840_write(client, 0x47e, 0xff & sc >> 16);
846
847 /* Sets VBI parameters */
848 if (std & V4L2_STD_625_50) {
849 cx25840_write(client, 0x47f, 0x01);
850 state->vbi_line_offset = 5;
851 } else {
852 cx25840_write(client, 0x47f, 0x00);
853 state->vbi_line_offset = 8;
854 }
855}
856
857/* ----------------------------------------------------------------------- */
858
bd985160
HV		 859static void input_change(struct i2c_client *client)
860{
9357b31c 861 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
081b496a 862 v4l2_std_id std = state->std;
bd985160 863
73dcddc5
HV		 864 /* Follow step 8c and 8d of section 3.16 in the cx25840 datasheet */
865 if (std & V4L2_STD_SECAM) {
866 cx25840_write(client, 0x402, 0);
867 }
868 else {
869 cx25840_write(client, 0x402, 0x04);
870 cx25840_write(client, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
871 }
872 cx25840_and_or(client, 0x401, ~0x60, 0);
873 cx25840_and_or(client, 0x401, ~0x60, 0x60);
82677618 874 cx25840_and_or(client, 0x810, ~0x01, 1);
73dcddc5 875
39c4ad6a
HV		 876 if (state->radio) {
877 cx25840_write(client, 0x808, 0xf9);
878 cx25840_write(client, 0x80b, 0x00);
879 }
880 else if (std & V4L2_STD_525_60) {
d97a11e0
HV		 881 /* Certain Hauppauge PVR150 models have a hardware bug
882 that causes audio to drop out. For these models the
883 audio standard must be set explicitly.
884 To be precise: it affects cards with tuner models
885 85, 99 and 112 (model numbers from tveeprom). */
886 int hw_fix = state->pvr150_workaround;
887
888 if (std == V4L2_STD_NTSC_M_JP) {
f95006f8 889 /* Japan uses EIAJ audio standard */
d97a11e0
HV		 890 cx25840_write(client, 0x808, hw_fix ? 0x2f : 0xf7);
891 } else if (std == V4L2_STD_NTSC_M_KR) {
892 /* South Korea uses A2 audio standard */
893 cx25840_write(client, 0x808, hw_fix ? 0x3f : 0xf8);
f95006f8
HV		 894 } else {
895 /* Others use the BTSC audio standard */
d97a11e0 896 cx25840_write(client, 0x808, hw_fix ? 0x1f : 0xf6);
f95006f8 897 }
bd985160 898 cx25840_write(client, 0x80b, 0x00);
839e4a4a 899 } else if (std & V4L2_STD_PAL) {
3c3099d5 900 /* Autodetect audio standard and audio system */
839e4a4a 901 cx25840_write(client, 0x808, 0xff);
3c3099d5
AP		 902 /* Since system PAL-L is pretty much non-existant and
903 not used by any public broadcast network, force
904 6.5 MHz carrier to be interpreted as System DK,
905 this avoids DK audio detection instability */
906 cx25840_write(client, 0x80b, 0x00);
839e4a4a 907 } else if (std & V4L2_STD_SECAM) {
3c3099d5 908 /* Autodetect audio standard and audio system */
839e4a4a 909 cx25840_write(client, 0x808, 0xff);
3c3099d5
AP		 910 /* If only one of SECAM-DK / SECAM-L is required, then force
911 6.5MHz carrier, else autodetect it */
912 if ((std & V4L2_STD_SECAM_DK) &&
913 !(std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
914 /* 6.5 MHz carrier to be interpreted as System DK */
915 cx25840_write(client, 0x80b, 0x00);
916 } else if (!(std & V4L2_STD_SECAM_DK) &&
917 (std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
918 /* 6.5 MHz carrier to be interpreted as System L */
919 cx25840_write(client, 0x80b, 0x08);
920 } else {
921 /* 6.5 MHz carrier to be autodetected */
922 cx25840_write(client, 0x80b, 0x10);
923 }
bd985160
HV		 924 }
925
82677618 926 cx25840_and_or(client, 0x810, ~0x01, 0);
bd985160
HV		 927}
928
a8bbf12a
HV		 929static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
930 enum cx25840_audio_input aud_input)
bd985160 931{
9357b31c 932 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
a8bbf12a
HV		 933 u8 is_composite = (vid_input >= CX25840_COMPOSITE1 &&
934 vid_input <= CX25840_COMPOSITE8);
fb29ab96
DW		 935 u8 is_component = (vid_input & CX25840_COMPONENT_ON) ==
936 CX25840_COMPONENT_ON;
937 int luma = vid_input & 0xf0;
938 int chroma = vid_input & 0xf00;
a8bbf12a 939 u8 reg;
bd985160 940
f234081b
ST		 941 v4l_dbg(1, cx25840_debug, client,
942 "decoder set video input %d, audio input %d\n",
943 vid_input, aud_input);
bd985160 944
f234081b
ST		 945 if (vid_input >= CX25840_VIN1_CH1) {
946 v4l_dbg(1, cx25840_debug, client, "vid_input 0x%x\n",
947 vid_input);
948 reg = vid_input & 0xff;
10e43d90
KK		 949 is_composite = !is_component &&
950 ((vid_input & CX25840_SVIDEO_ON) != CX25840_SVIDEO_ON);
f234081b
ST		 951
952 v4l_dbg(1, cx25840_debug, client, "mux cfg 0x%x comp=%d\n",
953 reg, is_composite);
fb29ab96 954 } else if (is_composite) {
a8bbf12a
HV		 955 reg = 0xf0 + (vid_input - CX25840_COMPOSITE1);
956 } else {
a8bbf12a 957 if ((vid_input & ~0xff0) ||
45270a15 958 luma < CX25840_SVIDEO_LUMA1 || luma > CX25840_SVIDEO_LUMA8 ||
a8bbf12a 959 chroma < CX25840_SVIDEO_CHROMA4 || chroma > CX25840_SVIDEO_CHROMA8) {
f234081b
ST		 960 v4l_err(client, "0x%04x is not a valid video input!\n",
961 vid_input);
a8bbf12a 962 return -EINVAL;
bd985160 963 }
a8bbf12a
HV		 964 reg = 0xf0 + ((luma - CX25840_SVIDEO_LUMA1) >> 4);
965 if (chroma >= CX25840_SVIDEO_CHROMA7) {
966 reg &= 0x3f;
967 reg |= (chroma - CX25840_SVIDEO_CHROMA7) >> 2;
bd985160 968 } else {
a8bbf12a
HV		 969 reg &= 0xcf;
970 reg |= (chroma - CX25840_SVIDEO_CHROMA4) >> 4;
bd985160 971 }
a8bbf12a 972 }
bd985160 973
f234081b
ST		 974 /* The caller has previously prepared the correct routing
975 * configuration in reg (for the cx23885) so we have no
976 * need to attempt to flip bits for earlier av decoders.
977 */
2a03f034 978 if (!is_cx2388x(state) && !is_cx231xx(state)) {
f234081b
ST		 979 switch (aud_input) {
980 case CX25840_AUDIO_SERIAL:
981 /* do nothing, use serial audio input */
982 break;
983 case CX25840_AUDIO4: reg &= ~0x30; break;
984 case CX25840_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
985 case CX25840_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
986 case CX25840_AUDIO7: reg &= ~0xc0; break;
987 case CX25840_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
bd985160 988
f234081b
ST		 989 default:
990 v4l_err(client, "0x%04x is not a valid audio input!\n",
991 aud_input);
992 return -EINVAL;
993 }
bd985160
HV		 994 }
995
a8bbf12a 996 cx25840_write(client, 0x103, reg);
f234081b 997
fb29ab96
DW		 998 /* Set INPUT_MODE to Composite, S-Video or Component */
999 if (is_component)
1000 cx25840_and_or(client, 0x401, ~0x6, 0x6);
1001 else
1002 cx25840_and_or(client, 0x401, ~0x6, is_composite ? 0 : 0x02);
f234081b 1003
2a03f034 1004 if (!is_cx2388x(state) && !is_cx231xx(state)) {
f234081b
ST		 1005 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
1006 cx25840_and_or(client, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0);
1007 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2&CH3 */
1008 if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
1009 cx25840_and_or(client, 0x102, ~0x4, 4);
1010 else
1011 cx25840_and_or(client, 0x102, ~0x4, 0);
1012 } else {
fb29ab96
DW		 1013 /* Set DUAL_MODE_ADC2 to 1 if component*/
1014 cx25840_and_or(client, 0x102, ~0x4, is_component ? 0x4 : 0x0);
1015 if (is_composite) {
f234081b
ST		 1016 /* ADC2 input select channel 2 */
1017 cx25840_and_or(client, 0x102, ~0x2, 0);
fb29ab96
DW		 1018 } else if (!is_component) {
1019 /* S-Video */
1020 if (chroma >= CX25840_SVIDEO_CHROMA7) {
1021 /* ADC2 input select channel 3 */
1022 cx25840_and_or(client, 0x102, ~0x2, 2);
1023 } else {
1024 /* ADC2 input select channel 2 */
1025 cx25840_and_or(client, 0x102, ~0x2, 0);
1026 }
1027 }
f234081b 1028 }
a8bbf12a
HV		 1029
1030 state->vid_input = vid_input;
1031 state->aud_input = aud_input;
2a03f034 1032 if (!is_cx2583x(state)) {
e2b8cf4c
HV		 1033 cx25840_audio_set_path(client);
1034 input_change(client);
1035 }
f234081b 1036
2a03f034 1037 if (is_cx2388x(state)) {
f234081b
ST		 1038 /* Audio channel 1 src : Parallel 1 */
1039 cx25840_write(client, 0x124, 0x03);
1040
1041 /* Select AFE clock pad output source */
1042 cx25840_write(client, 0x144, 0x05);
1043
1044 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
1045 cx25840_write(client, 0x914, 0xa0);
1046
149783b5
SD		 1047 /* I2S_OUT_CTL:
1048 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
1049 * I2S_OUT_MASTER_MODE = Master
1050 */
1051 cx25840_write(client, 0x918, 0xa0);
1052 cx25840_write(client, 0x919, 0x01);
2a03f034 1053 } else if (is_cx231xx(state)) {
149783b5
SD		 1054 /* Audio channel 1 src : Parallel 1 */
1055 cx25840_write(client, 0x124, 0x03);
1056
1057 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
1058 cx25840_write(client, 0x914, 0xa0);
1059
f234081b
ST		 1060 /* I2S_OUT_CTL:
1061 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
1062 * I2S_OUT_MASTER_MODE = Master
1063 */
1064 cx25840_write(client, 0x918, 0xa0);
1065 cx25840_write(client, 0x919, 0x01);
1066 }
1067
bd985160
HV		 1068 return 0;
1069}
1070
1071/* ----------------------------------------------------------------------- */
1072
081b496a 1073static int set_v4lstd(struct i2c_client *client)
bd985160 1074{
9357b31c 1075 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
081b496a
HV		 1076 u8 fmt = 0; /* zero is autodetect */
1077 u8 pal_m = 0;
468a0a54
MCC		 1078
1079 /* First tests should be against specific std */
081b496a
HV		 1080 if (state->std == V4L2_STD_NTSC_M_JP) {
1081 fmt = 0x2;
1082 } else if (state->std == V4L2_STD_NTSC_443) {
1083 fmt = 0x3;
1084 } else if (state->std == V4L2_STD_PAL_M) {
1085 pal_m = 1;
1086 fmt = 0x5;
1087 } else if (state->std == V4L2_STD_PAL_N) {
1088 fmt = 0x6;
1089 } else if (state->std == V4L2_STD_PAL_Nc) {
1090 fmt = 0x7;
1091 } else if (state->std == V4L2_STD_PAL_60) {
1092 fmt = 0x8;
468a0a54
MCC		 1093 } else {
1094 /* Then, test against generic ones */
081b496a
HV		 1095 if (state->std & V4L2_STD_NTSC)
1096 fmt = 0x1;
1097 else if (state->std & V4L2_STD_PAL)
1098 fmt = 0x4;
1099 else if (state->std & V4L2_STD_SECAM)
1100 fmt = 0xc;
bd985160
HV		 1101 }
1102
839e4a4a
MCC		 1103 v4l_dbg(1, cx25840_debug, client, "changing video std to fmt %i\n",fmt);
1104
73dcddc5
HV		 1105 /* Follow step 9 of section 3.16 in the cx25840 datasheet.
1106 Without this PAL may display a vertical ghosting effect.
1107 This happens for example with the Yuan MPC622. */
1108 if (fmt >= 4 && fmt < 8) {
1109 /* Set format to NTSC-M */
1110 cx25840_and_or(client, 0x400, ~0xf, 1);
1111 /* Turn off LCOMB */
1112 cx25840_and_or(client, 0x47b, ~6, 0);
1113 }
bd985160 1114 cx25840_and_or(client, 0x400, ~0xf, fmt);
081b496a 1115 cx25840_and_or(client, 0x403, ~0x3, pal_m);
cb5aa1c6 1116 cx25840_std_setup(client);
2a03f034 1117 if (!is_cx2583x(state))
081b496a 1118 input_change(client);
bd985160
HV		 1119 return 0;
1120}
1121
bd985160
HV		 1122/* ----------------------------------------------------------------------- */
1123
e34e658b 1124static int cx25840_s_ctrl(struct v4l2_ctrl *ctrl)
bd985160 1125{
e34e658b 1126 struct v4l2_subdev *sd = to_sd(ctrl);
9357b31c 1127 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160
HV		 1128
1129 switch (ctrl->id) {
bd985160 1130 case V4L2_CID_BRIGHTNESS:
e34e658b 1131 cx25840_write(client, 0x414, ctrl->val - 128);
bd985160
HV		 1132 break;
1133
1134 case V4L2_CID_CONTRAST:
e34e658b 1135 cx25840_write(client, 0x415, ctrl->val << 1);
bd985160
HV		 1136 break;
1137
1138 case V4L2_CID_SATURATION:
e34e658b
HV		 1139 cx25840_write(client, 0x420, ctrl->val << 1);
1140 cx25840_write(client, 0x421, ctrl->val << 1);
bd985160
HV		 1141 break;
1142
1143 case V4L2_CID_HUE:
e34e658b 1144 cx25840_write(client, 0x422, ctrl->val);
bd985160
HV		 1145 break;
1146
bd985160
HV		 1147 default:
1148 return -EINVAL;
1149 }
1150
1151 return 0;
1152}
1153
1154/* ----------------------------------------------------------------------- */
1155
96fd004f 1156static int cx25840_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
bd985160 1157{
9357b31c
HV		 1158 struct cx25840_state *state = to_state(sd);
1159 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1160 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
081b496a 1161 int is_50Hz = !(state->std & V4L2_STD_525_60);
bd985160 1162
96fd004f
HV		 1163 if (fmt->code != V4L2_MBUS_FMT_FIXED)
1164 return -EINVAL;
bd985160 1165
96fd004f
HV		 1166 fmt->field = V4L2_FIELD_INTERLACED;
1167 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
bd985160 1168
96fd004f
HV		 1169 Vsrc = (cx25840_read(client, 0x476) & 0x3f) << 4;
1170 Vsrc |= (cx25840_read(client, 0x475) & 0xf0) >> 4;
bd985160 1171
96fd004f
HV		 1172 Hsrc = (cx25840_read(client, 0x472) & 0x3f) << 4;
1173 Hsrc |= (cx25840_read(client, 0x471) & 0xf0) >> 4;
bd985160 1174
96fd004f 1175 Vlines = fmt->height + (is_50Hz ? 4 : 7);
bd985160 1176
96fd004f
HV		 1177 if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) ||
1178 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
1179 v4l_err(client, "%dx%d is not a valid size!\n",
1180 fmt->width, fmt->height);
1181 return -ERANGE;
1182 }
bd985160 1183
96fd004f
HV		 1184 HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20);
1185 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
1186 VSC &= 0x1fff;
1187
1188 if (fmt->width >= 385)
1189 filter = 0;
1190 else if (fmt->width > 192)
1191 filter = 1;
1192 else if (fmt->width > 96)
1193 filter = 2;
1194 else
1195 filter = 3;
1196
1197 v4l_dbg(1, cx25840_debug, client, "decoder set size %dx%d -> scale %ux%u\n",
1198 fmt->width, fmt->height, HSC, VSC);
1199
1200 /* HSCALE=HSC */
1201 cx25840_write(client, 0x418, HSC & 0xff);
1202 cx25840_write(client, 0x419, (HSC >> 8) & 0xff);
1203 cx25840_write(client, 0x41a, HSC >> 16);
1204 /* VSCALE=VSC */
1205 cx25840_write(client, 0x41c, VSC & 0xff);
1206 cx25840_write(client, 0x41d, VSC >> 8);
1207 /* VS_INTRLACE=1 VFILT=filter */
1208 cx25840_write(client, 0x41e, 0x8 | filter);
1209 return 0;
1210}
1211
bd985160
HV		 1212/* ----------------------------------------------------------------------- */
1213
1a39275a
HV		 1214static void log_video_status(struct i2c_client *client)
1215{
1216 static const char *const fmt_strs[] = {
1217 "0x0",
1218 "NTSC-M", "NTSC-J", "NTSC-4.43",
1219 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1220 "0x9", "0xA", "0xB",
1221 "SECAM",
1222 "0xD", "0xE", "0xF"
1223 };
1224
9357b31c 1225 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1a39275a
HV		 1226 u8 vidfmt_sel = cx25840_read(client, 0x400) & 0xf;
1227 u8 gen_stat1 = cx25840_read(client, 0x40d);
1228 u8 gen_stat2 = cx25840_read(client, 0x40e);
1229 int vid_input = state->vid_input;
1230
1231 v4l_info(client, "Video signal: %spresent\n",
1232 (gen_stat2 & 0x20) ? "" : "not ");
1233 v4l_info(client, "Detected format: %s\n",
1234 fmt_strs[gen_stat1 & 0xf]);
1235
1236 v4l_info(client, "Specified standard: %s\n",
1237 vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection");
1238
1239 if (vid_input >= CX25840_COMPOSITE1 &&
1240 vid_input <= CX25840_COMPOSITE8) {
1241 v4l_info(client, "Specified video input: Composite %d\n",
1242 vid_input - CX25840_COMPOSITE1 + 1);
1243 } else {
1244 v4l_info(client, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
1245 (vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8);
1246 }
1247
1248 v4l_info(client, "Specified audioclock freq: %d Hz\n", state->audclk_freq);
1249}
1250
1251/* ----------------------------------------------------------------------- */
1252
1253static void log_audio_status(struct i2c_client *client)
1254{
9357b31c 1255 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1a39275a
HV		 1256 u8 download_ctl = cx25840_read(client, 0x803);
1257 u8 mod_det_stat0 = cx25840_read(client, 0x804);
1258 u8 mod_det_stat1 = cx25840_read(client, 0x805);
1259 u8 audio_config = cx25840_read(client, 0x808);
1260 u8 pref_mode = cx25840_read(client, 0x809);
1261 u8 afc0 = cx25840_read(client, 0x80b);
1262 u8 mute_ctl = cx25840_read(client, 0x8d3);
1263 int aud_input = state->aud_input;
1264 char *p;
1265
1266 switch (mod_det_stat0) {
1267 case 0x00: p = "mono"; break;
1268 case 0x01: p = "stereo"; break;
1269 case 0x02: p = "dual"; break;
1270 case 0x04: p = "tri"; break;
1271 case 0x10: p = "mono with SAP"; break;
1272 case 0x11: p = "stereo with SAP"; break;
1273 case 0x12: p = "dual with SAP"; break;
1274 case 0x14: p = "tri with SAP"; break;
1275 case 0xfe: p = "forced mode"; break;
1276 default: p = "not defined";
1277 }
1278 v4l_info(client, "Detected audio mode: %s\n", p);
1279
1280 switch (mod_det_stat1) {
1281 case 0x00: p = "not defined"; break;
1282 case 0x01: p = "EIAJ"; break;
1283 case 0x02: p = "A2-M"; break;
1284 case 0x03: p = "A2-BG"; break;
1285 case 0x04: p = "A2-DK1"; break;
1286 case 0x05: p = "A2-DK2"; break;
1287 case 0x06: p = "A2-DK3"; break;
1288 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1289 case 0x08: p = "AM-L"; break;
1290 case 0x09: p = "NICAM-BG"; break;
1291 case 0x0a: p = "NICAM-DK"; break;
1292 case 0x0b: p = "NICAM-I"; break;
1293 case 0x0c: p = "NICAM-L"; break;
1294 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1295 case 0x0e: p = "IF FM Radio"; break;
1296 case 0x0f: p = "BTSC"; break;
1297 case 0x10: p = "high-deviation FM"; break;
1298 case 0x11: p = "very high-deviation FM"; break;
1299 case 0xfd: p = "unknown audio standard"; break;
1300 case 0xfe: p = "forced audio standard"; break;
1301 case 0xff: p = "no detected audio standard"; break;
1302 default: p = "not defined";
1303 }
1304 v4l_info(client, "Detected audio standard: %s\n", p);
1a39275a
HV		 1305 v4l_info(client, "Audio microcontroller: %s\n",
1306 (download_ctl & 0x10) ?
1307 ((mute_ctl & 0x2) ? "detecting" : "running") : "stopped");
1308
1309 switch (audio_config >> 4) {
1310 case 0x00: p = "undefined"; break;
1311 case 0x01: p = "BTSC"; break;
1312 case 0x02: p = "EIAJ"; break;
1313 case 0x03: p = "A2-M"; break;
1314 case 0x04: p = "A2-BG"; break;
1315 case 0x05: p = "A2-DK1"; break;
1316 case 0x06: p = "A2-DK2"; break;
1317 case 0x07: p = "A2-DK3"; break;
1318 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1319 case 0x09: p = "AM-L"; break;
1320 case 0x0a: p = "NICAM-BG"; break;
1321 case 0x0b: p = "NICAM-DK"; break;
1322 case 0x0c: p = "NICAM-I"; break;
1323 case 0x0d: p = "NICAM-L"; break;
1324 case 0x0e: p = "FM radio"; break;
1325 case 0x0f: p = "automatic detection"; break;
1326 default: p = "undefined";
1327 }
1328 v4l_info(client, "Configured audio standard: %s\n", p);
1329
1330 if ((audio_config >> 4) < 0xF) {
1331 switch (audio_config & 0xF) {
1332 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1333 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1334 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1335 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1336 case 0x04: p = "STEREO"; break;
1337 case 0x05: p = "DUAL1 (AB)"; break;
1338 case 0x06: p = "DUAL2 (AC) (FM)"; break;
1339 case 0x07: p = "DUAL3 (BC) (FM)"; break;
1340 case 0x08: p = "DUAL4 (AC) (AM)"; break;
1341 case 0x09: p = "DUAL5 (BC) (AM)"; break;
1342 case 0x0a: p = "SAP"; break;
1343 default: p = "undefined";
1344 }
1345 v4l_info(client, "Configured audio mode: %s\n", p);
1346 } else {
1347 switch (audio_config & 0xF) {
1348 case 0x00: p = "BG"; break;
1349 case 0x01: p = "DK1"; break;
1350 case 0x02: p = "DK2"; break;
1351 case 0x03: p = "DK3"; break;
1352 case 0x04: p = "I"; break;
1353 case 0x05: p = "L"; break;
1354 case 0x06: p = "BTSC"; break;
1355 case 0x07: p = "EIAJ"; break;
1356 case 0x08: p = "A2-M"; break;
1357 case 0x09: p = "FM Radio"; break;
1358 case 0x0f: p = "automatic standard and mode detection"; break;
1359 default: p = "undefined";
1360 }
1361 v4l_info(client, "Configured audio system: %s\n", p);
1362 }
1363
1364 if (aud_input) {
1365 v4l_info(client, "Specified audio input: Tuner (In%d)\n", aud_input);
1366 } else {
1367 v4l_info(client, "Specified audio input: External\n");
1368 }
1369
1370 switch (pref_mode & 0xf) {
1371 case 0: p = "mono/language A"; break;
1372 case 1: p = "language B"; break;
1373 case 2: p = "language C"; break;
1374 case 3: p = "analog fallback"; break;
1375 case 4: p = "stereo"; break;
1376 case 5: p = "language AC"; break;
1377 case 6: p = "language BC"; break;
1378 case 7: p = "language AB"; break;
1379 default: p = "undefined";
1380 }
1381 v4l_info(client, "Preferred audio mode: %s\n", p);
1382
1383 if ((audio_config & 0xf) == 0xf) {
1384 switch ((afc0 >> 3) & 0x3) {
1385 case 0: p = "system DK"; break;
1386 case 1: p = "system L"; break;
1387 case 2: p = "autodetect"; break;
1388 default: p = "undefined";
1389 }
1390 v4l_info(client, "Selected 65 MHz format: %s\n", p);
1391
1392 switch (afc0 & 0x7) {
1393 case 0: p = "chroma"; break;
1394 case 1: p = "BTSC"; break;
1395 case 2: p = "EIAJ"; break;
1396 case 3: p = "A2-M"; break;
1397 case 4: p = "autodetect"; break;
1398 default: p = "undefined";
1399 }
1400 v4l_info(client, "Selected 45 MHz format: %s\n", p);
1401 }
1402}
1403
1404/* ----------------------------------------------------------------------- */
1405
cc26b076 1406/* This load_fw operation must be called to load the driver's firmware.
6ca187ab
HV		 1407 Without this the audio standard detection will fail and you will
1408 only get mono.
1409
1410 Since loading the firmware is often problematic when the driver is
1411 compiled into the kernel I recommend postponing calling this function
1412 until the first open of the video device. Another reason for
1413 postponing it is that loading this firmware takes a long time (seconds)
1414 due to the slow i2c bus speed. So it will speed up the boot process if
1415 you can avoid loading the fw as long as the video device isn't used. */
cc26b076 1416static int cx25840_load_fw(struct v4l2_subdev *sd)
bd985160 1417{
9357b31c
HV		 1418 struct cx25840_state *state = to_state(sd);
1419 struct i2c_client *client = v4l2_get_subdevdata(sd);
c976bc82
HV		 1420
1421 if (!state->is_initialized) {
cc26b076 1422 /* initialize and load firmware */
c976bc82 1423 state->is_initialized = 1;
2a03f034 1424 if (is_cx2583x(state))
c976bc82 1425 cx25836_initialize(client);
2a03f034 1426 else if (is_cx2388x(state))
f234081b 1427 cx23885_initialize(client);
2a03f034 1428 else if (is_cx231xx(state))
149783b5 1429 cx231xx_initialize(client);
c976bc82 1430 else
89fc4eb9 1431 cx25840_initialize(client);
c976bc82 1432 }
9357b31c
HV		 1433 return 0;
1434}
c976bc82 1435
bd985160 1436#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 1437static int cx25840_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
9357b31c
HV		 1438{
1439 struct i2c_client *client = v4l2_get_subdevdata(sd);
f234081b 1440
aecde8b5 1441 if (!v4l2_chip_match_i2c_client(client, &reg->match))
9357b31c
HV		 1442 return -EINVAL;
1443 if (!capable(CAP_SYS_ADMIN))
1444 return -EPERM;
aecde8b5 1445 reg->size = 1;
9357b31c
HV		 1446 reg->val = cx25840_read(client, reg->reg & 0x0fff);
1447 return 0;
1448}
1449
aecde8b5 1450static int cx25840_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
9357b31c
HV		 1451{
1452 struct i2c_client *client = v4l2_get_subdevdata(sd);
1453
aecde8b5 1454 if (!v4l2_chip_match_i2c_client(client, &reg->match))
9357b31c
HV		 1455 return -EINVAL;
1456 if (!capable(CAP_SYS_ADMIN))
1457 return -EPERM;
1458 cx25840_write(client, reg->reg & 0x0fff, reg->val & 0xff);
1459 return 0;
1460}
bd985160
HV		 1461#endif
1462
3ccc646b
AW		 1463static int cx25840_s_audio_stream(struct v4l2_subdev *sd, int enable)
1464{
1465 struct cx25840_state *state = to_state(sd);
1466 struct i2c_client *client = v4l2_get_subdevdata(sd);
1467 u8 v;
1468
1469 if (is_cx2583x(state) || is_cx2388x(state) || is_cx231xx(state))
1470 return 0;
1471
1472 v4l_dbg(1, cx25840_debug, client, "%s audio output\n",
1473 enable ? "enable" : "disable");
1474
1475 if (enable) {
1476 v = cx25840_read(client, 0x115) | 0x80;
1477 cx25840_write(client, 0x115, v);
1478 v = cx25840_read(client, 0x116) | 0x03;
1479 cx25840_write(client, 0x116, v);
1480 } else {
1481 v = cx25840_read(client, 0x115) & ~(0x80);
1482 cx25840_write(client, 0x115, v);
1483 v = cx25840_read(client, 0x116) & ~(0x03);
1484 cx25840_write(client, 0x116, v);
1485 }
1486 return 0;
1487}
1488
9357b31c
HV		 1489static int cx25840_s_stream(struct v4l2_subdev *sd, int enable)
1490{
1491 struct cx25840_state *state = to_state(sd);
1492 struct i2c_client *client = v4l2_get_subdevdata(sd);
3ccc646b 1493 u8 v;
bd985160 1494
3ccc646b 1495 v4l_dbg(1, cx25840_debug, client, "%s video output\n",
9357b31c
HV		 1496 enable ? "enable" : "disable");
1497 if (enable) {
2a03f034 1498 if (is_cx2388x(state) || is_cx231xx(state)) {
3ccc646b 1499 v = cx25840_read(client, 0x421) | 0x0b;
f234081b
ST		 1500 cx25840_write(client, 0x421, v);
1501 } else {
3ccc646b
AW		 1502 v = cx25840_read(client, 0x115) | 0x0c;
1503 cx25840_write(client, 0x115, v);
1504 v = cx25840_read(client, 0x116) | 0x04;
1505 cx25840_write(client, 0x116, v);
f234081b 1506 }
9357b31c 1507 } else {
2a03f034 1508 if (is_cx2388x(state) || is_cx231xx(state)) {
3ccc646b 1509 v = cx25840_read(client, 0x421) & ~(0x0b);
f234081b
ST		 1510 cx25840_write(client, 0x421, v);
1511 } else {
3ccc646b
AW		 1512 v = cx25840_read(client, 0x115) & ~(0x0c);
1513 cx25840_write(client, 0x115, v);
1514 v = cx25840_read(client, 0x116) & ~(0x04);
1515 cx25840_write(client, 0x116, v);
f234081b 1516 }
9357b31c
HV		 1517 }
1518 return 0;
1519}
bd985160 1520
9357b31c
HV		 1521static int cx25840_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1522{
1523 struct cx25840_state *state = to_state(sd);
1524 struct i2c_client *client = v4l2_get_subdevdata(sd);
d92c20e0 1525
9357b31c
HV		 1526 if (state->radio == 0 && state->std == std)
1527 return 0;
1528 state->radio = 0;
1529 state->std = std;
1530 return set_v4lstd(client);
1531}
e2b8cf4c 1532
9357b31c
HV		 1533static int cx25840_s_radio(struct v4l2_subdev *sd)
1534{
1535 struct cx25840_state *state = to_state(sd);
d92c20e0 1536
9357b31c
HV		 1537 state->radio = 1;
1538 return 0;
1539}
bd985160 1540
5325b427
HV		 1541static int cx25840_s_video_routing(struct v4l2_subdev *sd,
1542 u32 input, u32 output, u32 config)
9357b31c
HV		 1543{
1544 struct cx25840_state *state = to_state(sd);
1545 struct i2c_client *client = v4l2_get_subdevdata(sd);
3faeeae4 1546
5325b427 1547 return set_input(client, input, state->aud_input);
9357b31c 1548}
bd985160 1549
5325b427
HV		 1550static int cx25840_s_audio_routing(struct v4l2_subdev *sd,
1551 u32 input, u32 output, u32 config)
9357b31c
HV		 1552{
1553 struct cx25840_state *state = to_state(sd);
1554 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1555
2a03f034 1556 if (is_cx2583x(state))
9357b31c 1557 return -EINVAL;
5325b427 1558 return set_input(client, state->vid_input, input);
9357b31c 1559}
bd985160 1560
9357b31c
HV		 1561static int cx25840_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1562{
1563 struct cx25840_state *state = to_state(sd);
1564 struct i2c_client *client = v4l2_get_subdevdata(sd);
a8bbf12a 1565
2a03f034 1566 if (!is_cx2583x(state))
9357b31c
HV		 1567 input_change(client);
1568 return 0;
1569}
a8bbf12a 1570
9357b31c
HV		 1571static int cx25840_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1572{
1573 struct cx25840_state *state = to_state(sd);
1574 struct i2c_client *client = v4l2_get_subdevdata(sd);
1575 u8 vpres = cx25840_read(client, 0x40e) & 0x20;
1576 u8 mode;
1577 int val = 0;
bd985160 1578
9357b31c
HV		 1579 if (state->radio)
1580 return 0;
bd985160 1581
9357b31c 1582 vt->signal = vpres ? 0xffff : 0x0;
2a03f034 1583 if (is_cx2583x(state))
9357b31c 1584 return 0;
3faeeae4 1585
9357b31c
HV		 1586 vt->capability |=
1587 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
1588 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
e2b8cf4c 1589
9357b31c 1590 mode = cx25840_read(client, 0x804);
bd985160 1591
9357b31c
HV		 1592 /* get rxsubchans and audmode */
1593 if ((mode & 0xf) == 1)
1594 val |= V4L2_TUNER_SUB_STEREO;
1595 else
1596 val |= V4L2_TUNER_SUB_MONO;
bd985160 1597
9357b31c
HV		 1598 if (mode == 2 || mode == 4)
1599 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
bd985160 1600
9357b31c
HV		 1601 if (mode & 0x10)
1602 val |= V4L2_TUNER_SUB_SAP;
bd985160 1603
9357b31c
HV		 1604 vt->rxsubchans = val;
1605 vt->audmode = state->audmode;
1606 return 0;
1607}
bd985160 1608
9357b31c
HV		 1609static int cx25840_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1610{
1611 struct cx25840_state *state = to_state(sd);
1612 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1613
2a03f034 1614 if (state->radio || is_cx2583x(state))
9357b31c 1615 return 0;
8a4b275f 1616
9357b31c 1617 switch (vt->audmode) {
bd985160 1618 case V4L2_TUNER_MODE_MONO:
8a4b275f
HV		 1619 /* mono -> mono
1620 stereo -> mono
1621 bilingual -> lang1 */
bd985160
HV		 1622 cx25840_and_or(client, 0x809, ~0xf, 0x00);
1623 break;
301e22d6 1624 case V4L2_TUNER_MODE_STEREO:
8a4b275f
HV		 1625 case V4L2_TUNER_MODE_LANG1:
1626 /* mono -> mono
1627 stereo -> stereo
1628 bilingual -> lang1 */
bd985160
HV		 1629 cx25840_and_or(client, 0x809, ~0xf, 0x04);
1630 break;
301e22d6 1631 case V4L2_TUNER_MODE_LANG1_LANG2:
8a4b275f
HV		 1632 /* mono -> mono
1633 stereo -> stereo
1634 bilingual -> lang1/lang2 */
1635 cx25840_and_or(client, 0x809, ~0xf, 0x07);
1636 break;
bd985160 1637 case V4L2_TUNER_MODE_LANG2:
8a4b275f 1638 /* mono -> mono
301e22d6 1639 stereo -> stereo
8a4b275f 1640 bilingual -> lang2 */
bd985160
HV		 1641 cx25840_and_or(client, 0x809, ~0xf, 0x01);
1642 break;
8a4b275f
HV		 1643 default:
1644 return -EINVAL;
9357b31c
HV		 1645 }
1646 state->audmode = vt->audmode;
1647 return 0;
1648}
bd985160 1649
9357b31c
HV		 1650static int cx25840_reset(struct v4l2_subdev *sd, u32 val)
1651{
1652 struct cx25840_state *state = to_state(sd);
1653 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1654
2a03f034 1655 if (is_cx2583x(state))
9357b31c 1656 cx25836_initialize(client);
2a03f034 1657 else if (is_cx2388x(state))
9357b31c 1658 cx23885_initialize(client);
2a03f034 1659 else if (is_cx231xx(state))
149783b5 1660 cx231xx_initialize(client);
9357b31c
HV		 1661 else
1662 cx25840_initialize(client);
1663 return 0;
1664}
bd985160 1665
aecde8b5 1666static int cx25840_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
9357b31c
HV		 1667{
1668 struct cx25840_state *state = to_state(sd);
1669 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1670
9357b31c
HV		 1671 return v4l2_chip_ident_i2c_client(client, chip, state->id, state->rev);
1672}
bd985160 1673
9357b31c
HV		 1674static int cx25840_log_status(struct v4l2_subdev *sd)
1675{
1676 struct cx25840_state *state = to_state(sd);
1677 struct i2c_client *client = v4l2_get_subdevdata(sd);
bd985160 1678
9357b31c 1679 log_video_status(client);
2a03f034 1680 if (!is_cx2583x(state))
9357b31c 1681 log_audio_status(client);
52fd3dda 1682 cx25840_ir_log_status(sd);
e34e658b 1683 v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
3faeeae4 1684 return 0;
bd985160
HV		 1685}
1686
72c851b0
HV		 1687static int cx25840_s_config(struct v4l2_subdev *sd, int irq, void *platform_data)
1688{
1689 struct cx25840_state *state = to_state(sd);
1690 struct i2c_client *client = v4l2_get_subdevdata(sd);
1691
1692 if (platform_data) {
1693 struct cx25840_platform_data *pdata = platform_data;
1694
1695 state->pvr150_workaround = pdata->pvr150_workaround;
1696 set_input(client, state->vid_input, state->aud_input);
1697 }
1698 return 0;
1699}
1700
52fd3dda
AW		 1701static int cx23885_irq_handler(struct v4l2_subdev *sd, u32 status,
1702 bool *handled)
1703{
1704 struct cx25840_state *state = to_state(sd);
1705 struct i2c_client *c = v4l2_get_subdevdata(sd);
1706 u8 irq_stat, aud_stat, aud_en, ir_stat, ir_en;
1707 u32 vid_stat, aud_mc_stat;
1708 bool block_handled;
1709 int ret = 0;
1710
1711 irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
1712 v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (entry): %s %s %s\n",
1713 irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : " ",
1714 irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : " ",
1715 irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : " ");
1716
1717 if ((is_cx23885(state) || is_cx23887(state))) {
1718 ir_stat = cx25840_read(c, CX25840_IR_STATS_REG);
1719 ir_en = cx25840_read(c, CX25840_IR_IRQEN_REG);
1720 v4l_dbg(2, cx25840_debug, c,
1721 "AV Core ir IRQ status: %#04x disables: %#04x\n",
1722 ir_stat, ir_en);
1723 if (irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT) {
1724 block_handled = false;
1725 ret = cx25840_ir_irq_handler(sd,
1726 status, &block_handled);
1727 if (block_handled)
1728 *handled = true;
1729 }
1730 }
1731
1732 aud_stat = cx25840_read(c, CX25840_AUD_INT_STAT_REG);
1733 aud_en = cx25840_read(c, CX25840_AUD_INT_CTRL_REG);
1734 v4l_dbg(2, cx25840_debug, c,
1735 "AV Core audio IRQ status: %#04x disables: %#04x\n",
1736 aud_stat, aud_en);
1737 aud_mc_stat = cx25840_read4(c, CX23885_AUD_MC_INT_MASK_REG);
1738 v4l_dbg(2, cx25840_debug, c,
1739 "AV Core audio MC IRQ status: %#06x enables: %#06x\n",
1740 aud_mc_stat >> CX23885_AUD_MC_INT_STAT_SHFT,
1741 aud_mc_stat & CX23885_AUD_MC_INT_CTRL_BITS);
1742 if (irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT) {
1743 if (aud_stat) {
1744 cx25840_write(c, CX25840_AUD_INT_STAT_REG, aud_stat);
1745 *handled = true;
1746 }
1747 }
1748
1749 vid_stat = cx25840_read4(c, CX25840_VID_INT_STAT_REG);
1750 v4l_dbg(2, cx25840_debug, c,
1751 "AV Core video IRQ status: %#06x disables: %#06x\n",
1752 vid_stat & CX25840_VID_INT_STAT_BITS,
1753 vid_stat >> CX25840_VID_INT_MASK_SHFT);
1754 if (irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT) {
1755 if (vid_stat & CX25840_VID_INT_STAT_BITS) {
1756 cx25840_write4(c, CX25840_VID_INT_STAT_REG, vid_stat);
1757 *handled = true;
1758 }
1759 }
1760
1761 irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
1762 v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (exit): %s %s %s\n",
1763 irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : " ",
1764 irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : " ",
1765 irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : " ");
1766
1767 return ret;
1768}
1769
1770static int cx25840_irq_handler(struct v4l2_subdev *sd, u32 status,
1771 bool *handled)
1772{
1773 struct cx25840_state *state = to_state(sd);
1774
1775 *handled = false;
1776
1777 /* Only support the CX2388[578] AV Core for now */
1778 if (is_cx2388x(state))
1779 return cx23885_irq_handler(sd, status, handled);
1780
1781 return -ENODEV;
1782}
1783
9357b31c
HV		 1784/* ----------------------------------------------------------------------- */
1785
e34e658b
HV		 1786static const struct v4l2_ctrl_ops cx25840_ctrl_ops = {
1787 .s_ctrl = cx25840_s_ctrl,
1788};
1789
9357b31c
HV		 1790static const struct v4l2_subdev_core_ops cx25840_core_ops = {
1791 .log_status = cx25840_log_status,
72c851b0 1792 .s_config = cx25840_s_config,
9357b31c 1793 .g_chip_ident = cx25840_g_chip_ident,
e34e658b
HV		 1794 .g_ctrl = v4l2_subdev_g_ctrl,
1795 .s_ctrl = v4l2_subdev_s_ctrl,
1796 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1797 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1798 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1799 .queryctrl = v4l2_subdev_queryctrl,
1800 .querymenu = v4l2_subdev_querymenu,
f41737ec 1801 .s_std = cx25840_s_std,
9357b31c 1802 .reset = cx25840_reset,
cc26b076 1803 .load_fw = cx25840_load_fw,
d06d5777 1804 .s_io_pin_config = common_s_io_pin_config,
9357b31c
HV		 1805#ifdef CONFIG_VIDEO_ADV_DEBUG
1806 .g_register = cx25840_g_register,
1807 .s_register = cx25840_s_register,
1808#endif
52fd3dda 1809 .interrupt_service_routine = cx25840_irq_handler,
9357b31c
HV		 1810};
1811
1812static const struct v4l2_subdev_tuner_ops cx25840_tuner_ops = {
1813 .s_frequency = cx25840_s_frequency,
9357b31c
HV		 1814 .s_radio = cx25840_s_radio,
1815 .g_tuner = cx25840_g_tuner,
1816 .s_tuner = cx25840_s_tuner,
1817};
1818
1819static const struct v4l2_subdev_audio_ops cx25840_audio_ops = {
1820 .s_clock_freq = cx25840_s_clock_freq,
1821 .s_routing = cx25840_s_audio_routing,
3ccc646b 1822 .s_stream = cx25840_s_audio_stream,
9357b31c
HV		 1823};
1824
1825static const struct v4l2_subdev_video_ops cx25840_video_ops = {
1826 .s_routing = cx25840_s_video_routing,
96fd004f 1827 .s_mbus_fmt = cx25840_s_mbus_fmt,
9357b31c
HV		 1828 .s_stream = cx25840_s_stream,
1829};
1830
32cd527f
HV		 1831static const struct v4l2_subdev_vbi_ops cx25840_vbi_ops = {
1832 .decode_vbi_line = cx25840_decode_vbi_line,
5393db43
HV		 1833 .s_raw_fmt = cx25840_s_raw_fmt,
1834 .s_sliced_fmt = cx25840_s_sliced_fmt,
1835 .g_sliced_fmt = cx25840_g_sliced_fmt,
32cd527f
HV		 1836};
1837
9357b31c
HV		 1838static const struct v4l2_subdev_ops cx25840_ops = {
1839 .core = &cx25840_core_ops,
1840 .tuner = &cx25840_tuner_ops,
1841 .audio = &cx25840_audio_ops,
1842 .video = &cx25840_video_ops,
32cd527f 1843 .vbi = &cx25840_vbi_ops,
52fd3dda 1844 .ir = &cx25840_ir_ops,
9357b31c
HV		 1845};
1846
bd985160
HV		 1847/* ----------------------------------------------------------------------- */
1848
c7dd1ecd
AW		 1849static u32 get_cx2388x_ident(struct i2c_client *client)
1850{
1851 u32 ret;
1852
1853 /* Come out of digital power down */
1854 cx25840_write(client, 0x000, 0);
1855
8c2d7821
ST		 1856 /* Detecting whether the part is cx23885/7/8 is more
1857 * difficult than it needs to be. No ID register. Instead we
1858 * probe certain registers indicated in the datasheets to look
1859 * for specific defaults that differ between the silicon designs. */
1860
1861 /* It's either 885/7 if the IR Tx Clk Divider register exists */
c7dd1ecd 1862 if (cx25840_read4(client, 0x204) & 0xffff) {
8c2d7821
ST		 1863 /* CX23885 returns bogus repetitive byte values for the DIF,
1864 * which doesn't exist for it. (Ex. 8a8a8a8a or 31313131) */
1865 ret = cx25840_read4(client, 0x300);
1866 if (((ret & 0xffff0000) >> 16) == (ret & 0xffff)) {
1867 /* No DIF */
1868 ret = V4L2_IDENT_CX23885_AV;
1869 } else {
1870 /* CX23887 has a broken DIF, but the registers
1871 * appear valid (but unsed), good enough to detect. */
1872 ret = V4L2_IDENT_CX23887_AV;
1873 }
c7dd1ecd
AW		 1874 } else if (cx25840_read4(client, 0x300) & 0x0fffffff) {
1875 /* DIF PLL Freq Word reg exists; chip must be a CX23888 */
1876 ret = V4L2_IDENT_CX23888_AV;
1877 } else {
8c2d7821 1878 v4l_err(client, "Unable to detect h/w, assuming cx23887\n");
c7dd1ecd
AW		 1879 ret = V4L2_IDENT_CX23887_AV;
1880 }
1881
1882 /* Back into digital power down */
1883 cx25840_write(client, 0x000, 2);
1884 return ret;
1885}
1886
d2653e92
JD		 1887static int cx25840_probe(struct i2c_client *client,
1888 const struct i2c_device_id *did)
bd985160 1889{
bd985160 1890 struct cx25840_state *state;
9357b31c 1891 struct v4l2_subdev *sd;
e34e658b 1892 int default_volume;
c7dd1ecd 1893 u32 id = V4L2_IDENT_NONE;
bd985160
HV		 1894 u16 device_id;
1895
188f3457
HV		 1896 /* Check if the adapter supports the needed features */
1897 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1898 return -EIO;
1899
21340ae0 1900 v4l_dbg(1, cx25840_debug, client, "detecting cx25840 client on address 0x%x\n", client->addr << 1);
bd985160
HV		 1901
1902 device_id = cx25840_read(client, 0x101) << 8;
1903 device_id |= cx25840_read(client, 0x100);
f234081b 1904 v4l_dbg(1, cx25840_debug, client, "device_id = 0x%04x\n", device_id);
bd985160
HV		 1905
1906 /* The high byte of the device ID should be
e2b8cf4c
HV		 1907 * 0x83 for the cx2583x and 0x84 for the cx2584x */
1908 if ((device_id & 0xff00) == 0x8300) {
1909 id = V4L2_IDENT_CX25836 + ((device_id >> 4) & 0xf) - 6;
c7dd1ecd 1910 } else if ((device_id & 0xff00) == 0x8400) {
e2b8cf4c 1911 id = V4L2_IDENT_CX25840 + ((device_id >> 4) & 0xf);
00ca7324 1912 } else if (device_id == 0x0000) {
c7dd1ecd 1913 id = get_cx2388x_ident(client);
149783b5 1914 } else if ((device_id & 0xfff0) == 0x5A30) {
c7dd1ecd
AW		 1915 /* The CX23100 (0x5A3C = 23100) doesn't have an A/V decoder */
1916 id = V4L2_IDENT_CX2310X_AV;
1917 } else if ((device_id & 0xff) == (device_id >> 8)) {
1918 v4l_err(client,
1919 "likely a confused/unresponsive cx2388[578] A/V decoder"
1920 " found @ 0x%x (%s)\n",
1921 client->addr << 1, client->adapter->name);
1922 v4l_err(client, "A method to reset it from the cx25840 driver"
1923 " software is not known at this time\n");
1924 return -ENODEV;
1925 } else {
b5fc7144 1926 v4l_dbg(1, cx25840_debug, client, "cx25840 not found\n");
188f3457 1927 return -ENODEV;
bd985160
HV		 1928 }
1929
21340ae0 1930 state = kzalloc(sizeof(struct cx25840_state), GFP_KERNEL);
9357b31c 1931 if (state == NULL)
21340ae0 1932 return -ENOMEM;
21340ae0 1933
9357b31c
HV		 1934 sd = &state->sd;
1935 v4l2_i2c_subdev_init(sd, client, &cx25840_ops);
e34e658b 1936
c7dd1ecd
AW		 1937 switch (id) {
1938 case V4L2_IDENT_CX23885_AV:
c7dd1ecd
AW		 1939 v4l_info(client, "cx23885 A/V decoder found @ 0x%x (%s)\n",
1940 client->addr << 1, client->adapter->name);
1941 break;
1942 case V4L2_IDENT_CX23887_AV:
c7dd1ecd
AW		 1943 v4l_info(client, "cx23887 A/V decoder found @ 0x%x (%s)\n",
1944 client->addr << 1, client->adapter->name);
1945 break;
1946 case V4L2_IDENT_CX23888_AV:
c7dd1ecd
AW		 1947 v4l_info(client, "cx23888 A/V decoder found @ 0x%x (%s)\n",
1948 client->addr << 1, client->adapter->name);
1949 break;
1950 case V4L2_IDENT_CX2310X_AV:
c7dd1ecd
AW		 1951 v4l_info(client, "cx%d A/V decoder found @ 0x%x (%s)\n",
1952 device_id, client->addr << 1, client->adapter->name);
1953 break;
1954 case V4L2_IDENT_CX25840:
1955 case V4L2_IDENT_CX25841:
1956 case V4L2_IDENT_CX25842:
1957 case V4L2_IDENT_CX25843:
1958 /* Note: revision '(device_id & 0x0f) == 2' was never built. The
1959 marking skips from 0x1 == 22 to 0x3 == 23. */
1960 v4l_info(client, "cx25%3x-2%x found @ 0x%x (%s)\n",
1961 (device_id & 0xfff0) >> 4,
1962 (device_id & 0x0f) < 3 ? (device_id & 0x0f) + 1
1963 : (device_id & 0x0f),
1964 client->addr << 1, client->adapter->name);
1965 break;
1966 case V4L2_IDENT_CX25836:
1967 case V4L2_IDENT_CX25837:
c7dd1ecd
AW		 1968 default:
1969 v4l_info(client, "cx25%3x-%x found @ 0x%x (%s)\n",
1970 (device_id & 0xfff0) >> 4, device_id & 0x0f,
1971 client->addr << 1, client->adapter->name);
1972 break;
1973 }
bd985160 1974
21340ae0 1975 state->c = client;
a8bbf12a
HV		 1976 state->vid_input = CX25840_COMPOSITE7;
1977 state->aud_input = CX25840_AUDIO8;
3578d3dd 1978 state->audclk_freq = 48000;
a8bbf12a 1979 state->pvr150_workaround = 0;
8a4b275f 1980 state->audmode = V4L2_TUNER_MODE_LANG1;
3e3bf277 1981 state->vbi_line_offset = 8;
e2b8cf4c 1982 state->id = id;
3434eb7e 1983 state->rev = device_id;
e34e658b
HV		 1984 v4l2_ctrl_handler_init(&state->hdl, 9);
1985 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1986 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1987 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1988 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1989 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1990 V4L2_CID_SATURATION, 0, 127, 1, 64);
1991 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
1992 V4L2_CID_HUE, -128, 127, 1, 0);
1993 if (!is_cx2583x(state)) {
1994 default_volume = 228 - cx25840_read(client, 0x8d4);
1995 default_volume = ((default_volume / 2) + 23) << 9;
1996
1997 state->volume = v4l2_ctrl_new_std(&state->hdl,
1998 &cx25840_audio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
fc00a1d9 1999 0, 65535, 65535 / 100, default_volume);
e34e658b
HV		 2000 state->mute = v4l2_ctrl_new_std(&state->hdl,
2001 &cx25840_audio_ctrl_ops, V4L2_CID_AUDIO_MUTE,
2002 0, 1, 1, 0);
2003 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2004 V4L2_CID_AUDIO_BALANCE,
2005 0, 65535, 65535 / 100, 32768);
2006 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2007 V4L2_CID_AUDIO_BASS,
2008 0, 65535, 65535 / 100, 32768);
2009 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
2010 V4L2_CID_AUDIO_TREBLE,
2011 0, 65535, 65535 / 100, 32768);
2012 }
2013 sd->ctrl_handler = &state->hdl;
2014 if (state->hdl.error) {
2015 int err = state->hdl.error;
2016
2017 v4l2_ctrl_handler_free(&state->hdl);
2018 kfree(state);
2019 return err;
2020 }
2021 v4l2_ctrl_cluster(2, &state->volume);
2022 v4l2_ctrl_handler_setup(&state->hdl);
f234081b 2023
52fd3dda 2024 cx25840_ir_probe(sd);
bd985160
HV		 2025 return 0;
2026}
2027
1a39275a 2028static int cx25840_remove(struct i2c_client *client)
bd985160 2029{
9357b31c 2030 struct v4l2_subdev *sd = i2c_get_clientdata(client);
e34e658b 2031 struct cx25840_state *state = to_state(sd);
9357b31c 2032
52fd3dda 2033 cx25840_ir_remove(sd);
9357b31c 2034 v4l2_device_unregister_subdev(sd);
e34e658b
HV		 2035 v4l2_ctrl_handler_free(&state->hdl);
2036 kfree(state);
bd985160
HV		 2037 return 0;
2038}
2039
af294867
JD		 2040static const struct i2c_device_id cx25840_id[] = {
2041 { "cx25840", 0 },
2042 { }
2043};
2044MODULE_DEVICE_TABLE(i2c, cx25840_id);
2045
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HV		 2046static struct v4l2_i2c_driver_data v4l2_i2c_data = {
2047 .name = "cx25840",
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HV		 2048 .probe = cx25840_probe,
2049 .remove = cx25840_remove,
af294867 2050 .id_table = cx25840_id,
bd985160 2051};
Clone of davem's net-next-2.6 tree