[net-next-2.6.git] / drivers / media / video / cx23885 / cx23885.h

/*
 *  Driver for the Conexant CX23885 PCIe bridge
 *
 *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/kdev_t.h>
#include <linux/slab.h>

#include <media/v4l2-device.h>
#include <media/tuner.h>
#include <media/tveeprom.h>
#include <media/videobuf-dma-sg.h>
#include <media/videobuf-dvb.h>

#include "btcx-risc.h"
#include "cx23885-reg.h"
#include "media/cx2341x.h"

#include <linux/version.h>
#include <linux/mutex.h>

#define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)

#define UNSET (-1U)

#define CX23885_MAXBOARDS 8

/* Max number of inputs by card */
#define MAX_CX23885_INPUT 8
#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
#define RESOURCE_OVERLAY       1
#define RESOURCE_VIDEO         2
#define RESOURCE_VBI           4

#define BUFFER_TIMEOUT     (HZ)  /* 0.5 seconds */

#define CX23885_BOARD_NOAUTO               UNSET
#define CX23885_BOARD_UNKNOWN                  0
#define CX23885_BOARD_HAUPPAUGE_HVR1800lp      1
#define CX23885_BOARD_HAUPPAUGE_HVR1800        2
#define CX23885_BOARD_HAUPPAUGE_HVR1250        3
#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP   4
#define CX23885_BOARD_HAUPPAUGE_HVR1500Q       5
#define CX23885_BOARD_HAUPPAUGE_HVR1500        6
#define CX23885_BOARD_HAUPPAUGE_HVR1200        7
#define CX23885_BOARD_HAUPPAUGE_HVR1700        8
#define CX23885_BOARD_HAUPPAUGE_HVR1400        9
#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F   13
#define CX23885_BOARD_TBS_6920                 14
#define CX23885_BOARD_TEVII_S470               15
#define CX23885_BOARD_DVBWORLD_2005            16
#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI      17
#define CX23885_BOARD_HAUPPAUGE_HVR1270        18
#define CX23885_BOARD_HAUPPAUGE_HVR1275        19
#define CX23885_BOARD_HAUPPAUGE_HVR1255        20
#define CX23885_BOARD_HAUPPAUGE_HVR1210        21
#define CX23885_BOARD_MYGICA_X8506             22
#define CX23885_BOARD_MAGICPRO_PROHDTVE2       23
#define CX23885_BOARD_HAUPPAUGE_HVR1850        24
#define CX23885_BOARD_COMPRO_VIDEOMATE_E800    25
#define CX23885_BOARD_HAUPPAUGE_HVR1290        26
#define CX23885_BOARD_MYGICA_X8558PRO          27
#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28

#define GPIO_0 0x00000001
#define GPIO_1 0x00000002
#define GPIO_2 0x00000004
#define GPIO_3 0x00000008
#define GPIO_4 0x00000010
#define GPIO_5 0x00000020
#define GPIO_6 0x00000040
#define GPIO_7 0x00000080
#define GPIO_8 0x00000100
#define GPIO_9 0x00000200
#define GPIO_10 0x00000400
#define GPIO_11 0x00000800
#define GPIO_12 0x00001000
#define GPIO_13 0x00002000
#define GPIO_14 0x00004000
#define GPIO_15 0x00008000

/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
#define CX23885_NORMS (\
	V4L2_STD_NTSC_M |  V4L2_STD_NTSC_M_JP |  V4L2_STD_NTSC_443 | \
	V4L2_STD_PAL_BG |  V4L2_STD_PAL_DK    |  V4L2_STD_PAL_I    | \
	V4L2_STD_PAL_M  |  V4L2_STD_PAL_N     |  V4L2_STD_PAL_Nc   | \
	V4L2_STD_PAL_60 |  V4L2_STD_SECAM_L   |  V4L2_STD_SECAM_DK)

struct cx23885_fmt {
	char  *name;
	u32   fourcc;          /* v4l2 format id */
	int   depth;
	int   flags;
	u32   cxformat;
};

struct cx23885_ctrl {
	struct v4l2_queryctrl v;
	u32                   off;
	u32                   reg;
	u32                   mask;
	u32                   shift;
};

struct cx23885_tvnorm {
	char		*name;
	v4l2_std_id	id;
	u32		cxiformat;
	u32		cxoformat;
};

struct cx23885_fh {
	struct cx23885_dev         *dev;
	enum v4l2_buf_type         type;
	int                        radio;
	u32                        resources;

	/* video overlay */
	struct v4l2_window         win;
	struct v4l2_clip           *clips;
	unsigned int               nclips;

	/* video capture */
	struct cx23885_fmt         *fmt;
	unsigned int               width, height;

	/* vbi capture */
	struct videobuf_queue      vidq;
	struct videobuf_queue      vbiq;

	/* MPEG Encoder specifics ONLY */
	struct videobuf_queue      mpegq;
	atomic_t                   v4l_reading;
};

enum cx23885_itype {
	CX23885_VMUX_COMPOSITE1 = 1,
	CX23885_VMUX_COMPOSITE2,
	CX23885_VMUX_COMPOSITE3,
	CX23885_VMUX_COMPOSITE4,
	CX23885_VMUX_SVIDEO,
	CX23885_VMUX_COMPONENT,
	CX23885_VMUX_TELEVISION,
	CX23885_VMUX_CABLE,
	CX23885_VMUX_DVB,
	CX23885_VMUX_DEBUG,
	CX23885_RADIO,
};

enum cx23885_src_sel_type {
	CX23885_SRC_SEL_EXT_656_VIDEO = 0,
	CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
};

/* buffer for one video frame */
struct cx23885_buffer {
	/* common v4l buffer stuff -- must be first */
	struct videobuf_buffer vb;

	/* cx23885 specific */
	unsigned int           bpl;
	struct btcx_riscmem    risc;
	struct cx23885_fmt     *fmt;
	u32                    count;
};

struct cx23885_input {
	enum cx23885_itype type;
	unsigned int    vmux;
	u32             gpio0, gpio1, gpio2, gpio3;
};

typedef enum {
	CX23885_MPEG_UNDEFINED = 0,
	CX23885_MPEG_DVB,
	CX23885_ANALOG_VIDEO,
	CX23885_MPEG_ENCODER,
} port_t;

struct cx23885_board {
	char                    *name;
	port_t			porta, portb, portc;
	unsigned int		tuner_type;
	unsigned int		radio_type;
	unsigned char		tuner_addr;
	unsigned char		radio_addr;

	/* Vendors can and do run the PCIe bridge at different
	 * clock rates, driven physically by crystals on the PCBs.
	 * The core has to accomodate this. This allows the user
	 * to add new boards with new frequencys. The value is
	 * expressed in Hz.
	 *
	 * The core framework will default this value based on
	 * current designs, but it can vary.
	 */
	u32			clk_freq;
	struct cx23885_input    input[MAX_CX23885_INPUT];
	int			cimax; /* for NetUP */
};

struct cx23885_subid {
	u16     subvendor;
	u16     subdevice;
	u32     card;
};

struct cx23885_i2c {
	struct cx23885_dev *dev;

	int                        nr;

	/* i2c i/o */
	struct i2c_adapter         i2c_adap;
	struct i2c_algo_bit_data   i2c_algo;
	struct i2c_client          i2c_client;
	u32                        i2c_rc;

	/* 885 registers used for raw addess */
	u32                        i2c_period;
	u32                        reg_ctrl;
	u32                        reg_stat;
	u32                        reg_addr;
	u32                        reg_rdata;
	u32                        reg_wdata;
};

struct cx23885_dmaqueue {
	struct list_head       active;
	struct list_head       queued;
	struct timer_list      timeout;
	struct btcx_riscmem    stopper;
	u32                    count;
};

struct cx23885_tsport {
	struct cx23885_dev *dev;

	int                        nr;
	int                        sram_chno;

	struct videobuf_dvb_frontends frontends;

	/* dma queues */
	struct cx23885_dmaqueue    mpegq;
	u32                        ts_packet_size;
	u32                        ts_packet_count;

	int                        width;
	int                        height;

	spinlock_t                 slock;

	/* registers */
	u32                        reg_gpcnt;
	u32                        reg_gpcnt_ctl;
	u32                        reg_dma_ctl;
	u32                        reg_lngth;
	u32                        reg_hw_sop_ctrl;
	u32                        reg_gen_ctrl;
	u32                        reg_bd_pkt_status;
	u32                        reg_sop_status;
	u32                        reg_fifo_ovfl_stat;
	u32                        reg_vld_misc;
	u32                        reg_ts_clk_en;
	u32                        reg_ts_int_msk;
	u32                        reg_ts_int_stat;
	u32                        reg_src_sel;

	/* Default register vals */
	int                        pci_irqmask;
	u32                        dma_ctl_val;
	u32                        ts_int_msk_val;
	u32                        gen_ctrl_val;
	u32                        ts_clk_en_val;
	u32                        src_sel_val;
	u32                        vld_misc_val;
	u32                        hw_sop_ctrl_val;

	/* Allow a single tsport to have multiple frontends */
	u32                        num_frontends;
	void                       *port_priv;
};

struct cx23885_dev {
	atomic_t                   refcount;
	struct v4l2_device 	   v4l2_dev;

	/* pci stuff */
	struct pci_dev             *pci;
	unsigned char              pci_rev, pci_lat;
	int                        pci_bus, pci_slot;
	u32                        __iomem *lmmio;
	u8                         __iomem *bmmio;
	int                        pci_irqmask;
	int                        hwrevision;

	/* This valud is board specific and is used to configure the
	 * AV core so we see nice clean and stable video and audio. */
	u32                        clk_freq;

	/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
	struct cx23885_i2c         i2c_bus[3];

	int                        nr;
	struct mutex               lock;
	struct mutex               gpio_lock;

	/* board details */
	unsigned int               board;
	char                       name[32];

	struct cx23885_tsport      ts1, ts2;

	/* sram configuration */
	struct sram_channel        *sram_channels;

	enum {
		CX23885_BRIDGE_UNDEFINED = 0,
		CX23885_BRIDGE_885 = 885,
		CX23885_BRIDGE_887 = 887,
		CX23885_BRIDGE_888 = 888,
	} bridge;

	/* Analog video */
	u32                        resources;
	unsigned int               input;
	u32                        tvaudio;
	v4l2_std_id                tvnorm;
	unsigned int               tuner_type;
	unsigned char              tuner_addr;
	unsigned int               radio_type;
	unsigned char              radio_addr;
	unsigned int               has_radio;
	struct v4l2_subdev 	   *sd_cx25840;

	/* Infrared */
	struct v4l2_subdev         *sd_ir;
	struct work_struct	   ir_rx_work;
	unsigned long		   ir_rx_notifications;
	struct work_struct	   ir_tx_work;
	unsigned long		   ir_tx_notifications;

	struct card_ir		   *ir_input;
	atomic_t		   ir_input_stopping;

	/* V4l */
	u32                        freq;
	struct video_device        *video_dev;
	struct video_device        *vbi_dev;
	struct video_device        *radio_dev;

	struct cx23885_dmaqueue    vidq;
	struct cx23885_dmaqueue    vbiq;
	spinlock_t                 slock;

	/* MPEG Encoder ONLY settings */
	u32                        cx23417_mailbox;
	struct cx2341x_mpeg_params mpeg_params;
	struct video_device        *v4l_device;
	atomic_t                   v4l_reader_count;
	struct cx23885_tvnorm      encodernorm;

};

static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
{
	return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
}

#define call_all(dev, o, f, args...) \
	v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)

#define CX23885_HW_888_IR (1 << 0)

#define call_hw(dev, grpid, o, f, args...) \
	v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)

extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);

#define SRAM_CH01  0 /* Video A */
#define SRAM_CH02  1 /* VBI A */
#define SRAM_CH03  2 /* Video B */
#define SRAM_CH04  3 /* Transport via B */
#define SRAM_CH05  4 /* VBI B */
#define SRAM_CH06  5 /* Video C */
#define SRAM_CH07  6 /* Transport via C */
#define SRAM_CH08  7 /* Audio Internal A */
#define SRAM_CH09  8 /* Audio Internal B */
#define SRAM_CH10  9 /* Audio External */
#define SRAM_CH11 10 /* COMB_3D_N */
#define SRAM_CH12 11 /* Comb 3D N1 */
#define SRAM_CH13 12 /* Comb 3D N2 */
#define SRAM_CH14 13 /* MOE Vid */
#define SRAM_CH15 14 /* MOE RSLT */

struct sram_channel {
	char *name;
	u32  cmds_start;
	u32  ctrl_start;
	u32  cdt;
	u32  fifo_start;
	u32  fifo_size;
	u32  ptr1_reg;
	u32  ptr2_reg;
	u32  cnt1_reg;
	u32  cnt2_reg;
	u32  jumponly;
};

/* ----------------------------------------------------------- */

#define cx_read(reg)             readl(dev->lmmio + ((reg)>>2))
#define cx_write(reg, value)     writel((value), dev->lmmio + ((reg)>>2))

#define cx_andor(reg, mask, value) \
  writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
  ((value) & (mask)), dev->lmmio+((reg)>>2))

#define cx_set(reg, bit)          cx_andor((reg), (bit), (bit))
#define cx_clear(reg, bit)        cx_andor((reg), (bit), 0)

/* ----------------------------------------------------------- */
/* cx23885-core.c                                              */

extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
	struct sram_channel *ch,
	unsigned int bpl, u32 risc);

extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
	struct sram_channel *ch);

extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
	u32 reg, u32 mask, u32 value);

extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
	struct scatterlist *sglist,
	unsigned int top_offset, unsigned int bottom_offset,
	unsigned int bpl, unsigned int padding, unsigned int lines);

void cx23885_cancel_buffers(struct cx23885_tsport *port);

extern int cx23885_restart_queue(struct cx23885_tsport *port,
				struct cx23885_dmaqueue *q);

extern void cx23885_wakeup(struct cx23885_tsport *port,
			   struct cx23885_dmaqueue *q, u32 count);

extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
	int asoutput);


/* ----------------------------------------------------------- */
/* cx23885-cards.c                                             */
extern struct cx23885_board cx23885_boards[];
extern const unsigned int cx23885_bcount;

extern struct cx23885_subid cx23885_subids[];
extern const unsigned int cx23885_idcount;

extern int cx23885_tuner_callback(void *priv, int component,
	int command, int arg);
extern void cx23885_card_list(struct cx23885_dev *dev);
extern int  cx23885_ir_init(struct cx23885_dev *dev);
extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
extern void cx23885_ir_fini(struct cx23885_dev *dev);
extern void cx23885_gpio_setup(struct cx23885_dev *dev);
extern void cx23885_card_setup(struct cx23885_dev *dev);
extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);

extern int cx23885_dvb_register(struct cx23885_tsport *port);
extern int cx23885_dvb_unregister(struct cx23885_tsport *port);

extern int cx23885_buf_prepare(struct videobuf_queue *q,
			       struct cx23885_tsport *port,
			       struct cx23885_buffer *buf,
			       enum v4l2_field field);
extern void cx23885_buf_queue(struct cx23885_tsport *port,
			      struct cx23885_buffer *buf);
extern void cx23885_free_buffer(struct videobuf_queue *q,
				struct cx23885_buffer *buf);

/* ----------------------------------------------------------- */
/* cx23885-video.c                                             */
/* Video */
extern int cx23885_video_register(struct cx23885_dev *dev);
extern void cx23885_video_unregister(struct cx23885_dev *dev);
extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);

/* ----------------------------------------------------------- */
/* cx23885-vbi.c                                               */
extern int cx23885_vbi_fmt(struct file *file, void *priv,
	struct v4l2_format *f);
extern void cx23885_vbi_timeout(unsigned long data);
extern struct videobuf_queue_ops cx23885_vbi_qops;

/* cx23885-i2c.c                                                */
extern int cx23885_i2c_register(struct cx23885_i2c *bus);
extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);

/* ----------------------------------------------------------- */
/* cx23885-417.c                                               */
extern int cx23885_417_register(struct cx23885_dev *dev);
extern void cx23885_417_unregister(struct cx23885_dev *dev);
extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
extern void cx23885_mc417_init(struct cx23885_dev *dev);
extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
extern int mc417_register_read(struct cx23885_dev *dev,
				u16 address, u32 *value);
extern int mc417_register_write(struct cx23885_dev *dev,
				u16 address, u32 value);
extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);


/* ----------------------------------------------------------- */
/* tv norms                                                    */

static inline unsigned int norm_maxw(v4l2_std_id norm)
{
	return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
}

static inline unsigned int norm_maxh(v4l2_std_id norm)
{
	return (norm & V4L2_STD_625_50) ? 576 : 480;
}

static inline unsigned int norm_swidth(v4l2_std_id norm)
{
	return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
}
Commit	Line	Data
d19770e5 ST	1	/*
	2	* Driver for the Conexant CX23885 PCIe bridge
	3	*
6d897616	4	* Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5 ST	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	*
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	20	*/
	21
	22	#include <linux/pci.h>
	23	#include <linux/i2c.h>
	24	#include <linux/i2c-algo-bit.h>
	25	#include <linux/kdev_t.h>
5a0e3ad6	26	#include <linux/slab.h>
d19770e5	27
c0714f6c	28	#include <media/v4l2-device.h>
d19770e5 ST	29	#include <media/tuner.h>
d19770e5 ST	30	#include <media/tveeprom.h>
409d84f8 TP	31	#include <media/videobuf-dma-sg.h>
409d84f8 TP	32	#include <media/videobuf-dvb.h>
d19770e5 ST	33
	34	#include "btcx-risc.h"
	35	#include "cx23885-reg.h"
b1b81f1d	36	#include "media/cx2341x.h"
d19770e5 ST	37
	38	#include <linux/version.h>
	39	#include <linux/mutex.h>
	40
3ff4ad81	41	#define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)
d19770e5 ST	42
	43	#define UNSET (-1U)
	44
	45	#define CX23885_MAXBOARDS 8
	46
d19770e5 ST	47	/* Max number of inputs by card */
d19770e5 ST	48	#define MAX_CX23885_INPUT 8
7b888014 ST	49	#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
	50	#define RESOURCE_OVERLAY 1
	51	#define RESOURCE_VIDEO 2
	52	#define RESOURCE_VBI 4
d19770e5	53
d19770e5 ST	54	#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
	55
	56	#define CX23885_BOARD_NOAUTO UNSET
	57	#define CX23885_BOARD_UNKNOWN 0
	58	#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
	59	#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc	60	#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa	61	#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55	62	#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835	63	#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166	64	#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c	65	#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373	66	#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7	67	#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186	68	#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a	69	#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8	70	#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c	71	#define CX23885_BOARD_TBS_6920 14
579943f5	72	#define CX23885_BOARD_TEVII_S470 15
c9b8b04b	73	#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076	74	#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
2074dffa	75	#define CX23885_BOARD_HAUPPAUGE_HVR1270 18
d099becb	76	#define CX23885_BOARD_HAUPPAUGE_HVR1275 19
19bc5796	77	#define CX23885_BOARD_HAUPPAUGE_HVR1255 20
6b926eca	78	#define CX23885_BOARD_HAUPPAUGE_HVR1210 21
493b7127	79	#define CX23885_BOARD_MYGICA_X8506 22
2365b2d3	80	#define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
13697380	81	#define CX23885_BOARD_HAUPPAUGE_HVR1850 24
34e383dd	82	#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
aee0b24c	83	#define CX23885_BOARD_HAUPPAUGE_HVR1290 26
ea5697fe	84	#define CX23885_BOARD_MYGICA_X8558PRO 27
0b32d65c	85	#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
d19770e5	86
6f8bee9b ST	87	#define GPIO_0 0x00000001
	88	#define GPIO_1 0x00000002
	89	#define GPIO_2 0x00000004
	90	#define GPIO_3 0x00000008
	91	#define GPIO_4 0x00000010
	92	#define GPIO_5 0x00000020
	93	#define GPIO_6 0x00000040
	94	#define GPIO_7 0x00000080
	95	#define GPIO_8 0x00000100
	96	#define GPIO_9 0x00000200
f659c513 ST	97	#define GPIO_10 0x00000400
	98	#define GPIO_11 0x00000800
	99	#define GPIO_12 0x00001000
	100	#define GPIO_13 0x00002000
	101	#define GPIO_14 0x00004000
	102	#define GPIO_15 0x00008000
6f8bee9b	103
7b888014 ST	104	/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
	105	#define CX23885_NORMS (\
	106	V4L2_STD_NTSC_M \| V4L2_STD_NTSC_M_JP \| V4L2_STD_NTSC_443 \| \
	107	V4L2_STD_PAL_BG \| V4L2_STD_PAL_DK \| V4L2_STD_PAL_I \| \
	108	V4L2_STD_PAL_M \| V4L2_STD_PAL_N \| V4L2_STD_PAL_Nc \| \
	109	V4L2_STD_PAL_60 \| V4L2_STD_SECAM_L \| V4L2_STD_SECAM_DK)
	110
	111	struct cx23885_fmt {
	112	char *name;
	113	u32 fourcc; /* v4l2 format id */
	114	int depth;
	115	int flags;
	116	u32 cxformat;
	117	};
	118
	119	struct cx23885_ctrl {
	120	struct v4l2_queryctrl v;
	121	u32 off;
	122	u32 reg;
	123	u32 mask;
	124	u32 shift;
	125	};
	126
	127	struct cx23885_tvnorm {
	128	char *name;
	129	v4l2_std_id id;
	130	u32 cxiformat;
	131	u32 cxoformat;
	132	};
	133
	134	struct cx23885_fh {
	135	struct cx23885_dev *dev;
	136	enum v4l2_buf_type type;
	137	int radio;
	138	u32 resources;
	139
	140	/* video overlay */
	141	struct v4l2_window win;
	142	struct v4l2_clip *clips;
	143	unsigned int nclips;
	144
	145	/* video capture */
	146	struct cx23885_fmt *fmt;
	147	unsigned int width, height;
	148
	149	/* vbi capture */
	150	struct videobuf_queue vidq;
	151	struct videobuf_queue vbiq;
	152
	153	/* MPEG Encoder specifics ONLY */
	154	struct videobuf_queue mpegq;
	155	atomic_t v4l_reading;
	156	};
	157
d19770e5 ST	158	enum cx23885_itype {
	159	CX23885_VMUX_COMPOSITE1 = 1,
	160	CX23885_VMUX_COMPOSITE2,
	161	CX23885_VMUX_COMPOSITE3,
	162	CX23885_VMUX_COMPOSITE4,
	163	CX23885_VMUX_SVIDEO,
dac65fa1	164	CX23885_VMUX_COMPONENT,
d19770e5 ST	165	CX23885_VMUX_TELEVISION,
	166	CX23885_VMUX_CABLE,
	167	CX23885_VMUX_DVB,
	168	CX23885_VMUX_DEBUG,
	169	CX23885_RADIO,
	170	};
	171
579f1163 ST	172	enum cx23885_src_sel_type {
	173	CX23885_SRC_SEL_EXT_656_VIDEO = 0,
	174	CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
	175	};
	176
d19770e5 ST	177	/* buffer for one video frame */
	178	struct cx23885_buffer {
	179	/* common v4l buffer stuff -- must be first */
	180	struct videobuf_buffer vb;
	181
	182	/* cx23885 specific */
	183	unsigned int bpl;
	184	struct btcx_riscmem risc;
	185	struct cx23885_fmt *fmt;
	186	u32 count;
	187	};
	188
	189	struct cx23885_input {
	190	enum cx23885_itype type;
	191	unsigned int vmux;
	192	u32 gpio0, gpio1, gpio2, gpio3;
	193	};
	194
661c7e44 ST	195	typedef enum {
661c7e44 ST	196	CX23885_MPEG_UNDEFINED = 0,
7b888014 ST	197	CX23885_MPEG_DVB,
7b888014 ST	198	CX23885_ANALOG_VIDEO,
b1b81f1d	199	CX23885_MPEG_ENCODER,
661c7e44 ST	200	} port_t;
661c7e44 ST	201
d19770e5 ST	202	struct cx23885_board {
d19770e5 ST	203	char *name;
7b888014 ST	204	port_t porta, portb, portc;
	205	unsigned int tuner_type;
	206	unsigned int radio_type;
	207	unsigned char tuner_addr;
	208	unsigned char radio_addr;
c7712613 ST	209
	210	/* Vendors can and do run the PCIe bridge at different
	211	* clock rates, driven physically by crystals on the PCBs.
	212	* The core has to accomodate this. This allows the user
	213	* to add new boards with new frequencys. The value is
	214	* expressed in Hz.
	215	*
	216	* The core framework will default this value based on
	217	* current designs, but it can vary.
	218	*/
	219	u32 clk_freq;
d19770e5	220	struct cx23885_input input[MAX_CX23885_INPUT];
5a23b076	221	int cimax; /* for NetUP */
d19770e5 ST	222	};
	223
	224	struct cx23885_subid {
	225	u16 subvendor;
	226	u16 subdevice;
	227	u32 card;
	228	};
	229
	230	struct cx23885_i2c {
	231	struct cx23885_dev *dev;
	232
	233	int nr;
	234
	235	/* i2c i/o */
	236	struct i2c_adapter i2c_adap;
	237	struct i2c_algo_bit_data i2c_algo;
	238	struct i2c_client i2c_client;
	239	u32 i2c_rc;
	240
	241	/* 885 registers used for raw addess */
	242	u32 i2c_period;
	243	u32 reg_ctrl;
	244	u32 reg_stat;
	245	u32 reg_addr;
	246	u32 reg_rdata;
	247	u32 reg_wdata;
	248	};
	249
	250	struct cx23885_dmaqueue {
	251	struct list_head active;
	252	struct list_head queued;
	253	struct timer_list timeout;
	254	struct btcx_riscmem stopper;
	255	u32 count;
	256	};
	257
	258	struct cx23885_tsport {
	259	struct cx23885_dev *dev;
	260
	261	int nr;
	262	int sram_chno;
	263
363c35fc	264	struct videobuf_dvb_frontends frontends;
d19770e5 ST	265
	266	/* dma queues */
	267	struct cx23885_dmaqueue mpegq;
	268	u32 ts_packet_size;
	269	u32 ts_packet_count;
	270
	271	int width;
	272	int height;
	273
	274	spinlock_t slock;
	275
	276	/* registers */
	277	u32 reg_gpcnt;
	278	u32 reg_gpcnt_ctl;
	279	u32 reg_dma_ctl;
	280	u32 reg_lngth;
	281	u32 reg_hw_sop_ctrl;
	282	u32 reg_gen_ctrl;
	283	u32 reg_bd_pkt_status;
	284	u32 reg_sop_status;
	285	u32 reg_fifo_ovfl_stat;
	286	u32 reg_vld_misc;
	287	u32 reg_ts_clk_en;
	288	u32 reg_ts_int_msk;
a6a3f140	289	u32 reg_ts_int_stat;
579f1163	290	u32 reg_src_sel;
d19770e5 ST	291
	292	/* Default register vals */
	293	int pci_irqmask;
	294	u32 dma_ctl_val;
	295	u32 ts_int_msk_val;
	296	u32 gen_ctrl_val;
	297	u32 ts_clk_en_val;
579f1163	298	u32 src_sel_val;
b1b81f1d ST	299	u32 vld_misc_val;
b1b81f1d ST	300	u32 hw_sop_ctrl_val;
a739a7e4 ST	301
	302	/* Allow a single tsport to have multiple frontends */
	303	u32 num_frontends;
5a23b076	304	void *port_priv;
d19770e5 ST	305	};
	306
	307	struct cx23885_dev {
d19770e5	308	atomic_t refcount;
c0714f6c	309	struct v4l2_device v4l2_dev;
d19770e5 ST	310
	311	/* pci stuff */
	312	struct pci_dev *pci;
	313	unsigned char pci_rev, pci_lat;
	314	int pci_bus, pci_slot;
	315	u32 __iomem *lmmio;
	316	u8 __iomem *bmmio;
d19770e5	317	int pci_irqmask;
0ac5881a	318	int hwrevision;
d19770e5	319
c7712613 ST	320	/* This valud is board specific and is used to configure the
	321	* AV core so we see nice clean and stable video and audio. */
	322	u32 clk_freq;
	323
44a6481d	324	/* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5 ST	325	struct cx23885_i2c i2c_bus[3];
	326
	327	int nr;
	328	struct mutex lock;
8386c27f	329	struct mutex gpio_lock;
d19770e5 ST	330
	331	/* board details */
	332	unsigned int board;
	333	char name[32];
	334
a6a3f140	335	struct cx23885_tsport ts1, ts2;
d19770e5 ST	336
	337	/* sram configuration */
	338	struct sram_channel *sram_channels;
e133be0f ST	339
	340	enum {
	341	CX23885_BRIDGE_UNDEFINED = 0,
	342	CX23885_BRIDGE_885 = 885,
	343	CX23885_BRIDGE_887 = 887,
25ea66e2	344	CX23885_BRIDGE_888 = 888,
e133be0f	345	} bridge;
7b888014 ST	346
	347	/* Analog video */
	348	u32 resources;
	349	unsigned int input;
	350	u32 tvaudio;
	351	v4l2_std_id tvnorm;
	352	unsigned int tuner_type;
	353	unsigned char tuner_addr;
	354	unsigned int radio_type;
	355	unsigned char radio_addr;
	356	unsigned int has_radio;
0d5a19f1	357	struct v4l2_subdev *sd_cx25840;
f59ad611 AW	358
	359	/* Infrared */
	360	struct v4l2_subdev *sd_ir;
	361	struct work_struct ir_rx_work;
	362	unsigned long ir_rx_notifications;
	363	struct work_struct ir_tx_work;
	364	unsigned long ir_tx_notifications;
7b888014	365
dbda8f70 AW	366	struct card_ir *ir_input;
	367	atomic_t ir_input_stopping;
	368
7b888014 ST	369	/* V4l */
	370	u32 freq;
	371	struct video_device *video_dev;
	372	struct video_device *vbi_dev;
	373	struct video_device *radio_dev;
	374
	375	struct cx23885_dmaqueue vidq;
	376	struct cx23885_dmaqueue vbiq;
	377	spinlock_t slock;
b1b81f1d ST	378
	379	/* MPEG Encoder ONLY settings */
	380	u32 cx23417_mailbox;
	381	struct cx2341x_mpeg_params mpeg_params;
	382	struct video_device *v4l_device;
	383	atomic_t v4l_reader_count;
	384	struct cx23885_tvnorm encodernorm;
	385
d19770e5 ST	386	};
d19770e5 ST	387
c0714f6c HV	388	static inline struct cx23885_dev to_cx23885(struct v4l2_device v4l2_dev)
	389	{
	390	return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
	391	}
	392
0d5a19f1 HV	393	#define call_all(dev, o, f, args...) \
	394	v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
	395
29f8a0a5 AW	396	#define CX23885_HW_888_IR (1 << 0)
	397
	398	#define call_hw(dev, grpid, o, f, args...) \
	399	v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
	400
	401	extern struct v4l2_subdev cx23885_find_hw(struct cx23885_dev dev, u32 hw);
	402
d19770e5 ST	403	#define SRAM_CH01 0 /* Video A */
	404	#define SRAM_CH02 1 /* VBI A */
	405	#define SRAM_CH03 2 /* Video B */
	406	#define SRAM_CH04 3 /* Transport via B */
	407	#define SRAM_CH05 4 /* VBI B */
	408	#define SRAM_CH06 5 /* Video C */
	409	#define SRAM_CH07 6 /* Transport via C */
	410	#define SRAM_CH08 7 /* Audio Internal A */
	411	#define SRAM_CH09 8 /* Audio Internal B */
	412	#define SRAM_CH10 9 /* Audio External */
	413	#define SRAM_CH11 10 /* COMB_3D_N */
	414	#define SRAM_CH12 11 /* Comb 3D N1 */
	415	#define SRAM_CH13 12 /* Comb 3D N2 */
	416	#define SRAM_CH14 13 /* MOE Vid */
	417	#define SRAM_CH15 14 /* MOE RSLT */
	418
	419	struct sram_channel {
	420	char *name;
	421	u32 cmds_start;
	422	u32 ctrl_start;
	423	u32 cdt;
1ebcad77	424	u32 fifo_start;
d19770e5 ST	425	u32 fifo_size;
	426	u32 ptr1_reg;
	427	u32 ptr2_reg;
	428	u32 cnt1_reg;
	429	u32 cnt2_reg;
	430	u32 jumponly;
	431	};
	432
	433	/* ----------------------------------------------------------- */
	434
	435	#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51	436	#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5	437
9c8ced51	438	#define cx_andor(reg, mask, value) \
d19770e5 ST	439	writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) \|\
	440	((value) & (mask)), dev->lmmio+((reg)>>2))
	441
9c8ced51 ST	442	#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
9c8ced51 ST	443	#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5	444
d19770e5	445	/* ----------------------------------------------------------- */
7b888014 ST	446	/* cx23885-core.c */
	447
	448	extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
	449	struct sram_channel *ch,
	450	unsigned int bpl, u32 risc);
	451
	452	extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
	453	struct sram_channel *ch);
d19770e5	454
7b888014 ST	455	extern int cx23885_risc_stopper(struct pci_dev pci, struct btcx_riscmem risc,
	456	u32 reg, u32 mask, u32 value);
	457
	458	extern int cx23885_risc_buffer(struct pci_dev pci, struct btcx_riscmem risc,
	459	struct scatterlist *sglist,
	460	unsigned int top_offset, unsigned int bottom_offset,
	461	unsigned int bpl, unsigned int padding, unsigned int lines);
	462
	463	void cx23885_cancel_buffers(struct cx23885_tsport *port);
	464
	465	extern int cx23885_restart_queue(struct cx23885_tsport *port,
	466	struct cx23885_dmaqueue *q);
	467
	468	extern void cx23885_wakeup(struct cx23885_tsport *port,
	469	struct cx23885_dmaqueue *q, u32 count);
	470
6f8bee9b ST	471	extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
6f8bee9b ST	472	extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
09ea33e5	473	extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
6f8bee9b ST	474	extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
	475	int asoutput);
	476
7b888014 ST	477
	478	/* ----------------------------------------------------------- */
	479	/* cx23885-cards.c */
d19770e5 ST	480	extern struct cx23885_board cx23885_boards[];
	481	extern const unsigned int cx23885_bcount;
	482
	483	extern struct cx23885_subid cx23885_subids[];
	484	extern const unsigned int cx23885_idcount;
	485
9c8ced51 ST	486	extern int cx23885_tuner_callback(void *priv, int component,
9c8ced51 ST	487	int command, int arg);
d19770e5	488	extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140	489	extern int cx23885_ir_init(struct cx23885_dev *dev);
f59ad611 AW	490	extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
f59ad611 AW	491	extern void cx23885_ir_fini(struct cx23885_dev *dev);
a6a3f140	492	extern void cx23885_gpio_setup(struct cx23885_dev *dev);
d19770e5 ST	493	extern void cx23885_card_setup(struct cx23885_dev *dev);
	494	extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
	495
	496	extern int cx23885_dvb_register(struct cx23885_tsport *port);
	497	extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
	498
44a6481d MK	499	extern int cx23885_buf_prepare(struct videobuf_queue *q,
	500	struct cx23885_tsport *port,
	501	struct cx23885_buffer *buf,
	502	enum v4l2_field field);
44a6481d MK	503	extern void cx23885_buf_queue(struct cx23885_tsport *port,
	504	struct cx23885_buffer *buf);
	505	extern void cx23885_free_buffer(struct videobuf_queue *q,
	506	struct cx23885_buffer *buf);
d19770e5 ST	507
d19770e5 ST	508	/* ----------------------------------------------------------- */
7b888014 ST	509	/* cx23885-video.c */
	510	/* Video */
	511	extern int cx23885_video_register(struct cx23885_dev *dev);
	512	extern void cx23885_video_unregister(struct cx23885_dev *dev);
	513	extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
	514
	515	/* ----------------------------------------------------------- */
	516	/* cx23885-vbi.c */
	517	extern int cx23885_vbi_fmt(struct file file, void priv,
	518	struct v4l2_format *f);
	519	extern void cx23885_vbi_timeout(unsigned long data);
	520	extern struct videobuf_queue_ops cx23885_vbi_qops;
	521
d19770e5 ST	522	/* cx23885-i2c.c */
	523	extern int cx23885_i2c_register(struct cx23885_i2c *bus);
	524	extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665	525	extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5	526
b1b81f1d ST	527	/* ----------------------------------------------------------- */
	528	/* cx23885-417.c */
	529	extern int cx23885_417_register(struct cx23885_dev *dev);
	530	extern void cx23885_417_unregister(struct cx23885_dev *dev);
	531	extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
	532	extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
	533	extern void cx23885_mc417_init(struct cx23885_dev *dev);
	534	extern int mc417_memory_read(struct cx23885_dev dev, u32 address, u32 value);
	535	extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
74618244 AW	536	extern int mc417_register_read(struct cx23885_dev *dev,
	537	u16 address, u32 *value);
	538	extern int mc417_register_write(struct cx23885_dev *dev,
	539	u16 address, u32 value);
f659c513 ST	540	extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
	541	extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
	542	extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
b1b81f1d ST	543
b1b81f1d ST	544
7b888014 ST	545	/* ----------------------------------------------------------- */
	546	/* tv norms */
	547
	548	static inline unsigned int norm_maxw(v4l2_std_id norm)
	549	{
	550	return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
	551	}
	552
	553	static inline unsigned int norm_maxh(v4l2_std_id norm)
	554	{
	555	return (norm & V4L2_STD_625_50) ? 576 : 480;
	556	}
	557
	558	static inline unsigned int norm_swidth(v4l2_std_id norm)
	559	{
	560	return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
	561	}