]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/media/video/cx18/cx18-streams.c
V4L/DVB (13910): cx18: Fix set indextable command to properly select I/P/B index...
[net-next-2.6.git] / drivers / media / video / cx18 / cx18-streams.c
CommitLineData
1c1e45d1
HV
1/*
2 * cx18 init/start/stop/exit stream functions
3 *
4 * Derived from ivtv-streams.c
5 *
6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
1ed9dcc8 7 * Copyright (C) 2008 Andy Walls <awalls@radix.net>
1c1e45d1
HV
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
22 * 02111-1307 USA
23 */
24
25#include "cx18-driver.h"
b1526421 26#include "cx18-io.h"
1c1e45d1
HV
27#include "cx18-fileops.h"
28#include "cx18-mailbox.h"
29#include "cx18-i2c.h"
30#include "cx18-queue.h"
31#include "cx18-ioctl.h"
32#include "cx18-streams.h"
33#include "cx18-cards.h"
34#include "cx18-scb.h"
1c1e45d1
HV
35#include "cx18-dvb.h"
36
37#define CX18_DSP0_INTERRUPT_MASK 0xd0004C
38
bec43661 39static struct v4l2_file_operations cx18_v4l2_enc_fops = {
daf20d95
HV
40 .owner = THIS_MODULE,
41 .read = cx18_v4l2_read,
42 .open = cx18_v4l2_open,
3b6fe58f 43 /* FIXME change to video_ioctl2 if serialization lock can be removed */
daf20d95 44 .ioctl = cx18_v4l2_ioctl,
daf20d95
HV
45 .release = cx18_v4l2_close,
46 .poll = cx18_v4l2_enc_poll,
1c1e45d1
HV
47};
48
49/* offset from 0 to register ts v4l2 minors on */
50#define CX18_V4L2_ENC_TS_OFFSET 16
51/* offset from 0 to register pcm v4l2 minors on */
52#define CX18_V4L2_ENC_PCM_OFFSET 24
53/* offset from 0 to register yuv v4l2 minors on */
54#define CX18_V4L2_ENC_YUV_OFFSET 32
55
56static struct {
57 const char *name;
58 int vfl_type;
dd89601d 59 int num_offset;
1c1e45d1
HV
60 int dma;
61 enum v4l2_buf_type buf_type;
1c1e45d1
HV
62} cx18_stream_info[] = {
63 { /* CX18_ENC_STREAM_TYPE_MPG */
64 "encoder MPEG",
65 VFL_TYPE_GRABBER, 0,
66 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
67 },
68 { /* CX18_ENC_STREAM_TYPE_TS */
69 "TS",
70 VFL_TYPE_GRABBER, -1,
71 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
72 },
73 { /* CX18_ENC_STREAM_TYPE_YUV */
74 "encoder YUV",
75 VFL_TYPE_GRABBER, CX18_V4L2_ENC_YUV_OFFSET,
76 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
77 },
78 { /* CX18_ENC_STREAM_TYPE_VBI */
79 "encoder VBI",
80 VFL_TYPE_VBI, 0,
81 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VBI_CAPTURE,
1c1e45d1
HV
82 },
83 { /* CX18_ENC_STREAM_TYPE_PCM */
84 "encoder PCM audio",
85 VFL_TYPE_GRABBER, CX18_V4L2_ENC_PCM_OFFSET,
86 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_PRIVATE,
1c1e45d1
HV
87 },
88 { /* CX18_ENC_STREAM_TYPE_IDX */
89 "encoder IDX",
90 VFL_TYPE_GRABBER, -1,
91 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
92 },
93 { /* CX18_ENC_STREAM_TYPE_RAD */
94 "encoder radio",
95 VFL_TYPE_RADIO, 0,
96 PCI_DMA_NONE, V4L2_BUF_TYPE_PRIVATE,
1c1e45d1
HV
97 },
98};
99
100static void cx18_stream_init(struct cx18 *cx, int type)
101{
102 struct cx18_stream *s = &cx->streams[type];
3d05913d 103 struct video_device *video_dev = s->video_dev;
1c1e45d1 104
3d05913d 105 /* we need to keep video_dev, so restore it afterwards */
1c1e45d1 106 memset(s, 0, sizeof(*s));
3d05913d 107 s->video_dev = video_dev;
1c1e45d1
HV
108
109 /* initialize cx18_stream fields */
110 s->cx = cx;
111 s->type = type;
112 s->name = cx18_stream_info[type].name;
d3c5e707 113 s->handle = CX18_INVALID_TASK_HANDLE;
1c1e45d1
HV
114
115 s->dma = cx18_stream_info[type].dma;
6ecd86dc 116 s->buffers = cx->stream_buffers[type];
1c1e45d1 117 s->buf_size = cx->stream_buf_size[type];
52fcb3ec
AW
118 INIT_LIST_HEAD(&s->buf_pool);
119 s->bufs_per_mdl = 1;
120 s->mdl_size = s->buf_size * s->bufs_per_mdl;
6ecd86dc 121
1c1e45d1
HV
122 init_waitqueue_head(&s->waitq);
123 s->id = -1;
40c5520f 124 spin_lock_init(&s->q_free.lock);
1c1e45d1 125 cx18_queue_init(&s->q_free);
40c5520f 126 spin_lock_init(&s->q_busy.lock);
66c2a6b0 127 cx18_queue_init(&s->q_busy);
40c5520f 128 spin_lock_init(&s->q_full.lock);
1c1e45d1 129 cx18_queue_init(&s->q_full);
52fcb3ec
AW
130 spin_lock_init(&s->q_idle.lock);
131 cx18_queue_init(&s->q_idle);
21a278b8
AW
132
133 INIT_WORK(&s->out_work_order, cx18_out_work_handler);
1c1e45d1
HV
134}
135
136static int cx18_prep_dev(struct cx18 *cx, int type)
137{
138 struct cx18_stream *s = &cx->streams[type];
139 u32 cap = cx->v4l2_cap;
dd89601d 140 int num_offset = cx18_stream_info[type].num_offset;
5811cf99 141 int num = cx->instance + cx18_first_minor + num_offset;
1c1e45d1 142
3d05913d 143 /* These four fields are always initialized. If video_dev == NULL, then
1c1e45d1
HV
144 this stream is not in use. In that case no other fields but these
145 four can be used. */
3d05913d 146 s->video_dev = NULL;
1c1e45d1
HV
147 s->cx = cx;
148 s->type = type;
149 s->name = cx18_stream_info[type].name;
150
151 /* Check whether the radio is supported */
152 if (type == CX18_ENC_STREAM_TYPE_RAD && !(cap & V4L2_CAP_RADIO))
153 return 0;
154
155 /* Check whether VBI is supported */
156 if (type == CX18_ENC_STREAM_TYPE_VBI &&
157 !(cap & (V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE)))
158 return 0;
159
1c1e45d1
HV
160 /* User explicitly selected 0 buffers for these streams, so don't
161 create them. */
162 if (cx18_stream_info[type].dma != PCI_DMA_NONE &&
6ecd86dc 163 cx->stream_buffers[type] == 0) {
1c1e45d1
HV
164 CX18_INFO("Disabled %s device\n", cx18_stream_info[type].name);
165 return 0;
166 }
167
168 cx18_stream_init(cx, type);
169
dd89601d 170 if (num_offset == -1)
1c1e45d1
HV
171 return 0;
172
173 /* allocate and initialize the v4l2 video device structure */
3d05913d
AW
174 s->video_dev = video_device_alloc();
175 if (s->video_dev == NULL) {
1c1e45d1
HV
176 CX18_ERR("Couldn't allocate v4l2 video_device for %s\n",
177 s->name);
178 return -ENOMEM;
179 }
180
5811cf99
AW
181 snprintf(s->video_dev->name, sizeof(s->video_dev->name), "%s %s",
182 cx->v4l2_dev.name, s->name);
1c1e45d1 183
3d05913d 184 s->video_dev->num = num;
5811cf99 185 s->video_dev->v4l2_dev = &cx->v4l2_dev;
3d05913d
AW
186 s->video_dev->fops = &cx18_v4l2_enc_fops;
187 s->video_dev->release = video_device_release;
188 s->video_dev->tvnorms = V4L2_STD_ALL;
189 cx18_set_funcs(s->video_dev);
1c1e45d1
HV
190 return 0;
191}
192
193/* Initialize v4l2 variables and register v4l2 devices */
194int cx18_streams_setup(struct cx18 *cx)
195{
9b4a7c8a 196 int type, ret;
1c1e45d1
HV
197
198 /* Setup V4L2 Devices */
199 for (type = 0; type < CX18_MAX_STREAMS; type++) {
200 /* Prepare device */
9b4a7c8a
AW
201 ret = cx18_prep_dev(cx, type);
202 if (ret < 0)
1c1e45d1
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203 break;
204
205 /* Allocate Stream */
9b4a7c8a
AW
206 ret = cx18_stream_alloc(&cx->streams[type]);
207 if (ret < 0)
1c1e45d1
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208 break;
209 }
210 if (type == CX18_MAX_STREAMS)
211 return 0;
212
213 /* One or more streams could not be initialized. Clean 'em all up. */
3f98387e 214 cx18_streams_cleanup(cx, 0);
9b4a7c8a 215 return ret;
1c1e45d1
HV
216}
217
218static int cx18_reg_dev(struct cx18 *cx, int type)
219{
220 struct cx18_stream *s = &cx->streams[type];
221 int vfl_type = cx18_stream_info[type].vfl_type;
38c7c036 222 const char *name;
9b4a7c8a 223 int num, ret;
1c1e45d1
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224
225 /* TODO: Shouldn't this be a VFL_TYPE_TRANSPORT or something?
226 * We need a VFL_TYPE_TS defined.
227 */
228 if (strcmp("TS", s->name) == 0) {
229 /* just return if no DVB is supported */
230 if ((cx->card->hw_all & CX18_HW_DVB) == 0)
231 return 0;
9b4a7c8a
AW
232 ret = cx18_dvb_register(s);
233 if (ret < 0) {
1c1e45d1 234 CX18_ERR("DVB failed to register\n");
9b4a7c8a 235 return ret;
1c1e45d1
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236 }
237 }
238
3d05913d 239 if (s->video_dev == NULL)
1c1e45d1
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240 return 0;
241
3d05913d 242 num = s->video_dev->num;
dd89601d
HV
243 /* card number + user defined offset + device offset */
244 if (type != CX18_ENC_STREAM_TYPE_MPG) {
245 struct cx18_stream *s_mpg = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
246
3d05913d
AW
247 if (s_mpg->video_dev)
248 num = s_mpg->video_dev->num
249 + cx18_stream_info[type].num_offset;
dd89601d 250 }
5811cf99 251 video_set_drvdata(s->video_dev, s);
1c1e45d1
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252
253 /* Register device. First try the desired minor, then any free one. */
6b5270d2 254 ret = video_register_device_no_warn(s->video_dev, vfl_type, num);
9b4a7c8a 255 if (ret < 0) {
581644d9 256 CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n",
dd89601d 257 s->name, num);
3d05913d
AW
258 video_device_release(s->video_dev);
259 s->video_dev = NULL;
9b4a7c8a 260 return ret;
1c1e45d1 261 }
38c7c036
LP
262
263 name = video_device_node_name(s->video_dev);
1c1e45d1
HV
264
265 switch (vfl_type) {
266 case VFL_TYPE_GRABBER:
38c7c036
LP
267 CX18_INFO("Registered device %s for %s (%d x %d.%02d kB)\n",
268 name, s->name, cx->stream_buffers[type],
22dce188
AW
269 cx->stream_buf_size[type] / 1024,
270 (cx->stream_buf_size[type] * 100 / 1024) % 100);
1c1e45d1
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271 break;
272
273 case VFL_TYPE_RADIO:
38c7c036 274 CX18_INFO("Registered device %s for %s\n", name, s->name);
1c1e45d1
HV
275 break;
276
277 case VFL_TYPE_VBI:
6ecd86dc 278 if (cx->stream_buffers[type])
38c7c036 279 CX18_INFO("Registered device %s for %s "
6ecd86dc 280 "(%d x %d bytes)\n",
38c7c036 281 name, s->name, cx->stream_buffers[type],
6ecd86dc 282 cx->stream_buf_size[type]);
1c1e45d1 283 else
38c7c036
LP
284 CX18_INFO("Registered device %s for %s\n",
285 name, s->name);
1c1e45d1
HV
286 break;
287 }
288
289 return 0;
290}
291
292/* Register v4l2 devices */
293int cx18_streams_register(struct cx18 *cx)
294{
295 int type;
9b4a7c8a
AW
296 int err;
297 int ret = 0;
1c1e45d1
HV
298
299 /* Register V4L2 devices */
9b4a7c8a
AW
300 for (type = 0; type < CX18_MAX_STREAMS; type++) {
301 err = cx18_reg_dev(cx, type);
302 if (err && ret == 0)
303 ret = err;
304 }
1c1e45d1 305
9b4a7c8a 306 if (ret == 0)
1c1e45d1
HV
307 return 0;
308
309 /* One or more streams could not be initialized. Clean 'em all up. */
3f98387e 310 cx18_streams_cleanup(cx, 1);
9b4a7c8a 311 return ret;
1c1e45d1
HV
312}
313
314/* Unregister v4l2 devices */
3f98387e 315void cx18_streams_cleanup(struct cx18 *cx, int unregister)
1c1e45d1
HV
316{
317 struct video_device *vdev;
318 int type;
319
320 /* Teardown all streams */
321 for (type = 0; type < CX18_MAX_STREAMS; type++) {
7b1dde03
AW
322
323 /* No struct video_device, but can have buffers allocated */
324 if (type == CX18_ENC_STREAM_TYPE_TS) {
325 if (cx->streams[type].dvb.enabled) {
326 cx18_dvb_unregister(&cx->streams[type]);
327 cx->streams[type].dvb.enabled = false;
328 cx18_stream_free(&cx->streams[type]);
329 }
330 continue;
331 }
332
333 /* No struct video_device, but can have buffers allocated */
334 if (type == CX18_ENC_STREAM_TYPE_IDX) {
335 if (cx->stream_buffers[type] != 0) {
336 cx->stream_buffers[type] = 0;
337 cx18_stream_free(&cx->streams[type]);
338 }
339 continue;
fac3639d 340 }
1c1e45d1 341
7b1dde03 342 /* If struct video_device exists, can have buffers allocated */
3d05913d 343 vdev = cx->streams[type].video_dev;
1c1e45d1 344
3d05913d 345 cx->streams[type].video_dev = NULL;
1c1e45d1
HV
346 if (vdev == NULL)
347 continue;
348
349 cx18_stream_free(&cx->streams[type]);
350
3f98387e
HV
351 /* Unregister or release device */
352 if (unregister)
353 video_unregister_device(vdev);
354 else
355 video_device_release(vdev);
1c1e45d1
HV
356 }
357}
358
359static void cx18_vbi_setup(struct cx18_stream *s)
360{
361 struct cx18 *cx = s->cx;
dd073434 362 int raw = cx18_raw_vbi(cx);
1c1e45d1
HV
363 u32 data[CX2341X_MBOX_MAX_DATA];
364 int lines;
365
366 if (cx->is_60hz) {
367 cx->vbi.count = 12;
368 cx->vbi.start[0] = 10;
369 cx->vbi.start[1] = 273;
370 } else { /* PAL/SECAM */
371 cx->vbi.count = 18;
372 cx->vbi.start[0] = 6;
373 cx->vbi.start[1] = 318;
374 }
375
376 /* setup VBI registers */
fa3e7036 377 v4l2_subdev_call(cx->sd_av, video, s_fmt, &cx->vbi.in);
1c1e45d1 378
dcc0ef88
AW
379 /*
380 * Send the CX18_CPU_SET_RAW_VBI_PARAM API command to setup Encoder Raw
381 * VBI when the first analog capture channel starts, as once it starts
382 * (e.g. MPEG), we can't effect any change in the Encoder Raw VBI setup
383 * (i.e. for the VBI capture channels). We also send it for each
384 * analog capture channel anyway just to make sure we get the proper
385 * behavior
386 */
1c1e45d1
HV
387 if (raw) {
388 lines = cx->vbi.count * 2;
389 } else {
812b1f9d
AW
390 /*
391 * For 525/60 systems, according to the VIP 2 & BT.656 std:
392 * The EAV RP code's Field bit toggles on line 4, a few lines
393 * after the Vertcal Blank bit has already toggled.
394 * Tell the encoder to capture 21-4+1=18 lines per field,
395 * since we want lines 10 through 21.
396 *
5ab74052
AW
397 * For 625/50 systems, according to the VIP 2 & BT.656 std:
398 * The EAV RP code's Field bit toggles on line 1, a few lines
399 * after the Vertcal Blank bit has already toggled.
929a3ad1
AW
400 * (We've actually set the digitizer so that the Field bit
401 * toggles on line 2.) Tell the encoder to capture 23-2+1=22
402 * lines per field, since we want lines 6 through 23.
812b1f9d 403 */
929a3ad1 404 lines = cx->is_60hz ? (21 - 4 + 1) * 2 : (23 - 2 + 1) * 2;
1c1e45d1
HV
405 }
406
1c1e45d1
HV
407 data[0] = s->handle;
408 /* Lines per field */
409 data[1] = (lines / 2) | ((lines / 2) << 16);
410 /* bytes per line */
302df970
AW
411 data[2] = (raw ? vbi_active_samples
412 : (cx->is_60hz ? vbi_hblank_samples_60Hz
413 : vbi_hblank_samples_50Hz));
1c1e45d1
HV
414 /* Every X number of frames a VBI interrupt arrives
415 (frames as in 25 or 30 fps) */
416 data[3] = 1;
302df970
AW
417 /*
418 * Set the SAV/EAV RP codes to look for as start/stop points
419 * when in VIP-1.1 mode
420 */
1c1e45d1 421 if (raw) {
302df970
AW
422 /*
423 * Start codes for beginning of "active" line in vertical blank
424 * 0x20 ( VerticalBlank )
425 * 0x60 ( EvenField VerticalBlank )
426 */
1c1e45d1 427 data[4] = 0x20602060;
302df970
AW
428 /*
429 * End codes for end of "active" raw lines and regular lines
430 * 0x30 ( VerticalBlank HorizontalBlank)
431 * 0x70 ( EvenField VerticalBlank HorizontalBlank)
432 * 0x90 (Task HorizontalBlank)
433 * 0xd0 (Task EvenField HorizontalBlank)
434 */
af009cf6 435 data[5] = 0x307090d0;
1c1e45d1 436 } else {
302df970
AW
437 /*
438 * End codes for active video, we want data in the hblank region
439 * 0xb0 (Task 0 VerticalBlank HorizontalBlank)
440 * 0xf0 (Task EvenField VerticalBlank HorizontalBlank)
441 *
442 * Since the V bit is only allowed to toggle in the EAV RP code,
443 * just before the first active region line, these two
812b1f9d 444 * are problematic:
302df970
AW
445 * 0x90 (Task HorizontalBlank)
446 * 0xd0 (Task EvenField HorizontalBlank)
812b1f9d 447 *
af7c58b1
AW
448 * We have set the digitzer such that we don't have to worry
449 * about these problem codes.
302df970 450 */
1c1e45d1 451 data[4] = 0xB0F0B0F0;
302df970
AW
452 /*
453 * Start codes for beginning of active line in vertical blank
454 * 0xa0 (Task VerticalBlank )
455 * 0xe0 (Task EvenField VerticalBlank )
456 */
1c1e45d1
HV
457 data[5] = 0xA0E0A0E0;
458 }
459
460 CX18_DEBUG_INFO("Setup VBI h: %d lines %x bpl %d fr %d %x %x\n",
461 data[0], data[1], data[2], data[3], data[4], data[5]);
462
dcc0ef88 463 cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data);
1c1e45d1
HV
464}
465
ef991797
AW
466void cx18_stream_rotate_idx_mdls(struct cx18 *cx)
467{
468 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
469 struct cx18_mdl *mdl;
470
471 if (!cx18_stream_enabled(s))
472 return;
473
474 /* Return if the firmware is not running low on MDLs */
475 if ((atomic_read(&s->q_free.depth) + atomic_read(&s->q_busy.depth)) >=
476 CX18_ENC_STREAM_TYPE_IDX_FW_MDL_MIN)
477 return;
478
479 /* Return if there are no MDLs to rotate back to the firmware */
480 if (atomic_read(&s->q_full.depth) < 2)
481 return;
482
483 /*
484 * Take the oldest IDX MDL still holding data, and discard its index
485 * entries by scheduling the MDL to go back to the firmware
486 */
487 mdl = cx18_dequeue(s, &s->q_full);
488 if (mdl != NULL)
489 cx18_enqueue(s, mdl, &s->q_free);
490}
491
87116159 492static
52fcb3ec
AW
493struct cx18_queue *_cx18_stream_put_mdl_fw(struct cx18_stream *s,
494 struct cx18_mdl *mdl)
66c2a6b0
AW
495{
496 struct cx18 *cx = s->cx;
497 struct cx18_queue *q;
498
499 /* Don't give it to the firmware, if we're not running a capture */
500 if (s->handle == CX18_INVALID_TASK_HANDLE ||
87116159 501 test_bit(CX18_F_S_STOPPING, &s->s_flags) ||
66c2a6b0 502 !test_bit(CX18_F_S_STREAMING, &s->s_flags))
52fcb3ec 503 return cx18_enqueue(s, mdl, &s->q_free);
66c2a6b0 504
52fcb3ec 505 q = cx18_enqueue(s, mdl, &s->q_busy);
66c2a6b0 506 if (q != &s->q_busy)
52fcb3ec 507 return q; /* The firmware has the max MDLs it can handle */
66c2a6b0 508
52fcb3ec 509 cx18_mdl_sync_for_device(s, mdl);
66c2a6b0 510 cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
52fcb3ec
AW
511 (void __iomem *) &cx->scb->cpu_mdl[mdl->id] - cx->enc_mem,
512 s->bufs_per_mdl, mdl->id, s->mdl_size);
66c2a6b0
AW
513 return q;
514}
515
87116159
AW
516static
517void _cx18_stream_load_fw_queue(struct cx18_stream *s)
66c2a6b0 518{
abb096de 519 struct cx18_queue *q;
52fcb3ec 520 struct cx18_mdl *mdl;
66c2a6b0 521
c37b11bf
AW
522 if (atomic_read(&s->q_free.depth) == 0 ||
523 atomic_read(&s->q_busy.depth) >= CX18_MAX_FW_MDLS_PER_STREAM)
abb096de
AW
524 return;
525
526 /* Move from q_free to q_busy notifying the firmware, until the limit */
527 do {
52fcb3ec
AW
528 mdl = cx18_dequeue(s, &s->q_free);
529 if (mdl == NULL)
abb096de 530 break;
52fcb3ec 531 q = _cx18_stream_put_mdl_fw(s, mdl);
c37b11bf 532 } while (atomic_read(&s->q_busy.depth) < CX18_MAX_FW_MDLS_PER_STREAM
0ef02892 533 && q == &s->q_busy);
66c2a6b0
AW
534}
535
87116159
AW
536void cx18_out_work_handler(struct work_struct *work)
537{
21a278b8
AW
538 struct cx18_stream *s =
539 container_of(work, struct cx18_stream, out_work_order);
87116159 540
21a278b8 541 _cx18_stream_load_fw_queue(s);
87116159
AW
542}
543
52fcb3ec
AW
544static void cx18_stream_configure_mdls(struct cx18_stream *s)
545{
546 cx18_unload_queues(s);
547
22dce188
AW
548 switch (s->type) {
549 case CX18_ENC_STREAM_TYPE_YUV:
550 /*
551 * Height should be a multiple of 32 lines.
552 * Set the MDL size to the exact size needed for one frame.
553 * Use enough buffers per MDL to cover the MDL size
554 */
555 s->mdl_size = 720 * s->cx->params.height * 3 / 2;
556 s->bufs_per_mdl = s->mdl_size / s->buf_size;
557 if (s->mdl_size % s->buf_size)
558 s->bufs_per_mdl++;
559 break;
127ce5f0
AW
560 case CX18_ENC_STREAM_TYPE_VBI:
561 s->bufs_per_mdl = 1;
562 if (cx18_raw_vbi(s->cx)) {
563 s->mdl_size = (s->cx->is_60hz ? 12 : 18)
564 * 2 * vbi_active_samples;
565 } else {
566 /*
567 * See comment in cx18_vbi_setup() below about the
568 * extra lines we capture in sliced VBI mode due to
569 * the lines on which EAV RP codes toggle.
570 */
571 s->mdl_size = s->cx->is_60hz
572 ? (21 - 4 + 1) * 2 * vbi_hblank_samples_60Hz
573 : (23 - 2 + 1) * 2 * vbi_hblank_samples_50Hz;
574 }
575 break;
22dce188
AW
576 default:
577 s->bufs_per_mdl = 1;
578 s->mdl_size = s->buf_size * s->bufs_per_mdl;
579 break;
580 }
52fcb3ec
AW
581
582 cx18_load_queues(s);
583}
584
1c1e45d1
HV
585int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
586{
587 u32 data[MAX_MB_ARGUMENTS];
588 struct cx18 *cx = s->cx;
1c1e45d1 589 int captype = 0;
dcc0ef88 590 struct cx18_api_func_private priv;
e46c54a8 591 struct cx18_stream *s_idx;
1c1e45d1 592
540bab93 593 if (!cx18_stream_enabled(s))
1c1e45d1
HV
594 return -EINVAL;
595
596 CX18_DEBUG_INFO("Start encoder stream %s\n", s->name);
597
598 switch (s->type) {
599 case CX18_ENC_STREAM_TYPE_MPG:
600 captype = CAPTURE_CHANNEL_TYPE_MPEG;
601 cx->mpg_data_received = cx->vbi_data_inserted = 0;
602 cx->dualwatch_jiffies = jiffies;
603 cx->dualwatch_stereo_mode = cx->params.audio_properties & 0x300;
604 cx->search_pack_header = 0;
605 break;
606
e46c54a8
AW
607 case CX18_ENC_STREAM_TYPE_IDX:
608 captype = CAPTURE_CHANNEL_TYPE_INDEX;
609 break;
1c1e45d1
HV
610 case CX18_ENC_STREAM_TYPE_TS:
611 captype = CAPTURE_CHANNEL_TYPE_TS;
1c1e45d1
HV
612 break;
613 case CX18_ENC_STREAM_TYPE_YUV:
614 captype = CAPTURE_CHANNEL_TYPE_YUV;
615 break;
616 case CX18_ENC_STREAM_TYPE_PCM:
617 captype = CAPTURE_CHANNEL_TYPE_PCM;
618 break;
619 case CX18_ENC_STREAM_TYPE_VBI:
dcc0ef88 620#ifdef CX18_ENCODER_PARSES_SLICED
dd073434
AW
621 captype = cx18_raw_vbi(cx) ?
622 CAPTURE_CHANNEL_TYPE_VBI : CAPTURE_CHANNEL_TYPE_SLICED_VBI;
dcc0ef88
AW
623#else
624 /*
625 * Currently we set things up so that Sliced VBI from the
626 * digitizer is handled as Raw VBI by the encoder
627 */
628 captype = CAPTURE_CHANNEL_TYPE_VBI;
629#endif
1c1e45d1
HV
630 cx->vbi.frame = 0;
631 cx->vbi.inserted_frame = 0;
632 memset(cx->vbi.sliced_mpeg_size,
633 0, sizeof(cx->vbi.sliced_mpeg_size));
634 break;
635 default:
636 return -EINVAL;
637 }
1c1e45d1 638
1c1e45d1
HV
639 /* Clear Streamoff flags in case left from last capture */
640 clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
641
642 cx18_vapi_result(cx, data, CX18_CREATE_TASK, 1, CPU_CMD_MASK_CAPTURE);
643 s->handle = data[0];
644 cx18_vapi(cx, CX18_CPU_SET_CHANNEL_TYPE, 2, s->handle, captype);
645
dcc0ef88
AW
646 /*
647 * For everything but CAPTURE_CHANNEL_TYPE_TS, play it safe and
648 * set up all the parameters, as it is not obvious which parameters the
649 * firmware shares across capture channel types and which it does not.
650 *
651 * Some of the cx18_vapi() calls below apply to only certain capture
652 * channel types. We're hoping there's no harm in calling most of them
653 * anyway, as long as the values are all consistent. Setting some
654 * shared parameters will have no effect once an analog capture channel
655 * has started streaming.
656 */
657 if (captype != CAPTURE_CHANNEL_TYPE_TS) {
1c1e45d1
HV
658 cx18_vapi(cx, CX18_CPU_SET_VER_CROP_LINE, 2, s->handle, 0);
659 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 3, 1);
660 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 8, 0);
661 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 4, 1);
1c1e45d1 662
dcc0ef88
AW
663 /*
664 * Audio related reset according to
665 * Documentation/video4linux/cx2341x/fw-encoder-api.txt
666 */
667 if (atomic_read(&cx->ana_capturing) == 0)
668 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2,
669 s->handle, 12);
670
671 /*
672 * Number of lines for Field 1 & Field 2 according to
673 * Documentation/video4linux/cx2341x/fw-encoder-api.txt
f37aa511
AW
674 * Field 1 is 312 for 625 line systems in BT.656
675 * Field 2 is 313 for 625 line systems in BT.656
dcc0ef88 676 */
1c1e45d1 677 cx18_vapi(cx, CX18_CPU_SET_CAPTURE_LINE_NO, 3,
f37aa511 678 s->handle, 312, 313);
1c1e45d1 679
1c1e45d1
HV
680 if (cx->v4l2_cap & V4L2_CAP_VBI_CAPTURE)
681 cx18_vbi_setup(s);
682
dcc0ef88 683 /*
e46c54a8
AW
684 * Select to receive I, P, and B frame index entries, if the
685 * index stream is enabled. Otherwise disable index entry
686 * generation.
dcc0ef88 687 */
e46c54a8 688 s_idx = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
5ada5773
AW
689 cx18_vapi_result(cx, data, CX18_CPU_SET_INDEXTABLE, 2,
690 s->handle, cx18_stream_enabled(s_idx) ? 7 : 0);
1c1e45d1 691
dcc0ef88 692 /* Call out to the common CX2341x API setup for user controls */
50b86bac
AW
693 priv.cx = cx;
694 priv.s = s;
695 cx2341x_update(&priv, cx18_api_func, NULL, &cx->params);
dcc0ef88
AW
696
697 /*
698 * When starting a capture and we're set for radio,
699 * ensure the video is muted, despite the user control.
700 */
701 if (!cx->params.video_mute &&
702 test_bit(CX18_F_I_RADIO_USER, &cx->i_flags))
703 cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle,
704 (cx->params.video_mute_yuv << 8) | 1);
1c1e45d1
HV
705 }
706
31554ae5 707 if (atomic_read(&cx->tot_capturing) == 0) {
1c1e45d1 708 clear_bit(CX18_F_I_EOS, &cx->i_flags);
b1526421 709 cx18_write_reg(cx, 7, CX18_DSP0_INTERRUPT_MASK);
1c1e45d1
HV
710 }
711
712 cx18_vapi(cx, CX18_CPU_DE_SET_MDL_ACK, 3, s->handle,
990c81c8
AV
713 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][0] - cx->enc_mem,
714 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][1] - cx->enc_mem);
1c1e45d1 715
66c2a6b0 716 /* Init all the cpu_mdls for this stream */
52fcb3ec 717 cx18_stream_configure_mdls(s);
87116159 718 _cx18_stream_load_fw_queue(s);
66c2a6b0 719
1c1e45d1
HV
720 /* begin_capture */
721 if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) {
722 CX18_DEBUG_WARN("Error starting capture!\n");
3b5df8ea 723 /* Ensure we're really not capturing before releasing MDLs */
87116159 724 set_bit(CX18_F_S_STOPPING, &s->s_flags);
3b5df8ea
AW
725 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
726 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1);
727 else
728 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
66c2a6b0
AW
729 clear_bit(CX18_F_S_STREAMING, &s->s_flags);
730 /* FIXME - CX18_F_S_STREAMOFF as well? */
3b5df8ea 731 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
1c1e45d1 732 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
66c2a6b0 733 s->handle = CX18_INVALID_TASK_HANDLE;
87116159 734 clear_bit(CX18_F_S_STOPPING, &s->s_flags);
66c2a6b0
AW
735 if (atomic_read(&cx->tot_capturing) == 0) {
736 set_bit(CX18_F_I_EOS, &cx->i_flags);
737 cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
738 }
1c1e45d1
HV
739 return -EINVAL;
740 }
741
742 /* you're live! sit back and await interrupts :) */
dcc0ef88 743 if (captype != CAPTURE_CHANNEL_TYPE_TS)
31554ae5
HV
744 atomic_inc(&cx->ana_capturing);
745 atomic_inc(&cx->tot_capturing);
1c1e45d1
HV
746 return 0;
747}
748
749void cx18_stop_all_captures(struct cx18 *cx)
750{
751 int i;
752
753 for (i = CX18_MAX_STREAMS - 1; i >= 0; i--) {
754 struct cx18_stream *s = &cx->streams[i];
755
540bab93 756 if (!cx18_stream_enabled(s))
1c1e45d1
HV
757 continue;
758 if (test_bit(CX18_F_S_STREAMING, &s->s_flags))
759 cx18_stop_v4l2_encode_stream(s, 0);
760 }
761}
762
763int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
764{
765 struct cx18 *cx = s->cx;
766 unsigned long then;
767
540bab93 768 if (!cx18_stream_enabled(s))
1c1e45d1
HV
769 return -EINVAL;
770
771 /* This function assumes that you are allowed to stop the capture
772 and that we are actually capturing */
773
774 CX18_DEBUG_INFO("Stop Capture\n");
775
31554ae5 776 if (atomic_read(&cx->tot_capturing) == 0)
1c1e45d1
HV
777 return 0;
778
87116159 779 set_bit(CX18_F_S_STOPPING, &s->s_flags);
1c1e45d1
HV
780 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
781 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end);
782 else
783 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
784
785 then = jiffies;
786
787 if (s->type == CX18_ENC_STREAM_TYPE_MPG && gop_end) {
788 CX18_INFO("ignoring gop_end: not (yet?) supported by the firmware\n");
789 }
790
31554ae5
HV
791 if (s->type != CX18_ENC_STREAM_TYPE_TS)
792 atomic_dec(&cx->ana_capturing);
793 atomic_dec(&cx->tot_capturing);
1c1e45d1
HV
794
795 /* Clear capture and no-read bits */
796 clear_bit(CX18_F_S_STREAMING, &s->s_flags);
797
f68d0cf5
AW
798 /* Tell the CX23418 it can't use our buffers anymore */
799 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
800
1c1e45d1 801 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
d3c5e707 802 s->handle = CX18_INVALID_TASK_HANDLE;
87116159 803 clear_bit(CX18_F_S_STOPPING, &s->s_flags);
1c1e45d1 804
31554ae5 805 if (atomic_read(&cx->tot_capturing) > 0)
1c1e45d1
HV
806 return 0;
807
b1526421 808 cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
1c1e45d1
HV
809 wake_up(&s->waitq);
810
811 return 0;
812}
813
814u32 cx18_find_handle(struct cx18 *cx)
815{
816 int i;
817
818 /* find first available handle to be used for global settings */
819 for (i = 0; i < CX18_MAX_STREAMS; i++) {
820 struct cx18_stream *s = &cx->streams[i];
821
3d05913d 822 if (s->video_dev && (s->handle != CX18_INVALID_TASK_HANDLE))
1c1e45d1
HV
823 return s->handle;
824 }
d3c5e707 825 return CX18_INVALID_TASK_HANDLE;
1c1e45d1 826}
ee2d64f5
AW
827
828struct cx18_stream *cx18_handle_to_stream(struct cx18 *cx, u32 handle)
829{
830 int i;
831 struct cx18_stream *s;
832
833 if (handle == CX18_INVALID_TASK_HANDLE)
834 return NULL;
835
836 for (i = 0; i < CX18_MAX_STREAMS; i++) {
837 s = &cx->streams[i];
838 if (s->handle != handle)
839 continue;
540bab93 840 if (cx18_stream_enabled(s))
ee2d64f5
AW
841 return s;
842 }
843 return NULL;
844}