[net-next-2.6.git] / drivers / media / video / cx18 / cx18-io.c

/*
 *  cx18 driver PCI memory mapped IO access routines
 *
 *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
 *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
 *  02111-1307  USA
 */

#include "cx18-driver.h"
#include "cx18-io.h"
#include "cx18-irq.h"

void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
{
	u8 __iomem *dst = addr;
	u16 val2 = val | (val << 8);
	u32 val4 = val2 | (val2 << 16);

	/* Align writes on the CX23418's addresses */
	if ((count > 0) && ((unsigned long)dst & 1)) {
		cx18_writeb(cx, (u8) val, dst);
		count--;
		dst++;
	}
	if ((count > 1) && ((unsigned long)dst & 2)) {
		cx18_writew(cx, val2, dst);
		count -= 2;
		dst += 2;
	}
	while (count > 3) {
		cx18_writel(cx, val4, dst);
		count -= 4;
		dst += 4;
	}
	if (count > 1) {
		cx18_writew(cx, val2, dst);
		count -= 2;
		dst += 2;
	}
	if (count > 0)
		cx18_writeb(cx, (u8) val, dst);
}

void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
{
	cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
	cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
	cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
}

void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
{
	cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
	cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
}

void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
{
	cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
	cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
	cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
}

void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
{
	cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
	cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
}

void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
{
	u32 r;
	r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
	cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
}

void cx18_setup_page(struct cx18 *cx, u32 addr)
{
	u32 val;
	val = cx18_read_reg(cx, 0xD000F8);
	val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
	cx18_write_reg(cx, val, 0xD000F8);
}
Commit	Line	Data
b1526421 AW	1	/*
	2	* cx18 driver PCI memory mapped IO access routines
	3	*
	4	* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6afdeaf8	5	* Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
b1526421 AW	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
	20	* 02111-1307 USA
	21	*/
	22
	23	#include "cx18-driver.h"
c641d09c	24	#include "cx18-io.h"
b1526421 AW	25	#include "cx18-irq.h"
b1526421 AW	26
b1526421 AW	27	void cx18_memset_io(struct cx18 cx, void __iomem addr, int val, size_t count)
b1526421 AW	28	{
2796073a	29	u8 __iomem *dst = addr;
c641d09c AW	30	u16 val2 = val \| (val << 8);
	31	u32 val4 = val2 \| (val2 << 16);
	32
	33	/* Align writes on the CX23418's addresses */
ac2b97b1 AW	34	if ((count > 0) && ((unsigned long)dst & 1)) {
ac2b97b1 AW	35	cx18_writeb(cx, (u8) val, dst);
c641d09c	36	count--;
ac2b97b1	37	dst++;
c641d09c	38	}
ac2b97b1 AW	39	if ((count > 1) && ((unsigned long)dst & 2)) {
ac2b97b1 AW	40	cx18_writew(cx, val2, dst);
c641d09c	41	count -= 2;
ac2b97b1	42	dst += 2;
c641d09c AW	43	}
c641d09c AW	44	while (count > 3) {
ac2b97b1	45	cx18_writel(cx, val4, dst);
c641d09c	46	count -= 4;
ac2b97b1	47	dst += 4;
c641d09c AW	48	}
c641d09c AW	49	if (count > 1) {
ac2b97b1	50	cx18_writew(cx, val2, dst);
c641d09c	51	count -= 2;
ac2b97b1	52	dst += 2;
c641d09c AW	53	}
c641d09c AW	54	if (count > 0)
ac2b97b1	55	cx18_writeb(cx, (u8) val, dst);
b1526421 AW	56	}
	57
	58	void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
	59	{
f056d29e	60	cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
d6c7e5f8 AW	61	cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) \| val;
d6c7e5f8 AW	62	cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
b1526421 AW	63	}
	64
	65	void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
	66	{
d6c7e5f8 AW	67	cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
d6c7e5f8 AW	68	cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
b1526421 AW	69	}
	70
	71	void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
	72	{
f056d29e	73	cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
d6c7e5f8 AW	74	cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) \| val;
d6c7e5f8 AW	75	cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
b1526421 AW	76	}
	77
	78	void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
	79	{
d6c7e5f8 AW	80	cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
d6c7e5f8 AW	81	cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
b1526421 AW	82	}
b1526421 AW	83
d20ceecd AW	84	void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
	85	{
	86	u32 r;
	87	r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
	88	cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
	89	}
	90
b1526421 AW	91	void cx18_setup_page(struct cx18 *cx, u32 addr)
	92	{
	93	u32 val;
	94	val = cx18_read_reg(cx, 0xD000F8);
	95	val = (val & ~0x1f00) \| ((addr >> 17) & 0x1f00);
	96	cx18_write_reg(cx, val, 0xD000F8);
	97	}