[net-next-2.6.git] / drivers / media / video / cx18 / cx18-av-core.h

/*
 *  cx18 ADEC header
 *
 *  Derived from cx25840-core.h
 *
 *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
 *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version 2
 *  of the License, or (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 *  02110-1301, USA.
 */

#ifndef _CX18_AV_CORE_H_
#define _CX18_AV_CORE_H_

#include <media/v4l2-device.h>

struct cx18;

enum cx18_av_video_input {
	/* Composite video inputs In1-In8 */
	CX18_AV_COMPOSITE1 = 1,
	CX18_AV_COMPOSITE2,
	CX18_AV_COMPOSITE3,
	CX18_AV_COMPOSITE4,
	CX18_AV_COMPOSITE5,
	CX18_AV_COMPOSITE6,
	CX18_AV_COMPOSITE7,
	CX18_AV_COMPOSITE8,

	/* S-Video inputs consist of one luma input (In1-In8) ORed with one
	   chroma input (In5-In8) */
	CX18_AV_SVIDEO_LUMA1 = 0x10,
	CX18_AV_SVIDEO_LUMA2 = 0x20,
	CX18_AV_SVIDEO_LUMA3 = 0x30,
	CX18_AV_SVIDEO_LUMA4 = 0x40,
	CX18_AV_SVIDEO_LUMA5 = 0x50,
	CX18_AV_SVIDEO_LUMA6 = 0x60,
	CX18_AV_SVIDEO_LUMA7 = 0x70,
	CX18_AV_SVIDEO_LUMA8 = 0x80,
	CX18_AV_SVIDEO_CHROMA4 = 0x400,
	CX18_AV_SVIDEO_CHROMA5 = 0x500,
	CX18_AV_SVIDEO_CHROMA6 = 0x600,
	CX18_AV_SVIDEO_CHROMA7 = 0x700,
	CX18_AV_SVIDEO_CHROMA8 = 0x800,

	/* S-Video aliases for common luma/chroma combinations */
	CX18_AV_SVIDEO1 = 0x510,
	CX18_AV_SVIDEO2 = 0x620,
	CX18_AV_SVIDEO3 = 0x730,
	CX18_AV_SVIDEO4 = 0x840,

	/* Component Video inputs consist of one luma input (In1-In8) ORed
	   with a red chroma (In4-In6) and blue chroma input (In7-In8) */
	CX18_AV_COMPONENT_LUMA1 = 0x1000,
	CX18_AV_COMPONENT_LUMA2 = 0x2000,
	CX18_AV_COMPONENT_LUMA3 = 0x3000,
	CX18_AV_COMPONENT_LUMA4 = 0x4000,
	CX18_AV_COMPONENT_LUMA5 = 0x5000,
	CX18_AV_COMPONENT_LUMA6 = 0x6000,
	CX18_AV_COMPONENT_LUMA7 = 0x7000,
	CX18_AV_COMPONENT_LUMA8 = 0x8000,
	CX18_AV_COMPONENT_R_CHROMA4 = 0x40000,
	CX18_AV_COMPONENT_R_CHROMA5 = 0x50000,
	CX18_AV_COMPONENT_R_CHROMA6 = 0x60000,
	CX18_AV_COMPONENT_B_CHROMA7 = 0x700000,
	CX18_AV_COMPONENT_B_CHROMA8 = 0x800000,

	/* Component Video aliases for common combinations */
	CX18_AV_COMPONENT1 = 0x861000,
};

enum cx18_av_audio_input {
	/* Audio inputs: serial or In4-In8 */
	CX18_AV_AUDIO_SERIAL1,
	CX18_AV_AUDIO_SERIAL2,
	CX18_AV_AUDIO4 = 4,
	CX18_AV_AUDIO5,
	CX18_AV_AUDIO6,
	CX18_AV_AUDIO7,
	CX18_AV_AUDIO8,
};

struct cx18_av_state {
	struct v4l2_subdev sd;
	int radio;
	v4l2_std_id std;
	enum cx18_av_video_input vid_input;
	enum cx18_av_audio_input aud_input;
	u32 audclk_freq;
	int audmode;
	int default_volume;
	u32 id;
	u32 rev;
	int is_initialized;

	/*
	 * The VBI slicer starts operating and counting lines, begining at
	 * slicer line count of 1, at D lines after the deassertion of VRESET.
	 * This staring field line, S, is 6 (& 319) or 10 (& 273) for 625 or 525
	 * line systems respectively.  Sliced ancillary data captured on VBI
	 * slicer line M is inserted after the VBI slicer is done with line M,
	 * when VBI slicer line count is N = M+1.  Thus when the VBI slicer
	 * reports a VBI slicer line number with ancillary data, the IDID0 byte
	 * indicates VBI slicer line N.  The actual field line that the captured
	 * data comes from is
	 *
	 * L = M+(S+D-1) = N-1+(S+D-1) = N + (S+D-2).
	 *
	 * L is the line in the field, not frame, from which the VBI data came.
	 * N is the line reported by the slicer in the ancillary data.
	 * D is the slicer_line_delay value programmed into register 0x47f.
	 * S is 6 for 625 line systems or 10 for 525 line systems
	 * (S+D-2) is the slicer_line_offset used to convert slicer reported
	 * line counts to actual field lines.
	 */
	int slicer_line_delay;
	int slicer_line_offset;
};


/* Registers */
#define CXADEC_CHIP_TYPE_TIGER     0x837
#define CXADEC_CHIP_TYPE_MAKO      0x843

#define CXADEC_HOST_REG1           0x000
#define CXADEC_HOST_REG2           0x001

#define CXADEC_CHIP_CTRL           0x100
#define CXADEC_AFE_CTRL            0x104
#define CXADEC_PLL_CTRL1           0x108
#define CXADEC_VID_PLL_FRAC        0x10C
#define CXADEC_AUX_PLL_FRAC        0x110
#define CXADEC_PIN_CTRL1           0x114
#define CXADEC_PIN_CTRL2           0x118
#define CXADEC_PIN_CFG1            0x11C
#define CXADEC_PIN_CFG2            0x120

#define CXADEC_PIN_CFG3            0x124
#define CXADEC_I2S_MCLK            0x127

#define CXADEC_AUD_LOCK1           0x128
#define CXADEC_AUD_LOCK2           0x12C
#define CXADEC_POWER_CTRL          0x130
#define CXADEC_AFE_DIAG_CTRL1      0x134
#define CXADEC_AFE_DIAG_CTRL2      0x138
#define CXADEC_AFE_DIAG_CTRL3      0x13C
#define CXADEC_PLL_DIAG_CTRL       0x140
#define CXADEC_TEST_CTRL1          0x144
#define CXADEC_TEST_CTRL2          0x148
#define CXADEC_BIST_STAT           0x14C
#define CXADEC_DLL1_DIAG_CTRL      0x158
#define CXADEC_DLL2_DIAG_CTRL      0x15C

/* IR registers */
#define CXADEC_IR_CTRL_REG         0x200
#define CXADEC_IR_TXCLK_REG        0x204
#define CXADEC_IR_RXCLK_REG        0x208
#define CXADEC_IR_CDUTY_REG        0x20C
#define CXADEC_IR_STAT_REG         0x210
#define CXADEC_IR_IRQEN_REG        0x214
#define CXADEC_IR_FILTER_REG       0x218
#define CXADEC_IR_FIFO_REG         0x21C

/* Video Registers */
#define CXADEC_MODE_CTRL           0x400
#define CXADEC_OUT_CTRL1           0x404
#define CXADEC_OUT_CTRL2           0x408
#define CXADEC_GEN_STAT            0x40C
#define CXADEC_INT_STAT_MASK       0x410
#define CXADEC_LUMA_CTRL           0x414

#define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414
#define CXADEC_CONTRAST_CTRL_BYTE  0x415
#define CXADEC_LUMA_CTRL_BYTE_3    0x416

#define CXADEC_HSCALE_CTRL         0x418
#define CXADEC_VSCALE_CTRL         0x41C

#define CXADEC_CHROMA_CTRL         0x420

#define CXADEC_USAT_CTRL_BYTE      0x420
#define CXADEC_VSAT_CTRL_BYTE      0x421
#define CXADEC_HUE_CTRL_BYTE       0x422

#define CXADEC_VBI_LINE_CTRL1      0x424
#define CXADEC_VBI_LINE_CTRL2      0x428
#define CXADEC_VBI_LINE_CTRL3      0x42C
#define CXADEC_VBI_LINE_CTRL4      0x430
#define CXADEC_VBI_LINE_CTRL5      0x434
#define CXADEC_VBI_FC_CFG          0x438
#define CXADEC_VBI_MISC_CFG1       0x43C
#define CXADEC_VBI_MISC_CFG2       0x440
#define CXADEC_VBI_PAY1            0x444
#define CXADEC_VBI_PAY2            0x448
#define CXADEC_VBI_CUST1_CFG1      0x44C
#define CXADEC_VBI_CUST1_CFG2      0x450
#define CXADEC_VBI_CUST1_CFG3      0x454
#define CXADEC_VBI_CUST2_CFG1      0x458
#define CXADEC_VBI_CUST2_CFG2      0x45C
#define CXADEC_VBI_CUST2_CFG3      0x460
#define CXADEC_VBI_CUST3_CFG1      0x464
#define CXADEC_VBI_CUST3_CFG2      0x468
#define CXADEC_VBI_CUST3_CFG3      0x46C
#define CXADEC_HORIZ_TIM_CTRL      0x470
#define CXADEC_VERT_TIM_CTRL       0x474
#define CXADEC_SRC_COMB_CFG        0x478
#define CXADEC_CHROMA_VBIOFF_CFG   0x47C
#define CXADEC_FIELD_COUNT         0x480
#define CXADEC_MISC_TIM_CTRL       0x484
#define CXADEC_DFE_CTRL1           0x488
#define CXADEC_DFE_CTRL2           0x48C
#define CXADEC_DFE_CTRL3           0x490
#define CXADEC_PLL_CTRL2           0x494
#define CXADEC_HTL_CTRL            0x498
#define CXADEC_COMB_CTRL           0x49C
#define CXADEC_CRUSH_CTRL          0x4A0
#define CXADEC_SOFT_RST_CTRL       0x4A4
#define CXADEC_MV_DT_CTRL2         0x4A8
#define CXADEC_MV_DT_CTRL3         0x4AC
#define CXADEC_MISC_DIAG_CTRL      0x4B8

#define CXADEC_DL_CTL              0x800
#define CXADEC_DL_CTL_ADDRESS_LOW  0x800   /* Byte 1 in DL_CTL */
#define CXADEC_DL_CTL_ADDRESS_HIGH 0x801   /* Byte 2 in DL_CTL */
#define CXADEC_DL_CTL_DATA         0x802   /* Byte 3 in DL_CTL */
#define CXADEC_DL_CTL_CONTROL      0x803   /* Byte 4 in DL_CTL */

#define CXADEC_STD_DET_STATUS      0x804

#define CXADEC_STD_DET_CTL         0x808
#define CXADEC_STD_DET_CTL_AUD_CTL   0x808 /* Byte 1 in STD_DET_CTL */
#define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */

#define CXADEC_DW8051_INT          0x80C
#define CXADEC_GENERAL_CTL         0x810
#define CXADEC_AAGC_CTL            0x814
#define CXADEC_IF_SRC_CTL          0x818
#define CXADEC_ANLOG_DEMOD_CTL     0x81C
#define CXADEC_ROT_FREQ_CTL        0x820
#define CXADEC_FM1_CTL             0x824
#define CXADEC_PDF_CTL             0x828
#define CXADEC_DFT1_CTL1           0x82C
#define CXADEC_DFT1_CTL2           0x830
#define CXADEC_DFT_STATUS          0x834
#define CXADEC_DFT2_CTL1           0x838
#define CXADEC_DFT2_CTL2           0x83C
#define CXADEC_DFT2_STATUS         0x840
#define CXADEC_DFT3_CTL1           0x844
#define CXADEC_DFT3_CTL2           0x848
#define CXADEC_DFT3_STATUS         0x84C
#define CXADEC_DFT4_CTL1           0x850
#define CXADEC_DFT4_CTL2           0x854
#define CXADEC_DFT4_STATUS         0x858
#define CXADEC_AM_MTS_DET          0x85C
#define CXADEC_ANALOG_MUX_CTL      0x860
#define CXADEC_DIG_PLL_CTL1        0x864
#define CXADEC_DIG_PLL_CTL2        0x868
#define CXADEC_DIG_PLL_CTL3        0x86C
#define CXADEC_DIG_PLL_CTL4        0x870
#define CXADEC_DIG_PLL_CTL5        0x874
#define CXADEC_DEEMPH_GAIN_CTL     0x878
#define CXADEC_DEEMPH_COEF1        0x87C
#define CXADEC_DEEMPH_COEF2        0x880
#define CXADEC_DBX1_CTL1           0x884
#define CXADEC_DBX1_CTL2           0x888
#define CXADEC_DBX1_STATUS         0x88C
#define CXADEC_DBX2_CTL1           0x890
#define CXADEC_DBX2_CTL2           0x894
#define CXADEC_DBX2_STATUS         0x898
#define CXADEC_AM_FM_DIFF          0x89C

/* NICAM registers go here */
#define CXADEC_NICAM_STATUS        0x8C8
#define CXADEC_DEMATRIX_CTL        0x8CC

#define CXADEC_PATH1_CTL1          0x8D0
#define CXADEC_PATH1_VOL_CTL       0x8D4
#define CXADEC_PATH1_EQ_CTL        0x8D8
#define CXADEC_PATH1_SC_CTL        0x8DC

#define CXADEC_PATH2_CTL1          0x8E0
#define CXADEC_PATH2_VOL_CTL       0x8E4
#define CXADEC_PATH2_EQ_CTL        0x8E8
#define CXADEC_PATH2_SC_CTL        0x8EC

#define CXADEC_SRC_CTL             0x8F0
#define CXADEC_SRC_LF_COEF         0x8F4
#define CXADEC_SRC1_CTL            0x8F8
#define CXADEC_SRC2_CTL            0x8FC
#define CXADEC_SRC3_CTL            0x900
#define CXADEC_SRC4_CTL            0x904
#define CXADEC_SRC5_CTL            0x908
#define CXADEC_SRC6_CTL            0x90C

#define CXADEC_BASEBAND_OUT_SEL    0x910
#define CXADEC_I2S_IN_CTL          0x914
#define CXADEC_I2S_OUT_CTL         0x918
#define CXADEC_AC97_CTL            0x91C
#define CXADEC_QAM_PDF             0x920
#define CXADEC_QAM_CONST_DEC       0x924
#define CXADEC_QAM_ROTATOR_FREQ    0x948

/* Bit definitions / settings used in Mako Audio */
#define CXADEC_PREF_MODE_MONO_LANGA        0
#define CXADEC_PREF_MODE_MONO_LANGB        1
#define CXADEC_PREF_MODE_MONO_LANGC        2
#define CXADEC_PREF_MODE_FALLBACK          3
#define CXADEC_PREF_MODE_STEREO            4
#define CXADEC_PREF_MODE_DUAL_LANG_AC      5
#define CXADEC_PREF_MODE_DUAL_LANG_BC      6
#define CXADEC_PREF_MODE_DUAL_LANG_AB      7


#define CXADEC_DETECT_STEREO               1
#define CXADEC_DETECT_DUAL                 2
#define CXADEC_DETECT_TRI                  4
#define CXADEC_DETECT_SAP                  0x10
#define CXADEC_DETECT_NO_SIGNAL            0xFF

#define CXADEC_SELECT_AUDIO_STANDARD_BG    0xF0  /* NICAM BG and A2 BG */
#define CXADEC_SELECT_AUDIO_STANDARD_DK1   0xF1  /* NICAM DK and A2 DK */
#define CXADEC_SELECT_AUDIO_STANDARD_DK2   0xF2
#define CXADEC_SELECT_AUDIO_STANDARD_DK3   0xF3
#define CXADEC_SELECT_AUDIO_STANDARD_I     0xF4  /* NICAM I and A1 */
#define CXADEC_SELECT_AUDIO_STANDARD_L     0xF5  /* NICAM L and System L AM */
#define CXADEC_SELECT_AUDIO_STANDARD_BTSC  0xF6
#define CXADEC_SELECT_AUDIO_STANDARD_EIAJ  0xF7
#define CXADEC_SELECT_AUDIO_STANDARD_A2_M  0xF8  /* A2 M */
#define CXADEC_SELECT_AUDIO_STANDARD_FM    0xF9  /* FM radio */
#define CXADEC_SELECT_AUDIO_STANDARD_AUTO  0xFF  /* Auto detect */

static inline struct cx18_av_state *to_cx18_av_state(struct v4l2_subdev *sd)
{
	return container_of(sd, struct cx18_av_state, sd);
}

/* ----------------------------------------------------------------------- */
/* cx18_av-core.c 							   */
int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value);
int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask);
int cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval,
			  u32 mask);
u8 cx18_av_read(struct cx18 *cx, u16 addr);
u32 cx18_av_read4(struct cx18 *cx, u16 addr);
int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value);
int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value);
void cx18_av_std_setup(struct cx18 *cx);

int cx18_av_probe(struct cx18 *cx);

/* ----------------------------------------------------------------------- */
/* cx18_av-firmware.c                                                      */
int cx18_av_loadfw(struct cx18 *cx);

/* ----------------------------------------------------------------------- */
/* cx18_av-audio.c                                                         */
int cx18_av_audio_g_ctrl(struct cx18 *cx, struct v4l2_control *ctrl);
int cx18_av_audio_s_ctrl(struct cx18 *cx, struct v4l2_control *ctrl);
int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
void cx18_av_audio_set_path(struct cx18 *cx);

/* ----------------------------------------------------------------------- */
/* cx18_av-vbi.c                                                           */
int cx18_av_decode_vbi_line(struct v4l2_subdev *sd,
			   struct v4l2_decode_vbi_line *vbi);
int cx18_av_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt);
int cx18_av_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt);
int cx18_av_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt);

#endif
Commit	Line	Data
1c1e45d1 HV	1	/*
	2	* cx18 ADEC header
	3	*
	4	* Derived from cx25840-core.h
	5	*
	6	* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6afdeaf8	7	* Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
1c1e45d1 HV	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version 2
	12	* of the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
	22	* 02110-1301, USA.
	23	*/
	24
	25	#ifndef _CX18_AV_CORE_H_
	26	#define _CX18_AV_CORE_H_
	27
1a267046 AW	28	#include <media/v4l2-device.h>
1a267046 AW	29
1c1e45d1 HV	30	struct cx18;
	31
	32	enum cx18_av_video_input {
	33	/* Composite video inputs In1-In8 */
	34	CX18_AV_COMPOSITE1 = 1,
	35	CX18_AV_COMPOSITE2,
	36	CX18_AV_COMPOSITE3,
	37	CX18_AV_COMPOSITE4,
	38	CX18_AV_COMPOSITE5,
	39	CX18_AV_COMPOSITE6,
	40	CX18_AV_COMPOSITE7,
	41	CX18_AV_COMPOSITE8,
	42
45270a15	43	/* S-Video inputs consist of one luma input (In1-In8) ORed with one
1c1e45d1 HV	44	chroma input (In5-In8) */
	45	CX18_AV_SVIDEO_LUMA1 = 0x10,
	46	CX18_AV_SVIDEO_LUMA2 = 0x20,
	47	CX18_AV_SVIDEO_LUMA3 = 0x30,
	48	CX18_AV_SVIDEO_LUMA4 = 0x40,
45270a15 HV	49	CX18_AV_SVIDEO_LUMA5 = 0x50,
	50	CX18_AV_SVIDEO_LUMA6 = 0x60,
	51	CX18_AV_SVIDEO_LUMA7 = 0x70,
	52	CX18_AV_SVIDEO_LUMA8 = 0x80,
1c1e45d1 HV	53	CX18_AV_SVIDEO_CHROMA4 = 0x400,
	54	CX18_AV_SVIDEO_CHROMA5 = 0x500,
	55	CX18_AV_SVIDEO_CHROMA6 = 0x600,
	56	CX18_AV_SVIDEO_CHROMA7 = 0x700,
	57	CX18_AV_SVIDEO_CHROMA8 = 0x800,
	58
	59	/* S-Video aliases for common luma/chroma combinations */
	60	CX18_AV_SVIDEO1 = 0x510,
	61	CX18_AV_SVIDEO2 = 0x620,
	62	CX18_AV_SVIDEO3 = 0x730,
	63	CX18_AV_SVIDEO4 = 0x840,
d9a325a8 AW	64
	65	/* Component Video inputs consist of one luma input (In1-In8) ORed
	66	with a red chroma (In4-In6) and blue chroma input (In7-In8) */
	67	CX18_AV_COMPONENT_LUMA1 = 0x1000,
	68	CX18_AV_COMPONENT_LUMA2 = 0x2000,
	69	CX18_AV_COMPONENT_LUMA3 = 0x3000,
	70	CX18_AV_COMPONENT_LUMA4 = 0x4000,
	71	CX18_AV_COMPONENT_LUMA5 = 0x5000,
	72	CX18_AV_COMPONENT_LUMA6 = 0x6000,
	73	CX18_AV_COMPONENT_LUMA7 = 0x7000,
	74	CX18_AV_COMPONENT_LUMA8 = 0x8000,
	75	CX18_AV_COMPONENT_R_CHROMA4 = 0x40000,
	76	CX18_AV_COMPONENT_R_CHROMA5 = 0x50000,
	77	CX18_AV_COMPONENT_R_CHROMA6 = 0x60000,
	78	CX18_AV_COMPONENT_B_CHROMA7 = 0x700000,
	79	CX18_AV_COMPONENT_B_CHROMA8 = 0x800000,
	80
	81	/* Component Video aliases for common combinations */
	82	CX18_AV_COMPONENT1 = 0x861000,
1c1e45d1 HV	83	};
	84
	85	enum cx18_av_audio_input {
	86	/* Audio inputs: serial or In4-In8 */
81cb727d HV	87	CX18_AV_AUDIO_SERIAL1,
81cb727d HV	88	CX18_AV_AUDIO_SERIAL2,
1c1e45d1 HV	89	CX18_AV_AUDIO4 = 4,
	90	CX18_AV_AUDIO5,
	91	CX18_AV_AUDIO6,
	92	CX18_AV_AUDIO7,
	93	CX18_AV_AUDIO8,
	94	};
	95
	96	struct cx18_av_state {
1a267046	97	struct v4l2_subdev sd;
1c1e45d1 HV	98	int radio;
	99	v4l2_std_id std;
	100	enum cx18_av_video_input vid_input;
	101	enum cx18_av_audio_input aud_input;
	102	u32 audclk_freq;
	103	int audmode;
ca130eef	104	int default_volume;
1c1e45d1 HV	105	u32 id;
	106	u32 rev;
	107	int is_initialized;
812b1f9d AW	108
	109	/*
	110	* The VBI slicer starts operating and counting lines, begining at
af7c58b1 AW	111	* slicer line count of 1, at D lines after the deassertion of VRESET.
	112	* This staring field line, S, is 6 (& 319) or 10 (& 273) for 625 or 525
	113	* line systems respectively. Sliced ancillary data captured on VBI
	114	* slicer line M is inserted after the VBI slicer is done with line M,
	115	* when VBI slicer line count is N = M+1. Thus when the VBI slicer
	116	* reports a VBI slicer line number with ancillary data, the IDID0 byte
	117	* indicates VBI slicer line N. The actual field line that the captured
	118	* data comes from is
	119	*
812b1f9d AW	120	* L = M+(S+D-1) = N-1+(S+D-1) = N + (S+D-2).
812b1f9d AW	121	*
af7c58b1 AW	122	* L is the line in the field, not frame, from which the VBI data came.
af7c58b1 AW	123	* N is the line reported by the slicer in the ancillary data.
812b1f9d	124	* D is the slicer_line_delay value programmed into register 0x47f.
af7c58b1	125	* S is 6 for 625 line systems or 10 for 525 line systems
812b1f9d AW	126	* (S+D-2) is the slicer_line_offset used to convert slicer reported
	127	* line counts to actual field lines.
	128	*/
	129	int slicer_line_delay;
	130	int slicer_line_offset;
1c1e45d1 HV	131	};
	132
	133
	134	/* Registers */
	135	#define CXADEC_CHIP_TYPE_TIGER 0x837
	136	#define CXADEC_CHIP_TYPE_MAKO 0x843
	137
	138	#define CXADEC_HOST_REG1 0x000
	139	#define CXADEC_HOST_REG2 0x001
	140
	141	#define CXADEC_CHIP_CTRL 0x100
	142	#define CXADEC_AFE_CTRL 0x104
	143	#define CXADEC_PLL_CTRL1 0x108
	144	#define CXADEC_VID_PLL_FRAC 0x10C
	145	#define CXADEC_AUX_PLL_FRAC 0x110
	146	#define CXADEC_PIN_CTRL1 0x114
	147	#define CXADEC_PIN_CTRL2 0x118
	148	#define CXADEC_PIN_CFG1 0x11C
	149	#define CXADEC_PIN_CFG2 0x120
	150
	151	#define CXADEC_PIN_CFG3 0x124
	152	#define CXADEC_I2S_MCLK 0x127
	153
	154	#define CXADEC_AUD_LOCK1 0x128
	155	#define CXADEC_AUD_LOCK2 0x12C
	156	#define CXADEC_POWER_CTRL 0x130
	157	#define CXADEC_AFE_DIAG_CTRL1 0x134
	158	#define CXADEC_AFE_DIAG_CTRL2 0x138
	159	#define CXADEC_AFE_DIAG_CTRL3 0x13C
	160	#define CXADEC_PLL_DIAG_CTRL 0x140
	161	#define CXADEC_TEST_CTRL1 0x144
	162	#define CXADEC_TEST_CTRL2 0x148
	163	#define CXADEC_BIST_STAT 0x14C
	164	#define CXADEC_DLL1_DIAG_CTRL 0x158
	165	#define CXADEC_DLL2_DIAG_CTRL 0x15C
	166
	167	/* IR registers */
	168	#define CXADEC_IR_CTRL_REG 0x200
	169	#define CXADEC_IR_TXCLK_REG 0x204
	170	#define CXADEC_IR_RXCLK_REG 0x208
	171	#define CXADEC_IR_CDUTY_REG 0x20C
	172	#define CXADEC_IR_STAT_REG 0x210
	173	#define CXADEC_IR_IRQEN_REG 0x214
	174	#define CXADEC_IR_FILTER_REG 0x218
	175	#define CXADEC_IR_FIFO_REG 0x21C
	176
	177	/* Video Registers */
	178	#define CXADEC_MODE_CTRL 0x400
	179	#define CXADEC_OUT_CTRL1 0x404
	180	#define CXADEC_OUT_CTRL2 0x408
	181	#define CXADEC_GEN_STAT 0x40C
	182	#define CXADEC_INT_STAT_MASK 0x410
	183	#define CXADEC_LUMA_CTRL 0x414
	184
	185	#define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414
	186	#define CXADEC_CONTRAST_CTRL_BYTE 0x415
	187	#define CXADEC_LUMA_CTRL_BYTE_3 0x416
	188
	189	#define CXADEC_HSCALE_CTRL 0x418
	190	#define CXADEC_VSCALE_CTRL 0x41C
	191
	192	#define CXADEC_CHROMA_CTRL 0x420
	193
	194	#define CXADEC_USAT_CTRL_BYTE 0x420
195	#define CXADEC_VSAT_CTRL_BYTE 0x421
196	#define CXADEC_HUE_CTRL_BYTE 0x422
197
198	#define CXADEC_VBI_LINE_CTRL1 0x424
199	#define CXADEC_VBI_LINE_CTRL2 0x428
200	#define CXADEC_VBI_LINE_CTRL3 0x42C
201	#define CXADEC_VBI_LINE_CTRL4 0x430
202	#define CXADEC_VBI_LINE_CTRL5 0x434
203	#define CXADEC_VBI_FC_CFG 0x438
204	#define CXADEC_VBI_MISC_CFG1 0x43C
205	#define CXADEC_VBI_MISC_CFG2 0x440
206	#define CXADEC_VBI_PAY1 0x444
207	#define CXADEC_VBI_PAY2 0x448
208	#define CXADEC_VBI_CUST1_CFG1 0x44C
209	#define CXADEC_VBI_CUST1_CFG2 0x450
210	#define CXADEC_VBI_CUST1_CFG3 0x454
211	#define CXADEC_VBI_CUST2_CFG1 0x458
212	#define CXADEC_VBI_CUST2_CFG2 0x45C
213	#define CXADEC_VBI_CUST2_CFG3 0x460
214	#define CXADEC_VBI_CUST3_CFG1 0x464
215	#define CXADEC_VBI_CUST3_CFG2 0x468
216	#define CXADEC_VBI_CUST3_CFG3 0x46C
217	#define CXADEC_HORIZ_TIM_CTRL 0x470
218	#define CXADEC_VERT_TIM_CTRL 0x474
219	#define CXADEC_SRC_COMB_CFG 0x478
220	#define CXADEC_CHROMA_VBIOFF_CFG 0x47C
221	#define CXADEC_FIELD_COUNT 0x480
222	#define CXADEC_MISC_TIM_CTRL 0x484
223	#define CXADEC_DFE_CTRL1 0x488
224	#define CXADEC_DFE_CTRL2 0x48C
225	#define CXADEC_DFE_CTRL3 0x490
226	#define CXADEC_PLL_CTRL2 0x494
227	#define CXADEC_HTL_CTRL 0x498
228	#define CXADEC_COMB_CTRL 0x49C
229	#define CXADEC_CRUSH_CTRL 0x4A0
230	#define CXADEC_SOFT_RST_CTRL 0x4A4
231	#define CXADEC_MV_DT_CTRL2 0x4A8
232	#define CXADEC_MV_DT_CTRL3 0x4AC
233	#define CXADEC_MISC_DIAG_CTRL 0x4B8
234
235	#define CXADEC_DL_CTL 0x800
236	#define CXADEC_DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */
237	#define CXADEC_DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */
238	#define CXADEC_DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */
239	#define CXADEC_DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */
240
241	#define CXADEC_STD_DET_STATUS 0x804
242
243	#define CXADEC_STD_DET_CTL 0x808
244	#define CXADEC_STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */
245	#define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
246
247	#define CXADEC_DW8051_INT 0x80C
248	#define CXADEC_GENERAL_CTL 0x810
249	#define CXADEC_AAGC_CTL 0x814
250	#define CXADEC_IF_SRC_CTL 0x818
251	#define CXADEC_ANLOG_DEMOD_CTL 0x81C
252	#define CXADEC_ROT_FREQ_CTL 0x820
253	#define CXADEC_FM1_CTL 0x824
254	#define CXADEC_PDF_CTL 0x828
255	#define CXADEC_DFT1_CTL1 0x82C
256	#define CXADEC_DFT1_CTL2 0x830
257	#define CXADEC_DFT_STATUS 0x834
258	#define CXADEC_DFT2_CTL1 0x838
259	#define CXADEC_DFT2_CTL2 0x83C
260	#define CXADEC_DFT2_STATUS 0x840
261	#define CXADEC_DFT3_CTL1 0x844
262	#define CXADEC_DFT3_CTL2 0x848
263	#define CXADEC_DFT3_STATUS 0x84C
264	#define CXADEC_DFT4_CTL1 0x850
265	#define CXADEC_DFT4_CTL2 0x854
266	#define CXADEC_DFT4_STATUS 0x858
267	#define CXADEC_AM_MTS_DET 0x85C
268	#define CXADEC_ANALOG_MUX_CTL 0x860
269	#define CXADEC_DIG_PLL_CTL1 0x864
270	#define CXADEC_DIG_PLL_CTL2 0x868
271	#define CXADEC_DIG_PLL_CTL3 0x86C
272	#define CXADEC_DIG_PLL_CTL4 0x870
273	#define CXADEC_DIG_PLL_CTL5 0x874
274	#define CXADEC_DEEMPH_GAIN_CTL 0x878
275	#define CXADEC_DEEMPH_COEF1 0x87C
276	#define CXADEC_DEEMPH_COEF2 0x880
277	#define CXADEC_DBX1_CTL1 0x884
278	#define CXADEC_DBX1_CTL2 0x888
279	#define CXADEC_DBX1_STATUS 0x88C
280	#define CXADEC_DBX2_CTL1 0x890
281	#define CXADEC_DBX2_CTL2 0x894
282	#define CXADEC_DBX2_STATUS 0x898
283	#define CXADEC_AM_FM_DIFF 0x89C
284
285	/* NICAM registers go here */
286	#define CXADEC_NICAM_STATUS 0x8C8
287	#define CXADEC_DEMATRIX_CTL 0x8CC
288
289	#define CXADEC_PATH1_CTL1 0x8D0
290	#define CXADEC_PATH1_VOL_CTL 0x8D4
291	#define CXADEC_PATH1_EQ_CTL 0x8D8
292	#define CXADEC_PATH1_SC_CTL 0x8DC
293
294	#define CXADEC_PATH2_CTL1 0x8E0
295	#define CXADEC_PATH2_VOL_CTL 0x8E4
296	#define CXADEC_PATH2_EQ_CTL 0x8E8
297	#define CXADEC_PATH2_SC_CTL 0x8EC
298
299	#define CXADEC_SRC_CTL 0x8F0
300	#define CXADEC_SRC_LF_COEF 0x8F4
301	#define CXADEC_SRC1_CTL 0x8F8
302	#define CXADEC_SRC2_CTL 0x8FC
303	#define CXADEC_SRC3_CTL 0x900
304	#define CXADEC_SRC4_CTL 0x904
305	#define CXADEC_SRC5_CTL 0x908
306	#define CXADEC_SRC6_CTL 0x90C
307
308	#define CXADEC_BASEBAND_OUT_SEL 0x910
309	#define CXADEC_I2S_IN_CTL 0x914
310	#define CXADEC_I2S_OUT_CTL 0x918
311	#define CXADEC_AC97_CTL 0x91C
312	#define CXADEC_QAM_PDF 0x920
313	#define CXADEC_QAM_CONST_DEC 0x924
314	#define CXADEC_QAM_ROTATOR_FREQ 0x948
315
6070d81e	316	/* Bit definitions / settings used in Mako Audio */
1c1e45d1 HV	317	#define CXADEC_PREF_MODE_MONO_LANGA 0
	318	#define CXADEC_PREF_MODE_MONO_LANGB 1
	319	#define CXADEC_PREF_MODE_MONO_LANGC 2
	320	#define CXADEC_PREF_MODE_FALLBACK 3
	321	#define CXADEC_PREF_MODE_STEREO 4
	322	#define CXADEC_PREF_MODE_DUAL_LANG_AC 5
	323	#define CXADEC_PREF_MODE_DUAL_LANG_BC 6
	324	#define CXADEC_PREF_MODE_DUAL_LANG_AB 7
	325
	326
	327	#define CXADEC_DETECT_STEREO 1
	328	#define CXADEC_DETECT_DUAL 2
	329	#define CXADEC_DETECT_TRI 4
	330	#define CXADEC_DETECT_SAP 0x10
	331	#define CXADEC_DETECT_NO_SIGNAL 0xFF
	332
	333	#define CXADEC_SELECT_AUDIO_STANDARD_BG 0xF0 /* NICAM BG and A2 BG */
	334	#define CXADEC_SELECT_AUDIO_STANDARD_DK1 0xF1 /* NICAM DK and A2 DK */
	335	#define CXADEC_SELECT_AUDIO_STANDARD_DK2 0xF2
	336	#define CXADEC_SELECT_AUDIO_STANDARD_DK3 0xF3
	337	#define CXADEC_SELECT_AUDIO_STANDARD_I 0xF4 /* NICAM I and A1 */
	338	#define CXADEC_SELECT_AUDIO_STANDARD_L 0xF5 /* NICAM L and System L AM */
	339	#define CXADEC_SELECT_AUDIO_STANDARD_BTSC 0xF6
	340	#define CXADEC_SELECT_AUDIO_STANDARD_EIAJ 0xF7
	341	#define CXADEC_SELECT_AUDIO_STANDARD_A2_M 0xF8 /* A2 M */
	342	#define CXADEC_SELECT_AUDIO_STANDARD_FM 0xF9 /* FM radio */
	343	#define CXADEC_SELECT_AUDIO_STANDARD_AUTO 0xFF /* Auto detect */
	344
1a267046 AW	345	static inline struct cx18_av_state to_cx18_av_state(struct v4l2_subdev sd)
	346	{
	347	return container_of(sd, struct cx18_av_state, sd);
	348	}
	349
1c1e45d1 HV	350	/* ----------------------------------------------------------------------- */
	351	/* cx18_av-core.c */
	352	int cx18_av_write(struct cx18 *cx, u16 addr, u8 value);
	353	int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value);
d267d851	354	int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value);
ced07371 AW	355	int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask);
	356	int cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval,
	357	u32 mask);
1c1e45d1 HV	358	u8 cx18_av_read(struct cx18 *cx, u16 addr);
	359	u32 cx18_av_read4(struct cx18 *cx, u16 addr);
	360	int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value);
	361	int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value);
03b52c36	362	void cx18_av_std_setup(struct cx18 *cx);
1c1e45d1	363
ff2a2001	364	int cx18_av_probe(struct cx18 *cx);
1a267046	365
1c1e45d1 HV	366	/* ----------------------------------------------------------------------- */
	367	/* cx18_av-firmware.c */
	368	int cx18_av_loadfw(struct cx18 *cx);
	369
	370	/* ----------------------------------------------------------------------- */
	371	/* cx18_av-audio.c */
41c129a8 HV	372	int cx18_av_audio_g_ctrl(struct cx18 cx, struct v4l2_control ctrl);
	373	int cx18_av_audio_s_ctrl(struct cx18 cx, struct v4l2_control ctrl);
	374	int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
1c1e45d1 HV	375	void cx18_av_audio_set_path(struct cx18 *cx);
	376
	377	/* ----------------------------------------------------------------------- */
	378	/* cx18_av-vbi.c */
41c129a8 HV	379	int cx18_av_decode_vbi_line(struct v4l2_subdev *sd,
41c129a8 HV	380	struct v4l2_decode_vbi_line *vbi);
1585927d HV	381	int cx18_av_s_raw_fmt(struct v4l2_subdev sd, struct v4l2_vbi_format fmt);
	382	int cx18_av_g_sliced_fmt(struct v4l2_subdev sd, struct v4l2_sliced_vbi_format fmt);
	383	int cx18_av_s_sliced_fmt(struct v4l2_subdev sd, struct v4l2_sliced_vbi_format fmt);
1c1e45d1 HV	384
1c1e45d1 HV	385	#endif