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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ryusuke...
[net-next-2.6.git] / drivers / media / dvb / ngene / ngene.h
CommitLineData
dae52d00
MB		 1/*
2 * ngene.h: nGene PCIe bridge driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#ifndef _NGENE_H_
25#define _NGENE_H_
26
dae52d00
MB		 27#include <linux/types.h>
28#include <linux/sched.h>
29#include <linux/interrupt.h>
30#include <linux/i2c.h>
31#include <asm/dma.h>
684688d8 32#include <linux/scatterlist.h>
dae52d00
MB		 33
34#include <linux/dvb/frontend.h>
dae52d00
MB		 35
36#include "dmxdev.h"
37#include "dvbdev.h"
38#include "dvb_demux.h"
39#include "dvb_frontend.h"
40#include "dvb_ringbuffer.h"
dae52d00 41
cbddcba6
DH		 42#define DEVICE_NAME "ngene"
43
dae52d00
MB		 44#define NGENE_VID 0x18c3
45#define NGENE_PID 0x0720
46
47#ifndef VIDEO_CAP_VC1
48#define VIDEO_CAP_AVC 128
49#define VIDEO_CAP_H264 128
50#define VIDEO_CAP_VC1 256
51#define VIDEO_CAP_WMV9 256
52#define VIDEO_CAP_MPEG4 512
53#endif
54
55enum STREAM {
56 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */
57 STREAM_VIDEOIN2,
58 STREAM_AUDIOIN1, /* I2S or SPI Input */
59 STREAM_AUDIOIN2,
60 STREAM_AUDIOOUT,
61 MAX_STREAM
62};
63
64enum SMODE_BITS {
65 SMODE_AUDIO_SPDIF = 0x20,
66 SMODE_AVSYNC = 0x10,
67 SMODE_TRANSPORT_STREAM = 0x08,
68 SMODE_AUDIO_CAPTURE = 0x04,
69 SMODE_VBI_CAPTURE = 0x02,
70 SMODE_VIDEO_CAPTURE = 0x01
71};
72
73enum STREAM_FLAG_BITS {
74 SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */
75 SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
76 SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */
77 SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */
78 SFLAG_COLORBAR = 0x04, /* Select colorbar */
79};
80
81#define PROGRAM_ROM 0x0000
82#define PROGRAM_SRAM 0x1000
83#define PERIPHERALS0 0x8000
84#define PERIPHERALS1 0x9000
85#define SHARED_BUFFER 0xC000
86
87#define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
88#define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
89#define NGENE_COMMAND (SHARED_BUFFER+0x0200)
90#define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
91#define NGENE_STATUS (SHARED_BUFFER+0x0208)
92#define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
93#define NGENE_EVENT (SHARED_BUFFER+0x0210)
94#define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
95#define VARIABLES (SHARED_BUFFER+0x0210)
96
97#define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
98#define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
99#define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
100
101#define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
102#define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
103#define EEPROM_AREA (SHARED_BUFFER+0x0A00)
104
105#define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
106#define SG_VBI_1 (SHARED_BUFFER+0x0B00)
107#define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
108#define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
109#define SG_VBI_2 (SHARED_BUFFER+0x0C80)
110#define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
111#define SG_V_OUT (SHARED_BUFFER+0x0D80)
112#define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
113
114#define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
115#define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
116#define DATA_A_OUT (SHARED_BUFFER+0x0F80)
117#define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
118#define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
119#define DATA_V_OUT (SHARED_BUFFER+0x3000)
120
121#define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
122
123#define TIMESTAMPS 0xA000
124#define SCRATCHPAD 0xA080
125#define FORCE_INT 0xA088
126#define FORCE_NMI 0xA090
127#define INT_STATUS 0xA0A0
128
129#define DEV_VER 0x9004
130
131#define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
132
133struct SG_ADDR {
134 u64 start;
135 u64 curr;
136 u16 curr_ptr;
137 u16 elements;
138 u32 pad[3];
139} __attribute__ ((__packed__));
140
141struct SHARED_MEMORY {
142 /* C000 */
143 u32 HostToNgene[64];
144
145 /* C100 */
146 u32 NgeneToHost[64];
147
148 /* C200 */
149 u64 NgeneCommand;
150 u64 NgeneStatus;
151 u64 NgeneEvent;
152
153 /* C210 */
154 u8 pad1[0xc260 - 0xc218];
155
156 /* C260 */
157 u32 IntCounts;
158 u32 IntEnable;
159
160 /* C268 */
161 u8 pad2[0xd000 - 0xc268];
162
163} __attribute__ ((__packed__));
164
165struct BUFFER_STREAM_RESULTS {
166 u32 Clock; /* Stream time in 100ns units */
167 u16 RemainingLines; /* Remaining lines in this field.
168 0 for complete field */
169 u8 FieldCount; /* Video field number */
170 u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
171 Bit 0 = FieldID */
172 u16 BlockCount; /* Audio block count (unused) */
173 u8 Reserved[2];
174 u32 DTOUpdate;
175} __attribute__ ((__packed__));
176
177struct HW_SCATTER_GATHER_ELEMENT {
178 u64 Address;
179 u32 Length;
180 u32 Reserved;
181} __attribute__ ((__packed__));
182
183struct BUFFER_HEADER {
184 u64 Next;
185 struct BUFFER_STREAM_RESULTS SR;
186
187 u32 Number_of_entries_1;
188 u32 Reserved5;
189 u64 Address_of_first_entry_1;
190
191 u32 Number_of_entries_2;
192 u32 Reserved7;
193 u64 Address_of_first_entry_2;
194} __attribute__ ((__packed__));
195
196struct EVENT_BUFFER {
197 u32 TimeStamp;
198 u8 GPIOStatus;
199 u8 UARTStatus;
200 u8 RXCharacter;
201 u8 EventStatus;
202 u32 Reserved[2];
203} __attribute__ ((__packed__));
204
dae52d00
MB		 205/* Firmware commands. */
206
207enum OPCODES {
208 CMD_NOP = 0,
209 CMD_FWLOAD_PREPARE = 0x01,
210 CMD_FWLOAD_FINISH = 0x02,
211 CMD_I2C_READ = 0x03,
212 CMD_I2C_WRITE = 0x04,
213
214 CMD_I2C_WRITE_NOSTOP = 0x05,
215 CMD_I2C_CONTINUE_WRITE = 0x06,
216 CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
217
218 CMD_DEBUG_OUTPUT = 0x09,
219
220 CMD_CONTROL = 0x10,
221 CMD_CONFIGURE_BUFFER = 0x11,
222 CMD_CONFIGURE_FREE_BUFFER = 0x12,
223
224 CMD_SPI_READ = 0x13,
225 CMD_SPI_WRITE = 0x14,
226
227 CMD_MEM_READ = 0x20,
228 CMD_MEM_WRITE = 0x21,
229 CMD_SFR_READ = 0x22,
230 CMD_SFR_WRITE = 0x23,
231 CMD_IRAM_READ = 0x24,
232 CMD_IRAM_WRITE = 0x25,
233 CMD_SET_GPIO_PIN = 0x26,
234 CMD_SET_GPIO_INT = 0x27,
235 CMD_CONFIGURE_UART = 0x28,
236 CMD_WRITE_UART = 0x29,
237 MAX_CMD
238};
239
240enum RESPONSES {
241 OK = 0,
242 ERROR = 1
243};
244
245struct FW_HEADER {
246 u8 Opcode;
247 u8 Length;
248} __attribute__ ((__packed__));
249
250struct FW_I2C_WRITE {
251 struct FW_HEADER hdr;
252 u8 Device;
253 u8 Data[250];
254} __attribute__ ((__packed__));
255
256struct FW_I2C_CONTINUE_WRITE {
257 struct FW_HEADER hdr;
258 u8 Data[250];
259} __attribute__ ((__packed__));
260
261struct FW_I2C_READ {
262 struct FW_HEADER hdr;
263 u8 Device;
264 u8 Data[252]; /* followed by two bytes of read data count */
265} __attribute__ ((__packed__));
266
267struct FW_SPI_WRITE {
268 struct FW_HEADER hdr;
269 u8 ModeSelect;
270 u8 Data[250];
271} __attribute__ ((__packed__));
272
273struct FW_SPI_READ {
274 struct FW_HEADER hdr;
275 u8 ModeSelect;
276 u8 Data[252]; /* followed by two bytes of read data count */
277} __attribute__ ((__packed__));
278
279struct FW_FWLOAD_PREPARE {
280 struct FW_HEADER hdr;
281} __attribute__ ((__packed__));
282
283struct FW_FWLOAD_FINISH {
284 struct FW_HEADER hdr;
285 u16 Address; /* address of final block */
286 u16 Length;
287} __attribute__ ((__packed__));
288
289/*
290 * Meaning of FW_STREAM_CONTROL::Mode bits:
291 * Bit 7: Loopback PEXin to PEXout using TVOut channel
292 * Bit 6: AVLOOP
293 * Bit 5: Audio select; 0=I2S, 1=SPDIF
294 * Bit 4: AVSYNC
295 * Bit 3: Enable transport stream
296 * Bit 2: Enable audio capture
297 * Bit 1: Enable ITU-Video VBI capture
298 * Bit 0: Enable ITU-Video capture
299 *
300 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
301 * Bit 7: continuous capture
302 * Bit 6: capture one field
303 * Bit 5: capture one frame
304 * Bit 4: unused
305 * Bit 3: starting field; 0=odd, 1=even
306 * Bit 2: sample size; 0=8-bit, 1=10-bit
307 * Bit 1: data format; 0=UYVY, 1=YUY2
308 * Bit 0: resets buffer pointers
309*/
310
311enum FSC_MODE_BITS {
312 SMODE_LOOPBACK = 0x80,
313 SMODE_AVLOOP = 0x40,
314 _SMODE_AUDIO_SPDIF = 0x20,
315 _SMODE_AVSYNC = 0x10,
316 _SMODE_TRANSPORT_STREAM = 0x08,
317 _SMODE_AUDIO_CAPTURE = 0x04,
318 _SMODE_VBI_CAPTURE = 0x02,
319 _SMODE_VIDEO_CAPTURE = 0x01
320};
321
322
323/* Meaning of FW_STREAM_CONTROL::Stream bits:
324 * Bit 3: Audio sample count: 0 = relative, 1 = absolute
325 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
326 * Bits 1-0: stream select, UVI1, UVI2, TVOUT
327 */
328
329struct FW_STREAM_CONTROL {
330 struct FW_HEADER hdr;
331 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */
332 u8 Control; /* Value written to UVI1_CTL */
333 u8 Mode; /* Controls clock source */
334 u8 SetupDataLen; /* Length of setup data, MSB=1 write
335 backwards */
336 u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer
337 for TS and Audio */
338 u64 Buffer_Address; /* Address of first buffer header */
339 u16 BytesPerVideoLine;
340 u16 MaxLinesPerField;
341 u16 MinLinesPerField;
342 u16 Reserved_1;
343 u16 BytesPerVBILine;
344 u16 MaxVBILinesPerField;
345 u16 MinVBILinesPerField;
346 u16 SetupDataAddr; /* ngene relative address of setup data */
347 u8 SetupData[32]; /* setup data */
348} __attribute__((__packed__));
349
350#define AUDIO_BLOCK_SIZE 256
351#define TS_BLOCK_SIZE 256
352
353struct FW_MEM_READ {
354 struct FW_HEADER hdr;
355 u16 address;
356} __attribute__ ((__packed__));
357
358struct FW_MEM_WRITE {
359 struct FW_HEADER hdr;
360 u16 address;
361 u8 data;
362} __attribute__ ((__packed__));
363
364struct FW_SFR_IRAM_READ {
365 struct FW_HEADER hdr;
366 u8 address;
367} __attribute__ ((__packed__));
368
369struct FW_SFR_IRAM_WRITE {
370 struct FW_HEADER hdr;
371 u8 address;
372 u8 data;
373} __attribute__ ((__packed__));
374
375struct FW_SET_GPIO_PIN {
376 struct FW_HEADER hdr;
377 u8 select;
378} __attribute__ ((__packed__));
379
380struct FW_SET_GPIO_INT {
381 struct FW_HEADER hdr;
382 u8 select;
383} __attribute__ ((__packed__));
384
385struct FW_SET_DEBUGMODE {
386 struct FW_HEADER hdr;
387 u8 debug_flags;
388} __attribute__ ((__packed__));
389
390struct FW_CONFIGURE_BUFFERS {
391 struct FW_HEADER hdr;
392 u8 config;
393} __attribute__ ((__packed__));
394
395enum _BUFFER_CONFIGS {
396 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
397 BUFFER_CONFIG_4422 = 0,
398 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
399 BUFFER_CONFIG_3333 = 1,
400 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
401 BUFFER_CONFIG_8022 = 2,
402 BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
403};
404
405struct FW_CONFIGURE_FREE_BUFFERS {
406 struct FW_HEADER hdr;
407 u8 UVI1_BufferLength;
408 u8 UVI2_BufferLength;
409 u8 TVO_BufferLength;
410 u8 AUD1_BufferLength;
411 u8 AUD2_BufferLength;
412 u8 TVA_BufferLength;
413} __attribute__ ((__packed__));
414
415struct FW_CONFIGURE_UART {
416 struct FW_HEADER hdr;
417 u8 UartControl;
418} __attribute__ ((__packed__));
419
420enum _UART_CONFIG {
421 _UART_BAUDRATE_19200 = 0,
422 _UART_BAUDRATE_9600 = 1,
423 _UART_BAUDRATE_4800 = 2,
424 _UART_BAUDRATE_2400 = 3,
425 _UART_RX_ENABLE = 0x40,
426 _UART_TX_ENABLE = 0x80,
427};
428
429struct FW_WRITE_UART {
430 struct FW_HEADER hdr;
431 u8 Data[252];
432} __attribute__ ((__packed__));
433
434
435struct ngene_command {
436 u32 in_len;
437 u32 out_len;
438 union {
439 u32 raw[64];
440 u8 raw8[256];
441 struct FW_HEADER hdr;
442 struct FW_I2C_WRITE I2CWrite;
443 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite;
444 struct FW_I2C_READ I2CRead;
445 struct FW_STREAM_CONTROL StreamControl;
446 struct FW_FWLOAD_PREPARE FWLoadPrepare;
447 struct FW_FWLOAD_FINISH FWLoadFinish;
448 struct FW_MEM_READ MemoryRead;
449 struct FW_MEM_WRITE MemoryWrite;
450 struct FW_SFR_IRAM_READ SfrIramRead;
451 struct FW_SFR_IRAM_WRITE SfrIramWrite;
452 struct FW_SPI_WRITE SPIWrite;
453 struct FW_SPI_READ SPIRead;
454 struct FW_SET_GPIO_PIN SetGpioPin;
455 struct FW_SET_GPIO_INT SetGpioInt;
456 struct FW_SET_DEBUGMODE SetDebugMode;
457 struct FW_CONFIGURE_BUFFERS ConfigureBuffers;
458 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
459 struct FW_CONFIGURE_UART ConfigureUart;
460 struct FW_WRITE_UART WriteUart;
461 } cmd;
462} __attribute__ ((__packed__));
463
464#define NGENE_INTERFACE_VERSION 0x103
465#define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
466#define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
467#define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
468#define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
469#define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
470 Max: (1920x1080i60) */
471
472#define OVERFLOW_BUFFER_SIZE (8192)
473
474#define RING_SIZE_VIDEO 4
475#define RING_SIZE_AUDIO 8
476#define RING_SIZE_TS 8
477
478#define NUM_SCATTER_GATHER_ENTRIES 8
479
480#define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
481 RING_SIZE_VIDEO * 2) + \
482 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
483 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
484 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
485 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
486 (RING_SIZE_TS * PAGE_SIZE * 4) + \
487 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
488
489#define EVENT_QUEUE_SIZE 16
490
dae52d00
MB		 491/* Gathers the current state of a single channel. */
492
493struct SBufferHeader {
494 struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */
495 struct SBufferHeader *Next;
496 void *Buffer1;
684688d8 497 struct HW_SCATTER_GATHER_ELEMENT *scList1;
dae52d00 498 void *Buffer2;
684688d8 499 struct HW_SCATTER_GATHER_ELEMENT *scList2;
dae52d00
MB		 500};
501
502/* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
503#define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
504
505enum HWSTATE {
506 HWSTATE_STOP,
507 HWSTATE_STARTUP,
508 HWSTATE_RUN,
509 HWSTATE_PAUSE,
510};
511
512enum KSSTATE {
513 KSSTATE_STOP,
514 KSSTATE_ACQUIRE,
515 KSSTATE_PAUSE,
516 KSSTATE_RUN,
517};
518
519struct SRingBufferDescriptor {
520 struct SBufferHeader *Head; /* Points to first buffer in ring buffer
521 structure*/
522 u64 PAHead; /* Physical address of first buffer */
523 u32 MemSize; /* Memory size of allocated ring buffers
524 (needed for freeing) */
525 u32 NumBuffers; /* Number of buffers in the ring */
526 u32 Buffer1Length; /* Allocated length of Buffer 1 */
527 u32 Buffer2Length; /* Allocated length of Buffer 2 */
528 void *SCListMem; /* Memory to hold scatter gather lists for this
529 ring */
530 u64 PASCListMem; /* Physical address .. */
531 u32 SCListMemSize; /* Size of this memory */
532};
533
534enum STREAMMODEFLAGS {
535 StreamMode_NONE = 0, /* Stream not used */
536 StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
537 StreamMode_TSIN = 2, /* Transport stream input (all) */
538 StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
539 (only stream 0) */
540 StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */
541};
542
543
544enum BufferExchangeFlags {
545 BEF_EVEN_FIELD = 0x00000001,
546 BEF_CONTINUATION = 0x00000002,
547 BEF_MORE_DATA = 0x00000004,
548 BEF_OVERFLOW = 0x00000008,
549 DF_SWAP32 = 0x00010000,
550};
551
552typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
553
684688d8 554struct MICI_STREAMINFO {
dae52d00
MB		 555 IBufferExchange *pExchange;
556 IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */
557 u8 Stream;
558 u8 Flags;
559 u8 Mode;
560 u8 Reserved;
561 u16 nLinesVideo;
562 u16 nBytesPerLineVideo;
563 u16 nLinesVBI;
564 u16 nBytesPerLineVBI;
565 u32 CaptureLength; /* Used for audio and transport stream */
684688d8 566};
dae52d00
MB		 567
568/****************************************************************************/
569/* STRUCTS ******************************************************************/
570/****************************************************************************/
571
572/* sound hardware definition */
573#define MIXER_ADDR_TVTUNER 0
574#define MIXER_ADDR_LAST 0
575
576struct ngene_channel;
577
578/*struct sound chip*/
579
580struct mychip {
581 struct ngene_channel *chan;
582 struct snd_card *card;
583 struct pci_dev *pci;
584 struct snd_pcm_substream *substream;
585 struct snd_pcm *pcm;
586 unsigned long port;
587 int irq;
588 spinlock_t mixer_lock;
589 spinlock_t lock;
590 int mixer_volume[MIXER_ADDR_LAST + 1][2];
591 int capture_source[MIXER_ADDR_LAST + 1][2];
592};
593
594#ifdef NGENE_V4L
595struct ngene_overlay {
596 int tvnorm;
597 struct v4l2_rect w;
598 enum v4l2_field field;
599 struct v4l2_clip *clips;
600 int nclips;
601 int setup_ok;
602};
603
604struct ngene_tvnorm {
605 int v4l2_id;
606 char *name;
607 u16 swidth, sheight; /* scaled standard width, height */
608 int tuner_norm;
609 int soundstd;
610};
611
612struct ngene_vopen {
613 struct ngene_channel *ch;
614 enum v4l2_priority prio;
615 int width;
616 int height;
617 int depth;
618 struct videobuf_queue vbuf_q;
619 struct videobuf_queue vbi;
620 int fourcc;
621 int picxcount;
622 int resources;
623 enum v4l2_buf_type type;
624 const struct ngene_format *fmt;
625
626 const struct ngene_format *ovfmt;
627 struct ngene_overlay ov;
628};
629#endif
630
631struct ngene_channel {
632 struct device device;
633 struct i2c_adapter i2c_adapter;
634
635 struct ngene *dev;
636 int number;
637 int type;
638 int mode;
639
640 struct dvb_frontend *fe;
641 struct dmxdev dmxdev;
642 struct dvb_demux demux;
643 struct dmx_frontend hw_frontend;
644 struct dmx_frontend mem_frontend;
645 int users;
646 struct video_device *v4l_dev;
dae52d00
MB		 647 struct tasklet_struct demux_tasklet;
648
649 struct SBufferHeader *nextBuffer;
650 enum KSSTATE State;
651 enum HWSTATE HWState;
652 u8 Stream;
653 u8 Flags;
654 u8 Mode;
655 IBufferExchange *pBufferExchange;
656 IBufferExchange *pBufferExchange2;
657
658 spinlock_t state_lock;
659 u16 nLines;
660 u16 nBytesPerLine;
661 u16 nVBILines;
662 u16 nBytesPerVBILine;
663 u16 itumode;
664 u32 Capture1Length;
665 u32 Capture2Length;
666 struct SRingBufferDescriptor RingBuffer;
667 struct SRingBufferDescriptor TSRingBuffer;
668 struct SRingBufferDescriptor TSIdleBuffer;
669
670 u32 DataFormatFlags;
671
672 int AudioDTOUpdated;
673 u32 AudioDTOValue;
674
675 int (*set_tone)(struct dvb_frontend *, fe_sec_tone_mode_t);
676 u8 lnbh;
677
678 /* stuff from analog driver */
679
680 int minor;
681 struct mychip *mychip;
682 struct snd_card *soundcard;
683 u8 *evenbuffer;
dae52d00
MB		 684 u8 dma_on;
685 int soundstreamon;
686 int audiomute;
687 int soundbuffisallocated;
688 int sndbuffflag;
689 int tun_rdy;
690 int dec_rdy;
691 int tun_dec_rdy;
692 int lastbufferflag;
693
694 struct ngene_tvnorm *tvnorms;
695 int tvnorm_num;
696 int tvnorm;
697
698#ifdef NGENE_V4L
699 int videousers;
700 struct v4l2_prio_state prio;
701 struct ngene_vopen init;
702 int resources;
703 struct v4l2_framebuffer fbuf;
704 struct ngene_buffer *screen; /* overlay */
705 struct list_head capture; /* video capture queue */
706 spinlock_t s_lock;
707 struct semaphore reslock;
708#endif
709
710 int running;
711};
712
713struct ngene;
714
715typedef void (rx_cb_t)(struct ngene *, u32, u8);
716typedef void (tx_cb_t)(struct ngene *, u32);
717
718struct ngene {
719 int nr;
720 struct pci_dev *pci_dev;
721 unsigned char *iomem;
722
dae52d00
MB		 723 /*struct i2c_adapter i2c_adapter;*/
724
725 u32 device_version;
726 u32 fw_interface_version;
727 u32 icounts;
43874181 728 bool msi_enabled;
5a2a1848 729 bool cmd_timeout_workaround;
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MB		 730
731 u8 *CmdDoneByte;
732 int BootFirmware;
733 void *OverflowBuffer;
734 dma_addr_t PAOverflowBuffer;
735 void *FWInterfaceBuffer;
736 dma_addr_t PAFWInterfaceBuffer;
737 u8 *ngenetohost;
738 u8 *hosttongene;
739
740 struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE];
741 int EventQueueOverflowCount;
742 int EventQueueOverflowFlag;
743 struct tasklet_struct event_tasklet;
744 struct EVENT_BUFFER *EventBuffer;
745 int EventQueueWriteIndex;
746 int EventQueueReadIndex;
747
748 wait_queue_head_t cmd_wq;
749 int cmd_done;
750 struct semaphore cmd_mutex;
751 struct semaphore stream_mutex;
752 struct semaphore pll_mutex;
753 struct semaphore i2c_switch_mutex;
754 int i2c_current_channel;
755 int i2c_current_bus;
756 spinlock_t cmd_lock;
757
cf1b12f2 758 struct dvb_adapter adapter[MAX_STREAM];
fdafc96c 759 struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */
dae52d00
MB		 760 struct ngene_channel channel[MAX_STREAM];
761
762 struct ngene_info *card_info;
763
764 tx_cb_t *TxEventNotify;
765 rx_cb_t *RxEventNotify;
766 int tx_busy;
767 wait_queue_head_t tx_wq;
768 wait_queue_head_t rx_wq;
769#define UART_RBUF_LEN 4096
770 u8 uart_rbuf[UART_RBUF_LEN];
771 int uart_rp, uart_wp;
772
773 u8 *tsout_buf;
774#define TSOUT_BUF_SIZE (512*188*8)
775 struct dvb_ringbuffer tsout_rbuf;
776
777 u8 *ain_buf;
778#define AIN_BUF_SIZE (128*1024)
779 struct dvb_ringbuffer ain_rbuf;
780
781
782 u8 *vin_buf;
783#define VIN_BUF_SIZE (4*1920*1080)
784 struct dvb_ringbuffer vin_rbuf;
785
786 unsigned long exp_val;
787 int prev_cmd;
788};
789
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MB		 790struct ngene_info {
791 int type;
792#define NGENE_APP 0
793#define NGENE_TERRATEC 1
794#define NGENE_SIDEWINDER 2
795#define NGENE_RACER 3
796#define NGENE_VIPER 4
797#define NGENE_PYTHON 5
798#define NGENE_VBOX_V1 6
799#define NGENE_VBOX_V2 7
800
801 int fw_version;
43874181 802 bool msi_supported;
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MB		 803 char *name;
804
805 int io_type[MAX_STREAM];
806#define NGENE_IO_NONE 0
807#define NGENE_IO_TV 1
808#define NGENE_IO_HDTV 2
809#define NGENE_IO_TSIN 4
810#define NGENE_IO_TSOUT 8
811#define NGENE_IO_AIN 16
812
813 void *fe_config[4];
814 void *tuner_config[4];
815
816 int (*demod_attach[4])(struct ngene_channel *);
817 int (*tuner_attach[4])(struct ngene_channel *);
818
819 u8 avf[4];
820 u8 msp[4];
821 u8 demoda[4];
822 u8 lnb[4];
823 int i2c_access;
824 u8 ntsc;
dae52d00
MB		 825 u8 tsf[4];
826 u8 i2s[4];
827
828 int (*gate_ctrl)(struct dvb_frontend *, int);
829 int (*switch_ctrl)(struct ngene_channel *, int, int);
830};
831
832#ifdef NGENE_V4L
833struct ngene_format{
834 char *name;
835 int fourcc; /* video4linux 2 */
836 int btformat; /* BT848_COLOR_FMT_* */
837 int format;
838 int btswap; /* BT848_COLOR_CTL_* */
839 int depth; /* bit/pixel */
840 int flags;
841 int hshift, vshift; /* for planar modes */
842 int palette;
843};
844
845#define RESOURCE_OVERLAY 1
846#define RESOURCE_VIDEO 2
847#define RESOURCE_VBI 4
848
849struct ngene_buffer {
850 /* common v4l buffer stuff -- must be first */
851 struct videobuf_buffer vb;
852
853 /* ngene specific */
854 const struct ngene_format *fmt;
855 int tvnorm;
856 int btformat;
857 int btswap;
858};
859#endif
860
dae52d00 861
cb1c0f8e 862/* Provided by ngene-core.c */
cbddcba6
DH		 863int __devinit ngene_probe(struct pci_dev *pci_dev,
864 const struct pci_device_id *id);
865void __devexit ngene_remove(struct pci_dev *pdev);
cb1c0f8e
DH		 866int ngene_command(struct ngene *dev, struct ngene_command *com);
867int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level);
1899e97c
DH		 868void set_transfer(struct ngene_channel *chan, int state);
869void FillTSBuffer(void *Buffer, int Length, u32 Flags);
cb1c0f8e
DH		 870
871/* Provided by ngene-i2c.c */
872int ngene_i2c_init(struct ngene *dev, int dev_nr);
873
1899e97c
DH		 874/* Provided by ngene-dvb.c */
875void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
876void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
877int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed);
878int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed);
879int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
880 int (*start_feed)(struct dvb_demux_feed *),
881 int (*stop_feed)(struct dvb_demux_feed *),
882 void *priv);
883int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
884 struct dvb_demux *dvbdemux,
885 struct dmx_frontend *hw_frontend,
886 struct dmx_frontend *mem_frontend,
887 struct dvb_adapter *dvb_adapter);
888
dae52d00
MB		 889#endif
890
891/* LocalWords: Endif
892 */
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