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KVM: Remove gratuitous casts from lapic.c
[net-next-2.6.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
e7d5d76c 19#include "x86_emulate.h"
85f455f7 20#include "irq.h"
6aa8b732 21#include "vmx.h"
e495606d
AK		 22#include "segment_descriptor.h"
23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e495606d 30
6aa8b732 31#include <asm/io.h>
3b3be0d1 32#include <asm/desc.h>
6aa8b732 33
6aa8b732
AK		 34MODULE_AUTHOR("Qumranet");
35MODULE_LICENSE("GPL");
36
c7addb90
AK		 37static int bypass_guest_pf = 1;
38module_param(bypass_guest_pf, bool, 0);
39
a2fa3e9f
GH		 40struct vmcs {
41 u32 revision_id;
42 u32 abort;
43 char data[0];
44};
45
46struct vcpu_vmx {
fb3f0f51 47 struct kvm_vcpu vcpu;
a2fa3e9f 48 int launched;
29bd8a78 49 u8 fail;
a2fa3e9f
GH		 50 struct kvm_msr_entry *guest_msrs;
51 struct kvm_msr_entry *host_msrs;
52 int nmsrs;
53 int save_nmsrs;
54 int msr_offset_efer;
55#ifdef CONFIG_X86_64
56 int msr_offset_kernel_gs_base;
57#endif
58 struct vmcs *vmcs;
59 struct {
60 int loaded;
61 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 62 int gs_ldt_reload_needed;
63 int fs_reload_needed;
51c6cf66 64 int guest_efer_loaded;
a2fa3e9f
GH		 65 }host_state;
66
67};
68
69static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
70{
fb3f0f51 71 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 72}
73
75880a01
AK		 74static int init_rmode_tss(struct kvm *kvm);
75
6aa8b732
AK		 76static DEFINE_PER_CPU(struct vmcs *, vmxarea);
77static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
78
fdef3ad1
HQ		 79static struct page *vmx_io_bitmap_a;
80static struct page *vmx_io_bitmap_b;
81
1c3d14fe 82static struct vmcs_config {
6aa8b732
AK		 83 int size;
84 int order;
85 u32 revision_id;
1c3d14fe
YS		 86 u32 pin_based_exec_ctrl;
87 u32 cpu_based_exec_ctrl;
88 u32 vmexit_ctrl;
89 u32 vmentry_ctrl;
90} vmcs_config;
6aa8b732
AK		 91
92#define VMX_SEGMENT_FIELD(seg) \
93 [VCPU_SREG_##seg] = { \
94 .selector = GUEST_##seg##_SELECTOR, \
95 .base = GUEST_##seg##_BASE, \
96 .limit = GUEST_##seg##_LIMIT, \
97 .ar_bytes = GUEST_##seg##_AR_BYTES, \
98 }
99
100static struct kvm_vmx_segment_field {
101 unsigned selector;
102 unsigned base;
103 unsigned limit;
104 unsigned ar_bytes;
105} kvm_vmx_segment_fields[] = {
106 VMX_SEGMENT_FIELD(CS),
107 VMX_SEGMENT_FIELD(DS),
108 VMX_SEGMENT_FIELD(ES),
109 VMX_SEGMENT_FIELD(FS),
110 VMX_SEGMENT_FIELD(GS),
111 VMX_SEGMENT_FIELD(SS),
112 VMX_SEGMENT_FIELD(TR),
113 VMX_SEGMENT_FIELD(LDTR),
114};
115
4d56c8a7
AK		 116/*
117 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
118 * away by decrementing the array size.
119 */
6aa8b732 120static const u32 vmx_msr_index[] = {
05b3e0c2 121#ifdef CONFIG_X86_64
6aa8b732
AK		 122 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
123#endif
124 MSR_EFER, MSR_K6_STAR,
125};
9d8f549d 126#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 127
a2fa3e9f
GH		 128static void load_msrs(struct kvm_msr_entry *e, int n)
129{
130 int i;
131
132 for (i = 0; i < n; ++i)
133 wrmsrl(e[i].index, e[i].data);
134}
135
136static void save_msrs(struct kvm_msr_entry *e, int n)
137{
138 int i;
139
140 for (i = 0; i < n; ++i)
141 rdmsrl(e[i].index, e[i].data);
142}
143
6aa8b732
AK		 144static inline int is_page_fault(u32 intr_info)
145{
146 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
147 INTR_INFO_VALID_MASK)) ==
148 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
149}
150
2ab455cc
AL		 151static inline int is_no_device(u32 intr_info)
152{
153 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
154 INTR_INFO_VALID_MASK)) ==
155 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
156}
157
7aa81cc0
AL		 158static inline int is_invalid_opcode(u32 intr_info)
159{
160 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
161 INTR_INFO_VALID_MASK)) ==
162 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
163}
164
6aa8b732
AK		 165static inline int is_external_interrupt(u32 intr_info)
166{
167 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
168 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
169}
170
6e5d865c
YS		 171static inline int cpu_has_vmx_tpr_shadow(void)
172{
173 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
174}
175
176static inline int vm_need_tpr_shadow(struct kvm *kvm)
177{
178 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
179}
180
8b9cf98c 181static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 182{
183 int i;
184
a2fa3e9f
GH		 185 for (i = 0; i < vmx->nmsrs; ++i)
186 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 187 return i;
188 return -1;
189}
190
8b9cf98c 191static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 192{
193 int i;
194
8b9cf98c 195 i = __find_msr_index(vmx, msr);
a75beee6 196 if (i >= 0)
a2fa3e9f 197 return &vmx->guest_msrs[i];
8b6d44c7 198 return NULL;
7725f0ba
AK		 199}
200
6aa8b732
AK		 201static void vmcs_clear(struct vmcs *vmcs)
202{
203 u64 phys_addr = __pa(vmcs);
204 u8 error;
205
206 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
207 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
208 : "cc", "memory");
209 if (error)
210 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
211 vmcs, phys_addr);
212}
213
214static void __vcpu_clear(void *arg)
215{
8b9cf98c 216 struct vcpu_vmx *vmx = arg;
d3b2c338 217 int cpu = raw_smp_processor_id();
6aa8b732 218
8b9cf98c 219 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 220 vmcs_clear(vmx->vmcs);
221 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 222 per_cpu(current_vmcs, cpu) = NULL;
8b9cf98c 223 rdtscll(vmx->vcpu.host_tsc);
6aa8b732
AK		 224}
225
8b9cf98c 226static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 227{
eae5ecb5
AK		 228 if (vmx->vcpu.cpu == -1)
229 return;
f566e09f 230 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
8b9cf98c 231 vmx->launched = 0;
8d0be2b3
AK		 232}
233
6aa8b732
AK		 234static unsigned long vmcs_readl(unsigned long field)
235{
236 unsigned long value;
237
238 asm volatile (ASM_VMX_VMREAD_RDX_RAX
239 : "=a"(value) : "d"(field) : "cc");
240 return value;
241}
242
243static u16 vmcs_read16(unsigned long field)
244{
245 return vmcs_readl(field);
246}
247
248static u32 vmcs_read32(unsigned long field)
249{
250 return vmcs_readl(field);
251}
252
253static u64 vmcs_read64(unsigned long field)
254{
05b3e0c2 255#ifdef CONFIG_X86_64
6aa8b732
AK		 256 return vmcs_readl(field);
257#else
258 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
259#endif
260}
261
e52de1b8
AK		 262static noinline void vmwrite_error(unsigned long field, unsigned long value)
263{
264 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
265 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
266 dump_stack();
267}
268
6aa8b732
AK		 269static void vmcs_writel(unsigned long field, unsigned long value)
270{
271 u8 error;
272
273 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
274 : "=q"(error) : "a"(value), "d"(field) : "cc" );
e52de1b8
AK		 275 if (unlikely(error))
276 vmwrite_error(field, value);
6aa8b732
AK		 277}
278
279static void vmcs_write16(unsigned long field, u16 value)
280{
281 vmcs_writel(field, value);
282}
283
284static void vmcs_write32(unsigned long field, u32 value)
285{
286 vmcs_writel(field, value);
287}
288
289static void vmcs_write64(unsigned long field, u64 value)
290{
05b3e0c2 291#ifdef CONFIG_X86_64
6aa8b732
AK		 292 vmcs_writel(field, value);
293#else
294 vmcs_writel(field, value);
295 asm volatile ("");
296 vmcs_writel(field+1, value >> 32);
297#endif
298}
299
2ab455cc
AL		 300static void vmcs_clear_bits(unsigned long field, u32 mask)
301{
302 vmcs_writel(field, vmcs_readl(field) & ~mask);
303}
304
305static void vmcs_set_bits(unsigned long field, u32 mask)
306{
307 vmcs_writel(field, vmcs_readl(field) | mask);
308}
309
abd3f2d6
AK		 310static void update_exception_bitmap(struct kvm_vcpu *vcpu)
311{
312 u32 eb;
313
7aa81cc0 314 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 315 if (!vcpu->fpu_active)
316 eb |= 1u << NM_VECTOR;
317 if (vcpu->guest_debug.enabled)
318 eb |= 1u << 1;
319 if (vcpu->rmode.active)
320 eb = ~0;
321 vmcs_write32(EXCEPTION_BITMAP, eb);
322}
323
33ed6329
AK		 324static void reload_tss(void)
325{
326#ifndef CONFIG_X86_64
327
328 /*
329 * VT restores TR but not its size. Useless.
330 */
331 struct descriptor_table gdt;
332 struct segment_descriptor *descs;
333
334 get_gdt(&gdt);
335 descs = (void *)gdt.base;
336 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
337 load_TR_desc();
338#endif
339}
340
8b9cf98c 341static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 342{
a2fa3e9f 343 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 344 u64 host_efer = vmx->host_msrs[efer_offset].data;
345 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
346 u64 ignore_bits;
347
348 if (efer_offset < 0)
349 return;
350 /*
351 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
352 * outside long mode
353 */
354 ignore_bits = EFER_NX | EFER_SCE;
355#ifdef CONFIG_X86_64
356 ignore_bits |= EFER_LMA | EFER_LME;
357 /* SCE is meaningful only in long mode on Intel */
358 if (guest_efer & EFER_LMA)
359 ignore_bits &= ~(u64)EFER_SCE;
360#endif
361 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
362 return;
2cc51560 363
51c6cf66
AK		 364 vmx->host_state.guest_efer_loaded = 1;
365 guest_efer &= ~ignore_bits;
366 guest_efer |= host_efer & ignore_bits;
367 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 368 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 369}
370
51c6cf66
AK		 371static void reload_host_efer(struct vcpu_vmx *vmx)
372{
373 if (vmx->host_state.guest_efer_loaded) {
374 vmx->host_state.guest_efer_loaded = 0;
375 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
376 }
377}
378
04d2cc77 379static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 380{
04d2cc77
AK		 381 struct vcpu_vmx *vmx = to_vmx(vcpu);
382
a2fa3e9f 383 if (vmx->host_state.loaded)
33ed6329
AK		 384 return;
385
a2fa3e9f 386 vmx->host_state.loaded = 1;
33ed6329
AK		 387 /*
388 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
389 * allow segment selectors with cpl > 0 or ti == 1.
390 */
a2fa3e9f 391 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 392 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 393 vmx->host_state.fs_sel = read_fs();
152d3f2f 394 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 395 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 396 vmx->host_state.fs_reload_needed = 0;
397 } else {
33ed6329 398 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 399 vmx->host_state.fs_reload_needed = 1;
33ed6329 400 }
a2fa3e9f
GH		 401 vmx->host_state.gs_sel = read_gs();
402 if (!(vmx->host_state.gs_sel & 7))
403 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 404 else {
405 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 406 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 407 }
408
409#ifdef CONFIG_X86_64
410 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
411 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
412#else
a2fa3e9f
GH		 413 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
414 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 415#endif
707c0874
AK		 416
417#ifdef CONFIG_X86_64
8b9cf98c 418 if (is_long_mode(&vmx->vcpu)) {
a2fa3e9f
GH		 419 save_msrs(vmx->host_msrs +
420 vmx->msr_offset_kernel_gs_base, 1);
707c0874
AK		 421 }
422#endif
a2fa3e9f 423 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 424 load_transition_efer(vmx);
33ed6329
AK		 425}
426
8b9cf98c 427static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 428{
15ad7146 429 unsigned long flags;
33ed6329 430
a2fa3e9f 431 if (!vmx->host_state.loaded)
33ed6329
AK		 432 return;
433
a2fa3e9f 434 vmx->host_state.loaded = 0;
152d3f2f 435 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 436 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 437 if (vmx->host_state.gs_ldt_reload_needed) {
438 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 439 /*
440 * If we have to reload gs, we must take care to
441 * preserve our gs base.
442 */
15ad7146 443 local_irq_save(flags);
a2fa3e9f 444 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 445#ifdef CONFIG_X86_64
446 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
447#endif
15ad7146 448 local_irq_restore(flags);
33ed6329 449 }
152d3f2f 450 reload_tss();
a2fa3e9f
GH		 451 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
452 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 453 reload_host_efer(vmx);
33ed6329
AK		 454}
455
6aa8b732
AK		 456/*
457 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
458 * vcpu mutex is already taken.
459 */
15ad7146 460static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 461{
a2fa3e9f
GH		 462 struct vcpu_vmx *vmx = to_vmx(vcpu);
463 u64 phys_addr = __pa(vmx->vmcs);
7700270e 464 u64 tsc_this, delta;
6aa8b732 465
a3d7f85f 466 if (vcpu->cpu != cpu) {
8b9cf98c 467 vcpu_clear(vmx);
a3d7f85f
ED		 468 kvm_migrate_apic_timer(vcpu);
469 }
6aa8b732 470
a2fa3e9f 471 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 472 u8 error;
473
a2fa3e9f 474 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 475 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
476 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
477 : "cc");
478 if (error)
479 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 480 vmx->vmcs, phys_addr);
6aa8b732
AK		 481 }
482
483 if (vcpu->cpu != cpu) {
484 struct descriptor_table dt;
485 unsigned long sysenter_esp;
486
487 vcpu->cpu = cpu;
488 /*
489 * Linux uses per-cpu TSS and GDT, so set these when switching
490 * processors.
491 */
492 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
493 get_gdt(&dt);
494 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
495
496 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
497 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 498
499 /*
500 * Make sure the time stamp counter is monotonous.
501 */
502 rdtscll(tsc_this);
503 delta = vcpu->host_tsc - tsc_this;
504 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
6aa8b732 505 }
6aa8b732
AK		 506}
507
508static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
509{
8b9cf98c 510 vmx_load_host_state(to_vmx(vcpu));
7702fd1f 511 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 512}
513
5fd86fcf
AK		 514static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
515{
516 if (vcpu->fpu_active)
517 return;
518 vcpu->fpu_active = 1;
707d92fa
RR		 519 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
520 if (vcpu->cr0 & X86_CR0_TS)
521 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 522 update_exception_bitmap(vcpu);
523}
524
525static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
526{
527 if (!vcpu->fpu_active)
528 return;
529 vcpu->fpu_active = 0;
707d92fa 530 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 531 update_exception_bitmap(vcpu);
532}
533
774c47f1
AK		 534static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
535{
8b9cf98c 536 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 537}
538
6aa8b732
AK		 539static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
540{
541 return vmcs_readl(GUEST_RFLAGS);
542}
543
544static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
545{
78f78268 546 if (vcpu->rmode.active)
053de044 547 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 548 vmcs_writel(GUEST_RFLAGS, rflags);
549}
550
551static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
552{
553 unsigned long rip;
554 u32 interruptibility;
555
556 rip = vmcs_readl(GUEST_RIP);
557 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
558 vmcs_writel(GUEST_RIP, rip);
559
560 /*
561 * We emulated an instruction, so temporary interrupt blocking
562 * should be removed, if set.
563 */
564 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
565 if (interruptibility & 3)
566 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
567 interruptibility & ~3);
c1150d8c 568 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 569}
570
571static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
572{
573 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
574 vmcs_readl(GUEST_RIP));
575 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
576 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
577 GP_VECTOR |
578 INTR_TYPE_EXCEPTION |
579 INTR_INFO_DELIEVER_CODE_MASK |
580 INTR_INFO_VALID_MASK);
581}
582
7aa81cc0
AL		 583static void vmx_inject_ud(struct kvm_vcpu *vcpu)
584{
585 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
586 UD_VECTOR |
587 INTR_TYPE_EXCEPTION |
588 INTR_INFO_VALID_MASK);
589}
590
a75beee6
ED		 591/*
592 * Swap MSR entry in host/guest MSR entry array.
593 */
54e11fa1 594#ifdef CONFIG_X86_64
8b9cf98c 595static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 596{
a2fa3e9f
GH		 597 struct kvm_msr_entry tmp;
598
599 tmp = vmx->guest_msrs[to];
600 vmx->guest_msrs[to] = vmx->guest_msrs[from];
601 vmx->guest_msrs[from] = tmp;
602 tmp = vmx->host_msrs[to];
603 vmx->host_msrs[to] = vmx->host_msrs[from];
604 vmx->host_msrs[from] = tmp;
a75beee6 605}
54e11fa1 606#endif
a75beee6 607
e38aea3e
AK		 608/*
609 * Set up the vmcs to automatically save and restore system
610 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
611 * mode, as fiddling with msrs is very expensive.
612 */
8b9cf98c 613static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 614{
2cc51560 615 int save_nmsrs;
e38aea3e 616
a75beee6
ED		 617 save_nmsrs = 0;
618#ifdef CONFIG_X86_64
8b9cf98c 619 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 620 int index;
621
8b9cf98c 622 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 623 if (index >= 0)
8b9cf98c
RR		 624 move_msr_up(vmx, index, save_nmsrs++);
625 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 626 if (index >= 0)
8b9cf98c
RR		 627 move_msr_up(vmx, index, save_nmsrs++);
628 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 629 if (index >= 0)
8b9cf98c
RR		 630 move_msr_up(vmx, index, save_nmsrs++);
631 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 632 if (index >= 0)
8b9cf98c 633 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 634 /*
635 * MSR_K6_STAR is only needed on long mode guests, and only
636 * if efer.sce is enabled.
637 */
8b9cf98c
RR		 638 index = __find_msr_index(vmx, MSR_K6_STAR);
639 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
640 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 641 }
642#endif
a2fa3e9f 643 vmx->save_nmsrs = save_nmsrs;
e38aea3e 644
4d56c8a7 645#ifdef CONFIG_X86_64
a2fa3e9f 646 vmx->msr_offset_kernel_gs_base =
8b9cf98c 647 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 648#endif
8b9cf98c 649 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 650}
651
6aa8b732
AK		 652/*
653 * reads and returns guest's timestamp counter "register"
654 * guest_tsc = host_tsc + tsc_offset -- 21.3
655 */
656static u64 guest_read_tsc(void)
657{
658 u64 host_tsc, tsc_offset;
659
660 rdtscll(host_tsc);
661 tsc_offset = vmcs_read64(TSC_OFFSET);
662 return host_tsc + tsc_offset;
663}
664
665/*
666 * writes 'guest_tsc' into guest's timestamp counter "register"
667 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
668 */
669static void guest_write_tsc(u64 guest_tsc)
670{
671 u64 host_tsc;
672
673 rdtscll(host_tsc);
674 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
675}
676
6aa8b732
AK		 677/*
678 * Reads an msr value (of 'msr_index') into 'pdata'.
679 * Returns 0 on success, non-0 otherwise.
680 * Assumes vcpu_load() was already called.
681 */
682static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
683{
684 u64 data;
a2fa3e9f 685 struct kvm_msr_entry *msr;
6aa8b732
AK		 686
687 if (!pdata) {
688 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
689 return -EINVAL;
690 }
691
692 switch (msr_index) {
05b3e0c2 693#ifdef CONFIG_X86_64
6aa8b732
AK		 694 case MSR_FS_BASE:
695 data = vmcs_readl(GUEST_FS_BASE);
696 break;
697 case MSR_GS_BASE:
698 data = vmcs_readl(GUEST_GS_BASE);
699 break;
700 case MSR_EFER:
3bab1f5d 701 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 702#endif
703 case MSR_IA32_TIME_STAMP_COUNTER:
704 data = guest_read_tsc();
705 break;
706 case MSR_IA32_SYSENTER_CS:
707 data = vmcs_read32(GUEST_SYSENTER_CS);
708 break;
709 case MSR_IA32_SYSENTER_EIP:
f5b42c33 710 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 711 break;
712 case MSR_IA32_SYSENTER_ESP:
f5b42c33 713 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 714 break;
6aa8b732 715 default:
8b9cf98c 716 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 717 if (msr) {
718 data = msr->data;
719 break;
6aa8b732 720 }
3bab1f5d 721 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 722 }
723
724 *pdata = data;
725 return 0;
726}
727
728/*
729 * Writes msr value into into the appropriate "register".
730 * Returns 0 on success, non-0 otherwise.
731 * Assumes vcpu_load() was already called.
732 */
733static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
734{
a2fa3e9f
GH		 735 struct vcpu_vmx *vmx = to_vmx(vcpu);
736 struct kvm_msr_entry *msr;
2cc51560
ED		 737 int ret = 0;
738
6aa8b732 739 switch (msr_index) {
05b3e0c2 740#ifdef CONFIG_X86_64
3bab1f5d 741 case MSR_EFER:
2cc51560 742 ret = kvm_set_msr_common(vcpu, msr_index, data);
51c6cf66
AK		 743 if (vmx->host_state.loaded) {
744 reload_host_efer(vmx);
8b9cf98c 745 load_transition_efer(vmx);
51c6cf66 746 }
2cc51560 747 break;
6aa8b732
AK		 748 case MSR_FS_BASE:
749 vmcs_writel(GUEST_FS_BASE, data);
750 break;
751 case MSR_GS_BASE:
752 vmcs_writel(GUEST_GS_BASE, data);
753 break;
754#endif
755 case MSR_IA32_SYSENTER_CS:
756 vmcs_write32(GUEST_SYSENTER_CS, data);
757 break;
758 case MSR_IA32_SYSENTER_EIP:
f5b42c33 759 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 760 break;
761 case MSR_IA32_SYSENTER_ESP:
f5b42c33 762 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 763 break;
d27d4aca 764 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 765 guest_write_tsc(data);
766 break;
6aa8b732 767 default:
8b9cf98c 768 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 769 if (msr) {
770 msr->data = data;
a2fa3e9f
GH		 771 if (vmx->host_state.loaded)
772 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 773 break;
6aa8b732 774 }
2cc51560 775 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 776 }
777
2cc51560 778 return ret;
6aa8b732
AK		 779}
780
781/*
782 * Sync the rsp and rip registers into the vcpu structure. This allows
783 * registers to be accessed by indexing vcpu->regs.
784 */
785static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
786{
787 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
788 vcpu->rip = vmcs_readl(GUEST_RIP);
789}
790
791/*
792 * Syncs rsp and rip back into the vmcs. Should be called after possible
793 * modification.
794 */
795static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
796{
797 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
798 vmcs_writel(GUEST_RIP, vcpu->rip);
799}
800
801static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
802{
803 unsigned long dr7 = 0x400;
6aa8b732
AK		 804 int old_singlestep;
805
6aa8b732
AK		 806 old_singlestep = vcpu->guest_debug.singlestep;
807
808 vcpu->guest_debug.enabled = dbg->enabled;
809 if (vcpu->guest_debug.enabled) {
810 int i;
811
812 dr7 |= 0x200; /* exact */
813 for (i = 0; i < 4; ++i) {
814 if (!dbg->breakpoints[i].enabled)
815 continue;
816 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
817 dr7 |= 2 << (i*2); /* global enable */
818 dr7 |= 0 << (i*4+16); /* execution breakpoint */
819 }
820
6aa8b732 821 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 822 } else
6aa8b732 823 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 824
825 if (old_singlestep && !vcpu->guest_debug.singlestep) {
826 unsigned long flags;
827
828 flags = vmcs_readl(GUEST_RFLAGS);
829 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
830 vmcs_writel(GUEST_RFLAGS, flags);
831 }
832
abd3f2d6 833 update_exception_bitmap(vcpu);
6aa8b732
AK		 834 vmcs_writel(GUEST_DR7, dr7);
835
836 return 0;
837}
838
2a8067f1
ED		 839static int vmx_get_irq(struct kvm_vcpu *vcpu)
840{
841 u32 idtv_info_field;
842
843 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
844 if (idtv_info_field & INTR_INFO_VALID_MASK) {
845 if (is_external_interrupt(idtv_info_field))
846 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
847 else
848 printk("pending exception: not handled yet\n");
849 }
850 return -1;
851}
852
6aa8b732
AK		 853static __init int cpu_has_kvm_support(void)
854{
855 unsigned long ecx = cpuid_ecx(1);
856 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
857}
858
859static __init int vmx_disabled_by_bios(void)
860{
861 u64 msr;
862
863 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 864 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
865 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
866 == MSR_IA32_FEATURE_CONTROL_LOCKED;
867 /* locked but not enabled */
6aa8b732
AK		 868}
869
774c47f1 870static void hardware_enable(void *garbage)
6aa8b732
AK		 871{
872 int cpu = raw_smp_processor_id();
873 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
874 u64 old;
875
876 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 877 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
878 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
879 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
880 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 881 /* enable and lock */
62b3ffb8
YS		 882 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
883 MSR_IA32_FEATURE_CONTROL_LOCKED |
884 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 885 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 886 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
887 : "memory", "cc");
888}
889
890static void hardware_disable(void *garbage)
891{
892 asm volatile (ASM_VMX_VMXOFF : : : "cc");
893}
894
1c3d14fe
YS		 895static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
896 u32 msr, u32* result)
897{
898 u32 vmx_msr_low, vmx_msr_high;
899 u32 ctl = ctl_min | ctl_opt;
900
901 rdmsr(msr, vmx_msr_low, vmx_msr_high);
902
903 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
904 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
905
906 /* Ensure minimum (required) set of control bits are supported. */
907 if (ctl_min & ~ctl)
002c7f7c 908 return -EIO;
1c3d14fe
YS		 909
910 *result = ctl;
911 return 0;
912}
913
002c7f7c 914static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 915{
916 u32 vmx_msr_low, vmx_msr_high;
1c3d14fe
YS		 917 u32 min, opt;
918 u32 _pin_based_exec_control = 0;
919 u32 _cpu_based_exec_control = 0;
920 u32 _vmexit_control = 0;
921 u32 _vmentry_control = 0;
922
923 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
924 opt = 0;
925 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
926 &_pin_based_exec_control) < 0)
002c7f7c 927 return -EIO;
1c3d14fe
YS		 928
929 min = CPU_BASED_HLT_EXITING |
930#ifdef CONFIG_X86_64
931 CPU_BASED_CR8_LOAD_EXITING |
932 CPU_BASED_CR8_STORE_EXITING |
933#endif
934 CPU_BASED_USE_IO_BITMAPS |
935 CPU_BASED_MOV_DR_EXITING |
936 CPU_BASED_USE_TSC_OFFSETING;
6e5d865c
YS		 937#ifdef CONFIG_X86_64
938 opt = CPU_BASED_TPR_SHADOW;
939#else
1c3d14fe 940 opt = 0;
6e5d865c 941#endif
1c3d14fe
YS		 942 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
943 &_cpu_based_exec_control) < 0)
002c7f7c 944 return -EIO;
6e5d865c
YS		 945#ifdef CONFIG_X86_64
946 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
947 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
948 ~CPU_BASED_CR8_STORE_EXITING;
949#endif
1c3d14fe
YS		 950
951 min = 0;
952#ifdef CONFIG_X86_64
953 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
954#endif
955 opt = 0;
956 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
957 &_vmexit_control) < 0)
002c7f7c 958 return -EIO;
1c3d14fe
YS		 959
960 min = opt = 0;
961 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
962 &_vmentry_control) < 0)
002c7f7c 963 return -EIO;
6aa8b732 964
c68876fd 965 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 966
967 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
968 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 969 return -EIO;
1c3d14fe
YS		 970
971#ifdef CONFIG_X86_64
972 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
973 if (vmx_msr_high & (1u<<16))
002c7f7c 974 return -EIO;
1c3d14fe
YS		 975#endif
976
977 /* Require Write-Back (WB) memory type for VMCS accesses. */
978 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 979 return -EIO;
1c3d14fe 980
002c7f7c
YS		 981 vmcs_conf->size = vmx_msr_high & 0x1fff;
982 vmcs_conf->order = get_order(vmcs_config.size);
983 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 984
002c7f7c
YS		 985 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
986 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
987 vmcs_conf->vmexit_ctrl = _vmexit_control;
988 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 989
990 return 0;
c68876fd 991}
6aa8b732
AK		 992
993static struct vmcs *alloc_vmcs_cpu(int cpu)
994{
995 int node = cpu_to_node(cpu);
996 struct page *pages;
997 struct vmcs *vmcs;
998
1c3d14fe 999 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1000 if (!pages)
1001 return NULL;
1002 vmcs = page_address(pages);
1c3d14fe
YS		 1003 memset(vmcs, 0, vmcs_config.size);
1004 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1005 return vmcs;
1006}
1007
1008static struct vmcs *alloc_vmcs(void)
1009{
d3b2c338 1010 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1011}
1012
1013static void free_vmcs(struct vmcs *vmcs)
1014{
1c3d14fe 1015 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1016}
1017
39959588 1018static void free_kvm_area(void)
6aa8b732
AK		 1019{
1020 int cpu;
1021
1022 for_each_online_cpu(cpu)
1023 free_vmcs(per_cpu(vmxarea, cpu));
1024}
1025
6aa8b732
AK		 1026static __init int alloc_kvm_area(void)
1027{
1028 int cpu;
1029
1030 for_each_online_cpu(cpu) {
1031 struct vmcs *vmcs;
1032
1033 vmcs = alloc_vmcs_cpu(cpu);
1034 if (!vmcs) {
1035 free_kvm_area();
1036 return -ENOMEM;
1037 }
1038
1039 per_cpu(vmxarea, cpu) = vmcs;
1040 }
1041 return 0;
1042}
1043
1044static __init int hardware_setup(void)
1045{
002c7f7c
YS		 1046 if (setup_vmcs_config(&vmcs_config) < 0)
1047 return -EIO;
6aa8b732
AK		 1048 return alloc_kvm_area();
1049}
1050
1051static __exit void hardware_unsetup(void)
1052{
1053 free_kvm_area();
1054}
1055
6aa8b732
AK		 1056static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1057{
1058 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1059
6af11b9e 1060 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1061 vmcs_write16(sf->selector, save->selector);
1062 vmcs_writel(sf->base, save->base);
1063 vmcs_write32(sf->limit, save->limit);
1064 vmcs_write32(sf->ar_bytes, save->ar);
1065 } else {
1066 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1067 << AR_DPL_SHIFT;
1068 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1069 }
1070}
1071
1072static void enter_pmode(struct kvm_vcpu *vcpu)
1073{
1074 unsigned long flags;
1075
1076 vcpu->rmode.active = 0;
1077
1078 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1079 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1080 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1081
1082 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1083 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
6aa8b732
AK		 1084 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1085 vmcs_writel(GUEST_RFLAGS, flags);
1086
66aee91a
RR		 1087 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1088 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1089
1090 update_exception_bitmap(vcpu);
1091
1092 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1093 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1094 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1095 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1096
1097 vmcs_write16(GUEST_SS_SELECTOR, 0);
1098 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1099
1100 vmcs_write16(GUEST_CS_SELECTOR,
1101 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1102 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1103}
1104
33f5fa16 1105static gva_t rmode_tss_base(struct kvm* kvm)
6aa8b732
AK		 1106{
1107 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
1108 return base_gfn << PAGE_SHIFT;
1109}
1110
1111static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1112{
1113 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1114
1115 save->selector = vmcs_read16(sf->selector);
1116 save->base = vmcs_readl(sf->base);
1117 save->limit = vmcs_read32(sf->limit);
1118 save->ar = vmcs_read32(sf->ar_bytes);
1119 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1120 vmcs_write32(sf->limit, 0xffff);
1121 vmcs_write32(sf->ar_bytes, 0xf3);
1122}
1123
1124static void enter_rmode(struct kvm_vcpu *vcpu)
1125{
1126 unsigned long flags;
1127
1128 vcpu->rmode.active = 1;
1129
1130 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1131 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1132
1133 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1134 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1135
1136 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1137 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1138
1139 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1140 vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1141
053de044 1142 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1143
1144 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1145 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1146 update_exception_bitmap(vcpu);
1147
1148 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1149 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1150 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1151
1152 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1153 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1154 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1155 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1156 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1157
1158 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1159 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1160 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1161 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
75880a01 1162
8668a3c4 1163 kvm_mmu_reset_context(vcpu);
75880a01 1164 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 1165}
1166
05b3e0c2 1167#ifdef CONFIG_X86_64
6aa8b732
AK		 1168
1169static void enter_lmode(struct kvm_vcpu *vcpu)
1170{
1171 u32 guest_tr_ar;
1172
1173 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1174 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1175 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1176 __FUNCTION__);
1177 vmcs_write32(GUEST_TR_AR_BYTES,
1178 (guest_tr_ar & ~AR_TYPE_MASK)
1179 | AR_TYPE_BUSY_64_TSS);
1180 }
1181
1182 vcpu->shadow_efer |= EFER_LMA;
1183
8b9cf98c 1184 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1185 vmcs_write32(VM_ENTRY_CONTROLS,
1186 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1187 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1188}
1189
1190static void exit_lmode(struct kvm_vcpu *vcpu)
1191{
1192 vcpu->shadow_efer &= ~EFER_LMA;
1193
1194 vmcs_write32(VM_ENTRY_CONTROLS,
1195 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1196 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1197}
1198
1199#endif
1200
25c4c276 1201static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1202{
399badf3
AK		 1203 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1204 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1205}
1206
6aa8b732
AK		 1207static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1208{
5fd86fcf
AK		 1209 vmx_fpu_deactivate(vcpu);
1210
707d92fa 1211 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1212 enter_pmode(vcpu);
1213
707d92fa 1214 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1215 enter_rmode(vcpu);
1216
05b3e0c2 1217#ifdef CONFIG_X86_64
6aa8b732 1218 if (vcpu->shadow_efer & EFER_LME) {
707d92fa 1219 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1220 enter_lmode(vcpu);
707d92fa 1221 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1222 exit_lmode(vcpu);
1223 }
1224#endif
1225
1226 vmcs_writel(CR0_READ_SHADOW, cr0);
1227 vmcs_writel(GUEST_CR0,
1228 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1229 vcpu->cr0 = cr0;
5fd86fcf 1230
707d92fa 1231 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1232 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1233}
1234
6aa8b732
AK		 1235static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1236{
1237 vmcs_writel(GUEST_CR3, cr3);
707d92fa 1238 if (vcpu->cr0 & X86_CR0_PE)
5fd86fcf 1239 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1240}
1241
1242static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1243{
1244 vmcs_writel(CR4_READ_SHADOW, cr4);
1245 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1246 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1247 vcpu->cr4 = cr4;
1248}
1249
05b3e0c2 1250#ifdef CONFIG_X86_64
6aa8b732
AK		 1251
1252static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1253{
8b9cf98c
RR		 1254 struct vcpu_vmx *vmx = to_vmx(vcpu);
1255 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732
AK		 1256
1257 vcpu->shadow_efer = efer;
1258 if (efer & EFER_LMA) {
1259 vmcs_write32(VM_ENTRY_CONTROLS,
1260 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1261 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1262 msr->data = efer;
1263
1264 } else {
1265 vmcs_write32(VM_ENTRY_CONTROLS,
1266 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1267 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1268
1269 msr->data = efer & ~EFER_LME;
1270 }
8b9cf98c 1271 setup_msrs(vmx);
6aa8b732
AK		 1272}
1273
1274#endif
1275
1276static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1277{
1278 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1279
1280 return vmcs_readl(sf->base);
1281}
1282
1283static void vmx_get_segment(struct kvm_vcpu *vcpu,
1284 struct kvm_segment *var, int seg)
1285{
1286 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1287 u32 ar;
1288
1289 var->base = vmcs_readl(sf->base);
1290 var->limit = vmcs_read32(sf->limit);
1291 var->selector = vmcs_read16(sf->selector);
1292 ar = vmcs_read32(sf->ar_bytes);
1293 if (ar & AR_UNUSABLE_MASK)
1294 ar = 0;
1295 var->type = ar & 15;
1296 var->s = (ar >> 4) & 1;
1297 var->dpl = (ar >> 5) & 3;
1298 var->present = (ar >> 7) & 1;
1299 var->avl = (ar >> 12) & 1;
1300 var->l = (ar >> 13) & 1;
1301 var->db = (ar >> 14) & 1;
1302 var->g = (ar >> 15) & 1;
1303 var->unusable = (ar >> 16) & 1;
1304}
1305
653e3108 1306static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1307{
6aa8b732
AK		 1308 u32 ar;
1309
653e3108 1310 if (var->unusable)
6aa8b732
AK		 1311 ar = 1 << 16;
1312 else {
1313 ar = var->type & 15;
1314 ar |= (var->s & 1) << 4;
1315 ar |= (var->dpl & 3) << 5;
1316 ar |= (var->present & 1) << 7;
1317 ar |= (var->avl & 1) << 12;
1318 ar |= (var->l & 1) << 13;
1319 ar |= (var->db & 1) << 14;
1320 ar |= (var->g & 1) << 15;
1321 }
f7fbf1fd
UL		 1322 if (ar == 0) /* a 0 value means unusable */
1323 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1324
1325 return ar;
1326}
1327
1328static void vmx_set_segment(struct kvm_vcpu *vcpu,
1329 struct kvm_segment *var, int seg)
1330{
1331 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1332 u32 ar;
1333
1334 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1335 vcpu->rmode.tr.selector = var->selector;
1336 vcpu->rmode.tr.base = var->base;
1337 vcpu->rmode.tr.limit = var->limit;
1338 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1339 return;
1340 }
1341 vmcs_writel(sf->base, var->base);
1342 vmcs_write32(sf->limit, var->limit);
1343 vmcs_write16(sf->selector, var->selector);
1344 if (vcpu->rmode.active && var->s) {
1345 /*
1346 * Hack real-mode segments into vm86 compatibility.
1347 */
1348 if (var->base == 0xffff0000 && var->selector == 0xf000)
1349 vmcs_writel(sf->base, 0xf0000);
1350 ar = 0xf3;
1351 } else
1352 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1353 vmcs_write32(sf->ar_bytes, ar);
1354}
1355
6aa8b732
AK		 1356static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1357{
1358 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1359
1360 *db = (ar >> 14) & 1;
1361 *l = (ar >> 13) & 1;
1362}
1363
1364static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1365{
1366 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1367 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1368}
1369
1370static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1371{
1372 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1373 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1374}
1375
1376static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1377{
1378 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1379 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1380}
1381
1382static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1383{
1384 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1385 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1386}
1387
1388static int init_rmode_tss(struct kvm* kvm)
1389{
6aa8b732 1390 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 1391 u16 data = 0;
1392 int r;
6aa8b732 1393
195aefde
IE		 1394 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1395 if (r < 0)
1396 return 0;
1397 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1398 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1399 if (r < 0)
1400 return 0;
1401 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1402 if (r < 0)
1403 return 0;
1404 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1405 if (r < 0)
1406 return 0;
1407 data = ~0;
1408 r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1409 sizeof(u8));
1410 if (r < 0)
6aa8b732 1411 return 0;
6aa8b732
AK		 1412 return 1;
1413}
1414
6aa8b732
AK		 1415static void seg_setup(int seg)
1416{
1417 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1418
1419 vmcs_write16(sf->selector, 0);
1420 vmcs_writel(sf->base, 0);
1421 vmcs_write32(sf->limit, 0xffff);
1422 vmcs_write32(sf->ar_bytes, 0x93);
1423}
1424
1425/*
1426 * Sets up the vmcs for emulated real mode.
1427 */
8b9cf98c 1428static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1429{
1430 u32 host_sysenter_cs;
1431 u32 junk;
1432 unsigned long a;
1433 struct descriptor_table dt;
1434 int i;
1435 int ret = 0;
cd2276a7 1436 unsigned long kvm_vmx_return;
7017fc3d 1437 u64 msr;
6e5d865c 1438 u32 exec_control;
6aa8b732 1439
8b9cf98c 1440 if (!init_rmode_tss(vmx->vcpu.kvm)) {
6aa8b732
AK		 1441 ret = -ENOMEM;
1442 goto out;
1443 }
1444
c5ec1534
HQ		 1445 vmx->vcpu.rmode.active = 0;
1446
8b9cf98c 1447 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
7017fc3d
ED		 1448 set_cr8(&vmx->vcpu, 0);
1449 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
8b9cf98c 1450 if (vmx->vcpu.vcpu_id == 0)
7017fc3d
ED		 1451 msr |= MSR_IA32_APICBASE_BSP;
1452 kvm_set_apic_base(&vmx->vcpu, msr);
6aa8b732 1453
8b9cf98c 1454 fx_init(&vmx->vcpu);
6aa8b732
AK		 1455
1456 /*
1457 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1458 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1459 */
c5ec1534
HQ		 1460 if (vmx->vcpu.vcpu_id == 0) {
1461 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1462 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1463 } else {
1464 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1465 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1466 }
6aa8b732
AK		 1467 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1468 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1469
1470 seg_setup(VCPU_SREG_DS);
1471 seg_setup(VCPU_SREG_ES);
1472 seg_setup(VCPU_SREG_FS);
1473 seg_setup(VCPU_SREG_GS);
1474 seg_setup(VCPU_SREG_SS);
1475
1476 vmcs_write16(GUEST_TR_SELECTOR, 0);
1477 vmcs_writel(GUEST_TR_BASE, 0);
1478 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1479 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1480
1481 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1482 vmcs_writel(GUEST_LDTR_BASE, 0);
1483 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1484 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1485
1486 vmcs_write32(GUEST_SYSENTER_CS, 0);
1487 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1488 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1489
1490 vmcs_writel(GUEST_RFLAGS, 0x02);
c5ec1534
HQ		 1491 if (vmx->vcpu.vcpu_id == 0)
1492 vmcs_writel(GUEST_RIP, 0xfff0);
1493 else
1494 vmcs_writel(GUEST_RIP, 0);
6aa8b732
AK		 1495 vmcs_writel(GUEST_RSP, 0);
1496
6aa8b732
AK		 1497 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1498 vmcs_writel(GUEST_DR7, 0x400);
1499
1500 vmcs_writel(GUEST_GDTR_BASE, 0);
1501 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1502
1503 vmcs_writel(GUEST_IDTR_BASE, 0);
1504 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1505
1506 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1507 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1508 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1509
1510 /* I/O */
fdef3ad1
HQ		 1511 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1512 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732
AK		 1513
1514 guest_write_tsc(0);
1515
1516 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1517
1518 /* Special registers */
1519 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1520
1521 /* Control */
1c3d14fe
YS		 1522 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1523 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1524
1525 exec_control = vmcs_config.cpu_based_exec_ctrl;
1526 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1527 exec_control &= ~CPU_BASED_TPR_SHADOW;
1528#ifdef CONFIG_X86_64
1529 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1530 CPU_BASED_CR8_LOAD_EXITING;
1531#endif
1532 }
1533 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1534
c7addb90
AK		 1535 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1536 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 1537 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1538
1539 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1540 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1541 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1542
1543 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1544 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1545 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1546 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1547 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1548 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1549#ifdef CONFIG_X86_64
6aa8b732
AK		 1550 rdmsrl(MSR_FS_BASE, a);
1551 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1552 rdmsrl(MSR_GS_BASE, a);
1553 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1554#else
1555 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1556 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1557#endif
1558
1559 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1560
1561 get_idt(&dt);
1562 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1563
cd2276a7
AK		 1564 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1565 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1566 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1567 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1568 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1569
1570 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1571 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1572 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1573 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1574 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1575 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1576
6aa8b732
AK		 1577 for (i = 0; i < NR_VMX_MSR; ++i) {
1578 u32 index = vmx_msr_index[i];
1579 u32 data_low, data_high;
1580 u64 data;
a2fa3e9f 1581 int j = vmx->nmsrs;
6aa8b732
AK		 1582
1583 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1584 continue;
432bd6cb
AK		 1585 if (wrmsr_safe(index, data_low, data_high) < 0)
1586 continue;
6aa8b732 1587 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1588 vmx->host_msrs[j].index = index;
1589 vmx->host_msrs[j].reserved = 0;
1590 vmx->host_msrs[j].data = data;
1591 vmx->guest_msrs[j] = vmx->host_msrs[j];
1592 ++vmx->nmsrs;
6aa8b732 1593 }
6aa8b732 1594
8b9cf98c 1595 setup_msrs(vmx);
e38aea3e 1596
1c3d14fe 1597 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1598
1599 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1600 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1601
6aa8b732
AK		 1602 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1603
3b99ab24 1604#ifdef CONFIG_X86_64
6e5d865c
YS		 1605 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1606 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1607 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1608 page_to_phys(vmx->vcpu.apic->regs_page));
1609 vmcs_write32(TPR_THRESHOLD, 0);
3b99ab24 1610#endif
6aa8b732 1611
25c4c276 1612 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
6aa8b732
AK		 1613 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1614
8b9cf98c
RR		 1615 vmx->vcpu.cr0 = 0x60000010;
1616 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); // enter rmode
1617 vmx_set_cr4(&vmx->vcpu, 0);
05b3e0c2 1618#ifdef CONFIG_X86_64
8b9cf98c 1619 vmx_set_efer(&vmx->vcpu, 0);
6aa8b732 1620#endif
8b9cf98c
RR		 1621 vmx_fpu_activate(&vmx->vcpu);
1622 update_exception_bitmap(&vmx->vcpu);
6aa8b732
AK		 1623
1624 return 0;
1625
6aa8b732
AK		 1626out:
1627 return ret;
1628}
1629
04d2cc77
AK		 1630static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1631{
1632 struct vcpu_vmx *vmx = to_vmx(vcpu);
1633
1634 vmx_vcpu_setup(vmx);
1635}
1636
6aa8b732
AK		 1637static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1638{
1639 u16 ent[2];
1640 u16 cs;
1641 u16 ip;
1642 unsigned long flags;
1643 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1644 u16 sp = vmcs_readl(GUEST_RSP);
1645 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1646
3964994b 1647 if (sp > ss_limit || sp < 6 ) {
6aa8b732
AK		 1648 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1649 __FUNCTION__,
1650 vmcs_readl(GUEST_RSP),
1651 vmcs_readl(GUEST_SS_BASE),
1652 vmcs_read32(GUEST_SS_LIMIT));
1653 return;
1654 }
1655
e7d5d76c
LV		 1656 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1657 X86EMUL_CONTINUE) {
6aa8b732
AK		 1658 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1659 return;
1660 }
1661
1662 flags = vmcs_readl(GUEST_RFLAGS);
1663 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1664 ip = vmcs_readl(GUEST_RIP);
1665
1666
e7d5d76c
LV		 1667 if (emulator_write_emulated(ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1668 emulator_write_emulated(ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1669 emulator_write_emulated(ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
6aa8b732
AK		 1670 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1671 return;
1672 }
1673
1674 vmcs_writel(GUEST_RFLAGS, flags &
1675 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1676 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1677 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1678 vmcs_writel(GUEST_RIP, ent[0]);
1679 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1680}
1681
85f455f7
ED		 1682static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1683{
1684 if (vcpu->rmode.active) {
1685 inject_rmode_irq(vcpu, irq);
1686 return;
1687 }
1688 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1689 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1690}
1691
6aa8b732
AK		 1692static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1693{
1694 int word_index = __ffs(vcpu->irq_summary);
1695 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1696 int irq = word_index * BITS_PER_LONG + bit_index;
1697
1698 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1699 if (!vcpu->irq_pending[word_index])
1700 clear_bit(word_index, &vcpu->irq_summary);
85f455f7 1701 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 1702}
1703
c1150d8c
DL		 1704
1705static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1706 struct kvm_run *kvm_run)
6aa8b732 1707{
c1150d8c
DL		 1708 u32 cpu_based_vm_exec_control;
1709
1710 vcpu->interrupt_window_open =
1711 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1712 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1713
1714 if (vcpu->interrupt_window_open &&
1715 vcpu->irq_summary &&
1716 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1717 /*
c1150d8c 1718 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1719 */
1720 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1721
1722 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1723 if (!vcpu->interrupt_window_open &&
1724 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1725 /*
1726 * Interrupts blocked. Wait for unblock.
1727 */
c1150d8c
DL		 1728 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1729 else
1730 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1731 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1732}
1733
1734static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1735{
1736 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1737
1738 set_debugreg(dbg->bp[0], 0);
1739 set_debugreg(dbg->bp[1], 1);
1740 set_debugreg(dbg->bp[2], 2);
1741 set_debugreg(dbg->bp[3], 3);
1742
1743 if (dbg->singlestep) {
1744 unsigned long flags;
1745
1746 flags = vmcs_readl(GUEST_RFLAGS);
1747 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1748 vmcs_writel(GUEST_RFLAGS, flags);
1749 }
1750}
1751
1752static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1753 int vec, u32 err_code)
1754{
1755 if (!vcpu->rmode.active)
1756 return 0;
1757
b3f37707
NK		 1758 /*
1759 * Instruction with address size override prefix opcode 0x67
1760 * Cause the #SS fault with 0 error code in VM86 mode.
1761 */
1762 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 1763 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732
AK		 1764 return 1;
1765 return 0;
1766}
1767
1768static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1769{
1770 u32 intr_info, error_code;
1771 unsigned long cr2, rip;
1772 u32 vect_info;
1773 enum emulation_result er;
e2dec939 1774 int r;
6aa8b732
AK		 1775
1776 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1777 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1778
1779 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1780 !is_page_fault(intr_info)) {
1781 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1782 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1783 }
1784
85f455f7 1785 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732
AK		 1786 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1787 set_bit(irq, vcpu->irq_pending);
1788 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1789 }
1790
1b6269db
AK		 1791 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1792 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 1793
1794 if (is_no_device(intr_info)) {
5fd86fcf 1795 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1796 return 1;
1797 }
1798
7aa81cc0 1799 if (is_invalid_opcode(intr_info)) {
3427318f 1800 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
7aa81cc0
AL		 1801 if (er != EMULATE_DONE)
1802 vmx_inject_ud(vcpu);
1803
1804 return 1;
1805 }
1806
6aa8b732
AK		 1807 error_code = 0;
1808 rip = vmcs_readl(GUEST_RIP);
1809 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1810 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1811 if (is_page_fault(intr_info)) {
1812 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1813
11ec2804 1814 mutex_lock(&vcpu->kvm->lock);
e2dec939
AK		 1815 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1816 if (r < 0) {
11ec2804 1817 mutex_unlock(&vcpu->kvm->lock);
e2dec939
AK		 1818 return r;
1819 }
1820 if (!r) {
11ec2804 1821 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1822 return 1;
1823 }
1824
3427318f 1825 er = emulate_instruction(vcpu, kvm_run, cr2, error_code, 0);
11ec2804 1826 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1827
1828 switch (er) {
1829 case EMULATE_DONE:
1830 return 1;
1831 case EMULATE_DO_MMIO:
1165f5fe 1832 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 1833 return 0;
1834 case EMULATE_FAIL:
054b1369 1835 kvm_report_emulation_failure(vcpu, "pagetable");
6aa8b732
AK		 1836 break;
1837 default:
1838 BUG();
1839 }
1840 }
1841
1842 if (vcpu->rmode.active &&
1843 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0
AK		 1844 error_code)) {
1845 if (vcpu->halt_request) {
1846 vcpu->halt_request = 0;
1847 return kvm_emulate_halt(vcpu);
1848 }
6aa8b732 1849 return 1;
72d6e5a0 1850 }
6aa8b732
AK		 1851
1852 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1853 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1854 return 0;
1855 }
1856 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1857 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1858 kvm_run->ex.error_code = error_code;
1859 return 0;
1860}
1861
1862static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1863 struct kvm_run *kvm_run)
1864{
1165f5fe 1865 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1866 return 1;
1867}
1868
988ad74f
AK		 1869static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1870{
1871 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1872 return 0;
1873}
6aa8b732 1874
6aa8b732
AK		 1875static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1876{
bfdaab09 1877 unsigned long exit_qualification;
039576c0
AK		 1878 int size, down, in, string, rep;
1879 unsigned port;
6aa8b732 1880
1165f5fe 1881 ++vcpu->stat.io_exits;
bfdaab09 1882 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 1883 string = (exit_qualification & 16) != 0;
e70669ab
LV		 1884
1885 if (string) {
3427318f
LV		 1886 if (emulate_instruction(vcpu,
1887 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1888 return 0;
1889 return 1;
1890 }
1891
1892 size = (exit_qualification & 7) + 1;
1893 in = (exit_qualification & 8) != 0;
039576c0 1894 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 1895 rep = (exit_qualification & 32) != 0;
1896 port = exit_qualification >> 16;
e70669ab 1897
3090dd73 1898 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1899}
1900
102d8325
IM		 1901static void
1902vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1903{
1904 /*
1905 * Patch in the VMCALL instruction:
1906 */
1907 hypercall[0] = 0x0f;
1908 hypercall[1] = 0x01;
1909 hypercall[2] = 0xc1;
102d8325
IM		 1910}
1911
6aa8b732
AK		 1912static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1913{
bfdaab09 1914 unsigned long exit_qualification;
6aa8b732
AK		 1915 int cr;
1916 int reg;
1917
bfdaab09 1918 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1919 cr = exit_qualification & 15;
1920 reg = (exit_qualification >> 8) & 15;
1921 switch ((exit_qualification >> 4) & 3) {
1922 case 0: /* mov to cr */
1923 switch (cr) {
1924 case 0:
1925 vcpu_load_rsp_rip(vcpu);
1926 set_cr0(vcpu, vcpu->regs[reg]);
1927 skip_emulated_instruction(vcpu);
1928 return 1;
1929 case 3:
1930 vcpu_load_rsp_rip(vcpu);
1931 set_cr3(vcpu, vcpu->regs[reg]);
1932 skip_emulated_instruction(vcpu);
1933 return 1;
1934 case 4:
1935 vcpu_load_rsp_rip(vcpu);
1936 set_cr4(vcpu, vcpu->regs[reg]);
1937 skip_emulated_instruction(vcpu);
1938 return 1;
1939 case 8:
1940 vcpu_load_rsp_rip(vcpu);
1941 set_cr8(vcpu, vcpu->regs[reg]);
1942 skip_emulated_instruction(vcpu);
253abdee
YS		 1943 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1944 return 0;
6aa8b732
AK		 1945 };
1946 break;
25c4c276
AL		 1947 case 2: /* clts */
1948 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1949 vmx_fpu_deactivate(vcpu);
707d92fa 1950 vcpu->cr0 &= ~X86_CR0_TS;
2ab455cc 1951 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
5fd86fcf 1952 vmx_fpu_activate(vcpu);
25c4c276
AL		 1953 skip_emulated_instruction(vcpu);
1954 return 1;
6aa8b732
AK		 1955 case 1: /*mov from cr*/
1956 switch (cr) {
1957 case 3:
1958 vcpu_load_rsp_rip(vcpu);
1959 vcpu->regs[reg] = vcpu->cr3;
1960 vcpu_put_rsp_rip(vcpu);
1961 skip_emulated_instruction(vcpu);
1962 return 1;
1963 case 8:
6aa8b732 1964 vcpu_load_rsp_rip(vcpu);
7017fc3d 1965 vcpu->regs[reg] = get_cr8(vcpu);
6aa8b732
AK		 1966 vcpu_put_rsp_rip(vcpu);
1967 skip_emulated_instruction(vcpu);
1968 return 1;
1969 }
1970 break;
1971 case 3: /* lmsw */
1972 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1973
1974 skip_emulated_instruction(vcpu);
1975 return 1;
1976 default:
1977 break;
1978 }
1979 kvm_run->exit_reason = 0;
f0242478 1980 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 1981 (int)(exit_qualification >> 4) & 3, cr);
1982 return 0;
1983}
1984
1985static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1986{
bfdaab09 1987 unsigned long exit_qualification;
6aa8b732
AK		 1988 unsigned long val;
1989 int dr, reg;
1990
1991 /*
1992 * FIXME: this code assumes the host is debugging the guest.
1993 * need to deal with guest debugging itself too.
1994 */
bfdaab09 1995 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1996 dr = exit_qualification & 7;
1997 reg = (exit_qualification >> 8) & 15;
1998 vcpu_load_rsp_rip(vcpu);
1999 if (exit_qualification & 16) {
2000 /* mov from dr */
2001 switch (dr) {
2002 case 6:
2003 val = 0xffff0ff0;
2004 break;
2005 case 7:
2006 val = 0x400;
2007 break;
2008 default:
2009 val = 0;
2010 }
2011 vcpu->regs[reg] = val;
2012 } else {
2013 /* mov to dr */
2014 }
2015 vcpu_put_rsp_rip(vcpu);
2016 skip_emulated_instruction(vcpu);
2017 return 1;
2018}
2019
2020static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2021{
06465c5a
AK		 2022 kvm_emulate_cpuid(vcpu);
2023 return 1;
6aa8b732
AK		 2024}
2025
2026static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2027{
2028 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2029 u64 data;
2030
2031 if (vmx_get_msr(vcpu, ecx, &data)) {
2032 vmx_inject_gp(vcpu, 0);
2033 return 1;
2034 }
2035
2036 /* FIXME: handling of bits 32:63 of rax, rdx */
2037 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2038 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2039 skip_emulated_instruction(vcpu);
2040 return 1;
2041}
2042
2043static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2044{
2045 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2046 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2047 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2048
2049 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2050 vmx_inject_gp(vcpu, 0);
2051 return 1;
2052 }
2053
2054 skip_emulated_instruction(vcpu);
2055 return 1;
2056}
2057
6e5d865c
YS		 2058static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2059 struct kvm_run *kvm_run)
2060{
2061 return 1;
2062}
2063
6aa8b732
AK		 2064static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2065 struct kvm_run *kvm_run)
2066{
85f455f7
ED		 2067 u32 cpu_based_vm_exec_control;
2068
2069 /* clear pending irq */
2070 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2071 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2072 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
c1150d8c
DL		 2073 /*
2074 * If the user space waits to inject interrupts, exit as soon as
2075 * possible
2076 */
2077 if (kvm_run->request_interrupt_window &&
022a9308 2078 !vcpu->irq_summary) {
c1150d8c 2079 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2080 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2081 return 0;
2082 }
6aa8b732
AK		 2083 return 1;
2084}
2085
2086static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2087{
2088 skip_emulated_instruction(vcpu);
d3bef15f 2089 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2090}
2091
c21415e8
IM		 2092static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2093{
510043da 2094 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2095 kvm_emulate_hypercall(vcpu);
2096 return 1;
c21415e8
IM		 2097}
2098
6aa8b732
AK		 2099/*
2100 * The exit handlers return 1 if the exit was handled fully and guest execution
2101 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2102 * to be done to userspace and return 0.
2103 */
2104static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2105 struct kvm_run *kvm_run) = {
2106 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2107 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2108 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2109 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2110 [EXIT_REASON_CR_ACCESS] = handle_cr,
2111 [EXIT_REASON_DR_ACCESS] = handle_dr,
2112 [EXIT_REASON_CPUID] = handle_cpuid,
2113 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2114 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2115 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2116 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2117 [EXIT_REASON_VMCALL] = handle_vmcall,
6e5d865c 2118 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold
6aa8b732
AK		 2119};
2120
2121static const int kvm_vmx_max_exit_handlers =
50a3485c 2122 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2123
2124/*
2125 * The guest has exited. See if we can fix it or if we need userspace
2126 * assistance.
2127 */
2128static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2129{
2130 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2131 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78
AK		 2132 struct vcpu_vmx *vmx = to_vmx(vcpu);
2133
2134 if (unlikely(vmx->fail)) {
2135 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2136 kvm_run->fail_entry.hardware_entry_failure_reason
2137 = vmcs_read32(VM_INSTRUCTION_ERROR);
2138 return 0;
2139 }
6aa8b732
AK		 2140
2141 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
2142 exit_reason != EXIT_REASON_EXCEPTION_NMI )
2143 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2144 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 2145 if (exit_reason < kvm_vmx_max_exit_handlers
2146 && kvm_vmx_exit_handlers[exit_reason])
2147 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2148 else {
2149 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2150 kvm_run->hw.hardware_exit_reason = exit_reason;
2151 }
2152 return 0;
2153}
2154
d9e368d6
AK		 2155static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2156{
d9e368d6
AK		 2157}
2158
6e5d865c
YS		 2159static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2160{
2161 int max_irr, tpr;
2162
2163 if (!vm_need_tpr_shadow(vcpu->kvm))
2164 return;
2165
2166 if (!kvm_lapic_enabled(vcpu) ||
2167 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2168 vmcs_write32(TPR_THRESHOLD, 0);
2169 return;
2170 }
2171
2172 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2173 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2174}
2175
85f455f7
ED		 2176static void enable_irq_window(struct kvm_vcpu *vcpu)
2177{
2178 u32 cpu_based_vm_exec_control;
2179
2180 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2181 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2182 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2183}
2184
2185static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2186{
2187 u32 idtv_info_field, intr_info_field;
2188 int has_ext_irq, interrupt_window_open;
1b9778da 2189 int vector;
85f455f7 2190
1b9778da 2191 kvm_inject_pending_timer_irqs(vcpu);
6e5d865c
YS		 2192 update_tpr_threshold(vcpu);
2193
85f455f7
ED		 2194 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2195 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2196 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2197 if (intr_info_field & INTR_INFO_VALID_MASK) {
2198 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2199 /* TODO: fault when IDT_Vectoring */
2200 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2201 }
2202 if (has_ext_irq)
2203 enable_irq_window(vcpu);
2204 return;
2205 }
2206 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2207 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2208 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2209 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2210
2211 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2212 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2213 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2214 if (unlikely(has_ext_irq))
2215 enable_irq_window(vcpu);
2216 return;
2217 }
2218 if (!has_ext_irq)
2219 return;
2220 interrupt_window_open =
2221 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2222 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2223 if (interrupt_window_open) {
2224 vector = kvm_cpu_get_interrupt(vcpu);
2225 vmx_inject_irq(vcpu, vector);
2226 kvm_timer_intr_post(vcpu, vector);
2227 } else
85f455f7
ED		 2228 enable_irq_window(vcpu);
2229}
2230
04d2cc77 2231static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2232{
a2fa3e9f 2233 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2234 u32 intr_info;
e6adf283
AK		 2235
2236 /*
2237 * Loading guest fpu may have cleared host cr0.ts
2238 */
2239 vmcs_writel(HOST_CR0, read_cr0());
2240
6aa8b732
AK		 2241 asm (
2242 /* Store host registers */
05b3e0c2 2243#ifdef CONFIG_X86_64
6aa8b732
AK		 2244 "push %%rax; push %%rbx; push %%rdx;"
2245 "push %%rsi; push %%rdi; push %%rbp;"
2246 "push %%r8; push %%r9; push %%r10; push %%r11;"
2247 "push %%r12; push %%r13; push %%r14; push %%r15;"
2248 "push %%rcx \n\t"
2249 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2250#else
2251 "pusha; push %%ecx \n\t"
2252 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2253#endif
2254 /* Check if vmlaunch of vmresume is needed */
2255 "cmp $0, %1 \n\t"
2256 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2257#ifdef CONFIG_X86_64
6aa8b732
AK		 2258 "mov %c[cr2](%3), %%rax \n\t"
2259 "mov %%rax, %%cr2 \n\t"
2260 "mov %c[rax](%3), %%rax \n\t"
2261 "mov %c[rbx](%3), %%rbx \n\t"
2262 "mov %c[rdx](%3), %%rdx \n\t"
2263 "mov %c[rsi](%3), %%rsi \n\t"
2264 "mov %c[rdi](%3), %%rdi \n\t"
2265 "mov %c[rbp](%3), %%rbp \n\t"
2266 "mov %c[r8](%3), %%r8 \n\t"
2267 "mov %c[r9](%3), %%r9 \n\t"
2268 "mov %c[r10](%3), %%r10 \n\t"
2269 "mov %c[r11](%3), %%r11 \n\t"
2270 "mov %c[r12](%3), %%r12 \n\t"
2271 "mov %c[r13](%3), %%r13 \n\t"
2272 "mov %c[r14](%3), %%r14 \n\t"
2273 "mov %c[r15](%3), %%r15 \n\t"
2274 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2275#else
2276 "mov %c[cr2](%3), %%eax \n\t"
2277 "mov %%eax, %%cr2 \n\t"
2278 "mov %c[rax](%3), %%eax \n\t"
2279 "mov %c[rbx](%3), %%ebx \n\t"
2280 "mov %c[rdx](%3), %%edx \n\t"
2281 "mov %c[rsi](%3), %%esi \n\t"
2282 "mov %c[rdi](%3), %%edi \n\t"
2283 "mov %c[rbp](%3), %%ebp \n\t"
2284 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2285#endif
2286 /* Enter guest mode */
cd2276a7 2287 "jne .Llaunched \n\t"
6aa8b732 2288 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2289 "jmp .Lkvm_vmx_return \n\t"
2290 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2291 ".Lkvm_vmx_return: "
6aa8b732 2292 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2293#ifdef CONFIG_X86_64
96958231 2294 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 2295 "mov %%rax, %c[rax](%3) \n\t"
2296 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 2297 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 2298 "mov %%rdx, %c[rdx](%3) \n\t"
2299 "mov %%rsi, %c[rsi](%3) \n\t"
2300 "mov %%rdi, %c[rdi](%3) \n\t"
2301 "mov %%rbp, %c[rbp](%3) \n\t"
2302 "mov %%r8, %c[r8](%3) \n\t"
2303 "mov %%r9, %c[r9](%3) \n\t"
2304 "mov %%r10, %c[r10](%3) \n\t"
2305 "mov %%r11, %c[r11](%3) \n\t"
2306 "mov %%r12, %c[r12](%3) \n\t"
2307 "mov %%r13, %c[r13](%3) \n\t"
2308 "mov %%r14, %c[r14](%3) \n\t"
2309 "mov %%r15, %c[r15](%3) \n\t"
2310 "mov %%cr2, %%rax \n\t"
2311 "mov %%rax, %c[cr2](%3) \n\t"
96958231 2312 "mov (%%rsp), %3 \n\t"
6aa8b732
AK		 2313
2314 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2315 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2316 "pop %%rbp; pop %%rdi; pop %%rsi;"
2317 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2318#else
96958231 2319 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 2320 "mov %%eax, %c[rax](%3) \n\t"
2321 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 2322 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 2323 "mov %%edx, %c[rdx](%3) \n\t"
2324 "mov %%esi, %c[rsi](%3) \n\t"
2325 "mov %%edi, %c[rdi](%3) \n\t"
2326 "mov %%ebp, %c[rbp](%3) \n\t"
2327 "mov %%cr2, %%eax \n\t"
2328 "mov %%eax, %c[cr2](%3) \n\t"
96958231 2329 "mov (%%esp), %3 \n\t"
6aa8b732
AK		 2330
2331 "pop %%ecx; popa \n\t"
2332#endif
2333 "setbe %0 \n\t"
29bd8a78 2334 : "=q" (vmx->fail)
a2fa3e9f 2335 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
6aa8b732
AK		 2336 "c"(vcpu),
2337 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2338 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2339 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2340 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2341 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2342 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2343 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 2344#ifdef CONFIG_X86_64
6aa8b732
AK		 2345 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2346 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2347 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2348 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2349 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2350 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2351 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2352 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2353#endif
2354 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2355 : "cc", "memory" );
2356
c1150d8c 2357 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2358
6aa8b732 2359 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2360 vmx->launched = 1;
1b6269db
AK		 2361
2362 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2363
2364 /* We need to handle NMIs before interrupts are enabled */
2365 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2366 asm("int $2");
6aa8b732
AK		 2367}
2368
6aa8b732
AK		 2369static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2370 unsigned long addr,
2371 u32 err_code)
2372{
2373 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2374
1165f5fe 2375 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2376
2377 if (is_page_fault(vect_info)) {
2378 printk(KERN_DEBUG "inject_page_fault: "
2379 "double fault 0x%lx @ 0x%lx\n",
2380 addr, vmcs_readl(GUEST_RIP));
2381 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2382 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2383 DF_VECTOR |
2384 INTR_TYPE_EXCEPTION |
2385 INTR_INFO_DELIEVER_CODE_MASK |
2386 INTR_INFO_VALID_MASK);
2387 return;
2388 }
2389 vcpu->cr2 = addr;
2390 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2391 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2392 PF_VECTOR |
2393 INTR_TYPE_EXCEPTION |
2394 INTR_INFO_DELIEVER_CODE_MASK |
2395 INTR_INFO_VALID_MASK);
2396
2397}
2398
2399static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2400{
a2fa3e9f
GH		 2401 struct vcpu_vmx *vmx = to_vmx(vcpu);
2402
2403 if (vmx->vmcs) {
8b9cf98c 2404 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2405 free_vmcs(vmx->vmcs);
2406 vmx->vmcs = NULL;
6aa8b732
AK		 2407 }
2408}
2409
2410static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2411{
fb3f0f51
RR		 2412 struct vcpu_vmx *vmx = to_vmx(vcpu);
2413
6aa8b732 2414 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2415 kfree(vmx->host_msrs);
2416 kfree(vmx->guest_msrs);
2417 kvm_vcpu_uninit(vcpu);
a4770347 2418 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2419}
2420
fb3f0f51 2421static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2422{
fb3f0f51 2423 int err;
c16f862d 2424 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2425 int cpu;
6aa8b732 2426
a2fa3e9f 2427 if (!vmx)
fb3f0f51
RR		 2428 return ERR_PTR(-ENOMEM);
2429
2430 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2431 if (err)
2432 goto free_vcpu;
965b58a5 2433
a2fa3e9f 2434 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2435 if (!vmx->guest_msrs) {
2436 err = -ENOMEM;
2437 goto uninit_vcpu;
2438 }
965b58a5 2439
a2fa3e9f
GH		 2440 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2441 if (!vmx->host_msrs)
fb3f0f51 2442 goto free_guest_msrs;
965b58a5 2443
a2fa3e9f
GH		 2444 vmx->vmcs = alloc_vmcs();
2445 if (!vmx->vmcs)
fb3f0f51 2446 goto free_msrs;
a2fa3e9f
GH		 2447
2448 vmcs_clear(vmx->vmcs);
2449
15ad7146
AK		 2450 cpu = get_cpu();
2451 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2452 err = vmx_vcpu_setup(vmx);
fb3f0f51 2453 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2454 put_cpu();
fb3f0f51
RR		 2455 if (err)
2456 goto free_vmcs;
2457
2458 return &vmx->vcpu;
2459
2460free_vmcs:
2461 free_vmcs(vmx->vmcs);
2462free_msrs:
2463 kfree(vmx->host_msrs);
2464free_guest_msrs:
2465 kfree(vmx->guest_msrs);
2466uninit_vcpu:
2467 kvm_vcpu_uninit(&vmx->vcpu);
2468free_vcpu:
a4770347 2469 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 2470 return ERR_PTR(err);
6aa8b732
AK		 2471}
2472
002c7f7c
YS		 2473static void __init vmx_check_processor_compat(void *rtn)
2474{
2475 struct vmcs_config vmcs_conf;
2476
2477 *(int *)rtn = 0;
2478 if (setup_vmcs_config(&vmcs_conf) < 0)
2479 *(int *)rtn = -EIO;
2480 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2481 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2482 smp_processor_id());
2483 *(int *)rtn = -EIO;
2484 }
2485}
2486
cbdd1bea 2487static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 2488 .cpu_has_kvm_support = cpu_has_kvm_support,
2489 .disabled_by_bios = vmx_disabled_by_bios,
2490 .hardware_setup = hardware_setup,
2491 .hardware_unsetup = hardware_unsetup,
002c7f7c 2492 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2493 .hardware_enable = hardware_enable,
2494 .hardware_disable = hardware_disable,
2495
2496 .vcpu_create = vmx_create_vcpu,
2497 .vcpu_free = vmx_free_vcpu,
04d2cc77 2498 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 2499
04d2cc77 2500 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 2501 .vcpu_load = vmx_vcpu_load,
2502 .vcpu_put = vmx_vcpu_put,
774c47f1 2503 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2504
2505 .set_guest_debug = set_guest_debug,
04d2cc77 2506 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 2507 .get_msr = vmx_get_msr,
2508 .set_msr = vmx_set_msr,
2509 .get_segment_base = vmx_get_segment_base,
2510 .get_segment = vmx_get_segment,
2511 .set_segment = vmx_set_segment,
6aa8b732 2512 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2513 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2514 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2515 .set_cr3 = vmx_set_cr3,
2516 .set_cr4 = vmx_set_cr4,
05b3e0c2 2517#ifdef CONFIG_X86_64
6aa8b732
AK		 2518 .set_efer = vmx_set_efer,
2519#endif
2520 .get_idt = vmx_get_idt,
2521 .set_idt = vmx_set_idt,
2522 .get_gdt = vmx_get_gdt,
2523 .set_gdt = vmx_set_gdt,
2524 .cache_regs = vcpu_load_rsp_rip,
2525 .decache_regs = vcpu_put_rsp_rip,
2526 .get_rflags = vmx_get_rflags,
2527 .set_rflags = vmx_set_rflags,
2528
2529 .tlb_flush = vmx_flush_tlb,
2530 .inject_page_fault = vmx_inject_page_fault,
2531
2532 .inject_gp = vmx_inject_gp,
2533
2534 .run = vmx_vcpu_run,
04d2cc77 2535 .handle_exit = kvm_handle_exit,
6aa8b732 2536 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2537 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 2538 .get_irq = vmx_get_irq,
2539 .set_irq = vmx_inject_irq,
04d2cc77
AK		 2540 .inject_pending_irq = vmx_intr_assist,
2541 .inject_pending_vectors = do_interrupt_requests,
6aa8b732
AK		 2542};
2543
2544static int __init vmx_init(void)
2545{
fdef3ad1
HQ		 2546 void *iova;
2547 int r;
2548
2549 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2550 if (!vmx_io_bitmap_a)
2551 return -ENOMEM;
2552
2553 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2554 if (!vmx_io_bitmap_b) {
2555 r = -ENOMEM;
2556 goto out;
2557 }
2558
2559 /*
2560 * Allow direct access to the PC debug port (it is often used for I/O
2561 * delays, but the vmexits simply slow things down).
2562 */
2563 iova = kmap(vmx_io_bitmap_a);
2564 memset(iova, 0xff, PAGE_SIZE);
2565 clear_bit(0x80, iova);
cd0536d7 2566 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2567
2568 iova = kmap(vmx_io_bitmap_b);
2569 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2570 kunmap(vmx_io_bitmap_b);
fdef3ad1 2571
cbdd1bea 2572 r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1
HQ		 2573 if (r)
2574 goto out1;
2575
c7addb90
AK		 2576 if (bypass_guest_pf)
2577 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2578
fdef3ad1
HQ		 2579 return 0;
2580
2581out1:
2582 __free_page(vmx_io_bitmap_b);
2583out:
2584 __free_page(vmx_io_bitmap_a);
2585 return r;
6aa8b732
AK		 2586}
2587
2588static void __exit vmx_exit(void)
2589{
fdef3ad1
HQ		 2590 __free_page(vmx_io_bitmap_b);
2591 __free_page(vmx_io_bitmap_a);
2592
cbdd1bea 2593 kvm_exit_x86();
6aa8b732
AK		 2594}
2595
2596module_init(vmx_init)
2597module_exit(vmx_exit)
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