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1da177e4 LT |
1 | /* |
2 | * HP i8042-based System Device Controller driver. | |
3 | * | |
4 | * Copyright (c) 2001 Brian S. Julin | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions, and the following disclaimer, | |
12 | * without modification. | |
13 | * 2. The name of the author may not be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * Alternatively, this software may be distributed under the terms of the | |
17 | * GNU General Public License ("GPL"). | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | |
20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR | |
23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
28 | * | |
29 | * References: | |
30 | * System Device Controller Microprocessor Firmware Theory of Operation | |
31 | * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2 | |
32 | * Helge Deller's original hilkbd.c port for PA-RISC. | |
33 | * | |
34 | * | |
35 | * Driver theory of operation: | |
36 | * | |
ffd51f46 HD |
37 | * hp_sdc_put does all writing to the SDC. ISR can run on a different |
38 | * CPU than hp_sdc_put, but only one CPU runs hp_sdc_put at a time | |
1da177e4 LT |
39 | * (it cannot really benefit from SMP anyway.) A tasket fit this perfectly. |
40 | * | |
ffd51f46 HD |
41 | * All data coming back from the SDC is sent via interrupt and can be read |
42 | * fully in the ISR, so there are no latency/throughput problems there. | |
43 | * The problem is with output, due to the slow clock speed of the SDC | |
44 | * compared to the CPU. This should not be too horrible most of the time, | |
45 | * but if used with HIL devices that support the multibyte transfer command, | |
46 | * keeping outbound throughput flowing at the 6500KBps that the HIL is | |
1da177e4 LT |
47 | * capable of is more than can be done at HZ=100. |
48 | * | |
ffd51f46 HD |
49 | * Busy polling for IBF clear wastes CPU cycles and bus cycles. hp_sdc.ibf |
50 | * is set to 0 when the IBF flag in the status register has cleared. ISR | |
51 | * may do this, and may also access the parts of queued transactions related | |
52 | * to reading data back from the SDC, but otherwise will not touch the | |
1da177e4 LT |
53 | * hp_sdc state. Whenever a register is written hp_sdc.ibf is set to 1. |
54 | * | |
55 | * The i8042 write index and the values in the 4-byte input buffer | |
56 | * starting at 0x70 are kept track of in hp_sdc.wi, and .r7[], respectively, | |
ffd51f46 | 57 | * to minimize the amount of IO needed to the SDC. However these values |
1da177e4 LT |
58 | * do not need to be locked since they are only ever accessed by hp_sdc_put. |
59 | * | |
60 | * A timer task schedules the tasklet once per second just to make | |
61 | * sure it doesn't freeze up and to allow for bad reads to time out. | |
62 | */ | |
63 | ||
64 | #include <linux/hp_sdc.h> | |
1da177e4 LT |
65 | #include <linux/errno.h> |
66 | #include <linux/init.h> | |
67 | #include <linux/module.h> | |
68 | #include <linux/ioport.h> | |
69 | #include <linux/time.h> | |
70 | #include <linux/slab.h> | |
71 | #include <linux/hil.h> | |
4933d075 | 72 | #include <linux/semaphore.h> |
1da177e4 LT |
73 | #include <asm/io.h> |
74 | #include <asm/system.h> | |
75 | ||
76 | /* Machine-specific abstraction */ | |
77 | ||
78 | #if defined(__hppa__) | |
79 | # include <asm/parisc-device.h> | |
80 | # define sdc_readb(p) gsc_readb(p) | |
81 | # define sdc_writeb(v,p) gsc_writeb((v),(p)) | |
82 | #elif defined(__mc68000__) | |
83 | # include <asm/uaccess.h> | |
84 | # define sdc_readb(p) in_8(p) | |
85 | # define sdc_writeb(v,p) out_8((p),(v)) | |
86 | #else | |
87 | # error "HIL is not supported on this platform" | |
88 | #endif | |
89 | ||
90 | #define PREFIX "HP SDC: " | |
91 | ||
92 | MODULE_AUTHOR("Brian S. Julin <bri@calyx.com>"); | |
93 | MODULE_DESCRIPTION("HP i8042-based SDC Driver"); | |
94 | MODULE_LICENSE("Dual BSD/GPL"); | |
95 | ||
96 | EXPORT_SYMBOL(hp_sdc_request_timer_irq); | |
97 | EXPORT_SYMBOL(hp_sdc_request_hil_irq); | |
98 | EXPORT_SYMBOL(hp_sdc_request_cooked_irq); | |
99 | ||
100 | EXPORT_SYMBOL(hp_sdc_release_timer_irq); | |
101 | EXPORT_SYMBOL(hp_sdc_release_hil_irq); | |
102 | EXPORT_SYMBOL(hp_sdc_release_cooked_irq); | |
103 | ||
9575499d | 104 | EXPORT_SYMBOL(__hp_sdc_enqueue_transaction); |
1da177e4 LT |
105 | EXPORT_SYMBOL(hp_sdc_enqueue_transaction); |
106 | EXPORT_SYMBOL(hp_sdc_dequeue_transaction); | |
107 | ||
108 | static hp_i8042_sdc hp_sdc; /* All driver state is kept in here. */ | |
109 | ||
110 | /*************** primitives for use in any context *********************/ | |
ffd51f46 HD |
111 | static inline uint8_t hp_sdc_status_in8(void) |
112 | { | |
1da177e4 LT |
113 | uint8_t status; |
114 | unsigned long flags; | |
115 | ||
116 | write_lock_irqsave(&hp_sdc.ibf_lock, flags); | |
117 | status = sdc_readb(hp_sdc.status_io); | |
ffd51f46 HD |
118 | if (!(status & HP_SDC_STATUS_IBF)) |
119 | hp_sdc.ibf = 0; | |
1da177e4 LT |
120 | write_unlock_irqrestore(&hp_sdc.ibf_lock, flags); |
121 | ||
122 | return status; | |
123 | } | |
124 | ||
ffd51f46 HD |
125 | static inline uint8_t hp_sdc_data_in8(void) |
126 | { | |
127 | return sdc_readb(hp_sdc.data_io); | |
1da177e4 LT |
128 | } |
129 | ||
ffd51f46 HD |
130 | static inline void hp_sdc_status_out8(uint8_t val) |
131 | { | |
1da177e4 LT |
132 | unsigned long flags; |
133 | ||
134 | write_lock_irqsave(&hp_sdc.ibf_lock, flags); | |
135 | hp_sdc.ibf = 1; | |
ffd51f46 HD |
136 | if ((val & 0xf0) == 0xe0) |
137 | hp_sdc.wi = 0xff; | |
1da177e4 LT |
138 | sdc_writeb(val, hp_sdc.status_io); |
139 | write_unlock_irqrestore(&hp_sdc.ibf_lock, flags); | |
140 | } | |
141 | ||
ffd51f46 HD |
142 | static inline void hp_sdc_data_out8(uint8_t val) |
143 | { | |
1da177e4 LT |
144 | unsigned long flags; |
145 | ||
146 | write_lock_irqsave(&hp_sdc.ibf_lock, flags); | |
147 | hp_sdc.ibf = 1; | |
148 | sdc_writeb(val, hp_sdc.data_io); | |
149 | write_unlock_irqrestore(&hp_sdc.ibf_lock, flags); | |
150 | } | |
151 | ||
ffd51f46 HD |
152 | /* Care must be taken to only invoke hp_sdc_spin_ibf when |
153 | * absolutely needed, or in rarely invoked subroutines. | |
154 | * Not only does it waste CPU cycles, it also wastes bus cycles. | |
1da177e4 | 155 | */ |
ffd51f46 HD |
156 | static inline void hp_sdc_spin_ibf(void) |
157 | { | |
1da177e4 LT |
158 | unsigned long flags; |
159 | rwlock_t *lock; | |
160 | ||
161 | lock = &hp_sdc.ibf_lock; | |
162 | ||
163 | read_lock_irqsave(lock, flags); | |
164 | if (!hp_sdc.ibf) { | |
165 | read_unlock_irqrestore(lock, flags); | |
166 | return; | |
167 | } | |
168 | read_unlock(lock); | |
169 | write_lock(lock); | |
ffd51f46 HD |
170 | while (sdc_readb(hp_sdc.status_io) & HP_SDC_STATUS_IBF) |
171 | { } | |
1da177e4 LT |
172 | hp_sdc.ibf = 0; |
173 | write_unlock_irqrestore(lock, flags); | |
174 | } | |
175 | ||
176 | ||
177 | /************************ Interrupt context functions ************************/ | |
ffd51f46 HD |
178 | static void hp_sdc_take(int irq, void *dev_id, uint8_t status, uint8_t data) |
179 | { | |
1da177e4 LT |
180 | hp_sdc_transaction *curr; |
181 | ||
182 | read_lock(&hp_sdc.rtq_lock); | |
183 | if (hp_sdc.rcurr < 0) { | |
ffd51f46 | 184 | read_unlock(&hp_sdc.rtq_lock); |
1da177e4 LT |
185 | return; |
186 | } | |
187 | curr = hp_sdc.tq[hp_sdc.rcurr]; | |
188 | read_unlock(&hp_sdc.rtq_lock); | |
189 | ||
190 | curr->seq[curr->idx++] = status; | |
191 | curr->seq[curr->idx++] = data; | |
192 | hp_sdc.rqty -= 2; | |
193 | do_gettimeofday(&hp_sdc.rtv); | |
194 | ||
195 | if (hp_sdc.rqty <= 0) { | |
196 | /* All data has been gathered. */ | |
ffd51f46 HD |
197 | if (curr->seq[curr->actidx] & HP_SDC_ACT_SEMAPHORE) |
198 | if (curr->act.semaphore) | |
199 | up(curr->act.semaphore); | |
200 | ||
201 | if (curr->seq[curr->actidx] & HP_SDC_ACT_CALLBACK) | |
1da177e4 LT |
202 | if (curr->act.irqhook) |
203 | curr->act.irqhook(irq, dev_id, status, data); | |
ffd51f46 | 204 | |
1da177e4 LT |
205 | curr->actidx = curr->idx; |
206 | curr->idx++; | |
207 | /* Return control of this transaction */ | |
208 | write_lock(&hp_sdc.rtq_lock); | |
ffd51f46 | 209 | hp_sdc.rcurr = -1; |
1da177e4 LT |
210 | hp_sdc.rqty = 0; |
211 | write_unlock(&hp_sdc.rtq_lock); | |
212 | tasklet_schedule(&hp_sdc.task); | |
213 | } | |
214 | } | |
215 | ||
ffd51f46 HD |
216 | static irqreturn_t hp_sdc_isr(int irq, void *dev_id) |
217 | { | |
1da177e4 LT |
218 | uint8_t status, data; |
219 | ||
220 | status = hp_sdc_status_in8(); | |
221 | /* Read data unconditionally to advance i8042. */ | |
222 | data = hp_sdc_data_in8(); | |
223 | ||
224 | /* For now we are ignoring these until we get the SDC to behave. */ | |
ffd51f46 HD |
225 | if (((status & 0xf1) == 0x51) && data == 0x82) |
226 | return IRQ_HANDLED; | |
1da177e4 | 227 | |
ffd51f46 HD |
228 | switch (status & HP_SDC_STATUS_IRQMASK) { |
229 | case 0: /* This case is not documented. */ | |
1da177e4 | 230 | break; |
ffd51f46 HD |
231 | |
232 | case HP_SDC_STATUS_USERTIMER: | |
233 | case HP_SDC_STATUS_PERIODIC: | |
234 | case HP_SDC_STATUS_TIMER: | |
1da177e4 | 235 | read_lock(&hp_sdc.hook_lock); |
ffd51f46 | 236 | if (hp_sdc.timer != NULL) |
1da177e4 LT |
237 | hp_sdc.timer(irq, dev_id, status, data); |
238 | read_unlock(&hp_sdc.hook_lock); | |
239 | break; | |
ffd51f46 HD |
240 | |
241 | case HP_SDC_STATUS_REG: | |
1da177e4 LT |
242 | hp_sdc_take(irq, dev_id, status, data); |
243 | break; | |
ffd51f46 HD |
244 | |
245 | case HP_SDC_STATUS_HILCMD: | |
246 | case HP_SDC_STATUS_HILDATA: | |
1da177e4 LT |
247 | read_lock(&hp_sdc.hook_lock); |
248 | if (hp_sdc.hil != NULL) | |
249 | hp_sdc.hil(irq, dev_id, status, data); | |
250 | read_unlock(&hp_sdc.hook_lock); | |
251 | break; | |
ffd51f46 HD |
252 | |
253 | case HP_SDC_STATUS_PUP: | |
1da177e4 LT |
254 | read_lock(&hp_sdc.hook_lock); |
255 | if (hp_sdc.pup != NULL) | |
256 | hp_sdc.pup(irq, dev_id, status, data); | |
ffd51f46 HD |
257 | else |
258 | printk(KERN_INFO PREFIX "HP SDC reports successful PUP.\n"); | |
1da177e4 LT |
259 | read_unlock(&hp_sdc.hook_lock); |
260 | break; | |
ffd51f46 HD |
261 | |
262 | default: | |
1da177e4 LT |
263 | read_lock(&hp_sdc.hook_lock); |
264 | if (hp_sdc.cooked != NULL) | |
265 | hp_sdc.cooked(irq, dev_id, status, data); | |
266 | read_unlock(&hp_sdc.hook_lock); | |
267 | break; | |
268 | } | |
ffd51f46 | 269 | |
1da177e4 LT |
270 | return IRQ_HANDLED; |
271 | } | |
272 | ||
273 | ||
ffd51f46 HD |
274 | static irqreturn_t hp_sdc_nmisr(int irq, void *dev_id) |
275 | { | |
1da177e4 | 276 | int status; |
ffd51f46 | 277 | |
1da177e4 LT |
278 | status = hp_sdc_status_in8(); |
279 | printk(KERN_WARNING PREFIX "NMI !\n"); | |
280 | ||
ffd51f46 | 281 | #if 0 |
1da177e4 LT |
282 | if (status & HP_SDC_NMISTATUS_FHS) { |
283 | read_lock(&hp_sdc.hook_lock); | |
ffd51f46 | 284 | if (hp_sdc.timer != NULL) |
1da177e4 LT |
285 | hp_sdc.timer(irq, dev_id, status, 0); |
286 | read_unlock(&hp_sdc.hook_lock); | |
ffd51f46 | 287 | } else { |
1da177e4 LT |
288 | /* TODO: pass this on to the HIL handler, or do SAK here? */ |
289 | printk(KERN_WARNING PREFIX "HIL NMI\n"); | |
290 | } | |
291 | #endif | |
ffd51f46 | 292 | |
1da177e4 LT |
293 | return IRQ_HANDLED; |
294 | } | |
295 | ||
296 | ||
297 | /***************** Kernel (tasklet) context functions ****************/ | |
298 | ||
299 | unsigned long hp_sdc_put(void); | |
300 | ||
ffd51f46 HD |
301 | static void hp_sdc_tasklet(unsigned long foo) |
302 | { | |
1da177e4 | 303 | write_lock_irq(&hp_sdc.rtq_lock); |
ffd51f46 | 304 | |
1da177e4 LT |
305 | if (hp_sdc.rcurr >= 0) { |
306 | struct timeval tv; | |
ffd51f46 | 307 | |
1da177e4 | 308 | do_gettimeofday(&tv); |
ffd51f46 HD |
309 | if (tv.tv_sec > hp_sdc.rtv.tv_sec) |
310 | tv.tv_usec += USEC_PER_SEC; | |
311 | ||
1da177e4 LT |
312 | if (tv.tv_usec - hp_sdc.rtv.tv_usec > HP_SDC_MAX_REG_DELAY) { |
313 | hp_sdc_transaction *curr; | |
314 | uint8_t tmp; | |
315 | ||
316 | curr = hp_sdc.tq[hp_sdc.rcurr]; | |
317 | /* If this turns out to be a normal failure mode | |
318 | * we'll need to figure out a way to communicate | |
319 | * it back to the application. and be less verbose. | |
320 | */ | |
321 | printk(KERN_WARNING PREFIX "read timeout (%ius)!\n", | |
322 | tv.tv_usec - hp_sdc.rtv.tv_usec); | |
323 | curr->idx += hp_sdc.rqty; | |
324 | hp_sdc.rqty = 0; | |
325 | tmp = curr->seq[curr->actidx]; | |
326 | curr->seq[curr->actidx] |= HP_SDC_ACT_DEAD; | |
ffd51f46 HD |
327 | if (tmp & HP_SDC_ACT_SEMAPHORE) |
328 | if (curr->act.semaphore) | |
1da177e4 | 329 | up(curr->act.semaphore); |
ffd51f46 HD |
330 | |
331 | if (tmp & HP_SDC_ACT_CALLBACK) { | |
1da177e4 LT |
332 | /* Note this means that irqhooks may be called |
333 | * in tasklet/bh context. | |
334 | */ | |
ffd51f46 | 335 | if (curr->act.irqhook) |
6ce6b3ae | 336 | curr->act.irqhook(0, NULL, 0, 0); |
1da177e4 | 337 | } |
ffd51f46 | 338 | |
1da177e4 LT |
339 | curr->actidx = curr->idx; |
340 | curr->idx++; | |
ffd51f46 | 341 | hp_sdc.rcurr = -1; |
1da177e4 LT |
342 | } |
343 | } | |
344 | write_unlock_irq(&hp_sdc.rtq_lock); | |
345 | hp_sdc_put(); | |
346 | } | |
347 | ||
ffd51f46 HD |
348 | unsigned long hp_sdc_put(void) |
349 | { | |
1da177e4 LT |
350 | hp_sdc_transaction *curr; |
351 | uint8_t act; | |
352 | int idx, curridx; | |
353 | ||
354 | int limit = 0; | |
355 | ||
356 | write_lock(&hp_sdc.lock); | |
357 | ||
358 | /* If i8042 buffers are full, we cannot do anything that | |
359 | requires output, so we skip to the administrativa. */ | |
360 | if (hp_sdc.ibf) { | |
361 | hp_sdc_status_in8(); | |
ffd51f46 HD |
362 | if (hp_sdc.ibf) |
363 | goto finish; | |
1da177e4 LT |
364 | } |
365 | ||
366 | anew: | |
367 | /* See if we are in the middle of a sequence. */ | |
ffd51f46 HD |
368 | if (hp_sdc.wcurr < 0) |
369 | hp_sdc.wcurr = 0; | |
1da177e4 | 370 | read_lock_irq(&hp_sdc.rtq_lock); |
ffd51f46 HD |
371 | if (hp_sdc.rcurr == hp_sdc.wcurr) |
372 | hp_sdc.wcurr++; | |
1da177e4 | 373 | read_unlock_irq(&hp_sdc.rtq_lock); |
ffd51f46 HD |
374 | if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN) |
375 | hp_sdc.wcurr = 0; | |
1da177e4 LT |
376 | curridx = hp_sdc.wcurr; |
377 | ||
ffd51f46 HD |
378 | if (hp_sdc.tq[curridx] != NULL) |
379 | goto start; | |
1da177e4 LT |
380 | |
381 | while (++curridx != hp_sdc.wcurr) { | |
382 | if (curridx >= HP_SDC_QUEUE_LEN) { | |
383 | curridx = -1; /* Wrap to top */ | |
384 | continue; | |
385 | } | |
386 | read_lock_irq(&hp_sdc.rtq_lock); | |
387 | if (hp_sdc.rcurr == curridx) { | |
388 | read_unlock_irq(&hp_sdc.rtq_lock); | |
389 | continue; | |
390 | } | |
391 | read_unlock_irq(&hp_sdc.rtq_lock); | |
ffd51f46 HD |
392 | if (hp_sdc.tq[curridx] != NULL) |
393 | break; /* Found one. */ | |
1da177e4 LT |
394 | } |
395 | if (curridx == hp_sdc.wcurr) { /* There's nothing queued to do. */ | |
396 | curridx = -1; | |
397 | } | |
398 | hp_sdc.wcurr = curridx; | |
399 | ||
400 | start: | |
401 | ||
402 | /* Check to see if the interrupt mask needs to be set. */ | |
403 | if (hp_sdc.set_im) { | |
404 | hp_sdc_status_out8(hp_sdc.im | HP_SDC_CMD_SET_IM); | |
405 | hp_sdc.set_im = 0; | |
406 | goto finish; | |
407 | } | |
408 | ||
ffd51f46 HD |
409 | if (hp_sdc.wcurr == -1) |
410 | goto done; | |
1da177e4 LT |
411 | |
412 | curr = hp_sdc.tq[curridx]; | |
413 | idx = curr->actidx; | |
414 | ||
415 | if (curr->actidx >= curr->endidx) { | |
416 | hp_sdc.tq[curridx] = NULL; | |
417 | /* Interleave outbound data between the transactions. */ | |
418 | hp_sdc.wcurr++; | |
ffd51f46 HD |
419 | if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN) |
420 | hp_sdc.wcurr = 0; | |
421 | goto finish; | |
1da177e4 LT |
422 | } |
423 | ||
424 | act = curr->seq[idx]; | |
425 | idx++; | |
426 | ||
427 | if (curr->idx >= curr->endidx) { | |
ffd51f46 HD |
428 | if (act & HP_SDC_ACT_DEALLOC) |
429 | kfree(curr); | |
1da177e4 LT |
430 | hp_sdc.tq[curridx] = NULL; |
431 | /* Interleave outbound data between the transactions. */ | |
432 | hp_sdc.wcurr++; | |
ffd51f46 HD |
433 | if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN) |
434 | hp_sdc.wcurr = 0; | |
435 | goto finish; | |
1da177e4 LT |
436 | } |
437 | ||
438 | while (act & HP_SDC_ACT_PRECMD) { | |
439 | if (curr->idx != idx) { | |
440 | idx++; | |
441 | act &= ~HP_SDC_ACT_PRECMD; | |
442 | break; | |
443 | } | |
444 | hp_sdc_status_out8(curr->seq[idx]); | |
445 | curr->idx++; | |
446 | /* act finished? */ | |
447 | if ((act & HP_SDC_ACT_DURING) == HP_SDC_ACT_PRECMD) | |
ffd51f46 | 448 | goto actdone; |
1da177e4 | 449 | /* skip quantity field if data-out sequence follows. */ |
ffd51f46 HD |
450 | if (act & HP_SDC_ACT_DATAOUT) |
451 | curr->idx++; | |
1da177e4 LT |
452 | goto finish; |
453 | } | |
454 | if (act & HP_SDC_ACT_DATAOUT) { | |
455 | int qty; | |
456 | ||
457 | qty = curr->seq[idx]; | |
458 | idx++; | |
459 | if (curr->idx - idx < qty) { | |
460 | hp_sdc_data_out8(curr->seq[curr->idx]); | |
461 | curr->idx++; | |
462 | /* act finished? */ | |
ffd51f46 HD |
463 | if (curr->idx - idx >= qty && |
464 | (act & HP_SDC_ACT_DURING) == HP_SDC_ACT_DATAOUT) | |
1da177e4 LT |
465 | goto actdone; |
466 | goto finish; | |
467 | } | |
468 | idx += qty; | |
469 | act &= ~HP_SDC_ACT_DATAOUT; | |
ffd51f46 HD |
470 | } else |
471 | while (act & HP_SDC_ACT_DATAREG) { | |
1da177e4 LT |
472 | int mask; |
473 | uint8_t w7[4]; | |
474 | ||
475 | mask = curr->seq[idx]; | |
476 | if (idx != curr->idx) { | |
477 | idx++; | |
478 | idx += !!(mask & 1); | |
479 | idx += !!(mask & 2); | |
480 | idx += !!(mask & 4); | |
481 | idx += !!(mask & 8); | |
482 | act &= ~HP_SDC_ACT_DATAREG; | |
483 | break; | |
484 | } | |
ffd51f46 | 485 | |
1da177e4 LT |
486 | w7[0] = (mask & 1) ? curr->seq[++idx] : hp_sdc.r7[0]; |
487 | w7[1] = (mask & 2) ? curr->seq[++idx] : hp_sdc.r7[1]; | |
488 | w7[2] = (mask & 4) ? curr->seq[++idx] : hp_sdc.r7[2]; | |
489 | w7[3] = (mask & 8) ? curr->seq[++idx] : hp_sdc.r7[3]; | |
ffd51f46 | 490 | |
1da177e4 | 491 | if (hp_sdc.wi > 0x73 || hp_sdc.wi < 0x70 || |
ffd51f46 | 492 | w7[hp_sdc.wi - 0x70] == hp_sdc.r7[hp_sdc.wi - 0x70]) { |
1da177e4 LT |
493 | int i = 0; |
494 | ||
ffd51f46 HD |
495 | /* Need to point the write index register */ |
496 | while (i < 4 && w7[i] == hp_sdc.r7[i]) | |
497 | i++; | |
498 | ||
1da177e4 LT |
499 | if (i < 4) { |
500 | hp_sdc_status_out8(HP_SDC_CMD_SET_D0 + i); | |
501 | hp_sdc.wi = 0x70 + i; | |
502 | goto finish; | |
503 | } | |
ffd51f46 | 504 | |
1da177e4 LT |
505 | idx++; |
506 | if ((act & HP_SDC_ACT_DURING) == HP_SDC_ACT_DATAREG) | |
507 | goto actdone; | |
ffd51f46 | 508 | |
1da177e4 LT |
509 | curr->idx = idx; |
510 | act &= ~HP_SDC_ACT_DATAREG; | |
511 | break; | |
512 | } | |
513 | ||
514 | hp_sdc_data_out8(w7[hp_sdc.wi - 0x70]); | |
515 | hp_sdc.r7[hp_sdc.wi - 0x70] = w7[hp_sdc.wi - 0x70]; | |
516 | hp_sdc.wi++; /* write index register autoincrements */ | |
517 | { | |
518 | int i = 0; | |
519 | ||
ffd51f46 HD |
520 | while ((i < 4) && w7[i] == hp_sdc.r7[i]) |
521 | i++; | |
1da177e4 LT |
522 | if (i >= 4) { |
523 | curr->idx = idx + 1; | |
ffd51f46 | 524 | if ((act & HP_SDC_ACT_DURING) == |
1da177e4 | 525 | HP_SDC_ACT_DATAREG) |
ffd51f46 | 526 | goto actdone; |
1da177e4 LT |
527 | } |
528 | } | |
529 | goto finish; | |
530 | } | |
531 | /* We don't go any further in the command if there is a pending read, | |
532 | because we don't want interleaved results. */ | |
533 | read_lock_irq(&hp_sdc.rtq_lock); | |
534 | if (hp_sdc.rcurr >= 0) { | |
535 | read_unlock_irq(&hp_sdc.rtq_lock); | |
536 | goto finish; | |
537 | } | |
538 | read_unlock_irq(&hp_sdc.rtq_lock); | |
539 | ||
540 | ||
541 | if (act & HP_SDC_ACT_POSTCMD) { | |
ffd51f46 | 542 | uint8_t postcmd; |
1da177e4 LT |
543 | |
544 | /* curr->idx should == idx at this point. */ | |
545 | postcmd = curr->seq[idx]; | |
546 | curr->idx++; | |
547 | if (act & HP_SDC_ACT_DATAIN) { | |
548 | ||
549 | /* Start a new read */ | |
ffd51f46 | 550 | hp_sdc.rqty = curr->seq[curr->idx]; |
1da177e4 LT |
551 | do_gettimeofday(&hp_sdc.rtv); |
552 | curr->idx++; | |
553 | /* Still need to lock here in case of spurious irq. */ | |
554 | write_lock_irq(&hp_sdc.rtq_lock); | |
ffd51f46 | 555 | hp_sdc.rcurr = curridx; |
1da177e4 LT |
556 | write_unlock_irq(&hp_sdc.rtq_lock); |
557 | hp_sdc_status_out8(postcmd); | |
558 | goto finish; | |
559 | } | |
560 | hp_sdc_status_out8(postcmd); | |
561 | goto actdone; | |
562 | } | |
563 | ||
ffd51f46 HD |
564 | actdone: |
565 | if (act & HP_SDC_ACT_SEMAPHORE) | |
1da177e4 | 566 | up(curr->act.semaphore); |
ffd51f46 | 567 | else if (act & HP_SDC_ACT_CALLBACK) |
6ce6b3ae | 568 | curr->act.irqhook(0,NULL,0,0); |
ffd51f46 | 569 | |
1da177e4 | 570 | if (curr->idx >= curr->endidx) { /* This transaction is over. */ |
ffd51f46 HD |
571 | if (act & HP_SDC_ACT_DEALLOC) |
572 | kfree(curr); | |
1da177e4 | 573 | hp_sdc.tq[curridx] = NULL; |
ffd51f46 | 574 | } else { |
1da177e4 LT |
575 | curr->actidx = idx + 1; |
576 | curr->idx = idx + 2; | |
577 | } | |
578 | /* Interleave outbound data between the transactions. */ | |
579 | hp_sdc.wcurr++; | |
ffd51f46 HD |
580 | if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN) |
581 | hp_sdc.wcurr = 0; | |
1da177e4 LT |
582 | |
583 | finish: | |
ffd51f46 | 584 | /* If by some quirk IBF has cleared and our ISR has run to |
1da177e4 | 585 | see that that has happened, do it all again. */ |
ffd51f46 HD |
586 | if (!hp_sdc.ibf && limit++ < 20) |
587 | goto anew; | |
1da177e4 LT |
588 | |
589 | done: | |
ffd51f46 HD |
590 | if (hp_sdc.wcurr >= 0) |
591 | tasklet_schedule(&hp_sdc.task); | |
1da177e4 | 592 | write_unlock(&hp_sdc.lock); |
ffd51f46 | 593 | |
1da177e4 LT |
594 | return 0; |
595 | } | |
596 | ||
597 | /******* Functions called in either user or kernel context ****/ | |
9575499d | 598 | int __hp_sdc_enqueue_transaction(hp_sdc_transaction *this) |
ffd51f46 | 599 | { |
1da177e4 LT |
600 | int i; |
601 | ||
602 | if (this == NULL) { | |
9575499d | 603 | BUG(); |
1da177e4 | 604 | return -EINVAL; |
ffd51f46 | 605 | } |
1da177e4 | 606 | |
1da177e4 | 607 | /* Can't have same transaction on queue twice */ |
ffd51f46 HD |
608 | for (i = 0; i < HP_SDC_QUEUE_LEN; i++) |
609 | if (hp_sdc.tq[i] == this) | |
610 | goto fail; | |
1da177e4 LT |
611 | |
612 | this->actidx = 0; | |
613 | this->idx = 1; | |
614 | ||
615 | /* Search for empty slot */ | |
ffd51f46 | 616 | for (i = 0; i < HP_SDC_QUEUE_LEN; i++) |
1da177e4 LT |
617 | if (hp_sdc.tq[i] == NULL) { |
618 | hp_sdc.tq[i] = this; | |
1da177e4 LT |
619 | tasklet_schedule(&hp_sdc.task); |
620 | return 0; | |
621 | } | |
ffd51f46 | 622 | |
1da177e4 LT |
623 | printk(KERN_WARNING PREFIX "No free slot to add transaction.\n"); |
624 | return -EBUSY; | |
625 | ||
626 | fail: | |
1da177e4 LT |
627 | printk(KERN_WARNING PREFIX "Transaction add failed: transaction already queued?\n"); |
628 | return -EINVAL; | |
629 | } | |
630 | ||
9575499d HD |
631 | int hp_sdc_enqueue_transaction(hp_sdc_transaction *this) { |
632 | unsigned long flags; | |
633 | int ret; | |
634 | ||
635 | write_lock_irqsave(&hp_sdc.lock, flags); | |
636 | ret = __hp_sdc_enqueue_transaction(this); | |
637 | write_unlock_irqrestore(&hp_sdc.lock,flags); | |
638 | ||
639 | return ret; | |
640 | } | |
641 | ||
ffd51f46 HD |
642 | int hp_sdc_dequeue_transaction(hp_sdc_transaction *this) |
643 | { | |
1da177e4 LT |
644 | unsigned long flags; |
645 | int i; | |
646 | ||
647 | write_lock_irqsave(&hp_sdc.lock, flags); | |
648 | ||
649 | /* TODO: don't remove it if it's not done. */ | |
650 | ||
ffd51f46 HD |
651 | for (i = 0; i < HP_SDC_QUEUE_LEN; i++) |
652 | if (hp_sdc.tq[i] == this) | |
653 | hp_sdc.tq[i] = NULL; | |
1da177e4 LT |
654 | |
655 | write_unlock_irqrestore(&hp_sdc.lock, flags); | |
656 | return 0; | |
657 | } | |
658 | ||
659 | ||
660 | ||
661 | /********************** User context functions **************************/ | |
ffd51f46 HD |
662 | int hp_sdc_request_timer_irq(hp_sdc_irqhook *callback) |
663 | { | |
664 | if (callback == NULL || hp_sdc.dev == NULL) | |
1da177e4 | 665 | return -EINVAL; |
ffd51f46 | 666 | |
1da177e4 LT |
667 | write_lock_irq(&hp_sdc.hook_lock); |
668 | if (hp_sdc.timer != NULL) { | |
669 | write_unlock_irq(&hp_sdc.hook_lock); | |
670 | return -EBUSY; | |
671 | } | |
672 | ||
673 | hp_sdc.timer = callback; | |
674 | /* Enable interrupts from the timers */ | |
675 | hp_sdc.im &= ~HP_SDC_IM_FH; | |
676 | hp_sdc.im &= ~HP_SDC_IM_PT; | |
677 | hp_sdc.im &= ~HP_SDC_IM_TIMERS; | |
678 | hp_sdc.set_im = 1; | |
679 | write_unlock_irq(&hp_sdc.hook_lock); | |
680 | ||
681 | tasklet_schedule(&hp_sdc.task); | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
ffd51f46 HD |
686 | int hp_sdc_request_hil_irq(hp_sdc_irqhook *callback) |
687 | { | |
688 | if (callback == NULL || hp_sdc.dev == NULL) | |
1da177e4 | 689 | return -EINVAL; |
ffd51f46 | 690 | |
1da177e4 LT |
691 | write_lock_irq(&hp_sdc.hook_lock); |
692 | if (hp_sdc.hil != NULL) { | |
693 | write_unlock_irq(&hp_sdc.hook_lock); | |
694 | return -EBUSY; | |
695 | } | |
696 | ||
697 | hp_sdc.hil = callback; | |
698 | hp_sdc.im &= ~(HP_SDC_IM_HIL | HP_SDC_IM_RESET); | |
699 | hp_sdc.set_im = 1; | |
700 | write_unlock_irq(&hp_sdc.hook_lock); | |
701 | ||
702 | tasklet_schedule(&hp_sdc.task); | |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
ffd51f46 HD |
707 | int hp_sdc_request_cooked_irq(hp_sdc_irqhook *callback) |
708 | { | |
709 | if (callback == NULL || hp_sdc.dev == NULL) | |
1da177e4 | 710 | return -EINVAL; |
ffd51f46 | 711 | |
1da177e4 LT |
712 | write_lock_irq(&hp_sdc.hook_lock); |
713 | if (hp_sdc.cooked != NULL) { | |
714 | write_unlock_irq(&hp_sdc.hook_lock); | |
715 | return -EBUSY; | |
716 | } | |
717 | ||
718 | /* Enable interrupts from the HIL MLC */ | |
719 | hp_sdc.cooked = callback; | |
720 | hp_sdc.im &= ~(HP_SDC_IM_HIL | HP_SDC_IM_RESET); | |
721 | hp_sdc.set_im = 1; | |
722 | write_unlock_irq(&hp_sdc.hook_lock); | |
723 | ||
724 | tasklet_schedule(&hp_sdc.task); | |
725 | ||
726 | return 0; | |
727 | } | |
728 | ||
ffd51f46 HD |
729 | int hp_sdc_release_timer_irq(hp_sdc_irqhook *callback) |
730 | { | |
1da177e4 LT |
731 | write_lock_irq(&hp_sdc.hook_lock); |
732 | if ((callback != hp_sdc.timer) || | |
733 | (hp_sdc.timer == NULL)) { | |
734 | write_unlock_irq(&hp_sdc.hook_lock); | |
735 | return -EINVAL; | |
736 | } | |
737 | ||
738 | /* Disable interrupts from the timers */ | |
739 | hp_sdc.timer = NULL; | |
740 | hp_sdc.im |= HP_SDC_IM_TIMERS; | |
741 | hp_sdc.im |= HP_SDC_IM_FH; | |
742 | hp_sdc.im |= HP_SDC_IM_PT; | |
743 | hp_sdc.set_im = 1; | |
744 | write_unlock_irq(&hp_sdc.hook_lock); | |
745 | tasklet_schedule(&hp_sdc.task); | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
ffd51f46 HD |
750 | int hp_sdc_release_hil_irq(hp_sdc_irqhook *callback) |
751 | { | |
1da177e4 LT |
752 | write_lock_irq(&hp_sdc.hook_lock); |
753 | if ((callback != hp_sdc.hil) || | |
754 | (hp_sdc.hil == NULL)) { | |
755 | write_unlock_irq(&hp_sdc.hook_lock); | |
756 | return -EINVAL; | |
757 | } | |
758 | ||
759 | hp_sdc.hil = NULL; | |
760 | /* Disable interrupts from HIL only if there is no cooked driver. */ | |
761 | if(hp_sdc.cooked == NULL) { | |
762 | hp_sdc.im |= (HP_SDC_IM_HIL | HP_SDC_IM_RESET); | |
763 | hp_sdc.set_im = 1; | |
764 | } | |
765 | write_unlock_irq(&hp_sdc.hook_lock); | |
766 | tasklet_schedule(&hp_sdc.task); | |
767 | ||
768 | return 0; | |
769 | } | |
770 | ||
ffd51f46 HD |
771 | int hp_sdc_release_cooked_irq(hp_sdc_irqhook *callback) |
772 | { | |
1da177e4 LT |
773 | write_lock_irq(&hp_sdc.hook_lock); |
774 | if ((callback != hp_sdc.cooked) || | |
775 | (hp_sdc.cooked == NULL)) { | |
776 | write_unlock_irq(&hp_sdc.hook_lock); | |
777 | return -EINVAL; | |
778 | } | |
779 | ||
780 | hp_sdc.cooked = NULL; | |
781 | /* Disable interrupts from HIL only if there is no raw HIL driver. */ | |
782 | if(hp_sdc.hil == NULL) { | |
783 | hp_sdc.im |= (HP_SDC_IM_HIL | HP_SDC_IM_RESET); | |
784 | hp_sdc.set_im = 1; | |
785 | } | |
786 | write_unlock_irq(&hp_sdc.hook_lock); | |
787 | tasklet_schedule(&hp_sdc.task); | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
792 | /************************* Keepalive timer task *********************/ | |
793 | ||
ffd51f46 HD |
794 | void hp_sdc_kicker (unsigned long data) |
795 | { | |
1da177e4 LT |
796 | tasklet_schedule(&hp_sdc.task); |
797 | /* Re-insert the periodic task. */ | |
798 | mod_timer(&hp_sdc.kicker, jiffies + HZ); | |
799 | } | |
800 | ||
801 | /************************** Module Initialization ***************************/ | |
802 | ||
803 | #if defined(__hppa__) | |
804 | ||
3acaf540 | 805 | static const struct parisc_device_id hp_sdc_tbl[] = { |
1da177e4 | 806 | { |
ffd51f46 | 807 | .hw_type = HPHW_FIO, |
1da177e4 LT |
808 | .hversion_rev = HVERSION_REV_ANY_ID, |
809 | .hversion = HVERSION_ANY_ID, | |
ffd51f46 | 810 | .sversion = 0x73, |
1da177e4 LT |
811 | }, |
812 | { 0, } | |
813 | }; | |
814 | ||
815 | MODULE_DEVICE_TABLE(parisc, hp_sdc_tbl); | |
816 | ||
817 | static int __init hp_sdc_init_hppa(struct parisc_device *d); | |
818 | ||
819 | static struct parisc_driver hp_sdc_driver = { | |
bdad1f83 | 820 | .name = "hp_sdc", |
1da177e4 LT |
821 | .id_table = hp_sdc_tbl, |
822 | .probe = hp_sdc_init_hppa, | |
823 | }; | |
824 | ||
825 | #endif /* __hppa__ */ | |
826 | ||
827 | static int __init hp_sdc_init(void) | |
828 | { | |
1da177e4 LT |
829 | char *errstr; |
830 | hp_sdc_transaction t_sync; | |
831 | uint8_t ts_sync[6]; | |
832 | struct semaphore s_sync; | |
833 | ||
ffd51f46 HD |
834 | rwlock_init(&hp_sdc.lock); |
835 | rwlock_init(&hp_sdc.ibf_lock); | |
836 | rwlock_init(&hp_sdc.rtq_lock); | |
837 | rwlock_init(&hp_sdc.hook_lock); | |
1da177e4 LT |
838 | |
839 | hp_sdc.timer = NULL; | |
840 | hp_sdc.hil = NULL; | |
841 | hp_sdc.pup = NULL; | |
842 | hp_sdc.cooked = NULL; | |
843 | hp_sdc.im = HP_SDC_IM_MASK; /* Mask maskable irqs */ | |
844 | hp_sdc.set_im = 1; | |
845 | hp_sdc.wi = 0xff; | |
846 | hp_sdc.r7[0] = 0xff; | |
847 | hp_sdc.r7[1] = 0xff; | |
848 | hp_sdc.r7[2] = 0xff; | |
849 | hp_sdc.r7[3] = 0xff; | |
850 | hp_sdc.ibf = 1; | |
851 | ||
ffd51f46 HD |
852 | memset(&hp_sdc.tq, 0, sizeof(hp_sdc.tq)); |
853 | ||
1da177e4 LT |
854 | hp_sdc.wcurr = -1; |
855 | hp_sdc.rcurr = -1; | |
856 | hp_sdc.rqty = 0; | |
857 | ||
858 | hp_sdc.dev_err = -ENODEV; | |
859 | ||
860 | errstr = "IO not found for"; | |
ffd51f46 HD |
861 | if (!hp_sdc.base_io) |
862 | goto err0; | |
1da177e4 LT |
863 | |
864 | errstr = "IRQ not found for"; | |
ffd51f46 HD |
865 | if (!hp_sdc.irq) |
866 | goto err0; | |
1da177e4 LT |
867 | |
868 | hp_sdc.dev_err = -EBUSY; | |
869 | ||
870 | #if defined(__hppa__) | |
871 | errstr = "IO not available for"; | |
ffd51f46 HD |
872 | if (request_region(hp_sdc.data_io, 2, hp_sdc_driver.name)) |
873 | goto err0; | |
874 | #endif | |
1da177e4 LT |
875 | |
876 | errstr = "IRQ not available for"; | |
3acaf540 | 877 | if (request_irq(hp_sdc.irq, &hp_sdc_isr, IRQF_SHARED|IRQF_SAMPLE_RANDOM, |
ffd51f46 HD |
878 | "HP SDC", &hp_sdc)) |
879 | goto err1; | |
1da177e4 LT |
880 | |
881 | errstr = "NMI not available for"; | |
3acaf540 | 882 | if (request_irq(hp_sdc.nmi, &hp_sdc_nmisr, IRQF_SHARED, |
ffd51f46 HD |
883 | "HP SDC NMI", &hp_sdc)) |
884 | goto err2; | |
1da177e4 | 885 | |
ffd51f46 | 886 | printk(KERN_INFO PREFIX "HP SDC at 0x%p, IRQ %d (NMI IRQ %d)\n", |
1da177e4 LT |
887 | (void *)hp_sdc.base_io, hp_sdc.irq, hp_sdc.nmi); |
888 | ||
889 | hp_sdc_status_in8(); | |
890 | hp_sdc_data_in8(); | |
891 | ||
892 | tasklet_init(&hp_sdc.task, hp_sdc_tasklet, 0); | |
893 | ||
894 | /* Sync the output buffer registers, thus scheduling hp_sdc_tasklet. */ | |
895 | t_sync.actidx = 0; | |
896 | t_sync.idx = 1; | |
897 | t_sync.endidx = 6; | |
898 | t_sync.seq = ts_sync; | |
899 | ts_sync[0] = HP_SDC_ACT_DATAREG | HP_SDC_ACT_SEMAPHORE; | |
900 | ts_sync[1] = 0x0f; | |
901 | ts_sync[2] = ts_sync[3] = ts_sync[4] = ts_sync[5] = 0; | |
902 | t_sync.act.semaphore = &s_sync; | |
903 | init_MUTEX_LOCKED(&s_sync); | |
904 | hp_sdc_enqueue_transaction(&t_sync); | |
905 | down(&s_sync); /* Wait for t_sync to complete */ | |
906 | ||
907 | /* Create the keepalive task */ | |
908 | init_timer(&hp_sdc.kicker); | |
909 | hp_sdc.kicker.expires = jiffies + HZ; | |
910 | hp_sdc.kicker.function = &hp_sdc_kicker; | |
911 | add_timer(&hp_sdc.kicker); | |
912 | ||
913 | hp_sdc.dev_err = 0; | |
914 | return 0; | |
915 | err2: | |
3acaf540 | 916 | free_irq(hp_sdc.irq, &hp_sdc); |
1da177e4 LT |
917 | err1: |
918 | release_region(hp_sdc.data_io, 2); | |
919 | err0: | |
ffd51f46 | 920 | printk(KERN_WARNING PREFIX ": %s SDC IO=0x%p IRQ=0x%x NMI=0x%x\n", |
1da177e4 LT |
921 | errstr, (void *)hp_sdc.base_io, hp_sdc.irq, hp_sdc.nmi); |
922 | hp_sdc.dev = NULL; | |
ffd51f46 | 923 | |
1da177e4 LT |
924 | return hp_sdc.dev_err; |
925 | } | |
926 | ||
927 | #if defined(__hppa__) | |
928 | ||
929 | static int __init hp_sdc_init_hppa(struct parisc_device *d) | |
930 | { | |
ffd51f46 HD |
931 | if (!d) |
932 | return 1; | |
933 | if (hp_sdc.dev != NULL) | |
934 | return 1; /* We only expect one SDC */ | |
1da177e4 LT |
935 | |
936 | hp_sdc.dev = d; | |
937 | hp_sdc.irq = d->irq; | |
938 | hp_sdc.nmi = d->aux_irq; | |
53f01bba MW |
939 | hp_sdc.base_io = d->hpa.start; |
940 | hp_sdc.data_io = d->hpa.start + 0x800; | |
941 | hp_sdc.status_io = d->hpa.start + 0x801; | |
1da177e4 LT |
942 | |
943 | return hp_sdc_init(); | |
944 | } | |
945 | ||
946 | #endif /* __hppa__ */ | |
947 | ||
1da177e4 | 948 | static void hp_sdc_exit(void) |
1da177e4 LT |
949 | { |
950 | write_lock_irq(&hp_sdc.lock); | |
951 | ||
952 | /* Turn off all maskable "sub-function" irq's. */ | |
953 | hp_sdc_spin_ibf(); | |
954 | sdc_writeb(HP_SDC_CMD_SET_IM | HP_SDC_IM_MASK, hp_sdc.status_io); | |
955 | ||
956 | /* Wait until we know this has been processed by the i8042 */ | |
957 | hp_sdc_spin_ibf(); | |
958 | ||
3acaf540 HD |
959 | free_irq(hp_sdc.nmi, &hp_sdc); |
960 | free_irq(hp_sdc.irq, &hp_sdc); | |
1da177e4 LT |
961 | write_unlock_irq(&hp_sdc.lock); |
962 | ||
963 | del_timer(&hp_sdc.kicker); | |
964 | ||
965 | tasklet_kill(&hp_sdc.task); | |
966 | ||
1da177e4 | 967 | #if defined(__hppa__) |
ffd51f46 | 968 | if (unregister_parisc_driver(&hp_sdc_driver)) |
1da177e4 LT |
969 | printk(KERN_WARNING PREFIX "Error unregistering HP SDC"); |
970 | #endif | |
971 | } | |
972 | ||
973 | static int __init hp_sdc_register(void) | |
974 | { | |
975 | hp_sdc_transaction tq_init; | |
976 | uint8_t tq_init_seq[5]; | |
977 | struct semaphore tq_init_sem; | |
978 | #if defined(__mc68000__) | |
979 | mm_segment_t fs; | |
980 | unsigned char i; | |
981 | #endif | |
ffd51f46 | 982 | |
1da177e4 LT |
983 | hp_sdc.dev = NULL; |
984 | hp_sdc.dev_err = 0; | |
985 | #if defined(__hppa__) | |
986 | if (register_parisc_driver(&hp_sdc_driver)) { | |
987 | printk(KERN_WARNING PREFIX "Error registering SDC with system bus tree.\n"); | |
988 | return -ENODEV; | |
989 | } | |
990 | #elif defined(__mc68000__) | |
991 | if (!MACH_IS_HP300) | |
992 | return -ENODEV; | |
993 | ||
994 | hp_sdc.irq = 1; | |
995 | hp_sdc.nmi = 7; | |
996 | hp_sdc.base_io = (unsigned long) 0xf0428000; | |
997 | hp_sdc.data_io = (unsigned long) hp_sdc.base_io + 1; | |
998 | hp_sdc.status_io = (unsigned long) hp_sdc.base_io + 3; | |
999 | fs = get_fs(); | |
1000 | set_fs(KERNEL_DS); | |
1001 | if (!get_user(i, (unsigned char *)hp_sdc.data_io)) | |
1002 | hp_sdc.dev = (void *)1; | |
1003 | set_fs(fs); | |
1004 | hp_sdc.dev_err = hp_sdc_init(); | |
1005 | #endif | |
1006 | if (hp_sdc.dev == NULL) { | |
1007 | printk(KERN_WARNING PREFIX "No SDC found.\n"); | |
1008 | return hp_sdc.dev_err; | |
1009 | } | |
1010 | ||
1011 | init_MUTEX_LOCKED(&tq_init_sem); | |
1012 | ||
1013 | tq_init.actidx = 0; | |
1014 | tq_init.idx = 1; | |
1015 | tq_init.endidx = 5; | |
1016 | tq_init.seq = tq_init_seq; | |
1017 | tq_init.act.semaphore = &tq_init_sem; | |
1018 | ||
ffd51f46 HD |
1019 | tq_init_seq[0] = |
1020 | HP_SDC_ACT_POSTCMD | HP_SDC_ACT_DATAIN | HP_SDC_ACT_SEMAPHORE; | |
1da177e4 LT |
1021 | tq_init_seq[1] = HP_SDC_CMD_READ_KCC; |
1022 | tq_init_seq[2] = 1; | |
1023 | tq_init_seq[3] = 0; | |
1024 | tq_init_seq[4] = 0; | |
1025 | ||
1026 | hp_sdc_enqueue_transaction(&tq_init); | |
1027 | ||
1028 | down(&tq_init_sem); | |
1029 | up(&tq_init_sem); | |
1030 | ||
1031 | if ((tq_init_seq[0] & HP_SDC_ACT_DEAD) == HP_SDC_ACT_DEAD) { | |
1032 | printk(KERN_WARNING PREFIX "Error reading config byte.\n"); | |
1033 | hp_sdc_exit(); | |
1034 | return -ENODEV; | |
1035 | } | |
1036 | hp_sdc.r11 = tq_init_seq[4]; | |
1037 | if (hp_sdc.r11 & HP_SDC_CFG_NEW) { | |
ffd51f46 | 1038 | const char *str; |
1da177e4 LT |
1039 | printk(KERN_INFO PREFIX "New style SDC\n"); |
1040 | tq_init_seq[1] = HP_SDC_CMD_READ_XTD; | |
1041 | tq_init.actidx = 0; | |
1042 | tq_init.idx = 1; | |
1043 | down(&tq_init_sem); | |
ffd51f46 | 1044 | hp_sdc_enqueue_transaction(&tq_init); |
1da177e4 LT |
1045 | down(&tq_init_sem); |
1046 | up(&tq_init_sem); | |
1047 | if ((tq_init_seq[0] & HP_SDC_ACT_DEAD) == HP_SDC_ACT_DEAD) { | |
1048 | printk(KERN_WARNING PREFIX "Error reading extended config byte.\n"); | |
1049 | return -ENODEV; | |
1050 | } | |
1051 | hp_sdc.r7e = tq_init_seq[4]; | |
1052 | HP_SDC_XTD_REV_STRINGS(hp_sdc.r7e & HP_SDC_XTD_REV, str) | |
1053 | printk(KERN_INFO PREFIX "Revision: %s\n", str); | |
ffd51f46 | 1054 | if (hp_sdc.r7e & HP_SDC_XTD_BEEPER) |
1da177e4 | 1055 | printk(KERN_INFO PREFIX "TI SN76494 beeper present\n"); |
ffd51f46 | 1056 | if (hp_sdc.r7e & HP_SDC_XTD_BBRTC) |
1da177e4 | 1057 | printk(KERN_INFO PREFIX "OKI MSM-58321 BBRTC present\n"); |
1da177e4 LT |
1058 | printk(KERN_INFO PREFIX "Spunking the self test register to force PUP " |
1059 | "on next firmware reset.\n"); | |
ffd51f46 | 1060 | tq_init_seq[0] = HP_SDC_ACT_PRECMD | |
1da177e4 LT |
1061 | HP_SDC_ACT_DATAOUT | HP_SDC_ACT_SEMAPHORE; |
1062 | tq_init_seq[1] = HP_SDC_CMD_SET_STR; | |
1063 | tq_init_seq[2] = 1; | |
1064 | tq_init_seq[3] = 0; | |
1065 | tq_init.actidx = 0; | |
1066 | tq_init.idx = 1; | |
1067 | tq_init.endidx = 4; | |
1068 | down(&tq_init_sem); | |
ffd51f46 | 1069 | hp_sdc_enqueue_transaction(&tq_init); |
1da177e4 LT |
1070 | down(&tq_init_sem); |
1071 | up(&tq_init_sem); | |
ffd51f46 HD |
1072 | } else |
1073 | printk(KERN_INFO PREFIX "Old style SDC (1820-%s).\n", | |
1da177e4 | 1074 | (hp_sdc.r11 & HP_SDC_CFG_REV) ? "3300" : "2564/3087"); |
1da177e4 LT |
1075 | |
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | module_init(hp_sdc_register); | |
1080 | module_exit(hp_sdc_exit); | |
1081 | ||
ffd51f46 | 1082 | /* Timing notes: These measurements taken on my 64MHz 7100-LC (715/64) |
1da177e4 LT |
1083 | * cycles cycles-adj time |
1084 | * between two consecutive mfctl(16)'s: 4 n/a 63ns | |
1085 | * hp_sdc_spin_ibf when idle: 119 115 1.7us | |
1086 | * gsc_writeb status register: 83 79 1.2us | |
1087 | * IBF to clear after sending SET_IM: 6204 6006 93us | |
ffd51f46 | 1088 | * IBF to clear after sending LOAD_RT: 4467 4352 68us |
1da177e4 LT |
1089 | * IBF to clear after sending two LOAD_RTs: 18974 18859 295us |
1090 | * READ_T1, read status/data, IRQ, call handler: 35564 n/a 556us | |
1091 | * cmd to ~IBF READ_T1 2nd time right after: 5158403 n/a 81ms | |
1092 | * between IRQ received and ~IBF for above: 2578877 n/a 40ms | |
1093 | * | |
1094 | * Performance stats after a run of this module configuring HIL and | |
1095 | * receiving a few mouse events: | |
1096 | * | |
1097 | * status in8 282508 cycles 7128 calls | |
1098 | * status out8 8404 cycles 341 calls | |
1099 | * data out8 1734 cycles 78 calls | |
1100 | * isr 174324 cycles 617 calls (includes take) | |
1101 | * take 1241 cycles 2 calls | |
1102 | * put 1411504 cycles 6937 calls | |
1103 | * task 1655209 cycles 6937 calls (includes put) | |
1104 | * | |
1105 | */ |