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1da177e4 LT |
1 | /* |
2 | * HP i8042-based System Device Controller driver. | |
3 | * | |
4 | * Copyright (c) 2001 Brian S. Julin | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions, and the following disclaimer, | |
12 | * without modification. | |
13 | * 2. The name of the author may not be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * Alternatively, this software may be distributed under the terms of the | |
17 | * GNU General Public License ("GPL"). | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | |
20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR | |
23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
28 | * | |
29 | * References: | |
30 | * System Device Controller Microprocessor Firmware Theory of Operation | |
31 | * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2 | |
32 | * Helge Deller's original hilkbd.c port for PA-RISC. | |
33 | * | |
34 | * | |
35 | * Driver theory of operation: | |
36 | * | |
ffd51f46 HD |
37 | * hp_sdc_put does all writing to the SDC. ISR can run on a different |
38 | * CPU than hp_sdc_put, but only one CPU runs hp_sdc_put at a time | |
1da177e4 LT |
39 | * (it cannot really benefit from SMP anyway.) A tasket fit this perfectly. |
40 | * | |
ffd51f46 HD |
41 | * All data coming back from the SDC is sent via interrupt and can be read |
42 | * fully in the ISR, so there are no latency/throughput problems there. | |
43 | * The problem is with output, due to the slow clock speed of the SDC | |
44 | * compared to the CPU. This should not be too horrible most of the time, | |
45 | * but if used with HIL devices that support the multibyte transfer command, | |
46 | * keeping outbound throughput flowing at the 6500KBps that the HIL is | |
1da177e4 LT |
47 | * capable of is more than can be done at HZ=100. |
48 | * | |
ffd51f46 HD |
49 | * Busy polling for IBF clear wastes CPU cycles and bus cycles. hp_sdc.ibf |
50 | * is set to 0 when the IBF flag in the status register has cleared. ISR | |
51 | * may do this, and may also access the parts of queued transactions related | |
52 | * to reading data back from the SDC, but otherwise will not touch the | |
1da177e4 LT |
53 | * hp_sdc state. Whenever a register is written hp_sdc.ibf is set to 1. |
54 | * | |
55 | * The i8042 write index and the values in the 4-byte input buffer | |
56 | * starting at 0x70 are kept track of in hp_sdc.wi, and .r7[], respectively, | |
ffd51f46 | 57 | * to minimize the amount of IO needed to the SDC. However these values |
1da177e4 LT |
58 | * do not need to be locked since they are only ever accessed by hp_sdc_put. |
59 | * | |
60 | * A timer task schedules the tasklet once per second just to make | |
61 | * sure it doesn't freeze up and to allow for bad reads to time out. | |
62 | */ | |
63 | ||
64 | #include <linux/hp_sdc.h> | |
1da177e4 LT |
65 | #include <linux/errno.h> |
66 | #include <linux/init.h> | |
67 | #include <linux/module.h> | |
68 | #include <linux/ioport.h> | |
69 | #include <linux/time.h> | |
70 | #include <linux/slab.h> | |
71 | #include <linux/hil.h> | |
72 | #include <asm/io.h> | |
73 | #include <asm/system.h> | |
74 | ||
75 | /* Machine-specific abstraction */ | |
76 | ||
77 | #if defined(__hppa__) | |
78 | # include <asm/parisc-device.h> | |
79 | # define sdc_readb(p) gsc_readb(p) | |
80 | # define sdc_writeb(v,p) gsc_writeb((v),(p)) | |
81 | #elif defined(__mc68000__) | |
82 | # include <asm/uaccess.h> | |
83 | # define sdc_readb(p) in_8(p) | |
84 | # define sdc_writeb(v,p) out_8((p),(v)) | |
85 | #else | |
86 | # error "HIL is not supported on this platform" | |
87 | #endif | |
88 | ||
89 | #define PREFIX "HP SDC: " | |
90 | ||
91 | MODULE_AUTHOR("Brian S. Julin <bri@calyx.com>"); | |
92 | MODULE_DESCRIPTION("HP i8042-based SDC Driver"); | |
93 | MODULE_LICENSE("Dual BSD/GPL"); | |
94 | ||
95 | EXPORT_SYMBOL(hp_sdc_request_timer_irq); | |
96 | EXPORT_SYMBOL(hp_sdc_request_hil_irq); | |
97 | EXPORT_SYMBOL(hp_sdc_request_cooked_irq); | |
98 | ||
99 | EXPORT_SYMBOL(hp_sdc_release_timer_irq); | |
100 | EXPORT_SYMBOL(hp_sdc_release_hil_irq); | |
101 | EXPORT_SYMBOL(hp_sdc_release_cooked_irq); | |
102 | ||
103 | EXPORT_SYMBOL(hp_sdc_enqueue_transaction); | |
104 | EXPORT_SYMBOL(hp_sdc_dequeue_transaction); | |
105 | ||
106 | static hp_i8042_sdc hp_sdc; /* All driver state is kept in here. */ | |
107 | ||
108 | /*************** primitives for use in any context *********************/ | |
ffd51f46 HD |
109 | static inline uint8_t hp_sdc_status_in8(void) |
110 | { | |
1da177e4 LT |
111 | uint8_t status; |
112 | unsigned long flags; | |
113 | ||
114 | write_lock_irqsave(&hp_sdc.ibf_lock, flags); | |
115 | status = sdc_readb(hp_sdc.status_io); | |
ffd51f46 HD |
116 | if (!(status & HP_SDC_STATUS_IBF)) |
117 | hp_sdc.ibf = 0; | |
1da177e4 LT |
118 | write_unlock_irqrestore(&hp_sdc.ibf_lock, flags); |
119 | ||
120 | return status; | |
121 | } | |
122 | ||
ffd51f46 HD |
123 | static inline uint8_t hp_sdc_data_in8(void) |
124 | { | |
125 | return sdc_readb(hp_sdc.data_io); | |
1da177e4 LT |
126 | } |
127 | ||
ffd51f46 HD |
128 | static inline void hp_sdc_status_out8(uint8_t val) |
129 | { | |
1da177e4 LT |
130 | unsigned long flags; |
131 | ||
132 | write_lock_irqsave(&hp_sdc.ibf_lock, flags); | |
133 | hp_sdc.ibf = 1; | |
ffd51f46 HD |
134 | if ((val & 0xf0) == 0xe0) |
135 | hp_sdc.wi = 0xff; | |
1da177e4 LT |
136 | sdc_writeb(val, hp_sdc.status_io); |
137 | write_unlock_irqrestore(&hp_sdc.ibf_lock, flags); | |
138 | } | |
139 | ||
ffd51f46 HD |
140 | static inline void hp_sdc_data_out8(uint8_t val) |
141 | { | |
1da177e4 LT |
142 | unsigned long flags; |
143 | ||
144 | write_lock_irqsave(&hp_sdc.ibf_lock, flags); | |
145 | hp_sdc.ibf = 1; | |
146 | sdc_writeb(val, hp_sdc.data_io); | |
147 | write_unlock_irqrestore(&hp_sdc.ibf_lock, flags); | |
148 | } | |
149 | ||
ffd51f46 HD |
150 | /* Care must be taken to only invoke hp_sdc_spin_ibf when |
151 | * absolutely needed, or in rarely invoked subroutines. | |
152 | * Not only does it waste CPU cycles, it also wastes bus cycles. | |
1da177e4 | 153 | */ |
ffd51f46 HD |
154 | static inline void hp_sdc_spin_ibf(void) |
155 | { | |
1da177e4 LT |
156 | unsigned long flags; |
157 | rwlock_t *lock; | |
158 | ||
159 | lock = &hp_sdc.ibf_lock; | |
160 | ||
161 | read_lock_irqsave(lock, flags); | |
162 | if (!hp_sdc.ibf) { | |
163 | read_unlock_irqrestore(lock, flags); | |
164 | return; | |
165 | } | |
166 | read_unlock(lock); | |
167 | write_lock(lock); | |
ffd51f46 HD |
168 | while (sdc_readb(hp_sdc.status_io) & HP_SDC_STATUS_IBF) |
169 | { } | |
1da177e4 LT |
170 | hp_sdc.ibf = 0; |
171 | write_unlock_irqrestore(lock, flags); | |
172 | } | |
173 | ||
174 | ||
175 | /************************ Interrupt context functions ************************/ | |
ffd51f46 HD |
176 | static void hp_sdc_take(int irq, void *dev_id, uint8_t status, uint8_t data) |
177 | { | |
1da177e4 LT |
178 | hp_sdc_transaction *curr; |
179 | ||
180 | read_lock(&hp_sdc.rtq_lock); | |
181 | if (hp_sdc.rcurr < 0) { | |
ffd51f46 | 182 | read_unlock(&hp_sdc.rtq_lock); |
1da177e4 LT |
183 | return; |
184 | } | |
185 | curr = hp_sdc.tq[hp_sdc.rcurr]; | |
186 | read_unlock(&hp_sdc.rtq_lock); | |
187 | ||
188 | curr->seq[curr->idx++] = status; | |
189 | curr->seq[curr->idx++] = data; | |
190 | hp_sdc.rqty -= 2; | |
191 | do_gettimeofday(&hp_sdc.rtv); | |
192 | ||
193 | if (hp_sdc.rqty <= 0) { | |
194 | /* All data has been gathered. */ | |
ffd51f46 HD |
195 | if (curr->seq[curr->actidx] & HP_SDC_ACT_SEMAPHORE) |
196 | if (curr->act.semaphore) | |
197 | up(curr->act.semaphore); | |
198 | ||
199 | if (curr->seq[curr->actidx] & HP_SDC_ACT_CALLBACK) | |
1da177e4 LT |
200 | if (curr->act.irqhook) |
201 | curr->act.irqhook(irq, dev_id, status, data); | |
ffd51f46 | 202 | |
1da177e4 LT |
203 | curr->actidx = curr->idx; |
204 | curr->idx++; | |
205 | /* Return control of this transaction */ | |
206 | write_lock(&hp_sdc.rtq_lock); | |
ffd51f46 | 207 | hp_sdc.rcurr = -1; |
1da177e4 LT |
208 | hp_sdc.rqty = 0; |
209 | write_unlock(&hp_sdc.rtq_lock); | |
210 | tasklet_schedule(&hp_sdc.task); | |
211 | } | |
212 | } | |
213 | ||
ffd51f46 HD |
214 | static irqreturn_t hp_sdc_isr(int irq, void *dev_id) |
215 | { | |
1da177e4 LT |
216 | uint8_t status, data; |
217 | ||
218 | status = hp_sdc_status_in8(); | |
219 | /* Read data unconditionally to advance i8042. */ | |
220 | data = hp_sdc_data_in8(); | |
221 | ||
222 | /* For now we are ignoring these until we get the SDC to behave. */ | |
ffd51f46 HD |
223 | if (((status & 0xf1) == 0x51) && data == 0x82) |
224 | return IRQ_HANDLED; | |
1da177e4 | 225 | |
ffd51f46 HD |
226 | switch (status & HP_SDC_STATUS_IRQMASK) { |
227 | case 0: /* This case is not documented. */ | |
1da177e4 | 228 | break; |
ffd51f46 HD |
229 | |
230 | case HP_SDC_STATUS_USERTIMER: | |
231 | case HP_SDC_STATUS_PERIODIC: | |
232 | case HP_SDC_STATUS_TIMER: | |
1da177e4 | 233 | read_lock(&hp_sdc.hook_lock); |
ffd51f46 | 234 | if (hp_sdc.timer != NULL) |
1da177e4 LT |
235 | hp_sdc.timer(irq, dev_id, status, data); |
236 | read_unlock(&hp_sdc.hook_lock); | |
237 | break; | |
ffd51f46 HD |
238 | |
239 | case HP_SDC_STATUS_REG: | |
1da177e4 LT |
240 | hp_sdc_take(irq, dev_id, status, data); |
241 | break; | |
ffd51f46 HD |
242 | |
243 | case HP_SDC_STATUS_HILCMD: | |
244 | case HP_SDC_STATUS_HILDATA: | |
1da177e4 LT |
245 | read_lock(&hp_sdc.hook_lock); |
246 | if (hp_sdc.hil != NULL) | |
247 | hp_sdc.hil(irq, dev_id, status, data); | |
248 | read_unlock(&hp_sdc.hook_lock); | |
249 | break; | |
ffd51f46 HD |
250 | |
251 | case HP_SDC_STATUS_PUP: | |
1da177e4 LT |
252 | read_lock(&hp_sdc.hook_lock); |
253 | if (hp_sdc.pup != NULL) | |
254 | hp_sdc.pup(irq, dev_id, status, data); | |
ffd51f46 HD |
255 | else |
256 | printk(KERN_INFO PREFIX "HP SDC reports successful PUP.\n"); | |
1da177e4 LT |
257 | read_unlock(&hp_sdc.hook_lock); |
258 | break; | |
ffd51f46 HD |
259 | |
260 | default: | |
1da177e4 LT |
261 | read_lock(&hp_sdc.hook_lock); |
262 | if (hp_sdc.cooked != NULL) | |
263 | hp_sdc.cooked(irq, dev_id, status, data); | |
264 | read_unlock(&hp_sdc.hook_lock); | |
265 | break; | |
266 | } | |
ffd51f46 | 267 | |
1da177e4 LT |
268 | return IRQ_HANDLED; |
269 | } | |
270 | ||
271 | ||
ffd51f46 HD |
272 | static irqreturn_t hp_sdc_nmisr(int irq, void *dev_id) |
273 | { | |
1da177e4 | 274 | int status; |
ffd51f46 | 275 | |
1da177e4 LT |
276 | status = hp_sdc_status_in8(); |
277 | printk(KERN_WARNING PREFIX "NMI !\n"); | |
278 | ||
ffd51f46 | 279 | #if 0 |
1da177e4 LT |
280 | if (status & HP_SDC_NMISTATUS_FHS) { |
281 | read_lock(&hp_sdc.hook_lock); | |
ffd51f46 | 282 | if (hp_sdc.timer != NULL) |
1da177e4 LT |
283 | hp_sdc.timer(irq, dev_id, status, 0); |
284 | read_unlock(&hp_sdc.hook_lock); | |
ffd51f46 | 285 | } else { |
1da177e4 LT |
286 | /* TODO: pass this on to the HIL handler, or do SAK here? */ |
287 | printk(KERN_WARNING PREFIX "HIL NMI\n"); | |
288 | } | |
289 | #endif | |
ffd51f46 | 290 | |
1da177e4 LT |
291 | return IRQ_HANDLED; |
292 | } | |
293 | ||
294 | ||
295 | /***************** Kernel (tasklet) context functions ****************/ | |
296 | ||
297 | unsigned long hp_sdc_put(void); | |
298 | ||
ffd51f46 HD |
299 | static void hp_sdc_tasklet(unsigned long foo) |
300 | { | |
1da177e4 | 301 | write_lock_irq(&hp_sdc.rtq_lock); |
ffd51f46 | 302 | |
1da177e4 LT |
303 | if (hp_sdc.rcurr >= 0) { |
304 | struct timeval tv; | |
ffd51f46 | 305 | |
1da177e4 | 306 | do_gettimeofday(&tv); |
ffd51f46 HD |
307 | if (tv.tv_sec > hp_sdc.rtv.tv_sec) |
308 | tv.tv_usec += USEC_PER_SEC; | |
309 | ||
1da177e4 LT |
310 | if (tv.tv_usec - hp_sdc.rtv.tv_usec > HP_SDC_MAX_REG_DELAY) { |
311 | hp_sdc_transaction *curr; | |
312 | uint8_t tmp; | |
313 | ||
314 | curr = hp_sdc.tq[hp_sdc.rcurr]; | |
315 | /* If this turns out to be a normal failure mode | |
316 | * we'll need to figure out a way to communicate | |
317 | * it back to the application. and be less verbose. | |
318 | */ | |
319 | printk(KERN_WARNING PREFIX "read timeout (%ius)!\n", | |
320 | tv.tv_usec - hp_sdc.rtv.tv_usec); | |
321 | curr->idx += hp_sdc.rqty; | |
322 | hp_sdc.rqty = 0; | |
323 | tmp = curr->seq[curr->actidx]; | |
324 | curr->seq[curr->actidx] |= HP_SDC_ACT_DEAD; | |
ffd51f46 HD |
325 | if (tmp & HP_SDC_ACT_SEMAPHORE) |
326 | if (curr->act.semaphore) | |
1da177e4 | 327 | up(curr->act.semaphore); |
ffd51f46 HD |
328 | |
329 | if (tmp & HP_SDC_ACT_CALLBACK) { | |
1da177e4 LT |
330 | /* Note this means that irqhooks may be called |
331 | * in tasklet/bh context. | |
332 | */ | |
ffd51f46 | 333 | if (curr->act.irqhook) |
6ce6b3ae | 334 | curr->act.irqhook(0, NULL, 0, 0); |
1da177e4 | 335 | } |
ffd51f46 | 336 | |
1da177e4 LT |
337 | curr->actidx = curr->idx; |
338 | curr->idx++; | |
ffd51f46 | 339 | hp_sdc.rcurr = -1; |
1da177e4 LT |
340 | } |
341 | } | |
342 | write_unlock_irq(&hp_sdc.rtq_lock); | |
343 | hp_sdc_put(); | |
344 | } | |
345 | ||
ffd51f46 HD |
346 | unsigned long hp_sdc_put(void) |
347 | { | |
1da177e4 LT |
348 | hp_sdc_transaction *curr; |
349 | uint8_t act; | |
350 | int idx, curridx; | |
351 | ||
352 | int limit = 0; | |
353 | ||
354 | write_lock(&hp_sdc.lock); | |
355 | ||
356 | /* If i8042 buffers are full, we cannot do anything that | |
357 | requires output, so we skip to the administrativa. */ | |
358 | if (hp_sdc.ibf) { | |
359 | hp_sdc_status_in8(); | |
ffd51f46 HD |
360 | if (hp_sdc.ibf) |
361 | goto finish; | |
1da177e4 LT |
362 | } |
363 | ||
364 | anew: | |
365 | /* See if we are in the middle of a sequence. */ | |
ffd51f46 HD |
366 | if (hp_sdc.wcurr < 0) |
367 | hp_sdc.wcurr = 0; | |
1da177e4 | 368 | read_lock_irq(&hp_sdc.rtq_lock); |
ffd51f46 HD |
369 | if (hp_sdc.rcurr == hp_sdc.wcurr) |
370 | hp_sdc.wcurr++; | |
1da177e4 | 371 | read_unlock_irq(&hp_sdc.rtq_lock); |
ffd51f46 HD |
372 | if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN) |
373 | hp_sdc.wcurr = 0; | |
1da177e4 LT |
374 | curridx = hp_sdc.wcurr; |
375 | ||
ffd51f46 HD |
376 | if (hp_sdc.tq[curridx] != NULL) |
377 | goto start; | |
1da177e4 LT |
378 | |
379 | while (++curridx != hp_sdc.wcurr) { | |
380 | if (curridx >= HP_SDC_QUEUE_LEN) { | |
381 | curridx = -1; /* Wrap to top */ | |
382 | continue; | |
383 | } | |
384 | read_lock_irq(&hp_sdc.rtq_lock); | |
385 | if (hp_sdc.rcurr == curridx) { | |
386 | read_unlock_irq(&hp_sdc.rtq_lock); | |
387 | continue; | |
388 | } | |
389 | read_unlock_irq(&hp_sdc.rtq_lock); | |
ffd51f46 HD |
390 | if (hp_sdc.tq[curridx] != NULL) |
391 | break; /* Found one. */ | |
1da177e4 LT |
392 | } |
393 | if (curridx == hp_sdc.wcurr) { /* There's nothing queued to do. */ | |
394 | curridx = -1; | |
395 | } | |
396 | hp_sdc.wcurr = curridx; | |
397 | ||
398 | start: | |
399 | ||
400 | /* Check to see if the interrupt mask needs to be set. */ | |
401 | if (hp_sdc.set_im) { | |
402 | hp_sdc_status_out8(hp_sdc.im | HP_SDC_CMD_SET_IM); | |
403 | hp_sdc.set_im = 0; | |
404 | goto finish; | |
405 | } | |
406 | ||
ffd51f46 HD |
407 | if (hp_sdc.wcurr == -1) |
408 | goto done; | |
1da177e4 LT |
409 | |
410 | curr = hp_sdc.tq[curridx]; | |
411 | idx = curr->actidx; | |
412 | ||
413 | if (curr->actidx >= curr->endidx) { | |
414 | hp_sdc.tq[curridx] = NULL; | |
415 | /* Interleave outbound data between the transactions. */ | |
416 | hp_sdc.wcurr++; | |
ffd51f46 HD |
417 | if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN) |
418 | hp_sdc.wcurr = 0; | |
419 | goto finish; | |
1da177e4 LT |
420 | } |
421 | ||
422 | act = curr->seq[idx]; | |
423 | idx++; | |
424 | ||
425 | if (curr->idx >= curr->endidx) { | |
ffd51f46 HD |
426 | if (act & HP_SDC_ACT_DEALLOC) |
427 | kfree(curr); | |
1da177e4 LT |
428 | hp_sdc.tq[curridx] = NULL; |
429 | /* Interleave outbound data between the transactions. */ | |
430 | hp_sdc.wcurr++; | |
ffd51f46 HD |
431 | if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN) |
432 | hp_sdc.wcurr = 0; | |
433 | goto finish; | |
1da177e4 LT |
434 | } |
435 | ||
436 | while (act & HP_SDC_ACT_PRECMD) { | |
437 | if (curr->idx != idx) { | |
438 | idx++; | |
439 | act &= ~HP_SDC_ACT_PRECMD; | |
440 | break; | |
441 | } | |
442 | hp_sdc_status_out8(curr->seq[idx]); | |
443 | curr->idx++; | |
444 | /* act finished? */ | |
445 | if ((act & HP_SDC_ACT_DURING) == HP_SDC_ACT_PRECMD) | |
ffd51f46 | 446 | goto actdone; |
1da177e4 | 447 | /* skip quantity field if data-out sequence follows. */ |
ffd51f46 HD |
448 | if (act & HP_SDC_ACT_DATAOUT) |
449 | curr->idx++; | |
1da177e4 LT |
450 | goto finish; |
451 | } | |
452 | if (act & HP_SDC_ACT_DATAOUT) { | |
453 | int qty; | |
454 | ||
455 | qty = curr->seq[idx]; | |
456 | idx++; | |
457 | if (curr->idx - idx < qty) { | |
458 | hp_sdc_data_out8(curr->seq[curr->idx]); | |
459 | curr->idx++; | |
460 | /* act finished? */ | |
ffd51f46 HD |
461 | if (curr->idx - idx >= qty && |
462 | (act & HP_SDC_ACT_DURING) == HP_SDC_ACT_DATAOUT) | |
1da177e4 LT |
463 | goto actdone; |
464 | goto finish; | |
465 | } | |
466 | idx += qty; | |
467 | act &= ~HP_SDC_ACT_DATAOUT; | |
ffd51f46 HD |
468 | } else |
469 | while (act & HP_SDC_ACT_DATAREG) { | |
1da177e4 LT |
470 | int mask; |
471 | uint8_t w7[4]; | |
472 | ||
473 | mask = curr->seq[idx]; | |
474 | if (idx != curr->idx) { | |
475 | idx++; | |
476 | idx += !!(mask & 1); | |
477 | idx += !!(mask & 2); | |
478 | idx += !!(mask & 4); | |
479 | idx += !!(mask & 8); | |
480 | act &= ~HP_SDC_ACT_DATAREG; | |
481 | break; | |
482 | } | |
ffd51f46 | 483 | |
1da177e4 LT |
484 | w7[0] = (mask & 1) ? curr->seq[++idx] : hp_sdc.r7[0]; |
485 | w7[1] = (mask & 2) ? curr->seq[++idx] : hp_sdc.r7[1]; | |
486 | w7[2] = (mask & 4) ? curr->seq[++idx] : hp_sdc.r7[2]; | |
487 | w7[3] = (mask & 8) ? curr->seq[++idx] : hp_sdc.r7[3]; | |
ffd51f46 | 488 | |
1da177e4 | 489 | if (hp_sdc.wi > 0x73 || hp_sdc.wi < 0x70 || |
ffd51f46 | 490 | w7[hp_sdc.wi - 0x70] == hp_sdc.r7[hp_sdc.wi - 0x70]) { |
1da177e4 LT |
491 | int i = 0; |
492 | ||
ffd51f46 HD |
493 | /* Need to point the write index register */ |
494 | while (i < 4 && w7[i] == hp_sdc.r7[i]) | |
495 | i++; | |
496 | ||
1da177e4 LT |
497 | if (i < 4) { |
498 | hp_sdc_status_out8(HP_SDC_CMD_SET_D0 + i); | |
499 | hp_sdc.wi = 0x70 + i; | |
500 | goto finish; | |
501 | } | |
ffd51f46 | 502 | |
1da177e4 LT |
503 | idx++; |
504 | if ((act & HP_SDC_ACT_DURING) == HP_SDC_ACT_DATAREG) | |
505 | goto actdone; | |
ffd51f46 | 506 | |
1da177e4 LT |
507 | curr->idx = idx; |
508 | act &= ~HP_SDC_ACT_DATAREG; | |
509 | break; | |
510 | } | |
511 | ||
512 | hp_sdc_data_out8(w7[hp_sdc.wi - 0x70]); | |
513 | hp_sdc.r7[hp_sdc.wi - 0x70] = w7[hp_sdc.wi - 0x70]; | |
514 | hp_sdc.wi++; /* write index register autoincrements */ | |
515 | { | |
516 | int i = 0; | |
517 | ||
ffd51f46 HD |
518 | while ((i < 4) && w7[i] == hp_sdc.r7[i]) |
519 | i++; | |
1da177e4 LT |
520 | if (i >= 4) { |
521 | curr->idx = idx + 1; | |
ffd51f46 | 522 | if ((act & HP_SDC_ACT_DURING) == |
1da177e4 | 523 | HP_SDC_ACT_DATAREG) |
ffd51f46 | 524 | goto actdone; |
1da177e4 LT |
525 | } |
526 | } | |
527 | goto finish; | |
528 | } | |
529 | /* We don't go any further in the command if there is a pending read, | |
530 | because we don't want interleaved results. */ | |
531 | read_lock_irq(&hp_sdc.rtq_lock); | |
532 | if (hp_sdc.rcurr >= 0) { | |
533 | read_unlock_irq(&hp_sdc.rtq_lock); | |
534 | goto finish; | |
535 | } | |
536 | read_unlock_irq(&hp_sdc.rtq_lock); | |
537 | ||
538 | ||
539 | if (act & HP_SDC_ACT_POSTCMD) { | |
ffd51f46 | 540 | uint8_t postcmd; |
1da177e4 LT |
541 | |
542 | /* curr->idx should == idx at this point. */ | |
543 | postcmd = curr->seq[idx]; | |
544 | curr->idx++; | |
545 | if (act & HP_SDC_ACT_DATAIN) { | |
546 | ||
547 | /* Start a new read */ | |
ffd51f46 | 548 | hp_sdc.rqty = curr->seq[curr->idx]; |
1da177e4 LT |
549 | do_gettimeofday(&hp_sdc.rtv); |
550 | curr->idx++; | |
551 | /* Still need to lock here in case of spurious irq. */ | |
552 | write_lock_irq(&hp_sdc.rtq_lock); | |
ffd51f46 | 553 | hp_sdc.rcurr = curridx; |
1da177e4 LT |
554 | write_unlock_irq(&hp_sdc.rtq_lock); |
555 | hp_sdc_status_out8(postcmd); | |
556 | goto finish; | |
557 | } | |
558 | hp_sdc_status_out8(postcmd); | |
559 | goto actdone; | |
560 | } | |
561 | ||
ffd51f46 HD |
562 | actdone: |
563 | if (act & HP_SDC_ACT_SEMAPHORE) | |
1da177e4 | 564 | up(curr->act.semaphore); |
ffd51f46 | 565 | else if (act & HP_SDC_ACT_CALLBACK) |
6ce6b3ae | 566 | curr->act.irqhook(0,NULL,0,0); |
ffd51f46 | 567 | |
1da177e4 | 568 | if (curr->idx >= curr->endidx) { /* This transaction is over. */ |
ffd51f46 HD |
569 | if (act & HP_SDC_ACT_DEALLOC) |
570 | kfree(curr); | |
1da177e4 | 571 | hp_sdc.tq[curridx] = NULL; |
ffd51f46 | 572 | } else { |
1da177e4 LT |
573 | curr->actidx = idx + 1; |
574 | curr->idx = idx + 2; | |
575 | } | |
576 | /* Interleave outbound data between the transactions. */ | |
577 | hp_sdc.wcurr++; | |
ffd51f46 HD |
578 | if (hp_sdc.wcurr >= HP_SDC_QUEUE_LEN) |
579 | hp_sdc.wcurr = 0; | |
1da177e4 LT |
580 | |
581 | finish: | |
ffd51f46 | 582 | /* If by some quirk IBF has cleared and our ISR has run to |
1da177e4 | 583 | see that that has happened, do it all again. */ |
ffd51f46 HD |
584 | if (!hp_sdc.ibf && limit++ < 20) |
585 | goto anew; | |
1da177e4 LT |
586 | |
587 | done: | |
ffd51f46 HD |
588 | if (hp_sdc.wcurr >= 0) |
589 | tasklet_schedule(&hp_sdc.task); | |
1da177e4 | 590 | write_unlock(&hp_sdc.lock); |
ffd51f46 | 591 | |
1da177e4 LT |
592 | return 0; |
593 | } | |
594 | ||
595 | /******* Functions called in either user or kernel context ****/ | |
ffd51f46 HD |
596 | int hp_sdc_enqueue_transaction(hp_sdc_transaction *this) |
597 | { | |
1da177e4 LT |
598 | unsigned long flags; |
599 | int i; | |
600 | ||
601 | if (this == NULL) { | |
602 | tasklet_schedule(&hp_sdc.task); | |
603 | return -EINVAL; | |
ffd51f46 | 604 | } |
1da177e4 LT |
605 | |
606 | write_lock_irqsave(&hp_sdc.lock, flags); | |
607 | ||
608 | /* Can't have same transaction on queue twice */ | |
ffd51f46 HD |
609 | for (i = 0; i < HP_SDC_QUEUE_LEN; i++) |
610 | if (hp_sdc.tq[i] == this) | |
611 | goto fail; | |
1da177e4 LT |
612 | |
613 | this->actidx = 0; | |
614 | this->idx = 1; | |
615 | ||
616 | /* Search for empty slot */ | |
ffd51f46 | 617 | for (i = 0; i < HP_SDC_QUEUE_LEN; i++) |
1da177e4 LT |
618 | if (hp_sdc.tq[i] == NULL) { |
619 | hp_sdc.tq[i] = this; | |
620 | write_unlock_irqrestore(&hp_sdc.lock, flags); | |
621 | tasklet_schedule(&hp_sdc.task); | |
622 | return 0; | |
623 | } | |
ffd51f46 | 624 | |
1da177e4 LT |
625 | write_unlock_irqrestore(&hp_sdc.lock, flags); |
626 | printk(KERN_WARNING PREFIX "No free slot to add transaction.\n"); | |
627 | return -EBUSY; | |
628 | ||
629 | fail: | |
630 | write_unlock_irqrestore(&hp_sdc.lock,flags); | |
631 | printk(KERN_WARNING PREFIX "Transaction add failed: transaction already queued?\n"); | |
632 | return -EINVAL; | |
633 | } | |
634 | ||
ffd51f46 HD |
635 | int hp_sdc_dequeue_transaction(hp_sdc_transaction *this) |
636 | { | |
1da177e4 LT |
637 | unsigned long flags; |
638 | int i; | |
639 | ||
640 | write_lock_irqsave(&hp_sdc.lock, flags); | |
641 | ||
642 | /* TODO: don't remove it if it's not done. */ | |
643 | ||
ffd51f46 HD |
644 | for (i = 0; i < HP_SDC_QUEUE_LEN; i++) |
645 | if (hp_sdc.tq[i] == this) | |
646 | hp_sdc.tq[i] = NULL; | |
1da177e4 LT |
647 | |
648 | write_unlock_irqrestore(&hp_sdc.lock, flags); | |
649 | return 0; | |
650 | } | |
651 | ||
652 | ||
653 | ||
654 | /********************** User context functions **************************/ | |
ffd51f46 HD |
655 | int hp_sdc_request_timer_irq(hp_sdc_irqhook *callback) |
656 | { | |
657 | if (callback == NULL || hp_sdc.dev == NULL) | |
1da177e4 | 658 | return -EINVAL; |
ffd51f46 | 659 | |
1da177e4 LT |
660 | write_lock_irq(&hp_sdc.hook_lock); |
661 | if (hp_sdc.timer != NULL) { | |
662 | write_unlock_irq(&hp_sdc.hook_lock); | |
663 | return -EBUSY; | |
664 | } | |
665 | ||
666 | hp_sdc.timer = callback; | |
667 | /* Enable interrupts from the timers */ | |
668 | hp_sdc.im &= ~HP_SDC_IM_FH; | |
669 | hp_sdc.im &= ~HP_SDC_IM_PT; | |
670 | hp_sdc.im &= ~HP_SDC_IM_TIMERS; | |
671 | hp_sdc.set_im = 1; | |
672 | write_unlock_irq(&hp_sdc.hook_lock); | |
673 | ||
674 | tasklet_schedule(&hp_sdc.task); | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
ffd51f46 HD |
679 | int hp_sdc_request_hil_irq(hp_sdc_irqhook *callback) |
680 | { | |
681 | if (callback == NULL || hp_sdc.dev == NULL) | |
1da177e4 | 682 | return -EINVAL; |
ffd51f46 | 683 | |
1da177e4 LT |
684 | write_lock_irq(&hp_sdc.hook_lock); |
685 | if (hp_sdc.hil != NULL) { | |
686 | write_unlock_irq(&hp_sdc.hook_lock); | |
687 | return -EBUSY; | |
688 | } | |
689 | ||
690 | hp_sdc.hil = callback; | |
691 | hp_sdc.im &= ~(HP_SDC_IM_HIL | HP_SDC_IM_RESET); | |
692 | hp_sdc.set_im = 1; | |
693 | write_unlock_irq(&hp_sdc.hook_lock); | |
694 | ||
695 | tasklet_schedule(&hp_sdc.task); | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
ffd51f46 HD |
700 | int hp_sdc_request_cooked_irq(hp_sdc_irqhook *callback) |
701 | { | |
702 | if (callback == NULL || hp_sdc.dev == NULL) | |
1da177e4 | 703 | return -EINVAL; |
ffd51f46 | 704 | |
1da177e4 LT |
705 | write_lock_irq(&hp_sdc.hook_lock); |
706 | if (hp_sdc.cooked != NULL) { | |
707 | write_unlock_irq(&hp_sdc.hook_lock); | |
708 | return -EBUSY; | |
709 | } | |
710 | ||
711 | /* Enable interrupts from the HIL MLC */ | |
712 | hp_sdc.cooked = callback; | |
713 | hp_sdc.im &= ~(HP_SDC_IM_HIL | HP_SDC_IM_RESET); | |
714 | hp_sdc.set_im = 1; | |
715 | write_unlock_irq(&hp_sdc.hook_lock); | |
716 | ||
717 | tasklet_schedule(&hp_sdc.task); | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
ffd51f46 HD |
722 | int hp_sdc_release_timer_irq(hp_sdc_irqhook *callback) |
723 | { | |
1da177e4 LT |
724 | write_lock_irq(&hp_sdc.hook_lock); |
725 | if ((callback != hp_sdc.timer) || | |
726 | (hp_sdc.timer == NULL)) { | |
727 | write_unlock_irq(&hp_sdc.hook_lock); | |
728 | return -EINVAL; | |
729 | } | |
730 | ||
731 | /* Disable interrupts from the timers */ | |
732 | hp_sdc.timer = NULL; | |
733 | hp_sdc.im |= HP_SDC_IM_TIMERS; | |
734 | hp_sdc.im |= HP_SDC_IM_FH; | |
735 | hp_sdc.im |= HP_SDC_IM_PT; | |
736 | hp_sdc.set_im = 1; | |
737 | write_unlock_irq(&hp_sdc.hook_lock); | |
738 | tasklet_schedule(&hp_sdc.task); | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
ffd51f46 HD |
743 | int hp_sdc_release_hil_irq(hp_sdc_irqhook *callback) |
744 | { | |
1da177e4 LT |
745 | write_lock_irq(&hp_sdc.hook_lock); |
746 | if ((callback != hp_sdc.hil) || | |
747 | (hp_sdc.hil == NULL)) { | |
748 | write_unlock_irq(&hp_sdc.hook_lock); | |
749 | return -EINVAL; | |
750 | } | |
751 | ||
752 | hp_sdc.hil = NULL; | |
753 | /* Disable interrupts from HIL only if there is no cooked driver. */ | |
754 | if(hp_sdc.cooked == NULL) { | |
755 | hp_sdc.im |= (HP_SDC_IM_HIL | HP_SDC_IM_RESET); | |
756 | hp_sdc.set_im = 1; | |
757 | } | |
758 | write_unlock_irq(&hp_sdc.hook_lock); | |
759 | tasklet_schedule(&hp_sdc.task); | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
ffd51f46 HD |
764 | int hp_sdc_release_cooked_irq(hp_sdc_irqhook *callback) |
765 | { | |
1da177e4 LT |
766 | write_lock_irq(&hp_sdc.hook_lock); |
767 | if ((callback != hp_sdc.cooked) || | |
768 | (hp_sdc.cooked == NULL)) { | |
769 | write_unlock_irq(&hp_sdc.hook_lock); | |
770 | return -EINVAL; | |
771 | } | |
772 | ||
773 | hp_sdc.cooked = NULL; | |
774 | /* Disable interrupts from HIL only if there is no raw HIL driver. */ | |
775 | if(hp_sdc.hil == NULL) { | |
776 | hp_sdc.im |= (HP_SDC_IM_HIL | HP_SDC_IM_RESET); | |
777 | hp_sdc.set_im = 1; | |
778 | } | |
779 | write_unlock_irq(&hp_sdc.hook_lock); | |
780 | tasklet_schedule(&hp_sdc.task); | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
785 | /************************* Keepalive timer task *********************/ | |
786 | ||
ffd51f46 HD |
787 | void hp_sdc_kicker (unsigned long data) |
788 | { | |
1da177e4 LT |
789 | tasklet_schedule(&hp_sdc.task); |
790 | /* Re-insert the periodic task. */ | |
791 | mod_timer(&hp_sdc.kicker, jiffies + HZ); | |
792 | } | |
793 | ||
794 | /************************** Module Initialization ***************************/ | |
795 | ||
796 | #if defined(__hppa__) | |
797 | ||
3acaf540 | 798 | static const struct parisc_device_id hp_sdc_tbl[] = { |
1da177e4 | 799 | { |
ffd51f46 | 800 | .hw_type = HPHW_FIO, |
1da177e4 LT |
801 | .hversion_rev = HVERSION_REV_ANY_ID, |
802 | .hversion = HVERSION_ANY_ID, | |
ffd51f46 | 803 | .sversion = 0x73, |
1da177e4 LT |
804 | }, |
805 | { 0, } | |
806 | }; | |
807 | ||
808 | MODULE_DEVICE_TABLE(parisc, hp_sdc_tbl); | |
809 | ||
810 | static int __init hp_sdc_init_hppa(struct parisc_device *d); | |
811 | ||
812 | static struct parisc_driver hp_sdc_driver = { | |
bdad1f83 | 813 | .name = "hp_sdc", |
1da177e4 LT |
814 | .id_table = hp_sdc_tbl, |
815 | .probe = hp_sdc_init_hppa, | |
816 | }; | |
817 | ||
818 | #endif /* __hppa__ */ | |
819 | ||
820 | static int __init hp_sdc_init(void) | |
821 | { | |
1da177e4 LT |
822 | char *errstr; |
823 | hp_sdc_transaction t_sync; | |
824 | uint8_t ts_sync[6]; | |
825 | struct semaphore s_sync; | |
826 | ||
ffd51f46 HD |
827 | rwlock_init(&hp_sdc.lock); |
828 | rwlock_init(&hp_sdc.ibf_lock); | |
829 | rwlock_init(&hp_sdc.rtq_lock); | |
830 | rwlock_init(&hp_sdc.hook_lock); | |
1da177e4 LT |
831 | |
832 | hp_sdc.timer = NULL; | |
833 | hp_sdc.hil = NULL; | |
834 | hp_sdc.pup = NULL; | |
835 | hp_sdc.cooked = NULL; | |
836 | hp_sdc.im = HP_SDC_IM_MASK; /* Mask maskable irqs */ | |
837 | hp_sdc.set_im = 1; | |
838 | hp_sdc.wi = 0xff; | |
839 | hp_sdc.r7[0] = 0xff; | |
840 | hp_sdc.r7[1] = 0xff; | |
841 | hp_sdc.r7[2] = 0xff; | |
842 | hp_sdc.r7[3] = 0xff; | |
843 | hp_sdc.ibf = 1; | |
844 | ||
ffd51f46 HD |
845 | memset(&hp_sdc.tq, 0, sizeof(hp_sdc.tq)); |
846 | ||
1da177e4 LT |
847 | hp_sdc.wcurr = -1; |
848 | hp_sdc.rcurr = -1; | |
849 | hp_sdc.rqty = 0; | |
850 | ||
851 | hp_sdc.dev_err = -ENODEV; | |
852 | ||
853 | errstr = "IO not found for"; | |
ffd51f46 HD |
854 | if (!hp_sdc.base_io) |
855 | goto err0; | |
1da177e4 LT |
856 | |
857 | errstr = "IRQ not found for"; | |
ffd51f46 HD |
858 | if (!hp_sdc.irq) |
859 | goto err0; | |
1da177e4 LT |
860 | |
861 | hp_sdc.dev_err = -EBUSY; | |
862 | ||
863 | #if defined(__hppa__) | |
864 | errstr = "IO not available for"; | |
ffd51f46 HD |
865 | if (request_region(hp_sdc.data_io, 2, hp_sdc_driver.name)) |
866 | goto err0; | |
867 | #endif | |
1da177e4 LT |
868 | |
869 | errstr = "IRQ not available for"; | |
3acaf540 | 870 | if (request_irq(hp_sdc.irq, &hp_sdc_isr, IRQF_SHARED|IRQF_SAMPLE_RANDOM, |
ffd51f46 HD |
871 | "HP SDC", &hp_sdc)) |
872 | goto err1; | |
1da177e4 LT |
873 | |
874 | errstr = "NMI not available for"; | |
3acaf540 | 875 | if (request_irq(hp_sdc.nmi, &hp_sdc_nmisr, IRQF_SHARED, |
ffd51f46 HD |
876 | "HP SDC NMI", &hp_sdc)) |
877 | goto err2; | |
1da177e4 | 878 | |
ffd51f46 | 879 | printk(KERN_INFO PREFIX "HP SDC at 0x%p, IRQ %d (NMI IRQ %d)\n", |
1da177e4 LT |
880 | (void *)hp_sdc.base_io, hp_sdc.irq, hp_sdc.nmi); |
881 | ||
882 | hp_sdc_status_in8(); | |
883 | hp_sdc_data_in8(); | |
884 | ||
885 | tasklet_init(&hp_sdc.task, hp_sdc_tasklet, 0); | |
886 | ||
887 | /* Sync the output buffer registers, thus scheduling hp_sdc_tasklet. */ | |
888 | t_sync.actidx = 0; | |
889 | t_sync.idx = 1; | |
890 | t_sync.endidx = 6; | |
891 | t_sync.seq = ts_sync; | |
892 | ts_sync[0] = HP_SDC_ACT_DATAREG | HP_SDC_ACT_SEMAPHORE; | |
893 | ts_sync[1] = 0x0f; | |
894 | ts_sync[2] = ts_sync[3] = ts_sync[4] = ts_sync[5] = 0; | |
895 | t_sync.act.semaphore = &s_sync; | |
896 | init_MUTEX_LOCKED(&s_sync); | |
897 | hp_sdc_enqueue_transaction(&t_sync); | |
898 | down(&s_sync); /* Wait for t_sync to complete */ | |
899 | ||
900 | /* Create the keepalive task */ | |
901 | init_timer(&hp_sdc.kicker); | |
902 | hp_sdc.kicker.expires = jiffies + HZ; | |
903 | hp_sdc.kicker.function = &hp_sdc_kicker; | |
904 | add_timer(&hp_sdc.kicker); | |
905 | ||
906 | hp_sdc.dev_err = 0; | |
907 | return 0; | |
908 | err2: | |
3acaf540 | 909 | free_irq(hp_sdc.irq, &hp_sdc); |
1da177e4 LT |
910 | err1: |
911 | release_region(hp_sdc.data_io, 2); | |
912 | err0: | |
ffd51f46 | 913 | printk(KERN_WARNING PREFIX ": %s SDC IO=0x%p IRQ=0x%x NMI=0x%x\n", |
1da177e4 LT |
914 | errstr, (void *)hp_sdc.base_io, hp_sdc.irq, hp_sdc.nmi); |
915 | hp_sdc.dev = NULL; | |
ffd51f46 | 916 | |
1da177e4 LT |
917 | return hp_sdc.dev_err; |
918 | } | |
919 | ||
920 | #if defined(__hppa__) | |
921 | ||
922 | static int __init hp_sdc_init_hppa(struct parisc_device *d) | |
923 | { | |
ffd51f46 HD |
924 | if (!d) |
925 | return 1; | |
926 | if (hp_sdc.dev != NULL) | |
927 | return 1; /* We only expect one SDC */ | |
1da177e4 LT |
928 | |
929 | hp_sdc.dev = d; | |
930 | hp_sdc.irq = d->irq; | |
931 | hp_sdc.nmi = d->aux_irq; | |
53f01bba MW |
932 | hp_sdc.base_io = d->hpa.start; |
933 | hp_sdc.data_io = d->hpa.start + 0x800; | |
934 | hp_sdc.status_io = d->hpa.start + 0x801; | |
1da177e4 LT |
935 | |
936 | return hp_sdc_init(); | |
937 | } | |
938 | ||
939 | #endif /* __hppa__ */ | |
940 | ||
941 | #if !defined(__mc68000__) /* Link error on m68k! */ | |
942 | static void __exit hp_sdc_exit(void) | |
943 | #else | |
944 | static void hp_sdc_exit(void) | |
945 | #endif | |
946 | { | |
947 | write_lock_irq(&hp_sdc.lock); | |
948 | ||
949 | /* Turn off all maskable "sub-function" irq's. */ | |
950 | hp_sdc_spin_ibf(); | |
951 | sdc_writeb(HP_SDC_CMD_SET_IM | HP_SDC_IM_MASK, hp_sdc.status_io); | |
952 | ||
953 | /* Wait until we know this has been processed by the i8042 */ | |
954 | hp_sdc_spin_ibf(); | |
955 | ||
3acaf540 HD |
956 | free_irq(hp_sdc.nmi, &hp_sdc); |
957 | free_irq(hp_sdc.irq, &hp_sdc); | |
1da177e4 LT |
958 | write_unlock_irq(&hp_sdc.lock); |
959 | ||
960 | del_timer(&hp_sdc.kicker); | |
961 | ||
962 | tasklet_kill(&hp_sdc.task); | |
963 | ||
1da177e4 | 964 | #if defined(__hppa__) |
ffd51f46 | 965 | if (unregister_parisc_driver(&hp_sdc_driver)) |
1da177e4 LT |
966 | printk(KERN_WARNING PREFIX "Error unregistering HP SDC"); |
967 | #endif | |
968 | } | |
969 | ||
970 | static int __init hp_sdc_register(void) | |
971 | { | |
972 | hp_sdc_transaction tq_init; | |
973 | uint8_t tq_init_seq[5]; | |
974 | struct semaphore tq_init_sem; | |
975 | #if defined(__mc68000__) | |
976 | mm_segment_t fs; | |
977 | unsigned char i; | |
978 | #endif | |
ffd51f46 | 979 | |
1da177e4 LT |
980 | hp_sdc.dev = NULL; |
981 | hp_sdc.dev_err = 0; | |
982 | #if defined(__hppa__) | |
983 | if (register_parisc_driver(&hp_sdc_driver)) { | |
984 | printk(KERN_WARNING PREFIX "Error registering SDC with system bus tree.\n"); | |
985 | return -ENODEV; | |
986 | } | |
987 | #elif defined(__mc68000__) | |
988 | if (!MACH_IS_HP300) | |
989 | return -ENODEV; | |
990 | ||
991 | hp_sdc.irq = 1; | |
992 | hp_sdc.nmi = 7; | |
993 | hp_sdc.base_io = (unsigned long) 0xf0428000; | |
994 | hp_sdc.data_io = (unsigned long) hp_sdc.base_io + 1; | |
995 | hp_sdc.status_io = (unsigned long) hp_sdc.base_io + 3; | |
996 | fs = get_fs(); | |
997 | set_fs(KERNEL_DS); | |
998 | if (!get_user(i, (unsigned char *)hp_sdc.data_io)) | |
999 | hp_sdc.dev = (void *)1; | |
1000 | set_fs(fs); | |
1001 | hp_sdc.dev_err = hp_sdc_init(); | |
1002 | #endif | |
1003 | if (hp_sdc.dev == NULL) { | |
1004 | printk(KERN_WARNING PREFIX "No SDC found.\n"); | |
1005 | return hp_sdc.dev_err; | |
1006 | } | |
1007 | ||
1008 | init_MUTEX_LOCKED(&tq_init_sem); | |
1009 | ||
1010 | tq_init.actidx = 0; | |
1011 | tq_init.idx = 1; | |
1012 | tq_init.endidx = 5; | |
1013 | tq_init.seq = tq_init_seq; | |
1014 | tq_init.act.semaphore = &tq_init_sem; | |
1015 | ||
ffd51f46 HD |
1016 | tq_init_seq[0] = |
1017 | HP_SDC_ACT_POSTCMD | HP_SDC_ACT_DATAIN | HP_SDC_ACT_SEMAPHORE; | |
1da177e4 LT |
1018 | tq_init_seq[1] = HP_SDC_CMD_READ_KCC; |
1019 | tq_init_seq[2] = 1; | |
1020 | tq_init_seq[3] = 0; | |
1021 | tq_init_seq[4] = 0; | |
1022 | ||
1023 | hp_sdc_enqueue_transaction(&tq_init); | |
1024 | ||
1025 | down(&tq_init_sem); | |
1026 | up(&tq_init_sem); | |
1027 | ||
1028 | if ((tq_init_seq[0] & HP_SDC_ACT_DEAD) == HP_SDC_ACT_DEAD) { | |
1029 | printk(KERN_WARNING PREFIX "Error reading config byte.\n"); | |
1030 | hp_sdc_exit(); | |
1031 | return -ENODEV; | |
1032 | } | |
1033 | hp_sdc.r11 = tq_init_seq[4]; | |
1034 | if (hp_sdc.r11 & HP_SDC_CFG_NEW) { | |
ffd51f46 | 1035 | const char *str; |
1da177e4 LT |
1036 | printk(KERN_INFO PREFIX "New style SDC\n"); |
1037 | tq_init_seq[1] = HP_SDC_CMD_READ_XTD; | |
1038 | tq_init.actidx = 0; | |
1039 | tq_init.idx = 1; | |
1040 | down(&tq_init_sem); | |
ffd51f46 | 1041 | hp_sdc_enqueue_transaction(&tq_init); |
1da177e4 LT |
1042 | down(&tq_init_sem); |
1043 | up(&tq_init_sem); | |
1044 | if ((tq_init_seq[0] & HP_SDC_ACT_DEAD) == HP_SDC_ACT_DEAD) { | |
1045 | printk(KERN_WARNING PREFIX "Error reading extended config byte.\n"); | |
1046 | return -ENODEV; | |
1047 | } | |
1048 | hp_sdc.r7e = tq_init_seq[4]; | |
1049 | HP_SDC_XTD_REV_STRINGS(hp_sdc.r7e & HP_SDC_XTD_REV, str) | |
1050 | printk(KERN_INFO PREFIX "Revision: %s\n", str); | |
ffd51f46 | 1051 | if (hp_sdc.r7e & HP_SDC_XTD_BEEPER) |
1da177e4 | 1052 | printk(KERN_INFO PREFIX "TI SN76494 beeper present\n"); |
ffd51f46 | 1053 | if (hp_sdc.r7e & HP_SDC_XTD_BBRTC) |
1da177e4 | 1054 | printk(KERN_INFO PREFIX "OKI MSM-58321 BBRTC present\n"); |
1da177e4 LT |
1055 | printk(KERN_INFO PREFIX "Spunking the self test register to force PUP " |
1056 | "on next firmware reset.\n"); | |
ffd51f46 | 1057 | tq_init_seq[0] = HP_SDC_ACT_PRECMD | |
1da177e4 LT |
1058 | HP_SDC_ACT_DATAOUT | HP_SDC_ACT_SEMAPHORE; |
1059 | tq_init_seq[1] = HP_SDC_CMD_SET_STR; | |
1060 | tq_init_seq[2] = 1; | |
1061 | tq_init_seq[3] = 0; | |
1062 | tq_init.actidx = 0; | |
1063 | tq_init.idx = 1; | |
1064 | tq_init.endidx = 4; | |
1065 | down(&tq_init_sem); | |
ffd51f46 | 1066 | hp_sdc_enqueue_transaction(&tq_init); |
1da177e4 LT |
1067 | down(&tq_init_sem); |
1068 | up(&tq_init_sem); | |
ffd51f46 HD |
1069 | } else |
1070 | printk(KERN_INFO PREFIX "Old style SDC (1820-%s).\n", | |
1da177e4 | 1071 | (hp_sdc.r11 & HP_SDC_CFG_REV) ? "3300" : "2564/3087"); |
1da177e4 LT |
1072 | |
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | module_init(hp_sdc_register); | |
1077 | module_exit(hp_sdc_exit); | |
1078 | ||
ffd51f46 | 1079 | /* Timing notes: These measurements taken on my 64MHz 7100-LC (715/64) |
1da177e4 LT |
1080 | * cycles cycles-adj time |
1081 | * between two consecutive mfctl(16)'s: 4 n/a 63ns | |
1082 | * hp_sdc_spin_ibf when idle: 119 115 1.7us | |
1083 | * gsc_writeb status register: 83 79 1.2us | |
1084 | * IBF to clear after sending SET_IM: 6204 6006 93us | |
ffd51f46 | 1085 | * IBF to clear after sending LOAD_RT: 4467 4352 68us |
1da177e4 LT |
1086 | * IBF to clear after sending two LOAD_RTs: 18974 18859 295us |
1087 | * READ_T1, read status/data, IRQ, call handler: 35564 n/a 556us | |
1088 | * cmd to ~IBF READ_T1 2nd time right after: 5158403 n/a 81ms | |
1089 | * between IRQ received and ~IBF for above: 2578877 n/a 40ms | |
1090 | * | |
1091 | * Performance stats after a run of this module configuring HIL and | |
1092 | * receiving a few mouse events: | |
1093 | * | |
1094 | * status in8 282508 cycles 7128 calls | |
1095 | * status out8 8404 cycles 341 calls | |
1096 | * data out8 1734 cycles 78 calls | |
1097 | * isr 174324 cycles 617 calls (includes take) | |
1098 | * take 1241 cycles 2 calls | |
1099 | * put 1411504 cycles 6937 calls | |
1100 | * task 1655209 cycles 6937 calls (includes put) | |
1101 | * | |
1102 | */ |