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[PATCH] IB: userspace SRQ support
[net-next-2.6.git] / drivers / infiniband / hw / mthca / mthca_cq.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
74c2174e 4 * Copyright (c) 2005 Cisco Systems, Inc. All rights reserved.
2a1d9b7f
RD		 5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
1da177e4
LT		 7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 *
36 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
37 */
38
39#include <linux/init.h>
40#include <linux/hardirq.h>
41
42#include <ib_pack.h>
43
44#include "mthca_dev.h"
45#include "mthca_cmd.h"
46#include "mthca_memfree.h"
47
48enum {
49 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
50};
51
52enum {
53 MTHCA_CQ_ENTRY_SIZE = 0x20
54};
55
56/*
57 * Must be packed because start is 64 bits but only aligned to 32 bits.
58 */
59struct mthca_cq_context {
97f52eb4
SH		 60 __be32 flags;
61 __be64 start;
62 __be32 logsize_usrpage;
63 __be32 error_eqn; /* Tavor only */
64 __be32 comp_eqn;
65 __be32 pd;
66 __be32 lkey;
67 __be32 last_notified_index;
68 __be32 solicit_producer_index;
69 __be32 consumer_index;
70 __be32 producer_index;
71 __be32 cqn;
72 __be32 ci_db; /* Arbel only */
73 __be32 state_db; /* Arbel only */
74 u32 reserved;
1da177e4
LT		 75} __attribute__((packed));
76
77#define MTHCA_CQ_STATUS_OK ( 0 << 28)
78#define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28)
79#define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28)
80#define MTHCA_CQ_FLAG_TR ( 1 << 18)
81#define MTHCA_CQ_FLAG_OI ( 1 << 17)
82#define MTHCA_CQ_STATE_DISARMED ( 0 << 8)
83#define MTHCA_CQ_STATE_ARMED ( 1 << 8)
84#define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8)
85#define MTHCA_EQ_STATE_FIRED (10 << 8)
86
87enum {
88 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
89};
90
91enum {
92 SYNDROME_LOCAL_LENGTH_ERR = 0x01,
93 SYNDROME_LOCAL_QP_OP_ERR = 0x02,
94 SYNDROME_LOCAL_EEC_OP_ERR = 0x03,
95 SYNDROME_LOCAL_PROT_ERR = 0x04,
96 SYNDROME_WR_FLUSH_ERR = 0x05,
97 SYNDROME_MW_BIND_ERR = 0x06,
98 SYNDROME_BAD_RESP_ERR = 0x10,
99 SYNDROME_LOCAL_ACCESS_ERR = 0x11,
100 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
101 SYNDROME_REMOTE_ACCESS_ERR = 0x13,
102 SYNDROME_REMOTE_OP_ERR = 0x14,
103 SYNDROME_RETRY_EXC_ERR = 0x15,
104 SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
105 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20,
106 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
107 SYNDROME_REMOTE_ABORTED_ERR = 0x22,
108 SYNDROME_INVAL_EECN_ERR = 0x23,
109 SYNDROME_INVAL_EEC_STATE_ERR = 0x24
110};
111
112struct mthca_cqe {
97f52eb4
SH		 113 __be32 my_qpn;
114 __be32 my_ee;
115 __be32 rqpn;
116 __be16 sl_g_mlpath;
117 __be16 rlid;
118 __be32 imm_etype_pkey_eec;
119 __be32 byte_cnt;
120 __be32 wqe;
121 u8 opcode;
122 u8 is_send;
123 u8 reserved;
124 u8 owner;
1da177e4
LT		 125};
126
127struct mthca_err_cqe {
97f52eb4
SH		 128 __be32 my_qpn;
129 u32 reserved1[3];
130 u8 syndrome;
131 u8 reserved2;
132 __be16 db_cnt;
133 u32 reserved3;
134 __be32 wqe;
135 u8 opcode;
136 u8 reserved4[2];
137 u8 owner;
1da177e4
LT		 138};
139
140#define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7)
141#define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7)
142
143#define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24)
144#define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24)
145#define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24)
146#define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24)
147#define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
148
149#define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24)
150#define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24)
151#define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
152
153static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
154{
155 if (cq->is_direct)
156 return cq->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
157 else
158 return cq->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
159 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
160}
161
162static inline struct mthca_cqe *cqe_sw(struct mthca_cq *cq, int i)
163{
164 struct mthca_cqe *cqe = get_cqe(cq, i);
165 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
166}
167
168static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
169{
170 return cqe_sw(cq, cq->cons_index & cq->ibcq.cqe);
171}
172
173static inline void set_cqe_hw(struct mthca_cqe *cqe)
174{
175 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
176}
177
bb2af78b
RD		 178static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
179{
180 __be32 *cqe = cqe_ptr;
181
182 (void) cqe; /* avoid warning if mthca_dbg compiled away... */
183 mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
184 be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
185 be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
186 be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
187}
188
1da177e4
LT		 189/*
190 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
191 * should be correct before calling update_cons_index().
192 */
193static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
194 int incr)
195{
97f52eb4 196 __be32 doorbell[2];
1da177e4 197
d10ddbf6 198 if (mthca_is_memfree(dev)) {
1da177e4
LT		 199 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
200 wmb();
201 } else {
202 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
203 doorbell[1] = cpu_to_be32(incr - 1);
204
205 mthca_write64(doorbell,
206 dev->kar + MTHCA_CQ_DOORBELL,
207 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
208 }
209}
210
211void mthca_cq_event(struct mthca_dev *dev, u32 cqn)
212{
213 struct mthca_cq *cq;
214
215 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
216
217 if (!cq) {
218 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
219 return;
220 }
221
222 ++cq->arm_sn;
223
224 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
225}
226
227void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn)
228{
229 struct mthca_cq *cq;
230 struct mthca_cqe *cqe;
231 int prod_index;
232 int nfreed = 0;
233
234 spin_lock_irq(&dev->cq_table.lock);
235 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
236 if (cq)
237 atomic_inc(&cq->refcount);
238 spin_unlock_irq(&dev->cq_table.lock);
239
240 if (!cq)
241 return;
242
243 spin_lock_irq(&cq->lock);
244
245 /*
246 * First we need to find the current producer index, so we
247 * know where to start cleaning from. It doesn't matter if HW
248 * adds new entries after this loop -- the QP we're worried
249 * about is already in RESET, so the new entries won't come
250 * from our QP and therefore don't need to be checked.
251 */
252 for (prod_index = cq->cons_index;
253 cqe_sw(cq, prod_index & cq->ibcq.cqe);
254 ++prod_index)
255 if (prod_index == cq->cons_index + cq->ibcq.cqe)
256 break;
257
258 if (0)
259 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
260 qpn, cqn, cq->cons_index, prod_index);
261
262 /*
263 * Now sweep backwards through the CQ, removing CQ entries
264 * that match our QP by copying older entries on top of them.
265 */
266 while (prod_index > cq->cons_index) {
267 cqe = get_cqe(cq, (prod_index - 1) & cq->ibcq.cqe);
268 if (cqe->my_qpn == cpu_to_be32(qpn))
269 ++nfreed;
270 else if (nfreed)
271 memcpy(get_cqe(cq, (prod_index - 1 + nfreed) &
272 cq->ibcq.cqe),
273 cqe,
274 MTHCA_CQ_ENTRY_SIZE);
275 --prod_index;
276 }
277
278 if (nfreed) {
279 wmb();
280 cq->cons_index += nfreed;
281 update_cons_index(dev, cq, nfreed);
282 }
283
284 spin_unlock_irq(&cq->lock);
285 if (atomic_dec_and_test(&cq->refcount))
286 wake_up(&cq->wait);
287}
288
289static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
290 struct mthca_qp *qp, int wqe_index, int is_send,
291 struct mthca_err_cqe *cqe,
292 struct ib_wc *entry, int *free_cqe)
293{
294 int err;
295 int dbd;
97f52eb4 296 __be32 new_wqe;
1da177e4 297
bb2af78b
RD		 298 if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
299 mthca_dbg(dev, "local QP operation err "
300 "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
301 be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
302 cq->cqn, cq->cons_index);
303 dump_cqe(dev, cqe);
1da177e4
LT		 304 }
305
306 /*
307 * For completions in error, only work request ID, status (and
308 * freed resource count for RD) have to be set.
309 */
310 switch (cqe->syndrome) {
311 case SYNDROME_LOCAL_LENGTH_ERR:
312 entry->status = IB_WC_LOC_LEN_ERR;
313 break;
314 case SYNDROME_LOCAL_QP_OP_ERR:
315 entry->status = IB_WC_LOC_QP_OP_ERR;
316 break;
317 case SYNDROME_LOCAL_EEC_OP_ERR:
318 entry->status = IB_WC_LOC_EEC_OP_ERR;
319 break;
320 case SYNDROME_LOCAL_PROT_ERR:
321 entry->status = IB_WC_LOC_PROT_ERR;
322 break;
323 case SYNDROME_WR_FLUSH_ERR:
324 entry->status = IB_WC_WR_FLUSH_ERR;
325 break;
326 case SYNDROME_MW_BIND_ERR:
327 entry->status = IB_WC_MW_BIND_ERR;
328 break;
329 case SYNDROME_BAD_RESP_ERR:
330 entry->status = IB_WC_BAD_RESP_ERR;
331 break;
332 case SYNDROME_LOCAL_ACCESS_ERR:
333 entry->status = IB_WC_LOC_ACCESS_ERR;
334 break;
335 case SYNDROME_REMOTE_INVAL_REQ_ERR:
336 entry->status = IB_WC_REM_INV_REQ_ERR;
337 break;
338 case SYNDROME_REMOTE_ACCESS_ERR:
339 entry->status = IB_WC_REM_ACCESS_ERR;
340 break;
341 case SYNDROME_REMOTE_OP_ERR:
342 entry->status = IB_WC_REM_OP_ERR;
343 break;
344 case SYNDROME_RETRY_EXC_ERR:
345 entry->status = IB_WC_RETRY_EXC_ERR;
346 break;
347 case SYNDROME_RNR_RETRY_EXC_ERR:
348 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
349 break;
350 case SYNDROME_LOCAL_RDD_VIOL_ERR:
351 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
352 break;
353 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
354 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
355 break;
356 case SYNDROME_REMOTE_ABORTED_ERR:
357 entry->status = IB_WC_REM_ABORT_ERR;
358 break;
359 case SYNDROME_INVAL_EECN_ERR:
360 entry->status = IB_WC_INV_EECN_ERR;
361 break;
362 case SYNDROME_INVAL_EEC_STATE_ERR:
363 entry->status = IB_WC_INV_EEC_STATE_ERR;
364 break;
365 default:
366 entry->status = IB_WC_GENERAL_ERR;
367 break;
368 }
369
370 err = mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
371 if (err)
372 return err;
373
374 /*
375 * If we're at the end of the WQE chain, or we've used up our
376 * doorbell count, free the CQE. Otherwise just update it for
377 * the next poll operation.
42b1806d
RD		 378 *
379 * This does not apply to mem-free HCAs: they don't use the
380 * doorbell count field, and so we should always free the CQE.
1da177e4 381 */
42b1806d
RD		 382 if (mthca_is_memfree(dev) ||
383 !(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
1da177e4
LT		 384 return 0;
385
386 cqe->db_cnt = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
387 cqe->wqe = new_wqe;
388 cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
389
390 *free_cqe = 0;
391
392 return 0;
393}
394
1da177e4
LT		 395static inline int mthca_poll_one(struct mthca_dev *dev,
396 struct mthca_cq *cq,
397 struct mthca_qp **cur_qp,
398 int *freed,
399 struct ib_wc *entry)
400{
401 struct mthca_wq *wq;
402 struct mthca_cqe *cqe;
403 int wqe_index;
404 int is_error;
405 int is_send;
406 int free_cqe = 1;
407 int err = 0;
408
409 cqe = next_cqe_sw(cq);
410 if (!cqe)
411 return -EAGAIN;
412
413 /*
414 * Make sure we read CQ entry contents after we've checked the
415 * ownership bit.
416 */
417 rmb();
418
419 if (0) {
420 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
421 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
422 be32_to_cpu(cqe->wqe));
bb2af78b 423 dump_cqe(dev, cqe);
1da177e4
LT		 424 }
425
426 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
427 MTHCA_ERROR_CQE_OPCODE_MASK;
428 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
429
430 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
431 /*
432 * We do not have to take the QP table lock here,
433 * because CQs will be locked while QPs are removed
434 * from the table.
435 */
436 *cur_qp = mthca_array_get(&dev->qp_table.qp,
437 be32_to_cpu(cqe->my_qpn) &
438 (dev->limits.num_qps - 1));
439 if (!*cur_qp) {
440 mthca_warn(dev, "CQ entry for unknown QP %06x\n",
441 be32_to_cpu(cqe->my_qpn) & 0xffffff);
442 err = -EINVAL;
443 goto out;
444 }
445 }
446
447 entry->qp_num = (*cur_qp)->qpn;
448
449 if (is_send) {
450 wq = &(*cur_qp)->sq;
451 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
452 >> wq->wqe_shift);
453 entry->wr_id = (*cur_qp)->wrid[wqe_index +
454 (*cur_qp)->rq.max];
455 } else {
456 wq = &(*cur_qp)->rq;
457 wqe_index = be32_to_cpu(cqe->wqe) >> wq->wqe_shift;
458 entry->wr_id = (*cur_qp)->wrid[wqe_index];
459 }
460
461 if (wq->last_comp < wqe_index)
462 wq->tail += wqe_index - wq->last_comp;
463 else
464 wq->tail += wqe_index + wq->max - wq->last_comp;
465
466 wq->last_comp = wqe_index;
467
468 if (0)
469 mthca_dbg(dev, "%s completion for QP %06x, index %d (nr %d)\n",
470 is_send ? "Send" : "Receive",
471 (*cur_qp)->qpn, wqe_index, wq->max);
472
473 if (is_error) {
474 err = handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
475 (struct mthca_err_cqe *) cqe,
476 entry, &free_cqe);
477 goto out;
478 }
479
480 if (is_send) {
2a4443a6
MT		 481 entry->wc_flags = 0;
482 switch (cqe->opcode) {
483 case MTHCA_OPCODE_RDMA_WRITE:
484 entry->opcode = IB_WC_RDMA_WRITE;
485 break;
486 case MTHCA_OPCODE_RDMA_WRITE_IMM:
487 entry->opcode = IB_WC_RDMA_WRITE;
488 entry->wc_flags |= IB_WC_WITH_IMM;
489 break;
490 case MTHCA_OPCODE_SEND:
491 entry->opcode = IB_WC_SEND;
492 break;
493 case MTHCA_OPCODE_SEND_IMM:
494 entry->opcode = IB_WC_SEND;
495 entry->wc_flags |= IB_WC_WITH_IMM;
496 break;
497 case MTHCA_OPCODE_RDMA_READ:
498 entry->opcode = IB_WC_RDMA_READ;
499 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
500 break;
501 case MTHCA_OPCODE_ATOMIC_CS:
502 entry->opcode = IB_WC_COMP_SWAP;
503 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
504 break;
505 case MTHCA_OPCODE_ATOMIC_FA:
506 entry->opcode = IB_WC_FETCH_ADD;
507 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
508 break;
509 case MTHCA_OPCODE_BIND_MW:
510 entry->opcode = IB_WC_BIND_MW;
511 break;
512 default:
513 entry->opcode = MTHCA_OPCODE_INVALID;
514 break;
515 }
1da177e4
LT		 516 } else {
517 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
518 switch (cqe->opcode & 0x1f) {
519 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
520 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
521 entry->wc_flags = IB_WC_WITH_IMM;
522 entry->imm_data = cqe->imm_etype_pkey_eec;
523 entry->opcode = IB_WC_RECV;
524 break;
525 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
526 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
527 entry->wc_flags = IB_WC_WITH_IMM;
528 entry->imm_data = cqe->imm_etype_pkey_eec;
529 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
530 break;
531 default:
532 entry->wc_flags = 0;
533 entry->opcode = IB_WC_RECV;
534 break;
535 }
536 entry->slid = be16_to_cpu(cqe->rlid);
537 entry->sl = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
538 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff;
539 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
540 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
541 entry->wc_flags |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
542 IB_WC_GRH : 0;
543 }
544
545 entry->status = IB_WC_SUCCESS;
546
547 out:
548 if (likely(free_cqe)) {
549 set_cqe_hw(cqe);
550 ++(*freed);
551 ++cq->cons_index;
552 }
553
554 return err;
555}
556
557int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
558 struct ib_wc *entry)
559{
560 struct mthca_dev *dev = to_mdev(ibcq->device);
561 struct mthca_cq *cq = to_mcq(ibcq);
562 struct mthca_qp *qp = NULL;
563 unsigned long flags;
564 int err = 0;
565 int freed = 0;
566 int npolled;
567
568 spin_lock_irqsave(&cq->lock, flags);
569
570 for (npolled = 0; npolled < num_entries; ++npolled) {
571 err = mthca_poll_one(dev, cq, &qp,
572 &freed, entry + npolled);
573 if (err)
574 break;
575 }
576
577 if (freed) {
578 wmb();
579 update_cons_index(dev, cq, freed);
580 }
581
582 spin_unlock_irqrestore(&cq->lock, flags);
583
584 return err == 0 || err == -EAGAIN ? npolled : err;
585}
586
587int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
588{
97f52eb4 589 __be32 doorbell[2];
1da177e4
LT		 590
591 doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
592 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
593 MTHCA_TAVOR_CQ_DB_REQ_NOT) |
594 to_mcq(cq)->cqn);
97f52eb4 595 doorbell[1] = (__force __be32) 0xffffffff;
1da177e4
LT		 596
597 mthca_write64(doorbell,
598 to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
599 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
600
601 return 0;
602}
603
604int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
605{
606 struct mthca_cq *cq = to_mcq(ibcq);
97f52eb4 607 __be32 doorbell[2];
1da177e4 608 u32 sn;
97f52eb4 609 __be32 ci;
1da177e4
LT		 610
611 sn = cq->arm_sn & 3;
612 ci = cpu_to_be32(cq->cons_index);
613
614 doorbell[0] = ci;
615 doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
616 (notify == IB_CQ_SOLICITED ? 1 : 2));
617
618 mthca_write_db_rec(doorbell, cq->arm_db);
619
620 /*
621 * Make sure that the doorbell record in host memory is
622 * written before ringing the doorbell via PCI MMIO.
623 */
624 wmb();
625
626 doorbell[0] = cpu_to_be32((sn << 28) |
627 (notify == IB_CQ_SOLICITED ?
628 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
629 MTHCA_ARBEL_CQ_DB_REQ_NOT) |
630 cq->cqn);
631 doorbell[1] = ci;
632
633 mthca_write64(doorbell,
634 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
635 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
636
637 return 0;
638}
639
640static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
641{
642 int i;
643 int size;
644
645 if (cq->is_direct)
64dc81fc
RD		 646 dma_free_coherent(&dev->pdev->dev,
647 (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
648 cq->queue.direct.buf,
649 pci_unmap_addr(&cq->queue.direct,
650 mapping));
1da177e4
LT		 651 else {
652 size = (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE;
653 for (i = 0; i < (size + PAGE_SIZE - 1) / PAGE_SIZE; ++i)
654 if (cq->queue.page_list[i].buf)
64dc81fc
RD		 655 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
656 cq->queue.page_list[i].buf,
657 pci_unmap_addr(&cq->queue.page_list[i],
658 mapping));
1da177e4
LT		 659
660 kfree(cq->queue.page_list);
661 }
662}
663
664static int mthca_alloc_cq_buf(struct mthca_dev *dev, int size,
665 struct mthca_cq *cq)
666{
667 int err = -ENOMEM;
668 int npages, shift;
669 u64 *dma_list = NULL;
670 dma_addr_t t;
671 int i;
672
673 if (size <= MTHCA_MAX_DIRECT_CQ_SIZE) {
674 cq->is_direct = 1;
675 npages = 1;
676 shift = get_order(size) + PAGE_SHIFT;
677
64dc81fc
RD		 678 cq->queue.direct.buf = dma_alloc_coherent(&dev->pdev->dev,
679 size, &t, GFP_KERNEL);
1da177e4
LT		 680 if (!cq->queue.direct.buf)
681 return -ENOMEM;
682
683 pci_unmap_addr_set(&cq->queue.direct, mapping, t);
684
685 memset(cq->queue.direct.buf, 0, size);
686
687 while (t & ((1 << shift) - 1)) {
688 --shift;
689 npages *= 2;
690 }
691
692 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
693 if (!dma_list)
694 goto err_free;
695
696 for (i = 0; i < npages; ++i)
697 dma_list[i] = t + i * (1 << shift);
698 } else {
699 cq->is_direct = 0;
700 npages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
701 shift = PAGE_SHIFT;
702
703 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
704 if (!dma_list)
705 return -ENOMEM;
706
707 cq->queue.page_list = kmalloc(npages * sizeof *cq->queue.page_list,
708 GFP_KERNEL);
709 if (!cq->queue.page_list)
710 goto err_out;
711
712 for (i = 0; i < npages; ++i)
713 cq->queue.page_list[i].buf = NULL;
714
715 for (i = 0; i < npages; ++i) {
716 cq->queue.page_list[i].buf =
64dc81fc
RD		 717 dma_alloc_coherent(&dev->pdev->dev, PAGE_SIZE,
718 &t, GFP_KERNEL);
1da177e4
LT		 719 if (!cq->queue.page_list[i].buf)
720 goto err_free;
721
722 dma_list[i] = t;
723 pci_unmap_addr_set(&cq->queue.page_list[i], mapping, t);
724
725 memset(cq->queue.page_list[i].buf, 0, PAGE_SIZE);
726 }
727 }
728
729 err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num,
730 dma_list, shift, npages,
731 0, size,
732 MTHCA_MPT_FLAG_LOCAL_WRITE |
733 MTHCA_MPT_FLAG_LOCAL_READ,
734 &cq->mr);
735 if (err)
736 goto err_free;
737
738 kfree(dma_list);
739
740 return 0;
741
742err_free:
743 mthca_free_cq_buf(dev, cq);
744
745err_out:
746 kfree(dma_list);
747
748 return err;
749}
750
751int mthca_init_cq(struct mthca_dev *dev, int nent,
74c2174e 752 struct mthca_ucontext *ctx, u32 pdn,
1da177e4
LT		 753 struct mthca_cq *cq)
754{
755 int size = nent * MTHCA_CQ_ENTRY_SIZE;
ed878458 756 struct mthca_mailbox *mailbox;
1da177e4
LT		 757 struct mthca_cq_context *cq_context;
758 int err = -ENOMEM;
759 u8 status;
760 int i;
761
762 might_sleep();
763
74c2174e
RD		 764 cq->ibcq.cqe = nent - 1;
765 cq->is_kernel = !ctx;
1da177e4
LT		 766
767 cq->cqn = mthca_alloc(&dev->cq_table.alloc);
768 if (cq->cqn == -1)
769 return -ENOMEM;
770
d10ddbf6 771 if (mthca_is_memfree(dev)) {
1da177e4
LT		 772 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
773 if (err)
774 goto err_out;
775
74c2174e
RD		 776 if (cq->is_kernel) {
777 cq->arm_sn = 1;
778
779 err = -ENOMEM;
1da177e4 780
74c2174e
RD		 781 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
782 cq->cqn, &cq->set_ci_db);
783 if (cq->set_ci_db_index < 0)
784 goto err_out_icm;
1da177e4 785
74c2174e
RD		 786 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
787 cq->cqn, &cq->arm_db);
788 if (cq->arm_db_index < 0)
789 goto err_out_ci;
790 }
1da177e4
LT		 791 }
792
ed878458
RD		 793 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
794 if (IS_ERR(mailbox))
795 goto err_out_arm;
1da177e4 796
ed878458 797 cq_context = mailbox->buf;
1da177e4 798
74c2174e
RD		 799 if (cq->is_kernel) {
800 err = mthca_alloc_cq_buf(dev, size, cq);
801 if (err)
802 goto err_out_mailbox;
1da177e4 803
74c2174e
RD		 804 for (i = 0; i < nent; ++i)
805 set_cqe_hw(get_cqe(cq, i));
806 }
1da177e4
LT		 807
808 spin_lock_init(&cq->lock);
809 atomic_set(&cq->refcount, 1);
810 init_waitqueue_head(&cq->wait);
811
812 memset(cq_context, 0, sizeof *cq_context);
813 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK |
814 MTHCA_CQ_STATE_DISARMED |
815 MTHCA_CQ_FLAG_TR);
74c2174e
RD		 816 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
817 if (ctx)
818 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
819 else
820 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
1da177e4
LT		 821 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
822 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
74c2174e 823 cq_context->pd = cpu_to_be32(pdn);
1da177e4
LT		 824 cq_context->lkey = cpu_to_be32(cq->mr.ibmr.lkey);
825 cq_context->cqn = cpu_to_be32(cq->cqn);
826
d10ddbf6 827 if (mthca_is_memfree(dev)) {
1da177e4
LT		 828 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index);
829 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
830 }
831
ed878458 832 err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
1da177e4
LT		 833 if (err) {
834 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
835 goto err_out_free_mr;
836 }
837
838 if (status) {
839 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
840 status);
841 err = -EINVAL;
842 goto err_out_free_mr;
843 }
844
845 spin_lock_irq(&dev->cq_table.lock);
846 if (mthca_array_set(&dev->cq_table.cq,
847 cq->cqn & (dev->limits.num_cqs - 1),
848 cq)) {
849 spin_unlock_irq(&dev->cq_table.lock);
850 goto err_out_free_mr;
851 }
852 spin_unlock_irq(&dev->cq_table.lock);
853
854 cq->cons_index = 0;
855
ed878458 856 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 857
858 return 0;
859
860err_out_free_mr:
74c2174e
RD		 861 if (cq->is_kernel) {
862 mthca_free_mr(dev, &cq->mr);
863 mthca_free_cq_buf(dev, cq);
864 }
1da177e4
LT		 865
866err_out_mailbox:
ed878458 867 mthca_free_mailbox(dev, mailbox);
1da177e4 868
ed878458 869err_out_arm:
74c2174e 870 if (cq->is_kernel && mthca_is_memfree(dev))
b635fa21 871 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
1da177e4
LT		 872
873err_out_ci:
74c2174e 874 if (cq->is_kernel && mthca_is_memfree(dev))
b635fa21 875 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
1da177e4
LT		 876
877err_out_icm:
878 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
879
880err_out:
881 mthca_free(&dev->cq_table.alloc, cq->cqn);
882
883 return err;
884}
885
886void mthca_free_cq(struct mthca_dev *dev,
887 struct mthca_cq *cq)
888{
ed878458 889 struct mthca_mailbox *mailbox;
1da177e4
LT		 890 int err;
891 u8 status;
892
893 might_sleep();
894
ed878458
RD		 895 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
896 if (IS_ERR(mailbox)) {
1da177e4
LT		 897 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
898 return;
899 }
900
ed878458 901 err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
1da177e4
LT		 902 if (err)
903 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
904 else if (status)
ed878458 905 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
1da177e4
LT		 906
907 if (0) {
97f52eb4 908 __be32 *ctx = mailbox->buf;
1da177e4
LT		 909 int j;
910
911 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
74c2174e
RD		 912 cq->cqn, cq->cons_index,
913 cq->is_kernel ? !!next_cqe_sw(cq) : 0);
1da177e4
LT		 914 for (j = 0; j < 16; ++j)
915 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
916 }
917
918 spin_lock_irq(&dev->cq_table.lock);
919 mthca_array_clear(&dev->cq_table.cq,
920 cq->cqn & (dev->limits.num_cqs - 1));
921 spin_unlock_irq(&dev->cq_table.lock);
922
923 if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
924 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
925 else
926 synchronize_irq(dev->pdev->irq);
927
928 atomic_dec(&cq->refcount);
929 wait_event(cq->wait, !atomic_read(&cq->refcount));
930
74c2174e
RD		 931 if (cq->is_kernel) {
932 mthca_free_mr(dev, &cq->mr);
933 mthca_free_cq_buf(dev, cq);
934 if (mthca_is_memfree(dev)) {
935 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
936 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
937 }
1da177e4
LT		 938 }
939
a03a5a67 940 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
1da177e4 941 mthca_free(&dev->cq_table.alloc, cq->cqn);
ed878458 942 mthca_free_mailbox(dev, mailbox);
1da177e4
LT		 943}
944
945int __devinit mthca_init_cq_table(struct mthca_dev *dev)
946{
947 int err;
948
949 spin_lock_init(&dev->cq_table.lock);
950
951 err = mthca_alloc_init(&dev->cq_table.alloc,
952 dev->limits.num_cqs,
953 (1 << 24) - 1,
954 dev->limits.reserved_cqs);
955 if (err)
956 return err;
957
958 err = mthca_array_init(&dev->cq_table.cq,
959 dev->limits.num_cqs);
960 if (err)
961 mthca_alloc_cleanup(&dev->cq_table.alloc);
962
963 return err;
964}
965
966void __devexit mthca_cleanup_cq_table(struct mthca_dev *dev)
967{
968 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
969 mthca_alloc_cleanup(&dev->cq_table.alloc);
970}
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