]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/infiniband/hw/mthca/mthca_cq.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] IB/mthca: Clean up error messages
[net-next-2.6.git] / drivers / infiniband / hw / mthca / mthca_cq.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
1da177e4
LT		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
34 */
35
36#include <linux/init.h>
37#include <linux/hardirq.h>
38
39#include <ib_pack.h>
40
41#include "mthca_dev.h"
42#include "mthca_cmd.h"
43#include "mthca_memfree.h"
44
45enum {
46 MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
47};
48
49enum {
50 MTHCA_CQ_ENTRY_SIZE = 0x20
51};
52
53/*
54 * Must be packed because start is 64 bits but only aligned to 32 bits.
55 */
56struct mthca_cq_context {
57 u32 flags;
58 u64 start;
59 u32 logsize_usrpage;
60 u32 error_eqn; /* Tavor only */
61 u32 comp_eqn;
62 u32 pd;
63 u32 lkey;
64 u32 last_notified_index;
65 u32 solicit_producer_index;
66 u32 consumer_index;
67 u32 producer_index;
68 u32 cqn;
69 u32 ci_db; /* Arbel only */
70 u32 state_db; /* Arbel only */
71 u32 reserved;
72} __attribute__((packed));
73
74#define MTHCA_CQ_STATUS_OK ( 0 << 28)
75#define MTHCA_CQ_STATUS_OVERFLOW ( 9 << 28)
76#define MTHCA_CQ_STATUS_WRITE_FAIL (10 << 28)
77#define MTHCA_CQ_FLAG_TR ( 1 << 18)
78#define MTHCA_CQ_FLAG_OI ( 1 << 17)
79#define MTHCA_CQ_STATE_DISARMED ( 0 << 8)
80#define MTHCA_CQ_STATE_ARMED ( 1 << 8)
81#define MTHCA_CQ_STATE_ARMED_SOL ( 4 << 8)
82#define MTHCA_EQ_STATE_FIRED (10 << 8)
83
84enum {
85 MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
86};
87
88enum {
89 SYNDROME_LOCAL_LENGTH_ERR = 0x01,
90 SYNDROME_LOCAL_QP_OP_ERR = 0x02,
91 SYNDROME_LOCAL_EEC_OP_ERR = 0x03,
92 SYNDROME_LOCAL_PROT_ERR = 0x04,
93 SYNDROME_WR_FLUSH_ERR = 0x05,
94 SYNDROME_MW_BIND_ERR = 0x06,
95 SYNDROME_BAD_RESP_ERR = 0x10,
96 SYNDROME_LOCAL_ACCESS_ERR = 0x11,
97 SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
98 SYNDROME_REMOTE_ACCESS_ERR = 0x13,
99 SYNDROME_REMOTE_OP_ERR = 0x14,
100 SYNDROME_RETRY_EXC_ERR = 0x15,
101 SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
102 SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20,
103 SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
104 SYNDROME_REMOTE_ABORTED_ERR = 0x22,
105 SYNDROME_INVAL_EECN_ERR = 0x23,
106 SYNDROME_INVAL_EEC_STATE_ERR = 0x24
107};
108
109struct mthca_cqe {
110 u32 my_qpn;
111 u32 my_ee;
112 u32 rqpn;
113 u16 sl_g_mlpath;
114 u16 rlid;
115 u32 imm_etype_pkey_eec;
116 u32 byte_cnt;
117 u32 wqe;
118 u8 opcode;
119 u8 is_send;
120 u8 reserved;
121 u8 owner;
122};
123
124struct mthca_err_cqe {
125 u32 my_qpn;
126 u32 reserved1[3];
127 u8 syndrome;
128 u8 reserved2;
129 u16 db_cnt;
130 u32 reserved3;
131 u32 wqe;
132 u8 opcode;
133 u8 reserved4[2];
134 u8 owner;
135};
136
137#define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7)
138#define MTHCA_CQ_ENTRY_OWNER_HW (1 << 7)
139
140#define MTHCA_TAVOR_CQ_DB_INC_CI (1 << 24)
141#define MTHCA_TAVOR_CQ_DB_REQ_NOT (2 << 24)
142#define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24)
143#define MTHCA_TAVOR_CQ_DB_SET_CI (4 << 24)
144#define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
145
146#define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24)
147#define MTHCA_ARBEL_CQ_DB_REQ_NOT (2 << 24)
148#define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
149
150static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
151{
152 if (cq->is_direct)
153 return cq->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
154 else
155 return cq->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
156 + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
157}
158
159static inline struct mthca_cqe *cqe_sw(struct mthca_cq *cq, int i)
160{
161 struct mthca_cqe *cqe = get_cqe(cq, i);
162 return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
163}
164
165static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
166{
167 return cqe_sw(cq, cq->cons_index & cq->ibcq.cqe);
168}
169
170static inline void set_cqe_hw(struct mthca_cqe *cqe)
171{
172 cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
173}
174
175/*
176 * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
177 * should be correct before calling update_cons_index().
178 */
179static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
180 int incr)
181{
182 u32 doorbell[2];
183
d10ddbf6 184 if (mthca_is_memfree(dev)) {
1da177e4
LT		 185 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
186 wmb();
187 } else {
188 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
189 doorbell[1] = cpu_to_be32(incr - 1);
190
191 mthca_write64(doorbell,
192 dev->kar + MTHCA_CQ_DOORBELL,
193 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
194 }
195}
196
197void mthca_cq_event(struct mthca_dev *dev, u32 cqn)
198{
199 struct mthca_cq *cq;
200
201 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
202
203 if (!cq) {
204 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
205 return;
206 }
207
208 ++cq->arm_sn;
209
210 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
211}
212
213void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn)
214{
215 struct mthca_cq *cq;
216 struct mthca_cqe *cqe;
217 int prod_index;
218 int nfreed = 0;
219
220 spin_lock_irq(&dev->cq_table.lock);
221 cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
222 if (cq)
223 atomic_inc(&cq->refcount);
224 spin_unlock_irq(&dev->cq_table.lock);
225
226 if (!cq)
227 return;
228
229 spin_lock_irq(&cq->lock);
230
231 /*
232 * First we need to find the current producer index, so we
233 * know where to start cleaning from. It doesn't matter if HW
234 * adds new entries after this loop -- the QP we're worried
235 * about is already in RESET, so the new entries won't come
236 * from our QP and therefore don't need to be checked.
237 */
238 for (prod_index = cq->cons_index;
239 cqe_sw(cq, prod_index & cq->ibcq.cqe);
240 ++prod_index)
241 if (prod_index == cq->cons_index + cq->ibcq.cqe)
242 break;
243
244 if (0)
245 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
246 qpn, cqn, cq->cons_index, prod_index);
247
248 /*
249 * Now sweep backwards through the CQ, removing CQ entries
250 * that match our QP by copying older entries on top of them.
251 */
252 while (prod_index > cq->cons_index) {
253 cqe = get_cqe(cq, (prod_index - 1) & cq->ibcq.cqe);
254 if (cqe->my_qpn == cpu_to_be32(qpn))
255 ++nfreed;
256 else if (nfreed)
257 memcpy(get_cqe(cq, (prod_index - 1 + nfreed) &
258 cq->ibcq.cqe),
259 cqe,
260 MTHCA_CQ_ENTRY_SIZE);
261 --prod_index;
262 }
263
264 if (nfreed) {
265 wmb();
266 cq->cons_index += nfreed;
267 update_cons_index(dev, cq, nfreed);
268 }
269
270 spin_unlock_irq(&cq->lock);
271 if (atomic_dec_and_test(&cq->refcount))
272 wake_up(&cq->wait);
273}
274
275static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
276 struct mthca_qp *qp, int wqe_index, int is_send,
277 struct mthca_err_cqe *cqe,
278 struct ib_wc *entry, int *free_cqe)
279{
280 int err;
281 int dbd;
282 u32 new_wqe;
283
284 if (1 && cqe->syndrome != SYNDROME_WR_FLUSH_ERR) {
285 int j;
286
287 mthca_dbg(dev, "%x/%d: error CQE -> QPN %06x, WQE @ %08x\n",
288 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
289 be32_to_cpu(cqe->wqe));
290
291 for (j = 0; j < 8; ++j)
292 printk(KERN_DEBUG " [%2x] %08x\n",
293 j * 4, be32_to_cpu(((u32 *) cqe)[j]));
294 }
295
296 /*
297 * For completions in error, only work request ID, status (and
298 * freed resource count for RD) have to be set.
299 */
300 switch (cqe->syndrome) {
301 case SYNDROME_LOCAL_LENGTH_ERR:
302 entry->status = IB_WC_LOC_LEN_ERR;
303 break;
304 case SYNDROME_LOCAL_QP_OP_ERR:
305 entry->status = IB_WC_LOC_QP_OP_ERR;
306 break;
307 case SYNDROME_LOCAL_EEC_OP_ERR:
308 entry->status = IB_WC_LOC_EEC_OP_ERR;
309 break;
310 case SYNDROME_LOCAL_PROT_ERR:
311 entry->status = IB_WC_LOC_PROT_ERR;
312 break;
313 case SYNDROME_WR_FLUSH_ERR:
314 entry->status = IB_WC_WR_FLUSH_ERR;
315 break;
316 case SYNDROME_MW_BIND_ERR:
317 entry->status = IB_WC_MW_BIND_ERR;
318 break;
319 case SYNDROME_BAD_RESP_ERR:
320 entry->status = IB_WC_BAD_RESP_ERR;
321 break;
322 case SYNDROME_LOCAL_ACCESS_ERR:
323 entry->status = IB_WC_LOC_ACCESS_ERR;
324 break;
325 case SYNDROME_REMOTE_INVAL_REQ_ERR:
326 entry->status = IB_WC_REM_INV_REQ_ERR;
327 break;
328 case SYNDROME_REMOTE_ACCESS_ERR:
329 entry->status = IB_WC_REM_ACCESS_ERR;
330 break;
331 case SYNDROME_REMOTE_OP_ERR:
332 entry->status = IB_WC_REM_OP_ERR;
333 break;
334 case SYNDROME_RETRY_EXC_ERR:
335 entry->status = IB_WC_RETRY_EXC_ERR;
336 break;
337 case SYNDROME_RNR_RETRY_EXC_ERR:
338 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
339 break;
340 case SYNDROME_LOCAL_RDD_VIOL_ERR:
341 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
342 break;
343 case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
344 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
345 break;
346 case SYNDROME_REMOTE_ABORTED_ERR:
347 entry->status = IB_WC_REM_ABORT_ERR;
348 break;
349 case SYNDROME_INVAL_EECN_ERR:
350 entry->status = IB_WC_INV_EECN_ERR;
351 break;
352 case SYNDROME_INVAL_EEC_STATE_ERR:
353 entry->status = IB_WC_INV_EEC_STATE_ERR;
354 break;
355 default:
356 entry->status = IB_WC_GENERAL_ERR;
357 break;
358 }
359
360 err = mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
361 if (err)
362 return err;
363
364 /*
365 * If we're at the end of the WQE chain, or we've used up our
366 * doorbell count, free the CQE. Otherwise just update it for
367 * the next poll operation.
368 */
369 if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
370 return 0;
371
372 cqe->db_cnt = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
373 cqe->wqe = new_wqe;
374 cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
375
376 *free_cqe = 0;
377
378 return 0;
379}
380
381static void dump_cqe(struct mthca_cqe *cqe)
382{
383 int j;
384
385 for (j = 0; j < 8; ++j)
386 printk(KERN_DEBUG " [%2x] %08x\n",
387 j * 4, be32_to_cpu(((u32 *) cqe)[j]));
388}
389
390static inline int mthca_poll_one(struct mthca_dev *dev,
391 struct mthca_cq *cq,
392 struct mthca_qp **cur_qp,
393 int *freed,
394 struct ib_wc *entry)
395{
396 struct mthca_wq *wq;
397 struct mthca_cqe *cqe;
398 int wqe_index;
399 int is_error;
400 int is_send;
401 int free_cqe = 1;
402 int err = 0;
403
404 cqe = next_cqe_sw(cq);
405 if (!cqe)
406 return -EAGAIN;
407
408 /*
409 * Make sure we read CQ entry contents after we've checked the
410 * ownership bit.
411 */
412 rmb();
413
414 if (0) {
415 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
416 cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
417 be32_to_cpu(cqe->wqe));
418
419 dump_cqe(cqe);
420 }
421
422 is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
423 MTHCA_ERROR_CQE_OPCODE_MASK;
424 is_send = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
425
426 if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
427 /*
428 * We do not have to take the QP table lock here,
429 * because CQs will be locked while QPs are removed
430 * from the table.
431 */
432 *cur_qp = mthca_array_get(&dev->qp_table.qp,
433 be32_to_cpu(cqe->my_qpn) &
434 (dev->limits.num_qps - 1));
435 if (!*cur_qp) {
436 mthca_warn(dev, "CQ entry for unknown QP %06x\n",
437 be32_to_cpu(cqe->my_qpn) & 0xffffff);
438 err = -EINVAL;
439 goto out;
440 }
441 }
442
443 entry->qp_num = (*cur_qp)->qpn;
444
445 if (is_send) {
446 wq = &(*cur_qp)->sq;
447 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
448 >> wq->wqe_shift);
449 entry->wr_id = (*cur_qp)->wrid[wqe_index +
450 (*cur_qp)->rq.max];
451 } else {
452 wq = &(*cur_qp)->rq;
453 wqe_index = be32_to_cpu(cqe->wqe) >> wq->wqe_shift;
454 entry->wr_id = (*cur_qp)->wrid[wqe_index];
455 }
456
457 if (wq->last_comp < wqe_index)
458 wq->tail += wqe_index - wq->last_comp;
459 else
460 wq->tail += wqe_index + wq->max - wq->last_comp;
461
462 wq->last_comp = wqe_index;
463
464 if (0)
465 mthca_dbg(dev, "%s completion for QP %06x, index %d (nr %d)\n",
466 is_send ? "Send" : "Receive",
467 (*cur_qp)->qpn, wqe_index, wq->max);
468
469 if (is_error) {
470 err = handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
471 (struct mthca_err_cqe *) cqe,
472 entry, &free_cqe);
473 goto out;
474 }
475
476 if (is_send) {
2a4443a6
MT		 477 entry->wc_flags = 0;
478 switch (cqe->opcode) {
479 case MTHCA_OPCODE_RDMA_WRITE:
480 entry->opcode = IB_WC_RDMA_WRITE;
481 break;
482 case MTHCA_OPCODE_RDMA_WRITE_IMM:
483 entry->opcode = IB_WC_RDMA_WRITE;
484 entry->wc_flags |= IB_WC_WITH_IMM;
485 break;
486 case MTHCA_OPCODE_SEND:
487 entry->opcode = IB_WC_SEND;
488 break;
489 case MTHCA_OPCODE_SEND_IMM:
490 entry->opcode = IB_WC_SEND;
491 entry->wc_flags |= IB_WC_WITH_IMM;
492 break;
493 case MTHCA_OPCODE_RDMA_READ:
494 entry->opcode = IB_WC_RDMA_READ;
495 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
496 break;
497 case MTHCA_OPCODE_ATOMIC_CS:
498 entry->opcode = IB_WC_COMP_SWAP;
499 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
500 break;
501 case MTHCA_OPCODE_ATOMIC_FA:
502 entry->opcode = IB_WC_FETCH_ADD;
503 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
504 break;
505 case MTHCA_OPCODE_BIND_MW:
506 entry->opcode = IB_WC_BIND_MW;
507 break;
508 default:
509 entry->opcode = MTHCA_OPCODE_INVALID;
510 break;
511 }
1da177e4
LT		 512 } else {
513 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
514 switch (cqe->opcode & 0x1f) {
515 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
516 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
517 entry->wc_flags = IB_WC_WITH_IMM;
518 entry->imm_data = cqe->imm_etype_pkey_eec;
519 entry->opcode = IB_WC_RECV;
520 break;
521 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
522 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
523 entry->wc_flags = IB_WC_WITH_IMM;
524 entry->imm_data = cqe->imm_etype_pkey_eec;
525 entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
526 break;
527 default:
528 entry->wc_flags = 0;
529 entry->opcode = IB_WC_RECV;
530 break;
531 }
532 entry->slid = be16_to_cpu(cqe->rlid);
533 entry->sl = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
534 entry->src_qp = be32_to_cpu(cqe->rqpn) & 0xffffff;
535 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
536 entry->pkey_index = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
537 entry->wc_flags |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
538 IB_WC_GRH : 0;
539 }
540
541 entry->status = IB_WC_SUCCESS;
542
543 out:
544 if (likely(free_cqe)) {
545 set_cqe_hw(cqe);
546 ++(*freed);
547 ++cq->cons_index;
548 }
549
550 return err;
551}
552
553int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
554 struct ib_wc *entry)
555{
556 struct mthca_dev *dev = to_mdev(ibcq->device);
557 struct mthca_cq *cq = to_mcq(ibcq);
558 struct mthca_qp *qp = NULL;
559 unsigned long flags;
560 int err = 0;
561 int freed = 0;
562 int npolled;
563
564 spin_lock_irqsave(&cq->lock, flags);
565
566 for (npolled = 0; npolled < num_entries; ++npolled) {
567 err = mthca_poll_one(dev, cq, &qp,
568 &freed, entry + npolled);
569 if (err)
570 break;
571 }
572
573 if (freed) {
574 wmb();
575 update_cons_index(dev, cq, freed);
576 }
577
578 spin_unlock_irqrestore(&cq->lock, flags);
579
580 return err == 0 || err == -EAGAIN ? npolled : err;
581}
582
583int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
584{
585 u32 doorbell[2];
586
587 doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
588 MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
589 MTHCA_TAVOR_CQ_DB_REQ_NOT) |
590 to_mcq(cq)->cqn);
591 doorbell[1] = 0xffffffff;
592
593 mthca_write64(doorbell,
594 to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
595 MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
596
597 return 0;
598}
599
600int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
601{
602 struct mthca_cq *cq = to_mcq(ibcq);
603 u32 doorbell[2];
604 u32 sn;
605 u32 ci;
606
607 sn = cq->arm_sn & 3;
608 ci = cpu_to_be32(cq->cons_index);
609
610 doorbell[0] = ci;
611 doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
612 (notify == IB_CQ_SOLICITED ? 1 : 2));
613
614 mthca_write_db_rec(doorbell, cq->arm_db);
615
616 /*
617 * Make sure that the doorbell record in host memory is
618 * written before ringing the doorbell via PCI MMIO.
619 */
620 wmb();
621
622 doorbell[0] = cpu_to_be32((sn << 28) |
623 (notify == IB_CQ_SOLICITED ?
624 MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
625 MTHCA_ARBEL_CQ_DB_REQ_NOT) |
626 cq->cqn);
627 doorbell[1] = ci;
628
629 mthca_write64(doorbell,
630 to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
631 MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
632
633 return 0;
634}
635
636static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
637{
638 int i;
639 int size;
640
641 if (cq->is_direct)
642 pci_free_consistent(dev->pdev,
643 (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
644 cq->queue.direct.buf,
645 pci_unmap_addr(&cq->queue.direct,
646 mapping));
647 else {
648 size = (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE;
649 for (i = 0; i < (size + PAGE_SIZE - 1) / PAGE_SIZE; ++i)
650 if (cq->queue.page_list[i].buf)
651 pci_free_consistent(dev->pdev, PAGE_SIZE,
652 cq->queue.page_list[i].buf,
653 pci_unmap_addr(&cq->queue.page_list[i],
654 mapping));
655
656 kfree(cq->queue.page_list);
657 }
658}
659
660static int mthca_alloc_cq_buf(struct mthca_dev *dev, int size,
661 struct mthca_cq *cq)
662{
663 int err = -ENOMEM;
664 int npages, shift;
665 u64 *dma_list = NULL;
666 dma_addr_t t;
667 int i;
668
669 if (size <= MTHCA_MAX_DIRECT_CQ_SIZE) {
670 cq->is_direct = 1;
671 npages = 1;
672 shift = get_order(size) + PAGE_SHIFT;
673
674 cq->queue.direct.buf = pci_alloc_consistent(dev->pdev,
675 size, &t);
676 if (!cq->queue.direct.buf)
677 return -ENOMEM;
678
679 pci_unmap_addr_set(&cq->queue.direct, mapping, t);
680
681 memset(cq->queue.direct.buf, 0, size);
682
683 while (t & ((1 << shift) - 1)) {
684 --shift;
685 npages *= 2;
686 }
687
688 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
689 if (!dma_list)
690 goto err_free;
691
692 for (i = 0; i < npages; ++i)
693 dma_list[i] = t + i * (1 << shift);
694 } else {
695 cq->is_direct = 0;
696 npages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
697 shift = PAGE_SHIFT;
698
699 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
700 if (!dma_list)
701 return -ENOMEM;
702
703 cq->queue.page_list = kmalloc(npages * sizeof *cq->queue.page_list,
704 GFP_KERNEL);
705 if (!cq->queue.page_list)
706 goto err_out;
707
708 for (i = 0; i < npages; ++i)
709 cq->queue.page_list[i].buf = NULL;
710
711 for (i = 0; i < npages; ++i) {
712 cq->queue.page_list[i].buf =
713 pci_alloc_consistent(dev->pdev, PAGE_SIZE, &t);
714 if (!cq->queue.page_list[i].buf)
715 goto err_free;
716
717 dma_list[i] = t;
718 pci_unmap_addr_set(&cq->queue.page_list[i], mapping, t);
719
720 memset(cq->queue.page_list[i].buf, 0, PAGE_SIZE);
721 }
722 }
723
724 err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num,
725 dma_list, shift, npages,
726 0, size,
727 MTHCA_MPT_FLAG_LOCAL_WRITE |
728 MTHCA_MPT_FLAG_LOCAL_READ,
729 &cq->mr);
730 if (err)
731 goto err_free;
732
733 kfree(dma_list);
734
735 return 0;
736
737err_free:
738 mthca_free_cq_buf(dev, cq);
739
740err_out:
741 kfree(dma_list);
742
743 return err;
744}
745
746int mthca_init_cq(struct mthca_dev *dev, int nent,
747 struct mthca_cq *cq)
748{
749 int size = nent * MTHCA_CQ_ENTRY_SIZE;
750 void *mailbox = NULL;
751 struct mthca_cq_context *cq_context;
752 int err = -ENOMEM;
753 u8 status;
754 int i;
755
756 might_sleep();
757
758 cq->ibcq.cqe = nent - 1;
759
760 cq->cqn = mthca_alloc(&dev->cq_table.alloc);
761 if (cq->cqn == -1)
762 return -ENOMEM;
763
d10ddbf6 764 if (mthca_is_memfree(dev)) {
1da177e4
LT		 765 cq->arm_sn = 1;
766
767 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
768 if (err)
769 goto err_out;
770
771 err = -ENOMEM;
772
773 cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
774 cq->cqn, &cq->set_ci_db);
775 if (cq->set_ci_db_index < 0)
776 goto err_out_icm;
777
778 cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
779 cq->cqn, &cq->arm_db);
780 if (cq->arm_db_index < 0)
781 goto err_out_ci;
782 }
783
784 mailbox = kmalloc(sizeof (struct mthca_cq_context) + MTHCA_CMD_MAILBOX_EXTRA,
785 GFP_KERNEL);
786 if (!mailbox)
787 goto err_out_mailbox;
788
789 cq_context = MAILBOX_ALIGN(mailbox);
790
791 err = mthca_alloc_cq_buf(dev, size, cq);
792 if (err)
793 goto err_out_mailbox;
794
795 for (i = 0; i < nent; ++i)
796 set_cqe_hw(get_cqe(cq, i));
797
798 spin_lock_init(&cq->lock);
799 atomic_set(&cq->refcount, 1);
800 init_waitqueue_head(&cq->wait);
801
802 memset(cq_context, 0, sizeof *cq_context);
803 cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK |
804 MTHCA_CQ_STATE_DISARMED |
805 MTHCA_CQ_FLAG_TR);
806 cq_context->start = cpu_to_be64(0);
807 cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24 |
808 dev->driver_uar.index);
809 cq_context->error_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
810 cq_context->comp_eqn = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
811 cq_context->pd = cpu_to_be32(dev->driver_pd.pd_num);
812 cq_context->lkey = cpu_to_be32(cq->mr.ibmr.lkey);
813 cq_context->cqn = cpu_to_be32(cq->cqn);
814
d10ddbf6 815 if (mthca_is_memfree(dev)) {
1da177e4
LT		 816 cq_context->ci_db = cpu_to_be32(cq->set_ci_db_index);
817 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
818 }
819
820 err = mthca_SW2HW_CQ(dev, cq_context, cq->cqn, &status);
821 if (err) {
822 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
823 goto err_out_free_mr;
824 }
825
826 if (status) {
827 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
828 status);
829 err = -EINVAL;
830 goto err_out_free_mr;
831 }
832
833 spin_lock_irq(&dev->cq_table.lock);
834 if (mthca_array_set(&dev->cq_table.cq,
835 cq->cqn & (dev->limits.num_cqs - 1),
836 cq)) {
837 spin_unlock_irq(&dev->cq_table.lock);
838 goto err_out_free_mr;
839 }
840 spin_unlock_irq(&dev->cq_table.lock);
841
842 cq->cons_index = 0;
843
844 kfree(mailbox);
845
846 return 0;
847
848err_out_free_mr:
849 mthca_free_mr(dev, &cq->mr);
850 mthca_free_cq_buf(dev, cq);
851
852err_out_mailbox:
853 kfree(mailbox);
854
d10ddbf6 855 if (mthca_is_memfree(dev))
b635fa21 856 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
1da177e4
LT		 857
858err_out_ci:
d10ddbf6 859 if (mthca_is_memfree(dev))
b635fa21 860 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
1da177e4
LT		 861
862err_out_icm:
863 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
864
865err_out:
866 mthca_free(&dev->cq_table.alloc, cq->cqn);
867
868 return err;
869}
870
871void mthca_free_cq(struct mthca_dev *dev,
872 struct mthca_cq *cq)
873{
874 void *mailbox;
875 int err;
876 u8 status;
877
878 might_sleep();
879
880 mailbox = kmalloc(sizeof (struct mthca_cq_context) + MTHCA_CMD_MAILBOX_EXTRA,
881 GFP_KERNEL);
882 if (!mailbox) {
883 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
884 return;
885 }
886
887 err = mthca_HW2SW_CQ(dev, MAILBOX_ALIGN(mailbox), cq->cqn, &status);
888 if (err)
889 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
890 else if (status)
891 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n",
892 status);
893
894 if (0) {
895 u32 *ctx = MAILBOX_ALIGN(mailbox);
896 int j;
897
898 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
899 cq->cqn, cq->cons_index, !!next_cqe_sw(cq));
900 for (j = 0; j < 16; ++j)
901 printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
902 }
903
904 spin_lock_irq(&dev->cq_table.lock);
905 mthca_array_clear(&dev->cq_table.cq,
906 cq->cqn & (dev->limits.num_cqs - 1));
907 spin_unlock_irq(&dev->cq_table.lock);
908
909 if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
910 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
911 else
912 synchronize_irq(dev->pdev->irq);
913
914 atomic_dec(&cq->refcount);
915 wait_event(cq->wait, !atomic_read(&cq->refcount));
916
917 mthca_free_mr(dev, &cq->mr);
918 mthca_free_cq_buf(dev, cq);
919
d10ddbf6 920 if (mthca_is_memfree(dev)) {
1da177e4
LT		 921 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
922 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
923 mthca_table_put(dev, dev->cq_table.table, cq->cqn);
924 }
925
926 mthca_free(&dev->cq_table.alloc, cq->cqn);
927 kfree(mailbox);
928}
929
930int __devinit mthca_init_cq_table(struct mthca_dev *dev)
931{
932 int err;
933
934 spin_lock_init(&dev->cq_table.lock);
935
936 err = mthca_alloc_init(&dev->cq_table.alloc,
937 dev->limits.num_cqs,
938 (1 << 24) - 1,
939 dev->limits.reserved_cqs);
940 if (err)
941 return err;
942
943 err = mthca_array_init(&dev->cq_table.cq,
944 dev->limits.num_cqs);
945 if (err)
946 mthca_alloc_cleanup(&dev->cq_table.alloc);
947
948 return err;
949}
950
951void __devexit mthca_cleanup_cq_table(struct mthca_dev *dev)
952{
953 mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
954 mthca_alloc_cleanup(&dev->cq_table.alloc);
955}
Clone of davem's net-next-2.6 tree