]>
Commit | Line | Data |
---|---|---|
d41d3aeb BS |
1 | #ifndef _IPATH_KERNEL_H |
2 | #define _IPATH_KERNEL_H | |
3 | /* | |
87427da5 | 4 | * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved. |
d41d3aeb BS |
5 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | /* | |
37 | * This header file is the base header file for infinipath kernel code | |
38 | * ipath_user.h serves a similar purpose for user code. | |
39 | */ | |
40 | ||
41 | #include <linux/interrupt.h> | |
1fd3b40f BS |
42 | #include <linux/pci.h> |
43 | #include <linux/dma-mapping.h> | |
d41d3aeb BS |
44 | #include <asm/io.h> |
45 | ||
46 | #include "ipath_common.h" | |
47 | #include "ipath_debug.h" | |
48 | #include "ipath_registers.h" | |
49 | ||
50 | /* only s/w major version of InfiniPath we can handle */ | |
51 | #define IPATH_CHIP_VERS_MAJ 2U | |
52 | ||
53 | /* don't care about this except printing */ | |
54 | #define IPATH_CHIP_VERS_MIN 0U | |
55 | ||
56 | /* temporary, maybe always */ | |
57 | extern struct infinipath_stats ipath_stats; | |
58 | ||
59 | #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ | |
aecd3b5a MA |
60 | /* |
61 | * First-cut critierion for "device is active" is | |
62 | * two thousand dwords combined Tx, Rx traffic per | |
63 | * 5-second interval. SMA packets are 64 dwords, | |
64 | * and occur "a few per second", presumably each way. | |
65 | */ | |
66 | #define IPATH_TRAFFIC_ACTIVE_THRESHOLD (2000) | |
67 | /* | |
68 | * Struct used to indicate which errors are logged in each of the | |
69 | * error-counters that are logged to EEPROM. A counter is incremented | |
70 | * _once_ (saturating at 255) for each event with any bits set in | |
71 | * the error or hwerror register masks below. | |
72 | */ | |
73 | #define IPATH_EEP_LOG_CNT (4) | |
74 | struct ipath_eep_log_mask { | |
75 | u64 errs_to_log; | |
76 | u64 hwerrs_to_log; | |
77 | }; | |
d41d3aeb BS |
78 | |
79 | struct ipath_portdata { | |
80 | void **port_rcvegrbuf; | |
81 | dma_addr_t *port_rcvegrbuf_phys; | |
82 | /* rcvhdrq base, needs mmap before useful */ | |
83 | void *port_rcvhdrq; | |
84 | /* kernel virtual address where hdrqtail is updated */ | |
1fd3b40f | 85 | void *port_rcvhdrtail_kvaddr; |
d41d3aeb BS |
86 | /* |
87 | * temp buffer for expected send setup, allocated at open, instead | |
88 | * of each setup call | |
89 | */ | |
90 | void *port_tid_pg_list; | |
91 | /* when waiting for rcv or pioavail */ | |
92 | wait_queue_head_t port_wait; | |
93 | /* | |
94 | * rcvegr bufs base, physical, must fit | |
95 | * in 44 bits so 32 bit programs mmap64 44 bit works) | |
96 | */ | |
97 | dma_addr_t port_rcvegr_phys; | |
98 | /* mmap of hdrq, must fit in 44 bits */ | |
99 | dma_addr_t port_rcvhdrq_phys; | |
f37bda92 | 100 | dma_addr_t port_rcvhdrqtailaddr_phys; |
d41d3aeb | 101 | /* |
9929b0fb BS |
102 | * number of opens (including slave subports) on this instance |
103 | * (ignoring forks, dup, etc. for now) | |
d41d3aeb BS |
104 | */ |
105 | int port_cnt; | |
106 | /* | |
107 | * how much space to leave at start of eager TID entries for | |
108 | * protocol use, on each TID | |
109 | */ | |
110 | /* instead of calculating it */ | |
111 | unsigned port_port; | |
9929b0fb BS |
112 | /* non-zero if port is being shared. */ |
113 | u16 port_subport_cnt; | |
114 | /* non-zero if port is being shared. */ | |
115 | u16 port_subport_id; | |
d41d3aeb BS |
116 | /* chip offset of PIO buffers for this port */ |
117 | u32 port_piobufs; | |
118 | /* how many alloc_pages() chunks in port_rcvegrbuf_pages */ | |
119 | u32 port_rcvegrbuf_chunks; | |
120 | /* how many egrbufs per chunk */ | |
121 | u32 port_rcvegrbufs_perchunk; | |
122 | /* order for port_rcvegrbuf_pages */ | |
123 | size_t port_rcvegrbuf_size; | |
124 | /* rcvhdrq size (for freeing) */ | |
125 | size_t port_rcvhdrq_size; | |
126 | /* next expected TID to check when looking for free */ | |
127 | u32 port_tidcursor; | |
128 | /* next expected TID to check */ | |
129 | unsigned long port_flag; | |
f2d04231 RW |
130 | /* what happened */ |
131 | unsigned long int_flag; | |
d41d3aeb BS |
132 | /* WAIT_RCV that timed out, no interrupt */ |
133 | u32 port_rcvwait_to; | |
134 | /* WAIT_PIO that timed out, no interrupt */ | |
135 | u32 port_piowait_to; | |
136 | /* WAIT_RCV already happened, no wait */ | |
137 | u32 port_rcvnowait; | |
138 | /* WAIT_PIO already happened, no wait */ | |
139 | u32 port_pionowait; | |
140 | /* total number of rcvhdrqfull errors */ | |
141 | u32 port_hdrqfull; | |
142 | /* pid of process using this port */ | |
143 | pid_t port_pid; | |
144 | /* same size as task_struct .comm[] */ | |
145 | char port_comm[16]; | |
146 | /* pkeys set by this use of this port */ | |
147 | u16 port_pkeys[4]; | |
148 | /* so file ops can get at unit */ | |
149 | struct ipath_devdata *port_dd; | |
9929b0fb BS |
150 | /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ |
151 | void *subport_uregbase; | |
152 | /* An array of pages for the eager receive buffers * N */ | |
153 | void *subport_rcvegrbuf; | |
154 | /* An array of pages for the eager header queue entries * N */ | |
155 | void *subport_rcvhdr_base; | |
156 | /* The version of the library which opened this port */ | |
157 | u32 userversion; | |
158 | /* Bitmask of active slaves */ | |
159 | u32 active_slaves; | |
f2d04231 RW |
160 | /* Type of packets or conditions we want to poll for */ |
161 | u16 poll_type; | |
d41d3aeb BS |
162 | }; |
163 | ||
164 | struct sk_buff; | |
165 | ||
166 | /* | |
167 | * control information for layered drivers | |
168 | */ | |
169 | struct _ipath_layer { | |
170 | void *l_arg; | |
171 | }; | |
172 | ||
1fd3b40f BS |
173 | struct ipath_skbinfo { |
174 | struct sk_buff *skb; | |
175 | dma_addr_t phys; | |
176 | }; | |
177 | ||
d41d3aeb BS |
178 | struct ipath_devdata { |
179 | struct list_head ipath_list; | |
180 | ||
181 | struct ipath_kregs const *ipath_kregs; | |
182 | struct ipath_cregs const *ipath_cregs; | |
183 | ||
184 | /* mem-mapped pointer to base of chip regs */ | |
185 | u64 __iomem *ipath_kregbase; | |
186 | /* end of mem-mapped chip space; range checking */ | |
187 | u64 __iomem *ipath_kregend; | |
188 | /* physical address of chip for io_remap, etc. */ | |
189 | unsigned long ipath_physaddr; | |
190 | /* base of memory alloced for ipath_kregbase, for free */ | |
191 | u64 *ipath_kregalloc; | |
d41d3aeb BS |
192 | /* |
193 | * virtual address where port0 rcvhdrqtail updated for this unit. | |
194 | * only written to by the chip, not the driver. | |
195 | */ | |
196 | volatile __le64 *ipath_hdrqtailptr; | |
d41d3aeb BS |
197 | /* ipath_cfgports pointers */ |
198 | struct ipath_portdata **ipath_pd; | |
199 | /* sk_buffs used by port 0 eager receive queue */ | |
1fd3b40f | 200 | struct ipath_skbinfo *ipath_port0_skbinfo; |
d41d3aeb BS |
201 | /* kvirt address of 1st 2k pio buffer */ |
202 | void __iomem *ipath_pio2kbase; | |
203 | /* kvirt address of 1st 4k pio buffer */ | |
204 | void __iomem *ipath_pio4kbase; | |
205 | /* | |
206 | * points to area where PIOavail registers will be DMA'ed. | |
207 | * Has to be on a page of it's own, because the page will be | |
208 | * mapped into user program space. This copy is *ONLY* ever | |
209 | * written by DMA, not by the driver! Need a copy per device | |
210 | * when we get to multiple devices | |
211 | */ | |
212 | volatile __le64 *ipath_pioavailregs_dma; | |
213 | /* physical address where updates occur */ | |
214 | dma_addr_t ipath_pioavailregs_phys; | |
215 | struct _ipath_layer ipath_layer; | |
216 | /* setup intr */ | |
217 | int (*ipath_f_intrsetup)(struct ipath_devdata *); | |
218 | /* setup on-chip bus config */ | |
219 | int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *); | |
220 | /* hard reset chip */ | |
221 | int (*ipath_f_reset)(struct ipath_devdata *); | |
222 | int (*ipath_f_get_boardname)(struct ipath_devdata *, char *, | |
223 | size_t); | |
224 | void (*ipath_f_init_hwerrors)(struct ipath_devdata *); | |
225 | void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *, | |
226 | size_t); | |
227 | void (*ipath_f_quiet_serdes)(struct ipath_devdata *); | |
228 | int (*ipath_f_bringup_serdes)(struct ipath_devdata *); | |
229 | int (*ipath_f_early_init)(struct ipath_devdata *); | |
230 | void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned); | |
231 | void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*, | |
232 | u32, unsigned long); | |
233 | void (*ipath_f_tidtemplate)(struct ipath_devdata *); | |
234 | void (*ipath_f_cleanup)(struct ipath_devdata *); | |
235 | void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64); | |
236 | /* fill out chip-specific fields */ | |
237 | int (*ipath_f_get_base_info)(struct ipath_portdata *, void *); | |
51f65ebc BS |
238 | /* free irq */ |
239 | void (*ipath_f_free_irq)(struct ipath_devdata *); | |
b1c1b6a3 BS |
240 | struct ipath_ibdev *verbs_dev; |
241 | struct timer_list verbs_timer; | |
d41d3aeb BS |
242 | /* total dwords sent (summed from counter) */ |
243 | u64 ipath_sword; | |
244 | /* total dwords rcvd (summed from counter) */ | |
245 | u64 ipath_rword; | |
246 | /* total packets sent (summed from counter) */ | |
247 | u64 ipath_spkts; | |
248 | /* total packets rcvd (summed from counter) */ | |
249 | u64 ipath_rpkts; | |
250 | /* ipath_statusp initially points to this. */ | |
251 | u64 _ipath_status; | |
252 | /* GUID for this interface, in network order */ | |
253 | __be64 ipath_guid; | |
254 | /* | |
255 | * aggregrate of error bits reported since last cleared, for | |
256 | * limiting of error reporting | |
257 | */ | |
258 | ipath_err_t ipath_lasterror; | |
259 | /* | |
260 | * aggregrate of error bits reported since last cleared, for | |
261 | * limiting of hwerror reporting | |
262 | */ | |
263 | ipath_err_t ipath_lasthwerror; | |
78d1e02f | 264 | /* errors masked because they occur too fast */ |
d41d3aeb BS |
265 | ipath_err_t ipath_maskederrs; |
266 | /* time in jiffies at which to re-enable maskederrs */ | |
267 | unsigned long ipath_unmasktime; | |
d41d3aeb BS |
268 | /* count of egrfull errors, combined for all ports */ |
269 | u64 ipath_last_tidfull; | |
270 | /* for ipath_qcheck() */ | |
271 | u64 ipath_lastport0rcv_cnt; | |
272 | /* template for writing TIDs */ | |
273 | u64 ipath_tidtemplate; | |
274 | /* value to write to free TIDs */ | |
275 | u64 ipath_tidinvalid; | |
525d0ca1 | 276 | /* IBA6120 rcv interrupt setup */ |
d41d3aeb BS |
277 | u64 ipath_rhdrhead_intr_off; |
278 | ||
279 | /* size of memory at ipath_kregbase */ | |
280 | u32 ipath_kregsize; | |
281 | /* number of registers used for pioavail */ | |
282 | u32 ipath_pioavregs; | |
283 | /* IPATH_POLL, etc. */ | |
284 | u32 ipath_flags; | |
0fd41363 BS |
285 | /* ipath_flags driver is waiting for */ |
286 | u32 ipath_state_wanted; | |
d41d3aeb BS |
287 | /* last buffer for user use, first buf for kernel use is this |
288 | * index. */ | |
289 | u32 ipath_lastport_piobuf; | |
290 | /* is a stats timer active */ | |
291 | u32 ipath_stats_timer_active; | |
3588423f AJ |
292 | /* number of interrupts for this device -- saturates... */ |
293 | u32 ipath_int_counter; | |
d41d3aeb BS |
294 | /* dwords sent read from counter */ |
295 | u32 ipath_lastsword; | |
296 | /* dwords received read from counter */ | |
297 | u32 ipath_lastrword; | |
298 | /* sent packets read from counter */ | |
299 | u32 ipath_lastspkts; | |
300 | /* received packets read from counter */ | |
301 | u32 ipath_lastrpkts; | |
302 | /* pio bufs allocated per port */ | |
303 | u32 ipath_pbufsport; | |
304 | /* | |
305 | * number of ports configured as max; zero is set to number chip | |
306 | * supports, less gives more pio bufs/port, etc. | |
307 | */ | |
308 | u32 ipath_cfgports; | |
309 | /* port0 rcvhdrq head offset */ | |
310 | u32 ipath_port0head; | |
311 | /* count of port 0 hdrqfull errors */ | |
312 | u32 ipath_p0_hdrqfull; | |
313 | ||
314 | /* | |
315 | * (*cfgports) used to suppress multiple instances of same | |
316 | * port staying stuck at same point | |
317 | */ | |
318 | u32 *ipath_lastrcvhdrqtails; | |
319 | /* | |
320 | * (*cfgports) used to suppress multiple instances of same | |
321 | * port staying stuck at same point | |
322 | */ | |
323 | u32 *ipath_lastegrheads; | |
324 | /* | |
325 | * index of last piobuffer we used. Speeds up searching, by | |
326 | * starting at this point. Doesn't matter if multiple cpu's use and | |
327 | * update, last updater is only write that matters. Whenever it | |
328 | * wraps, we update shadow copies. Need a copy per device when we | |
329 | * get to multiple devices | |
330 | */ | |
331 | u32 ipath_lastpioindex; | |
332 | /* max length of freezemsg */ | |
333 | u32 ipath_freezelen; | |
334 | /* | |
335 | * consecutive times we wanted a PIO buffer but were unable to | |
336 | * get one | |
337 | */ | |
338 | u32 ipath_consec_nopiobuf; | |
339 | /* | |
340 | * hint that we should update ipath_pioavailshadow before | |
341 | * looking for a PIO buffer | |
342 | */ | |
343 | u32 ipath_upd_pio_shadow; | |
344 | /* so we can rewrite it after a chip reset */ | |
345 | u32 ipath_pcibar0; | |
346 | /* so we can rewrite it after a chip reset */ | |
347 | u32 ipath_pcibar1; | |
d41d3aeb | 348 | |
51f65ebc BS |
349 | /* interrupt number */ |
350 | int ipath_irq; | |
d41d3aeb BS |
351 | /* HT/PCI Vendor ID (here for NodeInfo) */ |
352 | u16 ipath_vendorid; | |
353 | /* HT/PCI Device ID (here for NodeInfo) */ | |
354 | u16 ipath_deviceid; | |
355 | /* offset in HT config space of slave/primary interface block */ | |
356 | u8 ipath_ht_slave_off; | |
357 | /* for write combining settings */ | |
358 | unsigned long ipath_wc_cookie; | |
957670a5 BS |
359 | unsigned long ipath_wc_base; |
360 | unsigned long ipath_wc_len; | |
d41d3aeb BS |
361 | /* ref count for each pkey */ |
362 | atomic_t ipath_pkeyrefs[4]; | |
363 | /* shadow copy of all exptids physaddr; used only by funcsim */ | |
364 | u64 *ipath_tidsimshadow; | |
365 | /* shadow copy of struct page *'s for exp tid pages */ | |
366 | struct page **ipath_pageshadow; | |
1fd3b40f BS |
367 | /* shadow copy of dma handles for exp tid pages */ |
368 | dma_addr_t *ipath_physshadow; | |
d41d3aeb BS |
369 | /* lock to workaround chip bug 9437 */ |
370 | spinlock_t ipath_tid_lock; | |
371 | ||
372 | /* | |
373 | * IPATH_STATUS_*, | |
374 | * this address is mapped readonly into user processes so they can | |
375 | * get status cheaply, whenever they want. | |
376 | */ | |
377 | u64 *ipath_statusp; | |
378 | /* freeze msg if hw error put chip in freeze */ | |
379 | char *ipath_freezemsg; | |
380 | /* pci access data structure */ | |
381 | struct pci_dev *pcidev; | |
a2acb2ff BS |
382 | struct cdev *user_cdev; |
383 | struct cdev *diag_cdev; | |
384 | struct class_device *user_class_dev; | |
385 | struct class_device *diag_class_dev; | |
d41d3aeb BS |
386 | /* timer used to prevent stats overflow, error throttling, etc. */ |
387 | struct timer_list ipath_stats_timer; | |
35783ec0 BS |
388 | void *ipath_dummy_hdrq; /* used after port close */ |
389 | dma_addr_t ipath_dummy_hdrq_phys; | |
d41d3aeb BS |
390 | |
391 | /* | |
392 | * Shadow copies of registers; size indicates read access size. | |
393 | * Most of them are readonly, but some are write-only register, | |
394 | * where we manipulate the bits in the shadow copy, and then write | |
395 | * the shadow copy to infinipath. | |
396 | * | |
397 | * We deliberately make most of these 32 bits, since they have | |
398 | * restricted range. For any that we read, we won't to generate 32 | |
399 | * bit accesses, since Opteron will generate 2 separate 32 bit HT | |
400 | * transactions for a 64 bit read, and we want to avoid unnecessary | |
401 | * HT transactions. | |
402 | */ | |
403 | ||
404 | /* This is the 64 bit group */ | |
405 | ||
406 | /* | |
407 | * shadow of pioavail, check to be sure it's large enough at | |
408 | * init time. | |
409 | */ | |
410 | unsigned long ipath_pioavailshadow[8]; | |
411 | /* shadow of kr_gpio_out, for rmw ops */ | |
412 | u64 ipath_gpio_out; | |
8f140b40 AJ |
413 | /* shadow the gpio mask register */ |
414 | u64 ipath_gpio_mask; | |
17b2eb9f MA |
415 | /* shadow the gpio output enable, etc... */ |
416 | u64 ipath_extctrl; | |
d41d3aeb BS |
417 | /* kr_revision shadow */ |
418 | u64 ipath_revision; | |
419 | /* | |
420 | * shadow of ibcctrl, for interrupt handling of link changes, | |
421 | * etc. | |
422 | */ | |
423 | u64 ipath_ibcctrl; | |
424 | /* | |
425 | * last ibcstatus, to suppress "duplicate" status change messages, | |
426 | * mostly from 2 to 3 | |
427 | */ | |
428 | u64 ipath_lastibcstat; | |
429 | /* hwerrmask shadow */ | |
430 | ipath_err_t ipath_hwerrmask; | |
78d1e02f | 431 | ipath_err_t ipath_errormask; /* errormask shadow */ |
d41d3aeb BS |
432 | /* interrupt config reg shadow */ |
433 | u64 ipath_intconfig; | |
434 | /* kr_sendpiobufbase value */ | |
435 | u64 ipath_piobufbase; | |
436 | ||
437 | /* these are the "32 bit" regs */ | |
438 | ||
439 | /* | |
440 | * number of GUIDs in the flash for this interface; may need some | |
441 | * rethinking for setting on other ifaces | |
442 | */ | |
443 | u32 ipath_nguid; | |
444 | /* | |
445 | * the following two are 32-bit bitmasks, but {test,clear,set}_bit | |
446 | * all expect bit fields to be "unsigned long" | |
447 | */ | |
448 | /* shadow kr_rcvctrl */ | |
449 | unsigned long ipath_rcvctrl; | |
450 | /* shadow kr_sendctrl */ | |
451 | unsigned long ipath_sendctrl; | |
89d1e09b BS |
452 | /* ports waiting for PIOavail intr */ |
453 | unsigned long ipath_portpiowait; | |
454 | unsigned long ipath_lastcancel; /* to not count armlaunch after cancel */ | |
d41d3aeb BS |
455 | |
456 | /* value we put in kr_rcvhdrcnt */ | |
457 | u32 ipath_rcvhdrcnt; | |
458 | /* value we put in kr_rcvhdrsize */ | |
459 | u32 ipath_rcvhdrsize; | |
460 | /* value we put in kr_rcvhdrentsize */ | |
461 | u32 ipath_rcvhdrentsize; | |
462 | /* offset of last entry in rcvhdrq */ | |
463 | u32 ipath_hdrqlast; | |
464 | /* kr_portcnt value */ | |
465 | u32 ipath_portcnt; | |
466 | /* kr_pagealign value */ | |
467 | u32 ipath_palign; | |
468 | /* number of "2KB" PIO buffers */ | |
469 | u32 ipath_piobcnt2k; | |
470 | /* size in bytes of "2KB" PIO buffers */ | |
471 | u32 ipath_piosize2k; | |
472 | /* number of "4KB" PIO buffers */ | |
473 | u32 ipath_piobcnt4k; | |
474 | /* size in bytes of "4KB" PIO buffers */ | |
475 | u32 ipath_piosize4k; | |
476 | /* kr_rcvegrbase value */ | |
477 | u32 ipath_rcvegrbase; | |
478 | /* kr_rcvegrcnt value */ | |
479 | u32 ipath_rcvegrcnt; | |
480 | /* kr_rcvtidbase value */ | |
481 | u32 ipath_rcvtidbase; | |
482 | /* kr_rcvtidcnt value */ | |
483 | u32 ipath_rcvtidcnt; | |
484 | /* kr_sendregbase */ | |
485 | u32 ipath_sregbase; | |
486 | /* kr_userregbase */ | |
487 | u32 ipath_uregbase; | |
488 | /* kr_counterregbase */ | |
489 | u32 ipath_cregbase; | |
490 | /* shadow the control register contents */ | |
491 | u32 ipath_control; | |
d41d3aeb BS |
492 | /* PCI revision register (HTC rev on FPGA) */ |
493 | u32 ipath_pcirev; | |
494 | ||
495 | /* chip address space used by 4k pio buffers */ | |
496 | u32 ipath_4kalign; | |
497 | /* The MTU programmed for this unit */ | |
498 | u32 ipath_ibmtu; | |
499 | /* | |
500 | * The max size IB packet, included IB headers that we can send. | |
501 | * Starts same as ipath_piosize, but is affected when ibmtu is | |
502 | * changed, or by size of eager buffers | |
503 | */ | |
504 | u32 ipath_ibmaxlen; | |
505 | /* | |
506 | * ibmaxlen at init time, limited by chip and by receive buffer | |
507 | * size. Not changed after init. | |
508 | */ | |
509 | u32 ipath_init_ibmaxlen; | |
510 | /* size of each rcvegrbuffer */ | |
511 | u32 ipath_rcvegrbufsize; | |
512 | /* width (2,4,8,16,32) from HT config reg */ | |
513 | u32 ipath_htwidth; | |
514 | /* HT speed (200,400,800,1000) from HT config */ | |
515 | u32 ipath_htspeed; | |
d41d3aeb BS |
516 | /* |
517 | * number of sequential ibcstatus change for polling active/quiet | |
518 | * (i.e., link not coming up). | |
519 | */ | |
520 | u32 ipath_ibpollcnt; | |
521 | /* low and high portions of MSI capability/vector */ | |
522 | u32 ipath_msi_lo; | |
523 | /* saved after PCIe init for restore after reset */ | |
524 | u32 ipath_msi_hi; | |
525 | /* MSI data (vector) saved for restore */ | |
526 | u16 ipath_msi_data; | |
527 | /* MLID programmed for this instance */ | |
528 | u16 ipath_mlid; | |
529 | /* LID programmed for this instance */ | |
530 | u16 ipath_lid; | |
531 | /* list of pkeys programmed; 0 if not set */ | |
532 | u16 ipath_pkeys[4]; | |
8307c28e BS |
533 | /* |
534 | * ASCII serial number, from flash, large enough for original | |
535 | * all digit strings, and longer QLogic serial number format | |
536 | */ | |
537 | u8 ipath_serial[16]; | |
d41d3aeb BS |
538 | /* human readable board version */ |
539 | u8 ipath_boardversion[80]; | |
540 | /* chip major rev, from ipath_revision */ | |
541 | u8 ipath_majrev; | |
542 | /* chip minor rev, from ipath_revision */ | |
543 | u8 ipath_minrev; | |
544 | /* board rev, from ipath_revision */ | |
545 | u8 ipath_boardrev; | |
546 | /* unit # of this chip, if present */ | |
547 | int ipath_unit; | |
548 | /* saved for restore after reset */ | |
549 | u8 ipath_pci_cacheline; | |
550 | /* LID mask control */ | |
551 | u8 ipath_lmc; | |
30fc5c31 BS |
552 | /* Rx Polarity inversion (compensate for ~tx on partner) */ |
553 | u8 ipath_rx_pol_inv; | |
fba75200 BS |
554 | |
555 | /* local link integrity counter */ | |
556 | u32 ipath_lli_counter; | |
557 | /* local link integrity errors */ | |
558 | u32 ipath_lli_errors; | |
2c9446a1 BS |
559 | /* |
560 | * Above counts only cases where _successive_ LocalLinkIntegrity | |
561 | * errors were seen in the receive headers of kern-packets. | |
562 | * Below are the three (monotonically increasing) counters | |
563 | * maintained via GPIO interrupts on iba6120-rev2. | |
564 | */ | |
565 | u32 ipath_rxfc_unsupvl_errs; | |
566 | u32 ipath_overrun_thresh_errs; | |
567 | u32 ipath_lli_errs; | |
f62fe77a | 568 | |
3588423f AJ |
569 | /* status check work */ |
570 | struct delayed_work status_work; | |
571 | ||
f62fe77a BS |
572 | /* |
573 | * Not all devices managed by a driver instance are the same | |
574 | * type, so these fields must be per-device. | |
575 | */ | |
576 | u64 ipath_i_bitsextant; | |
577 | ipath_err_t ipath_e_bitsextant; | |
578 | ipath_err_t ipath_hwe_bitsextant; | |
579 | ||
580 | /* | |
581 | * Below should be computable from number of ports, | |
582 | * since they are never modified. | |
583 | */ | |
584 | u32 ipath_i_rcvavail_mask; | |
585 | u32 ipath_i_rcvurg_mask; | |
586 | ||
587 | /* | |
588 | * Register bits for selecting i2c direction and values, used for | |
589 | * I2C serial flash. | |
590 | */ | |
591 | u16 ipath_gpio_sda_num; | |
592 | u16 ipath_gpio_scl_num; | |
593 | u64 ipath_gpio_sda; | |
594 | u64 ipath_gpio_scl; | |
82466f00 | 595 | |
17b2eb9f MA |
596 | /* lock for doing RMW of shadows/regs for ExtCtrl and GPIO */ |
597 | spinlock_t ipath_gpio_lock; | |
598 | ||
82466f00 MA |
599 | /* used to override LED behavior */ |
600 | u8 ipath_led_override; /* Substituted for normal value, if non-zero */ | |
601 | u16 ipath_led_override_timeoff; /* delta to next timer event */ | |
602 | u8 ipath_led_override_vals[2]; /* Alternates per blink-frame */ | |
603 | u8 ipath_led_override_phase; /* Just counts, LSB picks from vals[] */ | |
604 | atomic_t ipath_led_override_timer_active; | |
605 | /* Used to flash LEDs in override mode */ | |
606 | struct timer_list ipath_led_override_timer; | |
607 | ||
aecd3b5a MA |
608 | /* Support (including locks) for EEPROM logging of errors and time */ |
609 | /* control access to actual counters, timer */ | |
610 | spinlock_t ipath_eep_st_lock; | |
611 | /* control high-level access to EEPROM */ | |
612 | struct semaphore ipath_eep_sem; | |
613 | /* Below inc'd by ipath_snap_cntrs(), locked by ipath_eep_st_lock */ | |
614 | uint64_t ipath_traffic_wds; | |
615 | /* active time is kept in seconds, but logged in hours */ | |
616 | atomic_t ipath_active_time; | |
617 | /* Below are nominal shadow of EEPROM, new since last EEPROM update */ | |
618 | uint8_t ipath_eep_st_errs[IPATH_EEP_LOG_CNT]; | |
619 | uint8_t ipath_eep_st_new_errs[IPATH_EEP_LOG_CNT]; | |
620 | uint16_t ipath_eep_hrs; | |
621 | /* | |
622 | * masks for which bits of errs, hwerrs that cause | |
623 | * each of the counters to increment. | |
624 | */ | |
625 | struct ipath_eep_log_mask ipath_eep_st_masks[IPATH_EEP_LOG_CNT]; | |
d41d3aeb BS |
626 | }; |
627 | ||
9929b0fb BS |
628 | /* Private data for file operations */ |
629 | struct ipath_filedata { | |
630 | struct ipath_portdata *pd; | |
631 | unsigned subport; | |
632 | unsigned tidcursor; | |
633 | }; | |
d41d3aeb BS |
634 | extern struct list_head ipath_dev_list; |
635 | extern spinlock_t ipath_devs_lock; | |
636 | extern struct ipath_devdata *ipath_lookup(int unit); | |
637 | ||
d41d3aeb BS |
638 | int ipath_init_chip(struct ipath_devdata *, int); |
639 | int ipath_enable_wc(struct ipath_devdata *dd); | |
640 | void ipath_disable_wc(struct ipath_devdata *dd); | |
641 | int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp); | |
642 | void ipath_shutdown_device(struct ipath_devdata *); | |
0f4fc5eb | 643 | void ipath_clear_freeze(struct ipath_devdata *); |
d41d3aeb BS |
644 | |
645 | struct file_operations; | |
2b8693c0 | 646 | int ipath_cdev_init(int minor, char *name, const struct file_operations *fops, |
d41d3aeb BS |
647 | struct cdev **cdevp, struct class_device **class_devp); |
648 | void ipath_cdev_cleanup(struct cdev **cdevp, | |
649 | struct class_device **class_devp); | |
650 | ||
a2acb2ff BS |
651 | int ipath_diag_add(struct ipath_devdata *); |
652 | void ipath_diag_remove(struct ipath_devdata *); | |
d41d3aeb | 653 | |
0fd41363 | 654 | extern wait_queue_head_t ipath_state_wait; |
d41d3aeb BS |
655 | |
656 | int ipath_user_add(struct ipath_devdata *dd); | |
a2acb2ff | 657 | void ipath_user_remove(struct ipath_devdata *dd); |
d41d3aeb BS |
658 | |
659 | struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t); | |
660 | ||
661 | extern int ipath_diag_inuse; | |
662 | ||
7d12e780 | 663 | irqreturn_t ipath_intr(int irq, void *devid); |
8ec1077b | 664 | int ipath_decode_err(char *buf, size_t blen, ipath_err_t err); |
d41d3aeb BS |
665 | #if __IPATH_INFO || __IPATH_DBG |
666 | extern const char *ipath_ibcstatus_str[]; | |
667 | #endif | |
668 | ||
669 | /* clean up any per-chip chip-specific stuff */ | |
670 | void ipath_chip_cleanup(struct ipath_devdata *); | |
671 | /* clean up any chip type-specific stuff */ | |
672 | void ipath_chip_done(void); | |
673 | ||
674 | /* check to see if we have to force ordering for write combining */ | |
675 | int ipath_unordered_wc(void); | |
676 | ||
677 | void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first, | |
678 | unsigned cnt); | |
3810f2a8 | 679 | void ipath_cancel_sends(struct ipath_devdata *, int); |
d41d3aeb BS |
680 | |
681 | int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *); | |
f37bda92 | 682 | void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *); |
d41d3aeb BS |
683 | |
684 | int ipath_parse_ushort(const char *str, unsigned short *valp); | |
685 | ||
d41d3aeb BS |
686 | void ipath_kreceive(struct ipath_devdata *); |
687 | int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned); | |
688 | int ipath_reset_device(int); | |
689 | void ipath_get_faststats(unsigned long); | |
34b2aafe BS |
690 | int ipath_set_linkstate(struct ipath_devdata *, u8); |
691 | int ipath_set_mtu(struct ipath_devdata *, u16); | |
692 | int ipath_set_lid(struct ipath_devdata *, u32, u8); | |
30fc5c31 | 693 | int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv); |
d41d3aeb BS |
694 | |
695 | /* for use in system calls, where we want to know device type, etc. */ | |
9929b0fb BS |
696 | #define port_fp(fp) ((struct ipath_filedata *)(fp)->private_data)->pd |
697 | #define subport_fp(fp) \ | |
698 | ((struct ipath_filedata *)(fp)->private_data)->subport | |
699 | #define tidcursor_fp(fp) \ | |
700 | ((struct ipath_filedata *)(fp)->private_data)->tidcursor | |
d41d3aeb BS |
701 | |
702 | /* | |
703 | * values for ipath_flags | |
704 | */ | |
705 | /* The chip is up and initted */ | |
706 | #define IPATH_INITTED 0x2 | |
707 | /* set if any user code has set kr_rcvhdrsize */ | |
708 | #define IPATH_RCVHDRSZ_SET 0x4 | |
709 | /* The chip is present and valid for accesses */ | |
710 | #define IPATH_PRESENT 0x8 | |
711 | /* HT link0 is only 8 bits wide, ignore upper byte crc | |
712 | * errors, etc. */ | |
713 | #define IPATH_8BIT_IN_HT0 0x10 | |
714 | /* HT link1 is only 8 bits wide, ignore upper byte crc | |
715 | * errors, etc. */ | |
716 | #define IPATH_8BIT_IN_HT1 0x20 | |
717 | /* The link is down */ | |
718 | #define IPATH_LINKDOWN 0x40 | |
719 | /* The link level is up (0x11) */ | |
720 | #define IPATH_LINKINIT 0x80 | |
721 | /* The link is in the armed (0x21) state */ | |
722 | #define IPATH_LINKARMED 0x100 | |
723 | /* The link is in the active (0x31) state */ | |
724 | #define IPATH_LINKACTIVE 0x200 | |
725 | /* link current state is unknown */ | |
726 | #define IPATH_LINKUNK 0x400 | |
727 | /* no IB cable, or no device on IB cable */ | |
728 | #define IPATH_NOCABLE 0x4000 | |
729 | /* Supports port zero per packet receive interrupts via | |
730 | * GPIO */ | |
731 | #define IPATH_GPIO_INTR 0x8000 | |
732 | /* uses the coded 4byte TID, not 8 byte */ | |
733 | #define IPATH_4BYTE_TID 0x10000 | |
734 | /* packet/word counters are 32 bit, else those 4 counters | |
735 | * are 64bit */ | |
736 | #define IPATH_32BITCOUNTERS 0x20000 | |
737 | /* can miss port0 rx interrupts */ | |
d41d3aeb | 738 | #define IPATH_DISABLED 0x80000 /* administratively disabled */ |
2c9446a1 BS |
739 | /* Use GPIO interrupts for new counters */ |
740 | #define IPATH_GPIO_ERRINTRS 0x100000 | |
741 | ||
742 | /* Bits in GPIO for the added interrupts */ | |
743 | #define IPATH_GPIO_PORT0_BIT 2 | |
744 | #define IPATH_GPIO_RXUVL_BIT 3 | |
745 | #define IPATH_GPIO_OVRUN_BIT 4 | |
746 | #define IPATH_GPIO_LLI_BIT 5 | |
747 | #define IPATH_GPIO_ERRINTR_MASK 0x38 | |
d41d3aeb BS |
748 | |
749 | /* portdata flag bit offsets */ | |
750 | /* waiting for a packet to arrive */ | |
751 | #define IPATH_PORT_WAITING_RCV 2 | |
752 | /* waiting for a PIO buffer to be available */ | |
753 | #define IPATH_PORT_WAITING_PIO 3 | |
947d7617 RC |
754 | /* master has not finished initializing */ |
755 | #define IPATH_PORT_MASTER_UNINIT 4 | |
f2d04231 RW |
756 | /* waiting for an urgent packet to arrive */ |
757 | #define IPATH_PORT_WAITING_URG 5 | |
758 | /* waiting for a header overflow */ | |
759 | #define IPATH_PORT_WAITING_OVERFLOW 6 | |
d41d3aeb BS |
760 | |
761 | /* free up any allocated data at closes */ | |
762 | void ipath_free_data(struct ipath_portdata *dd); | |
763 | int ipath_waitfor_mdio_cmdready(struct ipath_devdata *); | |
764 | int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *); | |
765 | u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *); | |
525d0ca1 BS |
766 | void ipath_init_iba6120_funcs(struct ipath_devdata *); |
767 | void ipath_init_iba6110_funcs(struct ipath_devdata *); | |
f2080fa3 | 768 | void ipath_get_eeprom_info(struct ipath_devdata *); |
aecd3b5a MA |
769 | int ipath_update_eeprom_log(struct ipath_devdata *dd); |
770 | void ipath_inc_eeprom_err(struct ipath_devdata *dd, u32 eidx, u32 incr); | |
d41d3aeb BS |
771 | u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg); |
772 | ||
82466f00 MA |
773 | /* |
774 | * Set LED override, only the two LSBs have "public" meaning, but | |
775 | * any non-zero value substitutes them for the Link and LinkTrain | |
776 | * LED states. | |
777 | */ | |
778 | #define IPATH_LED_PHYS 1 /* Physical (linktraining) GREEN LED */ | |
779 | #define IPATH_LED_LOG 2 /* Logical (link) YELLOW LED */ | |
780 | void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val); | |
781 | ||
d41d3aeb BS |
782 | /* |
783 | * number of words used for protocol header if not set by ipath_userinit(); | |
784 | */ | |
785 | #define IPATH_DFLT_RCVHDRSIZE 9 | |
786 | ||
787 | #define IPATH_MDIO_CMD_WRITE 1 | |
788 | #define IPATH_MDIO_CMD_READ 2 | |
789 | #define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */ | |
790 | #define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */ | |
791 | #define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */ | |
792 | #define IPATH_MDIO_CTRL_STD 0x0 | |
793 | ||
794 | static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data) | |
795 | { | |
796 | return (((u64) IPATH_MDIO_CLD_DIV) << 32) | | |
797 | (cmd << 26) | | |
798 | (dev << 21) | | |
799 | (reg << 16) | | |
800 | (data & 0xFFFF); | |
801 | } | |
802 | ||
803 | /* signal and fifo status, in bank 31 */ | |
804 | #define IPATH_MDIO_CTRL_XGXS_REG_8 0x8 | |
805 | /* controls loopback, redundancy */ | |
806 | #define IPATH_MDIO_CTRL_8355_REG_1 0x10 | |
807 | /* premph, encdec, etc. */ | |
808 | #define IPATH_MDIO_CTRL_8355_REG_2 0x11 | |
809 | /* Kchars, etc. */ | |
810 | #define IPATH_MDIO_CTRL_8355_REG_6 0x15 | |
811 | #define IPATH_MDIO_CTRL_8355_REG_9 0x18 | |
812 | #define IPATH_MDIO_CTRL_8355_REG_10 0x1D | |
813 | ||
814 | int ipath_get_user_pages(unsigned long, size_t, struct page **); | |
d41d3aeb BS |
815 | void ipath_release_user_pages(struct page **, size_t); |
816 | void ipath_release_user_pages_on_close(struct page **, size_t); | |
817 | int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int); | |
818 | int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int); | |
819 | ||
820 | /* these are used for the registers that vary with port */ | |
821 | void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg, | |
822 | unsigned, u64); | |
d41d3aeb BS |
823 | |
824 | /* | |
825 | * We could have a single register get/put routine, that takes a group type, | |
826 | * but this is somewhat clearer and cleaner. It also gives us some error | |
827 | * checking. 64 bit register reads should always work, but are inefficient | |
828 | * on opteron (the northbridge always generates 2 separate HT 32 bit reads), | |
829 | * so we use kreg32 wherever possible. User register and counter register | |
830 | * reads are always 32 bit reads, so only one form of those routines. | |
831 | */ | |
832 | ||
833 | /* | |
834 | * At the moment, none of the s-registers are writable, so no | |
835 | * ipath_write_sreg(), and none of the c-registers are writable, so no | |
836 | * ipath_write_creg(). | |
837 | */ | |
838 | ||
839 | /** | |
840 | * ipath_read_ureg32 - read 32-bit virtualized per-port register | |
841 | * @dd: device | |
842 | * @regno: register number | |
843 | * @port: port number | |
844 | * | |
845 | * Return the contents of a register that is virtualized to be per port. | |
685f97e8 BS |
846 | * Returns -1 on errors (not distinguishable from valid contents at |
847 | * runtime; we may add a separate error variable at some point). | |
d41d3aeb BS |
848 | */ |
849 | static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd, | |
850 | ipath_ureg regno, int port) | |
851 | { | |
c71c30dc | 852 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
853 | return 0; |
854 | ||
855 | return readl(regno + (u64 __iomem *) | |
856 | (dd->ipath_uregbase + | |
857 | (char __iomem *)dd->ipath_kregbase + | |
858 | dd->ipath_palign * port)); | |
859 | } | |
860 | ||
861 | /** | |
862 | * ipath_write_ureg - write 32-bit virtualized per-port register | |
863 | * @dd: device | |
864 | * @regno: register number | |
865 | * @value: value | |
866 | * @port: port | |
867 | * | |
868 | * Write the contents of a register that is virtualized to be per port. | |
869 | */ | |
870 | static inline void ipath_write_ureg(const struct ipath_devdata *dd, | |
871 | ipath_ureg regno, u64 value, int port) | |
872 | { | |
873 | u64 __iomem *ubase = (u64 __iomem *) | |
874 | (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase + | |
875 | dd->ipath_palign * port); | |
876 | if (dd->ipath_kregbase) | |
877 | writeq(value, &ubase[regno]); | |
878 | } | |
879 | ||
880 | static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd, | |
881 | ipath_kreg regno) | |
882 | { | |
c71c30dc | 883 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
884 | return -1; |
885 | return readl((u32 __iomem *) & dd->ipath_kregbase[regno]); | |
886 | } | |
887 | ||
888 | static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd, | |
889 | ipath_kreg regno) | |
890 | { | |
c71c30dc | 891 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
892 | return -1; |
893 | ||
894 | return readq(&dd->ipath_kregbase[regno]); | |
895 | } | |
896 | ||
897 | static inline void ipath_write_kreg(const struct ipath_devdata *dd, | |
898 | ipath_kreg regno, u64 value) | |
899 | { | |
900 | if (dd->ipath_kregbase) | |
901 | writeq(value, &dd->ipath_kregbase[regno]); | |
902 | } | |
903 | ||
904 | static inline u64 ipath_read_creg(const struct ipath_devdata *dd, | |
905 | ipath_sreg regno) | |
906 | { | |
c71c30dc | 907 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
908 | return 0; |
909 | ||
910 | return readq(regno + (u64 __iomem *) | |
911 | (dd->ipath_cregbase + | |
912 | (char __iomem *)dd->ipath_kregbase)); | |
913 | } | |
914 | ||
915 | static inline u32 ipath_read_creg32(const struct ipath_devdata *dd, | |
916 | ipath_sreg regno) | |
917 | { | |
c71c30dc | 918 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
919 | return 0; |
920 | return readl(regno + (u64 __iomem *) | |
921 | (dd->ipath_cregbase + | |
922 | (char __iomem *)dd->ipath_kregbase)); | |
923 | } | |
924 | ||
925 | /* | |
926 | * sysfs interface. | |
927 | */ | |
928 | ||
929 | struct device_driver; | |
930 | ||
b55f4f06 | 931 | extern const char ib_ipath_version[]; |
d41d3aeb BS |
932 | |
933 | int ipath_driver_create_group(struct device_driver *); | |
934 | void ipath_driver_remove_group(struct device_driver *); | |
935 | ||
936 | int ipath_device_create_group(struct device *, struct ipath_devdata *); | |
937 | void ipath_device_remove_group(struct device *, struct ipath_devdata *); | |
938 | int ipath_expose_reset(struct device *); | |
939 | ||
940 | int ipath_init_ipathfs(void); | |
941 | void ipath_exit_ipathfs(void); | |
942 | int ipathfs_add_device(struct ipath_devdata *); | |
943 | int ipathfs_remove_device(struct ipath_devdata *); | |
944 | ||
1fd3b40f BS |
945 | /* |
946 | * dma_addr wrappers - all 0's invalid for hw | |
947 | */ | |
948 | dma_addr_t ipath_map_page(struct pci_dev *, struct page *, unsigned long, | |
949 | size_t, int); | |
950 | dma_addr_t ipath_map_single(struct pci_dev *, void *, size_t, int); | |
951 | ||
d41d3aeb BS |
952 | /* |
953 | * Flush write combining store buffers (if present) and perform a write | |
954 | * barrier. | |
955 | */ | |
956 | #if defined(CONFIG_X86_64) | |
957 | #define ipath_flush_wc() asm volatile("sfence" ::: "memory") | |
958 | #else | |
959 | #define ipath_flush_wc() wmb() | |
960 | #endif | |
961 | ||
962 | extern unsigned ipath_debug; /* debugging bit mask */ | |
963 | ||
9783ab40 BS |
964 | #define IPATH_MAX_PARITY_ATTEMPTS 10000 /* max times to try recovery */ |
965 | ||
d41d3aeb BS |
966 | const char *ipath_get_unit_name(int unit); |
967 | ||
968 | extern struct mutex ipath_mutex; | |
969 | ||
b55f4f06 | 970 | #define IPATH_DRV_NAME "ib_ipath" |
d41d3aeb | 971 | #define IPATH_MAJOR 233 |
a2acb2ff | 972 | #define IPATH_USER_MINOR_BASE 0 |
98341f26 | 973 | #define IPATH_DIAGPKT_MINOR 127 |
a2acb2ff BS |
974 | #define IPATH_DIAG_MINOR_BASE 129 |
975 | #define IPATH_NMINORS 255 | |
d41d3aeb BS |
976 | |
977 | #define ipath_dev_err(dd,fmt,...) \ | |
978 | do { \ | |
979 | const struct ipath_devdata *__dd = (dd); \ | |
980 | if (__dd->pcidev) \ | |
981 | dev_err(&__dd->pcidev->dev, "%s: " fmt, \ | |
982 | ipath_get_unit_name(__dd->ipath_unit), \ | |
983 | ##__VA_ARGS__); \ | |
984 | else \ | |
985 | printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \ | |
986 | ipath_get_unit_name(__dd->ipath_unit), \ | |
987 | ##__VA_ARGS__); \ | |
988 | } while (0) | |
989 | ||
990 | #if _IPATH_DEBUGGING | |
991 | ||
992 | # define __IPATH_DBG_WHICH(which,fmt,...) \ | |
993 | do { \ | |
994 | if(unlikely(ipath_debug&(which))) \ | |
995 | printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \ | |
996 | __func__,##__VA_ARGS__); \ | |
997 | } while(0) | |
998 | ||
999 | # define ipath_dbg(fmt,...) \ | |
1000 | __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__) | |
1001 | # define ipath_cdbg(which,fmt,...) \ | |
1002 | __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__) | |
1003 | ||
1004 | #else /* ! _IPATH_DEBUGGING */ | |
1005 | ||
1006 | # define ipath_dbg(fmt,...) | |
1007 | # define ipath_cdbg(which,fmt,...) | |
1008 | ||
1009 | #endif /* _IPATH_DEBUGGING */ | |
1010 | ||
8d588f8b BS |
1011 | /* |
1012 | * this is used for formatting hw error messages... | |
1013 | */ | |
1014 | struct ipath_hwerror_msgs { | |
1015 | u64 mask; | |
1016 | const char *msg; | |
1017 | }; | |
1018 | ||
1019 | #define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b } | |
1020 | ||
1021 | /* in ipath_intr.c... */ | |
1022 | void ipath_format_hwerrors(u64 hwerrs, | |
1023 | const struct ipath_hwerror_msgs *hwerrmsgs, | |
1024 | size_t nhwerrmsgs, | |
1025 | char *msg, size_t lmsg); | |
1026 | ||
d41d3aeb | 1027 | #endif /* _IPATH_KERNEL_H */ |