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IB/ipath: Drop support for the original QHT7040 board
[net-next-2.6.git] / drivers / infiniband / hw / ipath / ipath_iba6110.c
CommitLineData
cc533a57 1/*
87427da5 2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
cc533a57
BS		 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34/*
35 * This file contains all of the code that is specific to the InfiniPath
525d0ca1 36 * HT chip.
cc533a57
BS		 37 */
38
a024291b 39#include <linux/vmalloc.h>
cc533a57
BS		 40#include <linux/pci.h>
41#include <linux/delay.h>
51f65ebc 42#include <linux/htirq.h>
cc533a57
BS		 43
44#include "ipath_kernel.h"
45#include "ipath_registers.h"
46
f5408ac7
BS		 47static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64);
48
49
cc533a57 50/*
525d0ca1 51 * This lists the InfiniPath registers, in the actual chip layout.
cc533a57
BS		 52 * This structure should never be directly accessed.
53 *
54 * The names are in InterCap form because they're taken straight from
55 * the chip specification. Since they're only used in this file, they
56 * don't pollute the rest of the source.
57*/
58
59struct _infinipath_do_not_use_kernel_regs {
60 unsigned long long Revision;
61 unsigned long long Control;
62 unsigned long long PageAlign;
63 unsigned long long PortCnt;
64 unsigned long long DebugPortSelect;
65 unsigned long long DebugPort;
66 unsigned long long SendRegBase;
67 unsigned long long UserRegBase;
68 unsigned long long CounterRegBase;
69 unsigned long long Scratch;
70 unsigned long long ReservedMisc1;
71 unsigned long long InterruptConfig;
72 unsigned long long IntBlocked;
73 unsigned long long IntMask;
74 unsigned long long IntStatus;
75 unsigned long long IntClear;
76 unsigned long long ErrorMask;
77 unsigned long long ErrorStatus;
78 unsigned long long ErrorClear;
79 unsigned long long HwErrMask;
80 unsigned long long HwErrStatus;
81 unsigned long long HwErrClear;
82 unsigned long long HwDiagCtrl;
83 unsigned long long MDIO;
84 unsigned long long IBCStatus;
85 unsigned long long IBCCtrl;
86 unsigned long long ExtStatus;
87 unsigned long long ExtCtrl;
88 unsigned long long GPIOOut;
89 unsigned long long GPIOMask;
90 unsigned long long GPIOStatus;
91 unsigned long long GPIOClear;
92 unsigned long long RcvCtrl;
93 unsigned long long RcvBTHQP;
94 unsigned long long RcvHdrSize;
95 unsigned long long RcvHdrCnt;
96 unsigned long long RcvHdrEntSize;
97 unsigned long long RcvTIDBase;
98 unsigned long long RcvTIDCnt;
99 unsigned long long RcvEgrBase;
100 unsigned long long RcvEgrCnt;
101 unsigned long long RcvBufBase;
102 unsigned long long RcvBufSize;
103 unsigned long long RxIntMemBase;
104 unsigned long long RxIntMemSize;
105 unsigned long long RcvPartitionKey;
106 unsigned long long ReservedRcv[10];
107 unsigned long long SendCtrl;
108 unsigned long long SendPIOBufBase;
109 unsigned long long SendPIOSize;
110 unsigned long long SendPIOBufCnt;
111 unsigned long long SendPIOAvailAddr;
112 unsigned long long TxIntMemBase;
113 unsigned long long TxIntMemSize;
114 unsigned long long ReservedSend[9];
115 unsigned long long SendBufferError;
116 unsigned long long SendBufferErrorCONT1;
117 unsigned long long SendBufferErrorCONT2;
118 unsigned long long SendBufferErrorCONT3;
119 unsigned long long ReservedSBE[4];
120 unsigned long long RcvHdrAddr0;
121 unsigned long long RcvHdrAddr1;
122 unsigned long long RcvHdrAddr2;
123 unsigned long long RcvHdrAddr3;
124 unsigned long long RcvHdrAddr4;
125 unsigned long long RcvHdrAddr5;
126 unsigned long long RcvHdrAddr6;
127 unsigned long long RcvHdrAddr7;
128 unsigned long long RcvHdrAddr8;
129 unsigned long long ReservedRHA[7];
130 unsigned long long RcvHdrTailAddr0;
131 unsigned long long RcvHdrTailAddr1;
132 unsigned long long RcvHdrTailAddr2;
133 unsigned long long RcvHdrTailAddr3;
134 unsigned long long RcvHdrTailAddr4;
135 unsigned long long RcvHdrTailAddr5;
136 unsigned long long RcvHdrTailAddr6;
137 unsigned long long RcvHdrTailAddr7;
138 unsigned long long RcvHdrTailAddr8;
139 unsigned long long ReservedRHTA[7];
140 unsigned long long Sync; /* Software only */
141 unsigned long long Dump; /* Software only */
142 unsigned long long SimVer; /* Software only */
143 unsigned long long ReservedSW[5];
144 unsigned long long SerdesConfig0;
145 unsigned long long SerdesConfig1;
146 unsigned long long SerdesStatus;
147 unsigned long long XGXSConfig;
148 unsigned long long ReservedSW2[4];
149};
150
3029fcc3
RC		 151struct _infinipath_do_not_use_counters {
152 __u64 LBIntCnt;
153 __u64 LBFlowStallCnt;
154 __u64 Reserved1;
155 __u64 TxUnsupVLErrCnt;
156 __u64 TxDataPktCnt;
157 __u64 TxFlowPktCnt;
158 __u64 TxDwordCnt;
159 __u64 TxLenErrCnt;
160 __u64 TxMaxMinLenErrCnt;
161 __u64 TxUnderrunCnt;
162 __u64 TxFlowStallCnt;
163 __u64 TxDroppedPktCnt;
164 __u64 RxDroppedPktCnt;
165 __u64 RxDataPktCnt;
166 __u64 RxFlowPktCnt;
167 __u64 RxDwordCnt;
168 __u64 RxLenErrCnt;
169 __u64 RxMaxMinLenErrCnt;
170 __u64 RxICRCErrCnt;
171 __u64 RxVCRCErrCnt;
172 __u64 RxFlowCtrlErrCnt;
173 __u64 RxBadFormatCnt;
174 __u64 RxLinkProblemCnt;
175 __u64 RxEBPCnt;
176 __u64 RxLPCRCErrCnt;
177 __u64 RxBufOvflCnt;
178 __u64 RxTIDFullErrCnt;
179 __u64 RxTIDValidErrCnt;
180 __u64 RxPKeyMismatchCnt;
181 __u64 RxP0HdrEgrOvflCnt;
182 __u64 RxP1HdrEgrOvflCnt;
183 __u64 RxP2HdrEgrOvflCnt;
184 __u64 RxP3HdrEgrOvflCnt;
185 __u64 RxP4HdrEgrOvflCnt;
186 __u64 RxP5HdrEgrOvflCnt;
187 __u64 RxP6HdrEgrOvflCnt;
188 __u64 RxP7HdrEgrOvflCnt;
189 __u64 RxP8HdrEgrOvflCnt;
190 __u64 Reserved6;
191 __u64 Reserved7;
192 __u64 IBStatusChangeCnt;
193 __u64 IBLinkErrRecoveryCnt;
194 __u64 IBLinkDownedCnt;
195 __u64 IBSymbolErrCnt;
196};
197
198#define IPATH_KREG_OFFSET(field) (offsetof( \
199 struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
cc533a57 200#define IPATH_CREG_OFFSET(field) (offsetof( \
3029fcc3 201 struct _infinipath_do_not_use_counters, field) / sizeof(u64))
cc533a57
BS		 202
203static const struct ipath_kregs ipath_ht_kregs = {
204 .kr_control = IPATH_KREG_OFFSET(Control),
205 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
206 .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
207 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
208 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
209 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
210 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
211 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
212 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
213 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
214 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
215 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
216 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
217 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
218 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
219 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
220 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
221 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
222 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
223 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
224 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
225 .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
226 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
227 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
228 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
229 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
230 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
231 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
232 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
233 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
234 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
235 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
236 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
237 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
238 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
239 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
240 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
241 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
242 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
243 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
244 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
245 .kr_revision = IPATH_KREG_OFFSET(Revision),
246 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
247 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
248 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
249 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
250 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
251 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
252 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
253 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
254 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
255 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
256 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
257 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
258 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
259 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
260 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
261 /*
c8c6f5d4
BS		 262 * These should not be used directly via ipath_write_kreg64(),
263 * use them with ipath_write_kreg64_port(),
cc533a57
BS		 264 */
265 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
266 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
267};
268
269static const struct ipath_cregs ipath_ht_cregs = {
270 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
271 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
272 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
273 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
274 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
275 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
276 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
277 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
278 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
279 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
280 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
281 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
282 /* calc from Reg_CounterRegBase + offset */
283 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
284 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
285 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
286 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
287 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
288 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
289 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
290 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
291 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
292 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
293 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
294 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
295 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
296 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
297 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
298 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
299 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
300 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
301 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
302 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
303 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
304};
305
306/* kr_intstatus, kr_intclear, kr_intmask bits */
f62fe77a
BS		 307#define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
308#define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
cc533a57
BS		 309
310/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
311#define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
312#define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
313#define INFINIPATH_HWE_HTCLNKABYTE0CRCERR 0x0000000000800000ULL
314#define INFINIPATH_HWE_HTCLNKABYTE1CRCERR 0x0000000001000000ULL
315#define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR 0x0000000002000000ULL
316#define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR 0x0000000004000000ULL
317#define INFINIPATH_HWE_HTCMISCERR4 0x0000000008000000ULL
318#define INFINIPATH_HWE_HTCMISCERR5 0x0000000010000000ULL
319#define INFINIPATH_HWE_HTCMISCERR6 0x0000000020000000ULL
320#define INFINIPATH_HWE_HTCMISCERR7 0x0000000040000000ULL
321#define INFINIPATH_HWE_HTCBUSTREQPARITYERR 0x0000000080000000ULL
322#define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
323#define INFINIPATH_HWE_HTCBUSIREQPARITYERR 0x0000000200000000ULL
324#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
325#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
326#define INFINIPATH_HWE_HTBPLL_FBSLIP 0x0200000000000000ULL
327#define INFINIPATH_HWE_HTBPLL_RFSLIP 0x0400000000000000ULL
328#define INFINIPATH_HWE_HTAPLL_FBSLIP 0x0800000000000000ULL
329#define INFINIPATH_HWE_HTAPLL_RFSLIP 0x1000000000000000ULL
330#define INFINIPATH_HWE_SERDESPLLFAILED 0x2000000000000000ULL
331
332/* kr_extstatus bits */
333#define INFINIPATH_EXTS_FREQSEL 0x2
334#define INFINIPATH_EXTS_SERDESSEL 0x4
335#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
336#define INFINIPATH_EXTS_MEMBIST_CORRECT 0x0000000000008000
337
9783ab40
BS		 338
339/* TID entries (memory), HT-only */
340#define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
341#define INFINIPATH_RT_VALID 0x8000000000000000ULL
342#define INFINIPATH_RT_ADDR_SHIFT 0
343#define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
344#define INFINIPATH_RT_BUFSIZE_SHIFT 48
345
d8274869
DO		 346#define INFINIPATH_R_INTRAVAIL_SHIFT 16
347#define INFINIPATH_R_TAILUPD_SHIFT 31
348
349/* kr_xgxsconfig bits */
350#define INFINIPATH_XGXS_RESET 0x7ULL
351
cc533a57
BS		 352/*
353 * masks and bits that are different in different chips, or present only
354 * in one
355 */
356static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
357 INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
358static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
359 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
360
361static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
362 INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
363static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
364 INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
365static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
366 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
367static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
368 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
369
370#define _IPATH_GPIO_SDA_NUM 1
371#define _IPATH_GPIO_SCL_NUM 0
372
373#define IPATH_GPIO_SDA \
374 (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
375#define IPATH_GPIO_SCL \
376 (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
377
378/* keep the code below somewhat more readonable; not used elsewhere */
379#define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
380 infinipath_hwe_htclnkabyte1crcerr)
381#define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr | \
382 infinipath_hwe_htclnkbbyte1crcerr)
383#define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
384 infinipath_hwe_htclnkbbyte0crcerr)
385#define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr | \
386 infinipath_hwe_htclnkbbyte1crcerr)
387
388static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
389 char *msg, size_t msgl)
390{
391 char bitsmsg[64];
392 ipath_err_t crcbits = hwerrs &
393 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
394 /* don't check if 8bit HT */
395 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
396 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
397 /* don't check if 8bit HT */
398 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
399 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
400 /*
401 * we'll want to ignore link errors on link that is
402 * not in use, if any. For now, complain about both
403 */
404 if (crcbits) {
405 u16 ctrl0, ctrl1;
406 snprintf(bitsmsg, sizeof bitsmsg,
51084775 407 "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
cc533a57
BS		 408 !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
409 "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
410 ? "1 (B)" : "0+1 (A+B)"),
411 !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
412 : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
413 "0+1"), (unsigned long long) crcbits);
414 strlcat(msg, bitsmsg, msgl);
415
416 /*
417 * print extra info for debugging. slave/primary
418 * config word 4, 8 (link control 0, 1)
419 */
420
421 if (pci_read_config_word(dd->pcidev,
422 dd->ipath_ht_slave_off + 0x4,
423 &ctrl0))
424 dev_info(&dd->pcidev->dev, "Couldn't read "
425 "linkctrl0 of slave/primary "
426 "config block\n");
427 else if (!(ctrl0 & 1 << 6))
428 /* not if EOC bit set */
429 ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
430 ((ctrl0 >> 8) & 7) ? " CRC" : "",
431 ((ctrl0 >> 4) & 1) ? "linkfail" :
432 "");
433 if (pci_read_config_word(dd->pcidev,
434 dd->ipath_ht_slave_off + 0x8,
435 &ctrl1))
436 dev_info(&dd->pcidev->dev, "Couldn't read "
437 "linkctrl1 of slave/primary "
438 "config block\n");
439 else if (!(ctrl1 & 1 << 6))
440 /* not if EOC bit set */
441 ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
442 ((ctrl1 >> 8) & 7) ? " CRC" : "",
443 ((ctrl1 >> 4) & 1) ? "linkfail" :
444 "");
445
446 /* disable until driver reloaded */
447 dd->ipath_hwerrmask &= ~crcbits;
448 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
449 dd->ipath_hwerrmask);
450 ipath_dbg("HT crc errs: %s\n", msg);
451 } else
452 ipath_dbg("ignoring HT crc errors 0x%llx, "
453 "not in use\n", (unsigned long long)
454 (hwerrs & (_IPATH_HTLINK0_CRCBITS |
455 _IPATH_HTLINK1_CRCBITS)));
456}
457
8d588f8b
BS		 458/* 6110 specific hardware errors... */
459static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
460 INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
461 INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
462 INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
463 INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
464 INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
465 INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
466 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
467 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
468};
469
9783ab40
BS		 470#define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
471 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
472 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
473#define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
474 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
475
476static int ipath_ht_txe_recover(struct ipath_devdata *);
477
cc533a57 478/**
8d588f8b 479 * ipath_ht_handle_hwerrors - display hardware errors.
cc533a57
BS		 480 * @dd: the infinipath device
481 * @msg: the output buffer
482 * @msgl: the size of the output buffer
483 *
8d588f8b
BS		 484 * Use same msg buffer as regular errors to avoid excessive stack
485 * use. Most hardware errors are catastrophic, but for right now,
486 * we'll print them and continue. We reuse the same message buffer as
487 * ipath_handle_errors() to avoid excessive stack usage.
cc533a57
BS		 488 */
489static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
490 size_t msgl)
491{
492 ipath_err_t hwerrs;
493 u32 bits, ctrl;
494 int isfatal = 0;
495 char bitsmsg[64];
aecd3b5a 496 int log_idx;
cc533a57
BS		 497
498 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
499
500 if (!hwerrs) {
501 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
502 /*
503 * better than printing cofusing messages
504 * This seems to be related to clearing the crc error, or
505 * the pll error during init.
506 */
507 goto bail;
508 } else if (hwerrs == -1LL) {
509 ipath_dev_err(dd, "Read of hardware error status failed "
510 "(all bits set); ignoring\n");
511 goto bail;
512 }
513 ipath_stats.sps_hwerrs++;
514
515 /* Always clear the error status register, except MEMBISTFAIL,
516 * regardless of whether we continue or stop using the chip.
517 * We want that set so we know it failed, even across driver reload.
518 * We'll still ignore it in the hwerrmask. We do this partly for
519 * diagnostics, but also for support */
520 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
521 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
522
523 hwerrs &= dd->ipath_hwerrmask;
524
aecd3b5a
MA		 525 /* We log some errors to EEPROM, check if we have any of those. */
526 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
527 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
528 ipath_inc_eeprom_err(dd, log_idx, 1);
529
cc533a57
BS		 530 /*
531 * make sure we get this much out, unless told to be quiet,
9783ab40 532 * it's a parity error we may recover from,
cc533a57
BS		 533 * or it's occurred within the last 5 seconds
534 */
9783ab40
BS		 535 if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
536 RXE_EAGER_PARITY)) ||
537 (ipath_debug & __IPATH_VERBDBG))
cc533a57
BS		 538 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
539 "(cleared)\n", (unsigned long long) hwerrs);
540 dd->ipath_lasthwerror |= hwerrs;
541
f62fe77a 542 if (hwerrs & ~dd->ipath_hwe_bitsextant)
cc533a57
BS		 543 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
544 "%llx set\n", (unsigned long long)
f62fe77a 545 (hwerrs & ~dd->ipath_hwe_bitsextant));
cc533a57
BS		 546
547 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
9783ab40 548 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
89d1e09b
BS		 549 /*
550 * parity errors in send memory are recoverable,
551 * just cancel the send (if indicated in * sendbuffererror),
552 * count the occurrence, unfreeze (if no other handled
553 * hardware error bits are set), and continue. They can
554 * occur if a processor speculative read is done to the PIO
555 * buffer while we are sending a packet, for example.
556 */
9783ab40
BS		 557 if ((hwerrs & TXE_PIO_PARITY) && ipath_ht_txe_recover(dd))
558 hwerrs &= ~TXE_PIO_PARITY;
559 if (hwerrs & RXE_EAGER_PARITY)
560 ipath_dev_err(dd, "RXE parity, Eager TID error is not "
561 "recoverable\n");
562 if (!hwerrs) {
563 ipath_dbg("Clearing freezemode on ignored or "
564 "recovered hardware error\n");
0f4fc5eb 565 ipath_clear_freeze(dd);
cc533a57
BS		 566 }
567 }
568
569 *msg = '\0';
570
571 /*
572 * may someday want to decode into which bits are which
573 * functional area for parity errors, etc.
574 */
575 if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
576 << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
577 bits = (u32) ((hwerrs >>
578 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
579 INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
580 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
581 bits);
582 strlcat(msg, bitsmsg, msgl);
583 }
8d588f8b
BS		 584
585 ipath_format_hwerrors(hwerrs,
586 ipath_6110_hwerror_msgs,
587 sizeof(ipath_6110_hwerror_msgs) /
588 sizeof(ipath_6110_hwerror_msgs[0]),
589 msg, msgl);
cc533a57
BS		 590
591 if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
592 hwerr_crcbits(dd, hwerrs, msg, msgl);
593
cc533a57 594 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
525d0ca1 595 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
cc533a57
BS		 596 msgl);
597 /* ignore from now on, so disable until driver reloaded */
598 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
599 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
600 dd->ipath_hwerrmask);
601 }
602#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
603 INFINIPATH_HWE_COREPLL_RFSLIP | \
604 INFINIPATH_HWE_HTBPLL_FBSLIP | \
605 INFINIPATH_HWE_HTBPLL_RFSLIP | \
606 INFINIPATH_HWE_HTAPLL_FBSLIP | \
607 INFINIPATH_HWE_HTAPLL_RFSLIP)
608
609 if (hwerrs & _IPATH_PLL_FAIL) {
610 snprintf(bitsmsg, sizeof bitsmsg,
525d0ca1 611 "[PLL failed (%llx), InfiniPath hardware unusable]",
cc533a57
BS		 612 (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
613 strlcat(msg, bitsmsg, msgl);
614 /* ignore from now on, so disable until driver reloaded */
615 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
616 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
617 dd->ipath_hwerrmask);
618 }
619
620 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
621 /*
622 * If it occurs, it is left masked since the eternal
623 * interface is unused
624 */
625 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
626 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
627 dd->ipath_hwerrmask);
628 }
629
9783ab40
BS		 630 if (hwerrs) {
631 /*
632 * if any set that we aren't ignoring; only
633 * make the complaint once, in case it's stuck
634 * or recurring, and we get here multiple
635 * times.
f5408ac7
BS		 636 * force link down, so switch knows, and
637 * LEDs are turned off
9783ab40 638 */
9783ab40 639 if (dd->ipath_flags & IPATH_INITTED) {
f5408ac7
BS		 640 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
641 ipath_setup_ht_setextled(dd,
642 INFINIPATH_IBCS_L_STATE_DOWN,
643 INFINIPATH_IBCS_LT_STATE_DISABLED);
9783ab40
BS		 644 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
645 "mode), no longer usable, SN %.16s\n",
646 dd->ipath_serial);
647 isfatal = 1;
648 }
649 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
650 /* mark as having had error */
651 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
652 /*
653 * mark as not usable, at a minimum until driver
654 * is reloaded, probably until reboot, since no
655 * other reset is possible.
656 */
657 dd->ipath_flags &= ~IPATH_INITTED;
658 }
659 else
660 *msg = 0; /* recovered from all of them */
f5408ac7
BS		 661 if (*msg)
662 ipath_dev_err(dd, "%s hardware error\n", msg);
cc533a57
BS		 663 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
664 /*
665 * for status file; if no trailing brace is copied,
666 * we'll know it was truncated.
667 */
668 snprintf(dd->ipath_freezemsg,
669 dd->ipath_freezelen, "{%s}", msg);
670
671bail:;
672}
673
674/**
675 * ipath_ht_boardname - fill in the board name
676 * @dd: the infinipath device
677 * @name: the output buffer
678 * @namelen: the size of the output buffer
679 *
680 * fill in the board name, based on the board revision register
681 */
682static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
683 size_t namelen)
684{
685 char *n = NULL;
686 u8 boardrev = dd->ipath_boardrev;
aa7c79ab 687 int ret = 0;
cc533a57
BS		 688
689 switch (boardrev) {
f2080fa3
BS		 690 case 5:
691 /*
525d0ca1 692 * original production board; two production levels, with
f2080fa3
BS		 693 * different serial number ranges. See ipath_ht_early_init() for
694 * case where we enable IPATH_GPIO_INTR for later serial # range.
aa7c79ab 695 * Original 112* serial number is no longer supported.
f2080fa3 696 */
525d0ca1 697 n = "InfiniPath_QHT7040";
cc533a57 698 break;
cc533a57 699 case 7:
525d0ca1
BS		 700 /* small form factor production board */
701 n = "InfiniPath_QHT7140";
cc533a57 702 break;
cc533a57
BS		 703 default: /* don't know, just print the number */
704 ipath_dev_err(dd, "Don't yet know about board "
705 "with ID %u\n", boardrev);
525d0ca1 706 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
cc533a57 707 boardrev);
aa7c79ab 708 ret = 1;
cc533a57
BS		 709 break;
710 }
711 if (n)
712 snprintf(name, namelen, "%s", n);
713
aa7c79ab 714 if (ret) {
9ca48655 715 ipath_dev_err(dd, "Unsupported InfiniPath board %s!\n", name);
9ca48655
RC		 716 goto bail;
717 }
9783ab40 718 if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
380bf5d3 719 dd->ipath_minrev > 4)) {
cc533a57 720 /*
380bf5d3 721 * This version of the driver only supports Rev 3.2 - 3.4
cc533a57
BS		 722 */
723 ipath_dev_err(dd,
525d0ca1 724 "Unsupported InfiniPath hardware revision %u.%u!\n",
cc533a57
BS		 725 dd->ipath_majrev, dd->ipath_minrev);
726 ret = 1;
727 goto bail;
728 }
729 /*
730 * pkt/word counters are 32 bit, and therefore wrap fast enough
731 * that we snapshot them from a timer, and maintain 64 bit shadow
732 * copies
733 */
734 dd->ipath_flags |= IPATH_32BITCOUNTERS;
9ca48655 735 dd->ipath_flags |= IPATH_GPIO_INTR;
cc533a57
BS		 736 if (dd->ipath_htspeed != 800)
737 ipath_dev_err(dd,
738 "Incorrectly configured for HT @ %uMHz\n",
739 dd->ipath_htspeed);
cc533a57
BS		 740 ret = 0;
741
a18e26ae
RC		 742 /*
743 * set here, not in ipath_init_*_funcs because we have to do
744 * it after we can read chip registers.
745 */
746 dd->ipath_ureg_align =
747 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
748
cc533a57
BS		 749bail:
750 return ret;
751}
752
753static void ipath_check_htlink(struct ipath_devdata *dd)
754{
755 u8 linkerr, link_off, i;
756
757 for (i = 0; i < 2; i++) {
758 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
759 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
760 dev_info(&dd->pcidev->dev, "Couldn't read "
761 "linkerror%d of HT slave/primary block\n",
762 i);
763 else if (linkerr & 0xf0) {
764 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
765 "clearing\n", linkerr >> 4, i);
766 /*
767 * writing the linkerr bits that are set should
768 * clear them
769 */
770 if (pci_write_config_byte(dd->pcidev, link_off,
771 linkerr))
772 ipath_dbg("Failed write to clear HT "
773 "linkerror%d\n", i);
774 if (pci_read_config_byte(dd->pcidev, link_off,
775 &linkerr))
776 dev_info(&dd->pcidev->dev,
777 "Couldn't reread linkerror%d of "
778 "HT slave/primary block\n", i);
779 else if (linkerr & 0xf0)
780 dev_info(&dd->pcidev->dev,
781 "HT linkerror%d bits 0x%x "
782 "couldn't be cleared\n",
783 i, linkerr >> 4);
784 }
785 }
786}
787
788static int ipath_setup_ht_reset(struct ipath_devdata *dd)
789{
525d0ca1 790 ipath_dbg("No reset possible for this InfiniPath hardware\n");
cc533a57
BS		 791 return 0;
792}
793
cc533a57
BS		 794#define HT_INTR_DISC_CONFIG 0x80 /* HT interrupt and discovery cap */
795#define HT_INTR_REG_INDEX 2 /* intconfig requires indirect accesses */
796
797/*
798 * Bits 13-15 of command==0 is slave/primary block. Clear any HT CRC
799 * errors. We only bother to do this at load time, because it's OK if
800 * it happened before we were loaded (first time after boot/reset),
801 * but any time after that, it's fatal anyway. Also need to not check
802 * for for upper byte errors if we are in 8 bit mode, so figure out
803 * our width. For now, at least, also complain if it's 8 bit.
804 */
805static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
806 int pos, u8 cap_type)
807{
808 u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
809 u16 linkctrl = 0;
810 int i;
811
812 dd->ipath_ht_slave_off = pos;
813 /* command word, master_host bit */
814 /* master host || slave */
815 if ((cap_type >> 2) & 1)
816 link_a_b_off = 4;
817 else
818 link_a_b_off = 0;
819 ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
820 link_a_b_off ? 1 : 0,
821 link_a_b_off ? 'B' : 'A');
822
823 link_a_b_off += pos;
824
825 /*
826 * check both link control registers; clear both HT CRC sets if
827 * necessary.
828 */
829 for (i = 0; i < 2; i++) {
830 link_off = pos + i * 4 + 0x4;
831 if (pci_read_config_word(pdev, link_off, &linkctrl))
832 ipath_dev_err(dd, "Couldn't read HT link control%d "
833 "register\n", i);
834 else if (linkctrl & (0xf << 8)) {
835 ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
836 "bits %x\n", i, linkctrl & (0xf << 8));
837 /*
838 * now write them back to clear the error.
839 */
840 pci_write_config_byte(pdev, link_off,
841 linkctrl & (0xf << 8));
842 }
843 }
844
845 /*
846 * As with HT CRC bits, same for protocol errors that might occur
847 * during boot.
848 */
849 for (i = 0; i < 2; i++) {
850 link_off = pos + i * 4 + 0xd;
851 if (pci_read_config_byte(pdev, link_off, &linkerr))
852 dev_info(&pdev->dev, "Couldn't read linkerror%d "
853 "of HT slave/primary block\n", i);
854 else if (linkerr & 0xf0) {
855 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
856 "clearing\n", linkerr >> 4, i);
857 /*
858 * writing the linkerr bits that are set will clear
859 * them
860 */
861 if (pci_write_config_byte
862 (pdev, link_off, linkerr))
863 ipath_dbg("Failed write to clear HT "
864 "linkerror%d\n", i);
865 if (pci_read_config_byte(pdev, link_off, &linkerr))
866 dev_info(&pdev->dev, "Couldn't reread "
867 "linkerror%d of HT slave/primary "
868 "block\n", i);
869 else if (linkerr & 0xf0)
870 dev_info(&pdev->dev, "HT linkerror%d bits "
871 "0x%x couldn't be cleared\n",
872 i, linkerr >> 4);
873 }
874 }
875
876 /*
877 * this is just for our link to the host, not devices connected
878 * through tunnel.
879 */
880
881 if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
882 ipath_dev_err(dd, "Couldn't read HT link width "
883 "config register\n");
884 else {
885 u32 width;
886 switch (linkwidth & 7) {
887 case 5:
888 width = 4;
889 break;
890 case 4:
891 width = 2;
892 break;
893 case 3:
894 width = 32;
895 break;
896 case 1:
897 width = 16;
898 break;
899 case 0:
900 default: /* if wrong, assume 8 bit */
901 width = 8;
902 break;
903 }
904
905 dd->ipath_htwidth = width;
906
907 if (linkwidth != 0x11) {
908 ipath_dev_err(dd, "Not configured for 16 bit HT "
909 "(%x)\n", linkwidth);
910 if (!(linkwidth & 0xf)) {
911 ipath_dbg("Will ignore HT lane1 errors\n");
912 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
913 }
914 }
915 }
916
917 /*
918 * this is just for our link to the host, not devices connected
919 * through tunnel.
920 */
921 if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
922 ipath_dev_err(dd, "Couldn't read HT link frequency "
923 "config register\n");
924 else {
925 u32 speed;
926 switch (linkwidth & 0xf) {
927 case 6:
928 speed = 1000;
929 break;
930 case 5:
931 speed = 800;
932 break;
933 case 4:
934 speed = 600;
935 break;
936 case 3:
937 speed = 500;
938 break;
939 case 2:
940 speed = 400;
941 break;
942 case 1:
943 speed = 300;
944 break;
945 default:
946 /*
947 * assume reserved and vendor-specific are 200...
948 */
949 case 0:
950 speed = 200;
951 break;
952 }
953 dd->ipath_htspeed = speed;
954 }
955}
956
51f65ebc 957static int ipath_ht_intconfig(struct ipath_devdata *dd)
cc533a57 958{
51f65ebc 959 int ret;
cc533a57 960
51f65ebc
BS		 961 if (dd->ipath_intconfig) {
962 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
963 dd->ipath_intconfig); /* interrupt address */
964 ret = 0;
965 } else {
966 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
967 "interrupt address\n");
968 ret = -EINVAL;
969 }
cc533a57 970
51f65ebc
BS		 971 return ret;
972}
973
974static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
975 struct ht_irq_msg *msg)
976{
977 struct ipath_devdata *dd = pci_get_drvdata(dev);
978 u64 prev_intconfig = dd->ipath_intconfig;
979
980 dd->ipath_intconfig = msg->address_lo;
981 dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
cc533a57
BS		 982
983 /*
51f65ebc
BS		 984 * If the previous value of dd->ipath_intconfig is zero, we're
985 * getting configured for the first time, and must not program the
986 * intconfig register here (it will be programmed later, when the
987 * hardware is ready). Otherwise, we should.
cc533a57 988 */
51f65ebc
BS		 989 if (prev_intconfig)
990 ipath_ht_intconfig(dd);
cc533a57
BS		 991}
992
993/**
994 * ipath_setup_ht_config - setup the interruptconfig register
995 * @dd: the infinipath device
996 * @pdev: the PCI device
997 *
998 * setup the interruptconfig register from the HT config info.
999 * Also clear CRC errors in HT linkcontrol, if necessary.
1000 * This is done only for the real hardware. It is done before
1001 * chip address space is initted, so can't touch infinipath registers
1002 */
1003static int ipath_setup_ht_config(struct ipath_devdata *dd,
1004 struct pci_dev *pdev)
1005{
51f65ebc
BS		 1006 int pos, ret;
1007
1008 ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
1009 if (ret < 0) {
1010 ipath_dev_err(dd, "Couldn't create interrupt handler: "
1011 "err %d\n", ret);
1012 goto bail;
1013 }
1014 dd->ipath_irq = ret;
1015 ret = 0;
cc533a57
BS		 1016
1017 /*
51f65ebc 1018 * Handle clearing CRC errors in linkctrl register if necessary. We
cc533a57
BS		 1019 * do this early, before we ever enable errors or hardware errors,
1020 * mostly to avoid causing the chip to enter freeze mode.
1021 */
46ff3463 1022 pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
cc533a57
BS		 1023 if (!pos) {
1024 ipath_dev_err(dd, "Couldn't find HyperTransport "
1025 "capability; no interrupts\n");
1026 ret = -ENODEV;
1027 goto bail;
1028 }
1029 do {
1030 u8 cap_type;
1031
9e2ef36b
DO		 1032 /*
1033 * The HT capability type byte is 3 bytes after the
cc533a57
BS		 1034 * capability byte.
1035 */
1036 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
1037 dev_info(&pdev->dev, "Couldn't read config "
1038 "command @ %d\n", pos);
1039 continue;
1040 }
1041 if (!(cap_type & 0xE0))
1042 slave_or_pri_blk(dd, pdev, pos, cap_type);
cc533a57 1043 } while ((pos = pci_find_next_capability(pdev, pos,
46ff3463 1044 PCI_CAP_ID_HT)));
cc533a57 1045
4ea61b54
RC		 1046 dd->ipath_flags |= IPATH_SWAP_PIOBUFS;
1047
cc533a57
BS		 1048bail:
1049 return ret;
1050}
1051
1052/**
1053 * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1054 * @dd: the infinipath device
1055 *
1056 * Called during driver unload.
525d0ca1 1057 * This is currently a nop for the HT chip, not for all chips
cc533a57
BS		 1058 */
1059static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1060{
1061}
1062
1063/**
1064 * ipath_setup_ht_setextled - set the state of the two external LEDs
1065 * @dd: the infinipath device
1066 * @lst: the L state
1067 * @ltst: the LT state
1068 *
1069 * Set the state of the two external LEDs, to indicate physical and
1070 * logical state of IB link. For this chip (at least with recommended
1071 * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1072 * (logical state)
1073 *
1074 * Note: We try to match the Mellanox HCA LED behavior as best
1075 * we can. Green indicates physical link state is OK (something is
1076 * plugged in, and we can train).
1077 * Amber indicates the link is logically up (ACTIVE).
1078 * Mellanox further blinks the amber LED to indicate data packet
1079 * activity, but we have no hardware support for that, so it would
1080 * require waking up every 10-20 msecs and checking the counters
1081 * on the chip, and then turning the LED off if appropriate. That's
1082 * visible overhead, so not something we will do.
1083 *
1084 */
1085static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1086 u64 lst, u64 ltst)
1087{
1088 u64 extctl;
17b2eb9f 1089 unsigned long flags = 0;
cc533a57
BS		 1090
1091 /* the diags use the LED to indicate diag info, so we leave
1092 * the external LED alone when the diags are running */
1093 if (ipath_diag_inuse)
1094 return;
1095
82466f00
MA		 1096 /* Allow override of LED display for, e.g. Locating system in rack */
1097 if (dd->ipath_led_override) {
1098 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1099 ? INFINIPATH_IBCS_LT_STATE_LINKUP
1100 : INFINIPATH_IBCS_LT_STATE_DISABLED;
1101 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1102 ? INFINIPATH_IBCS_L_STATE_ACTIVE
1103 : INFINIPATH_IBCS_L_STATE_DOWN;
1104 }
1105
17b2eb9f 1106 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
cc533a57
BS		 1107 /*
1108 * start by setting both LED control bits to off, then turn
1109 * on the appropriate bit(s).
1110 */
1111 if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1112 /*
1113 * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1114 * is inverted, because it is normally used to indicate
1115 * a hardware fault at reset, if there were errors
1116 */
1117 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1118 | INFINIPATH_EXTC_LEDGBLERR_OFF;
1119 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1120 extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1121 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1122 extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1123 }
1124 else {
1125 extctl = dd->ipath_extctrl &
1126 ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1127 INFINIPATH_EXTC_LED2PRIPORT_ON);
1128 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1129 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1130 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1131 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1132 }
1133 dd->ipath_extctrl = extctl;
1134 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
17b2eb9f 1135 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
cc533a57
BS		 1136}
1137
f62fe77a 1138static void ipath_init_ht_variables(struct ipath_devdata *dd)
cc533a57 1139{
f62fe77a
BS		 1140 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1141 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1142 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1143 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
cc533a57 1144
d8274869
DO		 1145 /* Fill in shifts for RcvCtrl. */
1146 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1147 dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1148 dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1149 dd->ipath_r_portcfg_shift = 0; /* Not on IBA6110 */
1150
f62fe77a 1151 dd->ipath_i_bitsextant =
cc533a57
BS		 1152 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1153 (INFINIPATH_I_RCVAVAIL_MASK <<
1154 INFINIPATH_I_RCVAVAIL_SHIFT) |
1155 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1156 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1157
f62fe77a 1158 dd->ipath_e_bitsextant =
cc533a57
BS		 1159 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1160 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1161 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1162 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1163 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1164 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1165 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1166 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1167 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1168 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1169 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1170 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1171 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1172 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1173 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1174 INFINIPATH_E_HARDWARE;
1175
f62fe77a 1176 dd->ipath_hwe_bitsextant =
cc533a57
BS		 1177 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1178 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1179 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1180 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1181 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1182 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1183 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1184 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1185 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1186 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1187 INFINIPATH_HWE_HTCMISCERR4 |
1188 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1189 INFINIPATH_HWE_HTCMISCERR7 |
1190 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1191 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1192 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1193 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1194 INFINIPATH_HWE_MEMBISTFAILED |
1195 INFINIPATH_HWE_COREPLL_FBSLIP |
1196 INFINIPATH_HWE_COREPLL_RFSLIP |
1197 INFINIPATH_HWE_HTBPLL_FBSLIP |
1198 INFINIPATH_HWE_HTBPLL_RFSLIP |
1199 INFINIPATH_HWE_HTAPLL_FBSLIP |
1200 INFINIPATH_HWE_HTAPLL_RFSLIP |
1201 INFINIPATH_HWE_SERDESPLLFAILED |
1202 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1203 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1204
f62fe77a
BS		 1205 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1206 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
aecd3b5a
MA		 1207
1208 /*
1209 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1210 * 2 is Some Misc, 3 is reserved for future.
1211 */
1212 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1213 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1214 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1215
1216 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1217 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1218 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1219
1220 dd->ipath_eep_st_masks[2].errs_to_log =
1221 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1222
cc533a57
BS		 1223}
1224
1225/**
1226 * ipath_ht_init_hwerrors - enable hardware errors
1227 * @dd: the infinipath device
1228 *
1229 * now that we have finished initializing everything that might reasonably
1230 * cause a hardware error, and cleared those errors bits as they occur,
1231 * we can enable hardware errors in the mask (potentially enabling
1232 * freeze mode), and enable hardware errors as errors (along with
1233 * everything else) in errormask
1234 */
1235static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1236{
1237 ipath_err_t val;
1238 u64 extsval;
1239
1240 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1241
1242 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1243 ipath_dev_err(dd, "MemBIST did not complete!\n");
9783ab40
BS		 1244 if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1245 ipath_dbg("MemBIST corrected\n");
cc533a57
BS		 1246
1247 ipath_check_htlink(dd);
1248
1249 /* barring bugs, all hwerrors become interrupts, which can */
1250 val = -1LL;
1251 /* don't look at crc lane1 if 8 bit */
1252 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1253 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1254 /* don't look at crc lane1 if 8 bit */
1255 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1256 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1257
1258 /*
1259 * disable RXDSYNCMEMPARITY because external serdes is unused,
1260 * and therefore the logic will never be used or initialized,
1261 * and uninitialized state will normally result in this error
1262 * being asserted. Similarly for the external serdess pll
1263 * lock signal.
1264 */
1265 val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1266 INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1267
1268 /*
1269 * Disable MISCERR4 because of an inversion in the HT core
1270 * logic checking for errors that cause this bit to be set.
1271 * The errata can also cause the protocol error bit to be set
1272 * in the HT config space linkerror register(s).
1273 */
1274 val &= ~INFINIPATH_HWE_HTCMISCERR4;
1275
1276 /*
1277 * PLL ignored because MDIO interface has a logic problem
1278 * for reads, on Comstock and Ponderosa. BRINGUP
1279 */
1280 if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1281 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1282 dd->ipath_hwerrmask = val;
1283}
1284
1285/**
1286 * ipath_ht_bringup_serdes - bring up the serdes
1287 * @dd: the infinipath device
1288 */
1289static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1290{
1291 u64 val, config1;
1292 int ret = 0, change = 0;
1293
1294 ipath_dbg("Trying to bringup serdes\n");
1295
1296 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1297 INFINIPATH_HWE_SERDESPLLFAILED)
1298 {
1299 ipath_dbg("At start, serdes PLL failed bit set in "
1300 "hwerrstatus, clearing and continuing\n");
1301 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1302 INFINIPATH_HWE_SERDESPLLFAILED);
1303 }
1304
1305 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1306 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1307
1308 ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1309 "config1=%llx, sstatus=%llx xgxs %llx\n",
1310 (unsigned long long) val, (unsigned long long) config1,
1311 (unsigned long long)
1312 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1313 (unsigned long long)
1314 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1315
1316 /* force reset on */
1317 val |= INFINIPATH_SERDC0_RESET_PLL
1318 /* | INFINIPATH_SERDC0_RESET_MASK */
1319 ;
1320 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1321 udelay(15); /* need pll reset set at least for a bit */
1322
1323 if (val & INFINIPATH_SERDC0_RESET_PLL) {
1324 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1325 /* set lane resets, and tx idle, during pll reset */
1326 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1327 INFINIPATH_SERDC0_TXIDLE;
1328 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1329 "%llx)\n", (unsigned long long) val2);
1330 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1331 val2);
1332 /*
1333 * be sure chip saw it
1334 */
1335 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1336 /*
1337 * need pll reset clear at least 11 usec before lane
1338 * resets cleared; give it a few more
1339 */
1340 udelay(15);
1341 val = val2; /* for check below */
1342 }
1343
1344 if (val & (INFINIPATH_SERDC0_RESET_PLL |
1345 INFINIPATH_SERDC0_RESET_MASK |
1346 INFINIPATH_SERDC0_TXIDLE)) {
1347 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1348 INFINIPATH_SERDC0_RESET_MASK |
1349 INFINIPATH_SERDC0_TXIDLE);
1350 /* clear them */
1351 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1352 val);
1353 }
1354
1355 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1356 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1357 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1358 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1359 INFINIPATH_XGXS_MDIOADDR_SHIFT);
1360 /*
1361 * we use address 3
1362 */
1363 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1364 change = 1;
1365 }
1366 if (val & INFINIPATH_XGXS_RESET) {
1367 /* normally true after boot */
1368 val &= ~INFINIPATH_XGXS_RESET;
1369 change = 1;
1370 }
30fc5c31
BS		 1371 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1372 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1373 /* need to compensate for Tx inversion in partner */
1374 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1375 INFINIPATH_XGXS_RX_POL_SHIFT);
1376 val |= dd->ipath_rx_pol_inv <<
1377 INFINIPATH_XGXS_RX_POL_SHIFT;
1378 change = 1;
1379 }
cc533a57
BS		 1380 if (change)
1381 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1382
1383 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1384
1385 /* clear current and de-emphasis bits */
1386 config1 &= ~0x0ffffffff00ULL;
1387 /* set current to 20ma */
1388 config1 |= 0x00000000000ULL;
1389 /* set de-emphasis to -5.68dB */
1390 config1 |= 0x0cccc000000ULL;
1391 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1392
1393 ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1394 "config1=%llx, sstatus=%llx xgxs %llx\n",
1395 (unsigned long long) val, (unsigned long long) config1,
1396 (unsigned long long)
1397 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1398 (unsigned long long)
1399 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1400
1401 if (!ipath_waitfor_mdio_cmdready(dd)) {
1402 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1403 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1404 IPATH_MDIO_CTRL_XGXS_REG_8,
1405 0));
1406 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1407 IPATH_MDIO_DATAVALID, &val))
1408 ipath_dbg("Never got MDIO data for XGXS status "
1409 "read\n");
1410 else
1411 ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1412 "'bank' 31 %x\n", (u32) val);
1413 } else
1414 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1415
1416 return ret; /* for now, say we always succeeded */
1417}
1418
1419/**
1420 * ipath_ht_quiet_serdes - set serdes to txidle
1421 * @dd: the infinipath device
1422 * driver is being unloaded
1423 */
1424static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1425{
1426 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1427
1428 val |= INFINIPATH_SERDC0_TXIDLE;
1429 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1430 (unsigned long long) val);
1431 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1432}
1433
cc533a57
BS		 1434/**
1435 * ipath_pe_put_tid - write a TID in chip
1436 * @dd: the infinipath device
1437 * @tidptr: pointer to the expected TID (in chip) to udpate
f716cdfe 1438 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
cc533a57
BS		 1439 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1440 *
1441 * This exists as a separate routine to allow for special locking etc.
1442 * It's used for both the full cleanup on exit, as well as the normal
1443 * setup and teardown.
1444 */
1445static void ipath_ht_put_tid(struct ipath_devdata *dd,
1446 u64 __iomem *tidptr, u32 type,
1447 unsigned long pa)
1448{
9783ab40
BS		 1449 if (!dd->ipath_kregbase)
1450 return;
1451
cc533a57
BS		 1452 if (pa != dd->ipath_tidinvalid) {
1453 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1454 dev_info(&dd->pcidev->dev,
1455 "physaddr %lx has more than "
1456 "40 bits, using only 40!!!\n", pa);
1457 pa &= INFINIPATH_RT_ADDR_MASK;
1458 }
f716cdfe 1459 if (type == RCVHQ_RCV_TYPE_EAGER)
cc533a57
BS		 1460 pa |= dd->ipath_tidtemplate;
1461 else {
1462 /* in words (fixed, full page). */
1463 u64 lenvalid = PAGE_SIZE >> 2;
1464 lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1465 pa |= lenvalid | INFINIPATH_RT_VALID;
1466 }
1467 }
9783ab40 1468 writeq(pa, tidptr);
cc533a57
BS		 1469}
1470
9783ab40 1471
cc533a57
BS		 1472/**
1473 * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1474 * @dd: the infinipath device
1475 * @port: the port
1476 *
1477 * Used from ipath_close(), and at chip initialization.
1478 */
1479static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1480{
1481 u64 __iomem *tidbase;
1482 int i;
1483
1484 if (!dd->ipath_kregbase)
1485 return;
1486
1487 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1488
1489 /*
1490 * need to invalidate all of the expected TID entries for this
1491 * port, so we don't have valid entries that might somehow get
1492 * used (early in next use of this port, or through some bug)
1493 */
1494 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1495 dd->ipath_rcvtidbase +
1496 port * dd->ipath_rcvtidcnt *
1497 sizeof(*tidbase));
1498 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
f716cdfe
JE		 1499 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1500 dd->ipath_tidinvalid);
cc533a57
BS		 1501
1502 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1503 dd->ipath_rcvegrbase +
1504 port * dd->ipath_rcvegrcnt *
1505 sizeof(*tidbase));
1506
1507 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
f716cdfe
JE		 1508 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1509 dd->ipath_tidinvalid);
cc533a57
BS		 1510}
1511
1512/**
1513 * ipath_ht_tidtemplate - setup constants for TID updates
1514 * @dd: the infinipath device
1515 *
1516 * We setup stuff that we use a lot, to avoid calculating each time
1517 */
1518static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1519{
1520 dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1521 dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1522 dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1523
1524 /*
1525 * work around chip errata bug 7358, by marking invalid tids
1526 * as having max length
1527 */
1528 dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1529 INFINIPATH_RT_BUFSIZE_SHIFT;
1530}
1531
1532static int ipath_ht_early_init(struct ipath_devdata *dd)
1533{
1534 u32 __iomem *piobuf;
44f8e3f3 1535 u32 pioincr, val32;
cc533a57
BS		 1536 int i;
1537
1538 /*
1539 * one cache line; long IB headers will spill over into received
1540 * buffer
1541 */
1542 dd->ipath_rcvhdrentsize = 16;
1543 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1544
1545 /*
525d0ca1 1546 * For HT, we allocate a somewhat overly large eager buffer,
cc533a57
BS		 1547 * such that we can guarantee that we can receive the largest
1548 * packet that we can send out. To truly support a 4KB MTU,
1549 * we need to bump this to a large value. To date, other than
1550 * testing, we have never encountered an HCA that can really
1551 * send 4KB MTU packets, so we do not handle that (we'll get
1552 * errors interrupts if we ever see one).
1553 */
1554 dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
cc533a57
BS		 1555
1556 /*
1557 * the min() check here is currently a nop, but it may not
1558 * always be, depending on just how we do ipath_rcvegrbufsize
1559 */
1560 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1561 dd->ipath_rcvegrbufsize);
1562 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1563 ipath_ht_tidtemplate(dd);
1564
1565 /*
1566 * zero all the TID entries at startup. We do this for sanity,
1567 * in case of a previous driver crash of some kind, and also
1568 * because the chip powers up with these memories in an unknown
1569 * state. Use portcnt, not cfgports, since this is for the
1570 * full chip, not for current (possibly different) configuration
1571 * value.
1572 * Chip Errata bug 6447
1573 */
1574 for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1575 ipath_ht_clear_tids(dd, val32);
1576
1577 /*
1578 * write the pbc of each buffer, to be sure it's initialized, then
1579 * cancel all the buffers, and also abort any packets that might
1580 * have been in flight for some reason (the latter is for driver
1581 * unload/reload, but isn't a bad idea at first init). PIO send
1582 * isn't enabled at this point, so there is no danger of sending
1583 * these out on the wire.
1584 * Chip Errata bug 6610
1585 */
1586 piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1587 dd->ipath_piobufbase);
1588 pioincr = dd->ipath_palign / sizeof(*piobuf);
1589 for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1590 /*
1591 * reasonable word count, just to init pbc
1592 */
1593 writel(16, piobuf);
1594 piobuf += pioincr;
1595 }
f2080fa3
BS		 1596
1597 ipath_get_eeprom_info(dd);
1f813ca8 1598 if (dd->ipath_boardrev == 5) {
f2080fa3 1599 /*
525d0ca1 1600 * Later production QHT7040 has same changes as QHT7140, so
f2080fa3
BS		 1601 * can use GPIO interrupts. They have serial #'s starting
1602 * with 128, rather than 112.
1603 */
aa7c79ab
DO		 1604 if (dd->ipath_serial[0] == '1' &&
1605 dd->ipath_serial[1] == '2' &&
1606 dd->ipath_serial[2] == '8')
1607 dd->ipath_flags |= IPATH_GPIO_INTR;
1608 else {
1609 ipath_dev_err(dd, "Unsupported InfiniPath board "
1610 "(serial number %.16s)!\n",
1611 dd->ipath_serial);
1612 return 1;
1613 }
1614 }
9ca48655 1615
327a338d
AJ		 1616 if (dd->ipath_minrev >= 4) {
1617 /* Rev4+ reports extra errors via internal GPIO pins */
1618 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
1619 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
1620 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
1621 dd->ipath_gpio_mask);
1622 }
1623
cc533a57
BS		 1624 return 0;
1625}
1626
9783ab40
BS		 1627
1628static int ipath_ht_txe_recover(struct ipath_devdata *dd)
1629{
1630 int cnt = ++ipath_stats.sps_txeparity;
1631 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS) {
1632 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1633 ipath_dev_err(dd,
1634 "Too many attempts to recover from "
1635 "TXE parity, giving up\n");
1636 return 0;
1637 }
1638 dev_info(&dd->pcidev->dev,
1639 "Recovering from TXE PIO parity error\n");
9783ab40
BS		 1640 return 1;
1641}
1642
1643
cc533a57
BS		 1644/**
1645 * ipath_init_ht_get_base_info - set chip-specific flags for user code
1646 * @dd: the infinipath device
1647 * @kbase: ipath_base_info pointer
1648 *
1649 * We set the PCIE flag because the lower bandwidth on PCIe vs
d08df601 1650 * HyperTransport can affect some user packet algorithms.
cc533a57
BS		 1651 */
1652static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1653{
1654 struct ipath_base_info *kinfo = kbase;
1655
20bed343
AJ		 1656 kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1657 IPATH_RUNTIME_PIO_REGSWAPPED;
4bec0b91
AJ		 1658
1659 if (pd->port_dd->ipath_minrev < 4)
1660 kinfo->spi_runtime_flags |= IPATH_RUNTIME_RCVHDR_COPY;
cc533a57
BS		 1661
1662 return 0;
1663}
1664
51f65ebc
BS		 1665static void ipath_ht_free_irq(struct ipath_devdata *dd)
1666{
1667 free_irq(dd->ipath_irq, dd);
1668 ht_destroy_irq(dd->ipath_irq);
1669 dd->ipath_irq = 0;
1670 dd->ipath_intconfig = 0;
1671}
1672
60948a41
RC		 1673static void ipath_ht_config_ports(struct ipath_devdata *dd, ushort cfgports)
1674{
1675 dd->ipath_portcnt =
1676 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1677 dd->ipath_p0_rcvegrcnt =
1678 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1679}
1680
3029fcc3
RC		 1681static void ipath_ht_read_counters(struct ipath_devdata *dd,
1682 struct infinipath_counters *cntrs)
1683{
1684 cntrs->LBIntCnt =
1685 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1686 cntrs->LBFlowStallCnt =
1687 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1688 cntrs->TxSDmaDescCnt = 0;
1689 cntrs->TxUnsupVLErrCnt =
1690 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1691 cntrs->TxDataPktCnt =
1692 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1693 cntrs->TxFlowPktCnt =
1694 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1695 cntrs->TxDwordCnt =
1696 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1697 cntrs->TxLenErrCnt =
1698 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1699 cntrs->TxMaxMinLenErrCnt =
1700 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1701 cntrs->TxUnderrunCnt =
1702 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1703 cntrs->TxFlowStallCnt =
1704 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1705 cntrs->TxDroppedPktCnt =
1706 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1707 cntrs->RxDroppedPktCnt =
1708 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1709 cntrs->RxDataPktCnt =
1710 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1711 cntrs->RxFlowPktCnt =
1712 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1713 cntrs->RxDwordCnt =
1714 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1715 cntrs->RxLenErrCnt =
1716 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1717 cntrs->RxMaxMinLenErrCnt =
1718 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1719 cntrs->RxICRCErrCnt =
1720 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1721 cntrs->RxVCRCErrCnt =
1722 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1723 cntrs->RxFlowCtrlErrCnt =
1724 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1725 cntrs->RxBadFormatCnt =
1726 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1727 cntrs->RxLinkProblemCnt =
1728 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1729 cntrs->RxEBPCnt =
1730 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1731 cntrs->RxLPCRCErrCnt =
1732 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1733 cntrs->RxBufOvflCnt =
1734 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1735 cntrs->RxTIDFullErrCnt =
1736 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1737 cntrs->RxTIDValidErrCnt =
1738 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1739 cntrs->RxPKeyMismatchCnt =
1740 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1741 cntrs->RxP0HdrEgrOvflCnt =
1742 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1743 cntrs->RxP1HdrEgrOvflCnt =
1744 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1745 cntrs->RxP2HdrEgrOvflCnt =
1746 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1747 cntrs->RxP3HdrEgrOvflCnt =
1748 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1749 cntrs->RxP4HdrEgrOvflCnt =
1750 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1751 cntrs->RxP5HdrEgrOvflCnt =
1752 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP5HdrEgrOvflCnt));
1753 cntrs->RxP6HdrEgrOvflCnt =
1754 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP6HdrEgrOvflCnt));
1755 cntrs->RxP7HdrEgrOvflCnt =
1756 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP7HdrEgrOvflCnt));
1757 cntrs->RxP8HdrEgrOvflCnt =
1758 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP8HdrEgrOvflCnt));
1759 cntrs->RxP9HdrEgrOvflCnt = 0;
1760 cntrs->RxP10HdrEgrOvflCnt = 0;
1761 cntrs->RxP11HdrEgrOvflCnt = 0;
1762 cntrs->RxP12HdrEgrOvflCnt = 0;
1763 cntrs->RxP13HdrEgrOvflCnt = 0;
1764 cntrs->RxP14HdrEgrOvflCnt = 0;
1765 cntrs->RxP15HdrEgrOvflCnt = 0;
1766 cntrs->RxP16HdrEgrOvflCnt = 0;
1767 cntrs->IBStatusChangeCnt =
1768 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1769 cntrs->IBLinkErrRecoveryCnt =
1770 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1771 cntrs->IBLinkDownedCnt =
1772 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1773 cntrs->IBSymbolErrCnt =
1774 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1775 cntrs->RxVL15DroppedPktCnt = 0;
1776 cntrs->RxOtherLocalPhyErrCnt = 0;
1777 cntrs->PcieRetryBufDiagQwordCnt = 0;
1778 cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1779 cntrs->LocalLinkIntegrityErrCnt =
1780 (dd->ipath_flags & IPATH_GPIO_ERRINTRS) ?
1781 dd->ipath_lli_errs : dd->ipath_lli_errors;
1782 cntrs->RxVlErrCnt = 0;
1783 cntrs->RxDlidFltrCnt = 0;
1784}
1785
cc533a57 1786/**
525d0ca1 1787 * ipath_init_iba6110_funcs - set up the chip-specific function pointers
cc533a57
BS		 1788 * @dd: the infinipath device
1789 *
1790 * This is global, and is called directly at init to set up the
1791 * chip-specific function pointers for later use.
1792 */
525d0ca1 1793void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
cc533a57
BS		 1794{
1795 dd->ipath_f_intrsetup = ipath_ht_intconfig;
1796 dd->ipath_f_bus = ipath_setup_ht_config;
1797 dd->ipath_f_reset = ipath_setup_ht_reset;
1798 dd->ipath_f_get_boardname = ipath_ht_boardname;
1799 dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
cc533a57
BS		 1800 dd->ipath_f_early_init = ipath_ht_early_init;
1801 dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1802 dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1803 dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1804 dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1805 dd->ipath_f_put_tid = ipath_ht_put_tid;
1806 dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1807 dd->ipath_f_setextled = ipath_setup_ht_setextled;
1808 dd->ipath_f_get_base_info = ipath_ht_get_base_info;
51f65ebc 1809 dd->ipath_f_free_irq = ipath_ht_free_irq;
60948a41 1810 dd->ipath_f_config_ports = ipath_ht_config_ports;
3029fcc3 1811 dd->ipath_f_read_counters = ipath_ht_read_counters;
cc533a57
BS		 1812
1813 /*
1814 * initialize chip-specific variables
1815 */
1816 dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1817
1818 /*
1819 * setup the register offsets, since they are different for each
1820 * chip
1821 */
1822 dd->ipath_kregs = &ipath_ht_kregs;
1823 dd->ipath_cregs = &ipath_ht_cregs;
1824
1825 /*
1826 * do very early init that is needed before ipath_f_bus is
1827 * called
1828 */
f62fe77a 1829 ipath_init_ht_variables(dd);
cc533a57 1830}
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