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1da177e4 LT |
1 | /* linux/drivers/i2c/busses/i2c-s3c2410.c |
2 | * | |
c564e6ae | 3 | * Copyright (C) 2004,2005,2009 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2410 I2C Controller | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | ||
26 | #include <linux/i2c.h> | |
27 | #include <linux/i2c-id.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/interrupt.h> | |
1da177e4 LT |
31 | #include <linux/delay.h> |
32 | #include <linux/errno.h> | |
33 | #include <linux/err.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
61c7cff8 | 36 | #include <linux/cpufreq.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
21782180 | 38 | #include <linux/io.h> |
1da177e4 | 39 | |
1da177e4 | 40 | #include <asm/irq.h> |
1da177e4 | 41 | |
9498cb79 BD |
42 | #include <plat/regs-iic.h> |
43 | #include <plat/iic.h> | |
1da177e4 LT |
44 | |
45 | /* i2c controller state */ | |
46 | ||
47 | enum s3c24xx_i2c_state { | |
48 | STATE_IDLE, | |
49 | STATE_START, | |
50 | STATE_READ, | |
51 | STATE_WRITE, | |
52 | STATE_STOP | |
53 | }; | |
54 | ||
7d85ccd8 BD |
55 | enum s3c24xx_i2c_type { |
56 | TYPE_S3C2410, | |
57 | TYPE_S3C2440, | |
58 | }; | |
59 | ||
1da177e4 LT |
60 | struct s3c24xx_i2c { |
61 | spinlock_t lock; | |
62 | wait_queue_head_t wait; | |
be44f01e | 63 | unsigned int suspended:1; |
1da177e4 LT |
64 | |
65 | struct i2c_msg *msg; | |
66 | unsigned int msg_num; | |
67 | unsigned int msg_idx; | |
68 | unsigned int msg_ptr; | |
69 | ||
e00a8cdf | 70 | unsigned int tx_setup; |
e0d1ec97 | 71 | unsigned int irq; |
e00a8cdf | 72 | |
1da177e4 | 73 | enum s3c24xx_i2c_state state; |
61c7cff8 | 74 | unsigned long clkrate; |
1da177e4 LT |
75 | |
76 | void __iomem *regs; | |
77 | struct clk *clk; | |
78 | struct device *dev; | |
1da177e4 LT |
79 | struct resource *ioarea; |
80 | struct i2c_adapter adap; | |
61c7cff8 BD |
81 | |
82 | #ifdef CONFIG_CPU_FREQ | |
83 | struct notifier_block freq_transition; | |
84 | #endif | |
1da177e4 LT |
85 | }; |
86 | ||
6a039cab | 87 | /* default platform data removed, dev should always carry data. */ |
1da177e4 LT |
88 | |
89 | /* s3c24xx_i2c_is2440() | |
90 | * | |
91 | * return true is this is an s3c2440 | |
92 | */ | |
93 | ||
94 | static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c) | |
95 | { | |
96 | struct platform_device *pdev = to_platform_device(i2c->dev); | |
7d85ccd8 | 97 | enum s3c24xx_i2c_type type; |
1da177e4 | 98 | |
7d85ccd8 BD |
99 | type = platform_get_device_id(pdev)->driver_data; |
100 | return type == TYPE_S3C2440; | |
1da177e4 LT |
101 | } |
102 | ||
1da177e4 LT |
103 | /* s3c24xx_i2c_master_complete |
104 | * | |
105 | * complete the message and wake up the caller, using the given return code, | |
106 | * or zero to mean ok. | |
107 | */ | |
108 | ||
109 | static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) | |
110 | { | |
111 | dev_dbg(i2c->dev, "master_complete %d\n", ret); | |
112 | ||
113 | i2c->msg_ptr = 0; | |
114 | i2c->msg = NULL; | |
3d0911bf | 115 | i2c->msg_idx++; |
1da177e4 LT |
116 | i2c->msg_num = 0; |
117 | if (ret) | |
118 | i2c->msg_idx = ret; | |
119 | ||
120 | wake_up(&i2c->wait); | |
121 | } | |
122 | ||
123 | static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) | |
124 | { | |
125 | unsigned long tmp; | |
3d0911bf | 126 | |
1da177e4 LT |
127 | tmp = readl(i2c->regs + S3C2410_IICCON); |
128 | writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
129 | } |
130 | ||
131 | static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) | |
132 | { | |
133 | unsigned long tmp; | |
3d0911bf | 134 | |
1da177e4 LT |
135 | tmp = readl(i2c->regs + S3C2410_IICCON); |
136 | writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
137 | } |
138 | ||
139 | /* irq enable/disable functions */ | |
140 | ||
141 | static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) | |
142 | { | |
143 | unsigned long tmp; | |
3d0911bf | 144 | |
1da177e4 LT |
145 | tmp = readl(i2c->regs + S3C2410_IICCON); |
146 | writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
147 | } | |
148 | ||
149 | static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) | |
150 | { | |
151 | unsigned long tmp; | |
3d0911bf | 152 | |
1da177e4 LT |
153 | tmp = readl(i2c->regs + S3C2410_IICCON); |
154 | writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
155 | } | |
156 | ||
157 | ||
158 | /* s3c24xx_i2c_message_start | |
159 | * | |
3d0911bf | 160 | * put the start of a message onto the bus |
1da177e4 LT |
161 | */ |
162 | ||
3d0911bf | 163 | static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, |
1da177e4 LT |
164 | struct i2c_msg *msg) |
165 | { | |
166 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
167 | unsigned long stat; | |
168 | unsigned long iiccon; | |
169 | ||
170 | stat = 0; | |
171 | stat |= S3C2410_IICSTAT_TXRXEN; | |
172 | ||
173 | if (msg->flags & I2C_M_RD) { | |
174 | stat |= S3C2410_IICSTAT_MASTER_RX; | |
175 | addr |= 1; | |
176 | } else | |
177 | stat |= S3C2410_IICSTAT_MASTER_TX; | |
178 | ||
179 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
180 | addr ^= 1; | |
181 | ||
3d0911bf | 182 | /* todo - check for wether ack wanted or not */ |
1da177e4 LT |
183 | s3c24xx_i2c_enable_ack(i2c); |
184 | ||
185 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
186 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 187 | |
1da177e4 LT |
188 | dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); |
189 | writeb(addr, i2c->regs + S3C2410_IICDS); | |
3d0911bf | 190 | |
e00a8cdf BD |
191 | /* delay here to ensure the data byte has gotten onto the bus |
192 | * before the transaction is started */ | |
193 | ||
194 | ndelay(i2c->tx_setup); | |
195 | ||
1da177e4 LT |
196 | dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); |
197 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
3d0911bf BD |
198 | |
199 | stat |= S3C2410_IICSTAT_START; | |
1da177e4 LT |
200 | writel(stat, i2c->regs + S3C2410_IICSTAT); |
201 | } | |
202 | ||
203 | static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) | |
204 | { | |
205 | unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
206 | ||
207 | dev_dbg(i2c->dev, "STOP\n"); | |
208 | ||
209 | /* stop the transfer */ | |
3d0911bf | 210 | iicstat &= ~S3C2410_IICSTAT_START; |
1da177e4 | 211 | writel(iicstat, i2c->regs + S3C2410_IICSTAT); |
3d0911bf | 212 | |
1da177e4 | 213 | i2c->state = STATE_STOP; |
3d0911bf | 214 | |
1da177e4 LT |
215 | s3c24xx_i2c_master_complete(i2c, ret); |
216 | s3c24xx_i2c_disable_irq(i2c); | |
217 | } | |
218 | ||
219 | /* helper functions to determine the current state in the set of | |
220 | * messages we are sending */ | |
221 | ||
222 | /* is_lastmsg() | |
223 | * | |
3d0911bf | 224 | * returns TRUE if the current message is the last in the set |
1da177e4 LT |
225 | */ |
226 | ||
227 | static inline int is_lastmsg(struct s3c24xx_i2c *i2c) | |
228 | { | |
229 | return i2c->msg_idx >= (i2c->msg_num - 1); | |
230 | } | |
231 | ||
232 | /* is_msglast | |
233 | * | |
234 | * returns TRUE if we this is the last byte in the current message | |
235 | */ | |
236 | ||
237 | static inline int is_msglast(struct s3c24xx_i2c *i2c) | |
238 | { | |
239 | return i2c->msg_ptr == i2c->msg->len-1; | |
240 | } | |
241 | ||
242 | /* is_msgend | |
243 | * | |
244 | * returns TRUE if we reached the end of the current message | |
245 | */ | |
246 | ||
247 | static inline int is_msgend(struct s3c24xx_i2c *i2c) | |
248 | { | |
249 | return i2c->msg_ptr >= i2c->msg->len; | |
250 | } | |
251 | ||
252 | /* i2s_s3c_irq_nextbyte | |
253 | * | |
254 | * process an interrupt and work out what to do | |
255 | */ | |
256 | ||
257 | static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) | |
258 | { | |
259 | unsigned long tmp; | |
260 | unsigned char byte; | |
261 | int ret = 0; | |
262 | ||
263 | switch (i2c->state) { | |
264 | ||
265 | case STATE_IDLE: | |
08882d20 | 266 | dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); |
1da177e4 LT |
267 | goto out; |
268 | break; | |
269 | ||
270 | case STATE_STOP: | |
08882d20 | 271 | dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); |
3d0911bf | 272 | s3c24xx_i2c_disable_irq(i2c); |
1da177e4 LT |
273 | goto out_ack; |
274 | ||
275 | case STATE_START: | |
276 | /* last thing we did was send a start condition on the | |
277 | * bus, or started a new i2c message | |
278 | */ | |
3d0911bf | 279 | |
63f5c289 | 280 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
1da177e4 LT |
281 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
282 | /* ack was not received... */ | |
283 | ||
284 | dev_dbg(i2c->dev, "ack was not received\n"); | |
63f5c289 | 285 | s3c24xx_i2c_stop(i2c, -ENXIO); |
1da177e4 LT |
286 | goto out_ack; |
287 | } | |
288 | ||
289 | if (i2c->msg->flags & I2C_M_RD) | |
290 | i2c->state = STATE_READ; | |
291 | else | |
292 | i2c->state = STATE_WRITE; | |
293 | ||
294 | /* terminate the transfer if there is nothing to do | |
63f5c289 | 295 | * as this is used by the i2c probe to find devices. */ |
1da177e4 LT |
296 | |
297 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | |
298 | s3c24xx_i2c_stop(i2c, 0); | |
299 | goto out_ack; | |
300 | } | |
301 | ||
302 | if (i2c->state == STATE_READ) | |
303 | goto prepare_read; | |
304 | ||
3d0911bf | 305 | /* fall through to the write state, as we will need to |
1da177e4 LT |
306 | * send a byte as well */ |
307 | ||
308 | case STATE_WRITE: | |
309 | /* we are writing data to the device... check for the | |
310 | * end of the message, and if so, work out what to do | |
311 | */ | |
312 | ||
2709781b BD |
313 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
314 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | |
315 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | |
316 | ||
317 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | |
318 | goto out_ack; | |
319 | } | |
320 | } | |
321 | ||
3d0911bf | 322 | retry_write: |
2709781b | 323 | |
1da177e4 LT |
324 | if (!is_msgend(i2c)) { |
325 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
326 | writeb(byte, i2c->regs + S3C2410_IICDS); | |
e00a8cdf BD |
327 | |
328 | /* delay after writing the byte to allow the | |
329 | * data setup time on the bus, as writing the | |
330 | * data to the register causes the first bit | |
331 | * to appear on SDA, and SCL will change as | |
332 | * soon as the interrupt is acknowledged */ | |
333 | ||
334 | ndelay(i2c->tx_setup); | |
335 | ||
1da177e4 LT |
336 | } else if (!is_lastmsg(i2c)) { |
337 | /* we need to go to the next i2c message */ | |
338 | ||
339 | dev_dbg(i2c->dev, "WRITE: Next Message\n"); | |
340 | ||
341 | i2c->msg_ptr = 0; | |
3d0911bf | 342 | i2c->msg_idx++; |
1da177e4 | 343 | i2c->msg++; |
3d0911bf | 344 | |
1da177e4 LT |
345 | /* check to see if we need to do another message */ |
346 | if (i2c->msg->flags & I2C_M_NOSTART) { | |
347 | ||
348 | if (i2c->msg->flags & I2C_M_RD) { | |
349 | /* cannot do this, the controller | |
350 | * forces us to send a new START | |
351 | * when we change direction */ | |
352 | ||
353 | s3c24xx_i2c_stop(i2c, -EINVAL); | |
354 | } | |
355 | ||
356 | goto retry_write; | |
357 | } else { | |
1da177e4 LT |
358 | /* send the new start */ |
359 | s3c24xx_i2c_message_start(i2c, i2c->msg); | |
360 | i2c->state = STATE_START; | |
361 | } | |
362 | ||
363 | } else { | |
364 | /* send stop */ | |
365 | ||
366 | s3c24xx_i2c_stop(i2c, 0); | |
367 | } | |
368 | break; | |
369 | ||
370 | case STATE_READ: | |
3d0911bf | 371 | /* we have a byte of data in the data register, do |
1da177e4 LT |
372 | * something with it, and then work out wether we are |
373 | * going to do any more read/write | |
374 | */ | |
375 | ||
1da177e4 LT |
376 | byte = readb(i2c->regs + S3C2410_IICDS); |
377 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
378 | ||
3d0911bf | 379 | prepare_read: |
1da177e4 LT |
380 | if (is_msglast(i2c)) { |
381 | /* last byte of buffer */ | |
382 | ||
383 | if (is_lastmsg(i2c)) | |
384 | s3c24xx_i2c_disable_ack(i2c); | |
3d0911bf | 385 | |
1da177e4 LT |
386 | } else if (is_msgend(i2c)) { |
387 | /* ok, we've read the entire buffer, see if there | |
388 | * is anything else we need to do */ | |
389 | ||
390 | if (is_lastmsg(i2c)) { | |
391 | /* last message, send stop and complete */ | |
392 | dev_dbg(i2c->dev, "READ: Send Stop\n"); | |
393 | ||
394 | s3c24xx_i2c_stop(i2c, 0); | |
395 | } else { | |
396 | /* go to the next transfer */ | |
397 | dev_dbg(i2c->dev, "READ: Next Transfer\n"); | |
398 | ||
399 | i2c->msg_ptr = 0; | |
400 | i2c->msg_idx++; | |
401 | i2c->msg++; | |
402 | } | |
403 | } | |
404 | ||
405 | break; | |
406 | } | |
407 | ||
408 | /* acknowlegde the IRQ and get back on with the work */ | |
409 | ||
410 | out_ack: | |
3d0911bf | 411 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
412 | tmp &= ~S3C2410_IICCON_IRQPEND; |
413 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
414 | out: | |
415 | return ret; | |
416 | } | |
417 | ||
418 | /* s3c24xx_i2c_irq | |
419 | * | |
420 | * top level IRQ servicing routine | |
421 | */ | |
422 | ||
7d12e780 | 423 | static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) |
1da177e4 LT |
424 | { |
425 | struct s3c24xx_i2c *i2c = dev_id; | |
426 | unsigned long status; | |
427 | unsigned long tmp; | |
428 | ||
429 | status = readl(i2c->regs + S3C2410_IICSTAT); | |
430 | ||
431 | if (status & S3C2410_IICSTAT_ARBITR) { | |
3d0911bf | 432 | /* deal with arbitration loss */ |
1da177e4 LT |
433 | dev_err(i2c->dev, "deal with arbitration loss\n"); |
434 | } | |
435 | ||
436 | if (i2c->state == STATE_IDLE) { | |
437 | dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); | |
438 | ||
3d0911bf | 439 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
440 | tmp &= ~S3C2410_IICCON_IRQPEND; |
441 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
442 | goto out; | |
443 | } | |
3d0911bf | 444 | |
1da177e4 LT |
445 | /* pretty much this leaves us with the fact that we've |
446 | * transmitted or received whatever byte we last sent */ | |
447 | ||
448 | i2s_s3c_irq_nextbyte(i2c, status); | |
449 | ||
450 | out: | |
451 | return IRQ_HANDLED; | |
452 | } | |
453 | ||
454 | ||
455 | /* s3c24xx_i2c_set_master | |
456 | * | |
457 | * get the i2c bus for a master transaction | |
458 | */ | |
459 | ||
460 | static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) | |
461 | { | |
462 | unsigned long iicstat; | |
463 | int timeout = 400; | |
464 | ||
465 | while (timeout-- > 0) { | |
466 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 467 | |
1da177e4 LT |
468 | if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) |
469 | return 0; | |
470 | ||
471 | msleep(1); | |
472 | } | |
473 | ||
1da177e4 LT |
474 | return -ETIMEDOUT; |
475 | } | |
476 | ||
477 | /* s3c24xx_i2c_doxfer | |
478 | * | |
479 | * this starts an i2c transfer | |
480 | */ | |
481 | ||
3d0911bf BD |
482 | static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, |
483 | struct i2c_msg *msgs, int num) | |
1da177e4 | 484 | { |
1bc2962e MB |
485 | unsigned long iicstat, timeout; |
486 | int spins = 20; | |
1da177e4 LT |
487 | int ret; |
488 | ||
be44f01e | 489 | if (i2c->suspended) |
61c7cff8 BD |
490 | return -EIO; |
491 | ||
1da177e4 LT |
492 | ret = s3c24xx_i2c_set_master(i2c); |
493 | if (ret != 0) { | |
494 | dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); | |
495 | ret = -EAGAIN; | |
496 | goto out; | |
497 | } | |
498 | ||
499 | spin_lock_irq(&i2c->lock); | |
500 | ||
501 | i2c->msg = msgs; | |
502 | i2c->msg_num = num; | |
503 | i2c->msg_ptr = 0; | |
504 | i2c->msg_idx = 0; | |
505 | i2c->state = STATE_START; | |
506 | ||
507 | s3c24xx_i2c_enable_irq(i2c); | |
508 | s3c24xx_i2c_message_start(i2c, msgs); | |
509 | spin_unlock_irq(&i2c->lock); | |
3d0911bf | 510 | |
1da177e4 LT |
511 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); |
512 | ||
513 | ret = i2c->msg_idx; | |
514 | ||
3d0911bf | 515 | /* having these next two as dev_err() makes life very |
1da177e4 LT |
516 | * noisy when doing an i2cdetect */ |
517 | ||
518 | if (timeout == 0) | |
519 | dev_dbg(i2c->dev, "timeout\n"); | |
520 | else if (ret != num) | |
521 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
522 | ||
523 | /* ensure the stop has been through the bus */ | |
524 | ||
1bc2962e MB |
525 | dev_dbg(i2c->dev, "waiting for bus idle\n"); |
526 | ||
527 | /* first, try busy waiting briefly */ | |
528 | do { | |
529 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
530 | } while ((iicstat & S3C2410_IICSTAT_START) && --spins); | |
531 | ||
532 | /* if that timed out sleep */ | |
533 | if (!spins) { | |
534 | msleep(1); | |
535 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
536 | } | |
537 | ||
538 | if (iicstat & S3C2410_IICSTAT_START) | |
539 | dev_warn(i2c->dev, "timeout waiting for bus idle\n"); | |
1da177e4 LT |
540 | |
541 | out: | |
542 | return ret; | |
543 | } | |
544 | ||
545 | /* s3c24xx_i2c_xfer | |
546 | * | |
547 | * first port of call from the i2c bus code when an message needs | |
44bbe87e | 548 | * transferring across the i2c bus. |
1da177e4 LT |
549 | */ |
550 | ||
551 | static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, | |
552 | struct i2c_msg *msgs, int num) | |
553 | { | |
554 | struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; | |
555 | int retry; | |
556 | int ret; | |
557 | ||
558 | for (retry = 0; retry < adap->retries; retry++) { | |
559 | ||
560 | ret = s3c24xx_i2c_doxfer(i2c, msgs, num); | |
561 | ||
562 | if (ret != -EAGAIN) | |
563 | return ret; | |
564 | ||
565 | dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); | |
566 | ||
567 | udelay(100); | |
568 | } | |
569 | ||
570 | return -EREMOTEIO; | |
571 | } | |
572 | ||
573 | /* declare our i2c functionality */ | |
574 | static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) | |
575 | { | |
576 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; | |
577 | } | |
578 | ||
579 | /* i2c bus registration info */ | |
580 | ||
8f9082c5 | 581 | static const struct i2c_algorithm s3c24xx_i2c_algorithm = { |
1da177e4 LT |
582 | .master_xfer = s3c24xx_i2c_xfer, |
583 | .functionality = s3c24xx_i2c_func, | |
584 | }; | |
585 | ||
1da177e4 LT |
586 | /* s3c24xx_i2c_calcdivisor |
587 | * | |
588 | * return the divisor settings for a given frequency | |
589 | */ | |
590 | ||
591 | static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, | |
592 | unsigned int *div1, unsigned int *divs) | |
593 | { | |
594 | unsigned int calc_divs = clkin / wanted; | |
595 | unsigned int calc_div1; | |
596 | ||
597 | if (calc_divs > (16*16)) | |
598 | calc_div1 = 512; | |
599 | else | |
600 | calc_div1 = 16; | |
601 | ||
602 | calc_divs += calc_div1-1; | |
603 | calc_divs /= calc_div1; | |
604 | ||
605 | if (calc_divs == 0) | |
606 | calc_divs = 1; | |
607 | if (calc_divs > 17) | |
608 | calc_divs = 17; | |
609 | ||
610 | *divs = calc_divs; | |
611 | *div1 = calc_div1; | |
612 | ||
613 | return clkin / (calc_divs * calc_div1); | |
614 | } | |
615 | ||
61c7cff8 | 616 | /* s3c24xx_i2c_clockrate |
1da177e4 LT |
617 | * |
618 | * work out a divisor for the user requested frequency setting, | |
619 | * either by the requested frequency, or scanning the acceptable | |
620 | * range of frequencies until something is found | |
621 | */ | |
622 | ||
61c7cff8 | 623 | static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) |
1da177e4 | 624 | { |
6a039cab | 625 | struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data; |
1da177e4 | 626 | unsigned long clkin = clk_get_rate(i2c->clk); |
1da177e4 | 627 | unsigned int divs, div1; |
c564e6ae | 628 | unsigned long target_frequency; |
61c7cff8 | 629 | u32 iiccon; |
1da177e4 | 630 | int freq; |
1da177e4 | 631 | |
61c7cff8 | 632 | i2c->clkrate = clkin; |
1da177e4 | 633 | clkin /= 1000; /* clkin now in KHz */ |
3d0911bf | 634 | |
c564e6ae | 635 | dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); |
1da177e4 | 636 | |
c564e6ae | 637 | target_frequency = pdata->frequency ? pdata->frequency : 100000; |
1da177e4 | 638 | |
c564e6ae | 639 | target_frequency /= 1000; /* Target frequency now in KHz */ |
1da177e4 | 640 | |
c564e6ae | 641 | freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); |
1da177e4 | 642 | |
c564e6ae DS |
643 | if (freq > target_frequency) { |
644 | dev_err(i2c->dev, | |
645 | "Unable to achieve desired frequency %luKHz." \ | |
646 | " Lowest achievable %dKHz\n", target_frequency, freq); | |
647 | return -EINVAL; | |
1da177e4 LT |
648 | } |
649 | ||
1da177e4 | 650 | *got = freq; |
61c7cff8 BD |
651 | |
652 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
653 | iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); | |
654 | iiccon |= (divs-1); | |
655 | ||
656 | if (div1 == 512) | |
657 | iiccon |= S3C2410_IICCON_TXDIV_512; | |
658 | ||
659 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
660 | ||
a192f715 BD |
661 | if (s3c24xx_i2c_is2440(i2c)) { |
662 | unsigned long sda_delay; | |
663 | ||
664 | if (pdata->sda_delay) { | |
7031307a MH |
665 | sda_delay = clkin * pdata->sda_delay; |
666 | sda_delay = DIV_ROUND_UP(sda_delay, 1000000); | |
a192f715 BD |
667 | sda_delay = DIV_ROUND_UP(sda_delay, 5); |
668 | if (sda_delay > 3) | |
669 | sda_delay = 3; | |
670 | sda_delay |= S3C2410_IICLC_FILTER_ON; | |
671 | } else | |
672 | sda_delay = 0; | |
673 | ||
674 | dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); | |
675 | writel(sda_delay, i2c->regs + S3C2440_IICLC); | |
676 | } | |
677 | ||
61c7cff8 BD |
678 | return 0; |
679 | } | |
680 | ||
681 | #ifdef CONFIG_CPU_FREQ | |
682 | ||
683 | #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) | |
684 | ||
685 | static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, | |
686 | unsigned long val, void *data) | |
687 | { | |
688 | struct s3c24xx_i2c *i2c = freq_to_i2c(nb); | |
689 | unsigned long flags; | |
690 | unsigned int got; | |
691 | int delta_f; | |
692 | int ret; | |
693 | ||
694 | delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; | |
695 | ||
696 | /* if we're post-change and the input clock has slowed down | |
697 | * or at pre-change and the clock is about to speed up, then | |
698 | * adjust our clock rate. <0 is slow, >0 speedup. | |
699 | */ | |
700 | ||
701 | if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || | |
702 | (val == CPUFREQ_PRECHANGE && delta_f > 0)) { | |
703 | spin_lock_irqsave(&i2c->lock, flags); | |
704 | ret = s3c24xx_i2c_clockrate(i2c, &got); | |
705 | spin_unlock_irqrestore(&i2c->lock, flags); | |
706 | ||
707 | if (ret < 0) | |
708 | dev_err(i2c->dev, "cannot find frequency\n"); | |
709 | else | |
710 | dev_info(i2c->dev, "setting freq %d\n", got); | |
711 | } | |
712 | ||
1da177e4 LT |
713 | return 0; |
714 | } | |
715 | ||
61c7cff8 BD |
716 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) |
717 | { | |
718 | i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; | |
719 | ||
720 | return cpufreq_register_notifier(&i2c->freq_transition, | |
721 | CPUFREQ_TRANSITION_NOTIFIER); | |
722 | } | |
723 | ||
724 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) | |
725 | { | |
726 | cpufreq_unregister_notifier(&i2c->freq_transition, | |
727 | CPUFREQ_TRANSITION_NOTIFIER); | |
728 | } | |
729 | ||
730 | #else | |
731 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) | |
732 | { | |
1da177e4 LT |
733 | return 0; |
734 | } | |
735 | ||
61c7cff8 BD |
736 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) |
737 | { | |
738 | } | |
739 | #endif | |
740 | ||
1da177e4 LT |
741 | /* s3c24xx_i2c_init |
742 | * | |
3d0911bf | 743 | * initialise the controller, set the IO lines and frequency |
1da177e4 LT |
744 | */ |
745 | ||
746 | static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) | |
747 | { | |
748 | unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; | |
749 | struct s3c2410_platform_i2c *pdata; | |
750 | unsigned int freq; | |
751 | ||
752 | /* get the plafrom data */ | |
753 | ||
6a039cab | 754 | pdata = i2c->dev->platform_data; |
1da177e4 LT |
755 | |
756 | /* inititalise the gpio */ | |
757 | ||
8be310a6 BD |
758 | if (pdata->cfg_gpio) |
759 | pdata->cfg_gpio(to_platform_device(i2c->dev)); | |
1da177e4 LT |
760 | |
761 | /* write slave address */ | |
3d0911bf | 762 | |
1da177e4 LT |
763 | writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); |
764 | ||
765 | dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); | |
766 | ||
61c7cff8 BD |
767 | writel(iicon, i2c->regs + S3C2410_IICCON); |
768 | ||
1da177e4 LT |
769 | /* we need to work out the divisors for the clock... */ |
770 | ||
61c7cff8 BD |
771 | if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { |
772 | writel(0, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
773 | dev_err(i2c->dev, "cannot meet bus frequency required\n"); |
774 | return -EINVAL; | |
775 | } | |
776 | ||
777 | /* todo - check that the i2c lines aren't being dragged anywhere */ | |
778 | ||
779 | dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); | |
780 | dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); | |
1da177e4 | 781 | |
1da177e4 LT |
782 | return 0; |
783 | } | |
784 | ||
1da177e4 LT |
785 | /* s3c24xx_i2c_probe |
786 | * | |
787 | * called by the bus driver when a suitable device is found | |
788 | */ | |
789 | ||
3ae5eaec | 790 | static int s3c24xx_i2c_probe(struct platform_device *pdev) |
1da177e4 | 791 | { |
692acbd3 | 792 | struct s3c24xx_i2c *i2c; |
399dee23 | 793 | struct s3c2410_platform_i2c *pdata; |
1da177e4 LT |
794 | struct resource *res; |
795 | int ret; | |
796 | ||
6a039cab BD |
797 | pdata = pdev->dev.platform_data; |
798 | if (!pdata) { | |
799 | dev_err(&pdev->dev, "no platform data\n"); | |
800 | return -EINVAL; | |
801 | } | |
399dee23 | 802 | |
692acbd3 BD |
803 | i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL); |
804 | if (!i2c) { | |
805 | dev_err(&pdev->dev, "no memory for state\n"); | |
806 | return -ENOMEM; | |
807 | } | |
808 | ||
809 | strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); | |
810 | i2c->adap.owner = THIS_MODULE; | |
811 | i2c->adap.algo = &s3c24xx_i2c_algorithm; | |
812 | i2c->adap.retries = 2; | |
813 | i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
814 | i2c->tx_setup = 50; | |
815 | ||
816 | spin_lock_init(&i2c->lock); | |
817 | init_waitqueue_head(&i2c->wait); | |
399dee23 | 818 | |
1da177e4 LT |
819 | /* find the clock and enable it */ |
820 | ||
3ae5eaec RK |
821 | i2c->dev = &pdev->dev; |
822 | i2c->clk = clk_get(&pdev->dev, "i2c"); | |
1da177e4 | 823 | if (IS_ERR(i2c->clk)) { |
3ae5eaec | 824 | dev_err(&pdev->dev, "cannot get clock\n"); |
1da177e4 | 825 | ret = -ENOENT; |
5b68790c | 826 | goto err_noclk; |
1da177e4 LT |
827 | } |
828 | ||
3ae5eaec | 829 | dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); |
1da177e4 | 830 | |
1da177e4 LT |
831 | clk_enable(i2c->clk); |
832 | ||
833 | /* map the registers */ | |
834 | ||
835 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
836 | if (res == NULL) { | |
3ae5eaec | 837 | dev_err(&pdev->dev, "cannot find IO resource\n"); |
1da177e4 | 838 | ret = -ENOENT; |
5b68790c | 839 | goto err_clk; |
1da177e4 LT |
840 | } |
841 | ||
933a2aec | 842 | i2c->ioarea = request_mem_region(res->start, resource_size(res), |
1da177e4 LT |
843 | pdev->name); |
844 | ||
845 | if (i2c->ioarea == NULL) { | |
3ae5eaec | 846 | dev_err(&pdev->dev, "cannot request IO\n"); |
1da177e4 | 847 | ret = -ENXIO; |
5b68790c | 848 | goto err_clk; |
1da177e4 LT |
849 | } |
850 | ||
933a2aec | 851 | i2c->regs = ioremap(res->start, resource_size(res)); |
1da177e4 LT |
852 | |
853 | if (i2c->regs == NULL) { | |
3ae5eaec | 854 | dev_err(&pdev->dev, "cannot map IO\n"); |
1da177e4 | 855 | ret = -ENXIO; |
5b68790c | 856 | goto err_ioarea; |
1da177e4 LT |
857 | } |
858 | ||
3d0911bf BD |
859 | dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", |
860 | i2c->regs, i2c->ioarea, res); | |
1da177e4 LT |
861 | |
862 | /* setup info block for the i2c core */ | |
863 | ||
864 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 865 | i2c->adap.dev.parent = &pdev->dev; |
1da177e4 LT |
866 | |
867 | /* initialise the i2c controller */ | |
868 | ||
869 | ret = s3c24xx_i2c_init(i2c); | |
870 | if (ret != 0) | |
5b68790c | 871 | goto err_iomap; |
1da177e4 LT |
872 | |
873 | /* find the IRQ for this unit (note, this relies on the init call to | |
3d0911bf | 874 | * ensure no current IRQs pending |
1da177e4 LT |
875 | */ |
876 | ||
e0d1ec97 BD |
877 | i2c->irq = ret = platform_get_irq(pdev, 0); |
878 | if (ret <= 0) { | |
3ae5eaec | 879 | dev_err(&pdev->dev, "cannot find IRQ\n"); |
5b68790c | 880 | goto err_iomap; |
1da177e4 LT |
881 | } |
882 | ||
e0d1ec97 BD |
883 | ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED, |
884 | dev_name(&pdev->dev), i2c); | |
1da177e4 LT |
885 | |
886 | if (ret != 0) { | |
e0d1ec97 | 887 | dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); |
5b68790c | 888 | goto err_iomap; |
1da177e4 LT |
889 | } |
890 | ||
61c7cff8 | 891 | ret = s3c24xx_i2c_register_cpufreq(i2c); |
1da177e4 | 892 | if (ret < 0) { |
61c7cff8 | 893 | dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); |
5b68790c | 894 | goto err_irq; |
1da177e4 LT |
895 | } |
896 | ||
399dee23 BD |
897 | /* Note, previous versions of the driver used i2c_add_adapter() |
898 | * to add the bus at any number. We now pass the bus number via | |
899 | * the platform data, so if unset it will now default to always | |
900 | * being bus 0. | |
901 | */ | |
902 | ||
903 | i2c->adap.nr = pdata->bus_num; | |
904 | ||
905 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
1da177e4 | 906 | if (ret < 0) { |
3ae5eaec | 907 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); |
61c7cff8 | 908 | goto err_cpufreq; |
1da177e4 LT |
909 | } |
910 | ||
3ae5eaec | 911 | platform_set_drvdata(pdev, i2c); |
1da177e4 | 912 | |
22e965c2 | 913 | dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); |
5b68790c | 914 | return 0; |
1da177e4 | 915 | |
61c7cff8 BD |
916 | err_cpufreq: |
917 | s3c24xx_i2c_deregister_cpufreq(i2c); | |
918 | ||
5b68790c | 919 | err_irq: |
e0d1ec97 | 920 | free_irq(i2c->irq, i2c); |
5b68790c BD |
921 | |
922 | err_iomap: | |
923 | iounmap(i2c->regs); | |
924 | ||
925 | err_ioarea: | |
926 | release_resource(i2c->ioarea); | |
927 | kfree(i2c->ioarea); | |
928 | ||
929 | err_clk: | |
930 | clk_disable(i2c->clk); | |
931 | clk_put(i2c->clk); | |
1da177e4 | 932 | |
5b68790c | 933 | err_noclk: |
692acbd3 | 934 | kfree(i2c); |
1da177e4 LT |
935 | return ret; |
936 | } | |
937 | ||
938 | /* s3c24xx_i2c_remove | |
939 | * | |
940 | * called when device is removed from the bus | |
941 | */ | |
942 | ||
3ae5eaec | 943 | static int s3c24xx_i2c_remove(struct platform_device *pdev) |
1da177e4 | 944 | { |
3ae5eaec | 945 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); |
5b68790c | 946 | |
61c7cff8 BD |
947 | s3c24xx_i2c_deregister_cpufreq(i2c); |
948 | ||
5b68790c | 949 | i2c_del_adapter(&i2c->adap); |
e0d1ec97 | 950 | free_irq(i2c->irq, i2c); |
5b68790c BD |
951 | |
952 | clk_disable(i2c->clk); | |
953 | clk_put(i2c->clk); | |
954 | ||
955 | iounmap(i2c->regs); | |
956 | ||
957 | release_resource(i2c->ioarea); | |
958 | kfree(i2c->ioarea); | |
692acbd3 | 959 | kfree(i2c); |
1da177e4 LT |
960 | |
961 | return 0; | |
962 | } | |
963 | ||
964 | #ifdef CONFIG_PM | |
6a6c6189 | 965 | static int s3c24xx_i2c_suspend_noirq(struct device *dev) |
be44f01e | 966 | { |
6a6c6189 MD |
967 | struct platform_device *pdev = to_platform_device(dev); |
968 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
969 | ||
be44f01e | 970 | i2c->suspended = 1; |
6a6c6189 | 971 | |
be44f01e BD |
972 | return 0; |
973 | } | |
974 | ||
6a6c6189 | 975 | static int s3c24xx_i2c_resume(struct device *dev) |
1da177e4 | 976 | { |
6a6c6189 MD |
977 | struct platform_device *pdev = to_platform_device(dev); |
978 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
9480e307 | 979 | |
be44f01e BD |
980 | i2c->suspended = 0; |
981 | s3c24xx_i2c_init(i2c); | |
1da177e4 LT |
982 | |
983 | return 0; | |
984 | } | |
985 | ||
47145210 | 986 | static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { |
6a6c6189 MD |
987 | .suspend_noirq = s3c24xx_i2c_suspend_noirq, |
988 | .resume = s3c24xx_i2c_resume, | |
989 | }; | |
990 | ||
991 | #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) | |
1da177e4 | 992 | #else |
6a6c6189 | 993 | #define S3C24XX_DEV_PM_OPS NULL |
1da177e4 LT |
994 | #endif |
995 | ||
996 | /* device driver for platform bus bits */ | |
997 | ||
7d85ccd8 BD |
998 | static struct platform_device_id s3c24xx_driver_ids[] = { |
999 | { | |
1000 | .name = "s3c2410-i2c", | |
1001 | .driver_data = TYPE_S3C2410, | |
1002 | }, { | |
1003 | .name = "s3c2440-i2c", | |
1004 | .driver_data = TYPE_S3C2440, | |
1005 | }, { }, | |
1da177e4 | 1006 | }; |
7d85ccd8 | 1007 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
1da177e4 | 1008 | |
7d85ccd8 | 1009 | static struct platform_driver s3c24xx_i2c_driver = { |
1da177e4 LT |
1010 | .probe = s3c24xx_i2c_probe, |
1011 | .remove = s3c24xx_i2c_remove, | |
7d85ccd8 | 1012 | .id_table = s3c24xx_driver_ids, |
3ae5eaec RK |
1013 | .driver = { |
1014 | .owner = THIS_MODULE, | |
7d85ccd8 | 1015 | .name = "s3c-i2c", |
6a6c6189 | 1016 | .pm = S3C24XX_DEV_PM_OPS, |
3ae5eaec | 1017 | }, |
1da177e4 LT |
1018 | }; |
1019 | ||
1020 | static int __init i2c_adap_s3c_init(void) | |
1021 | { | |
7d85ccd8 | 1022 | return platform_driver_register(&s3c24xx_i2c_driver); |
1da177e4 | 1023 | } |
18dc83a6 | 1024 | subsys_initcall(i2c_adap_s3c_init); |
1da177e4 LT |
1025 | |
1026 | static void __exit i2c_adap_s3c_exit(void) | |
1027 | { | |
7d85ccd8 | 1028 | platform_driver_unregister(&s3c24xx_i2c_driver); |
1da177e4 | 1029 | } |
1da177e4 LT |
1030 | module_exit(i2c_adap_s3c_exit); |
1031 | ||
1032 | MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |
1033 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
1034 | MODULE_LICENSE("GPL"); |