[net-next-2.6.git] / drivers / i2c / busses / i2c-i801.c

/*
    i801.c - Part of lm_sensors, Linux kernel modules for hardware
              monitoring
    Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
    Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
    <mdsxyz123@yahoo.com>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

/*
    SUPPORTED DEVICES	PCI ID
    82801AA		2413           
    82801AB		2423           
    82801BA		2443           
    82801CA/CAM		2483           
    82801DB		24C3   (HW PEC supported, 32 byte buffer not supported)
    82801EB		24D3   (HW PEC supported, 32 byte buffer not supported)
    6300ESB		25A4
    ICH6		266A
    ICH7		27DA
    ESB2		269B
    This driver supports several versions of Intel's I/O Controller Hubs (ICH).
    For SMBus support, they are similar to the PIIX4 and are part
    of Intel's '810' and other chipsets.
    See the doc/busses/i2c-i801 file for details.
    I2C Block Read and Process Call are not supported.
*/

/* Note: we assume there can only be one I801, with one SMBus interface */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <asm/io.h>

/* I801 SMBus address offsets */
#define SMBHSTSTS	(0 + i801_smba)
#define SMBHSTCNT	(2 + i801_smba)
#define SMBHSTCMD	(3 + i801_smba)
#define SMBHSTADD	(4 + i801_smba)
#define SMBHSTDAT0	(5 + i801_smba)
#define SMBHSTDAT1	(6 + i801_smba)
#define SMBBLKDAT	(7 + i801_smba)
#define SMBPEC		(8 + i801_smba)	/* ICH4 only */
#define SMBAUXSTS	(12 + i801_smba)	/* ICH4 only */
#define SMBAUXCTL	(13 + i801_smba)	/* ICH4 only */

/* PCI Address Constants */
#define SMBBA		0x020
#define SMBHSTCFG	0x040
#define SMBREV		0x008

/* Host configuration bits for SMBHSTCFG */
#define SMBHSTCFG_HST_EN	1
#define SMBHSTCFG_SMB_SMI_EN	2
#define SMBHSTCFG_I2C_EN	4

/* Other settings */
#define MAX_TIMEOUT		100
#define ENABLE_INT9		0	/* set to 0x01 to enable - untested */

/* I801 command constants */
#define I801_QUICK		0x00
#define I801_BYTE		0x04
#define I801_BYTE_DATA		0x08
#define I801_WORD_DATA		0x0C
#define I801_PROC_CALL		0x10	/* later chips only, unimplemented */
#define I801_BLOCK_DATA		0x14
#define I801_I2C_BLOCK_DATA	0x18	/* unimplemented */
#define I801_BLOCK_LAST		0x34
#define I801_I2C_BLOCK_LAST	0x38	/* unimplemented */
#define I801_START		0x40
#define I801_PEC_EN		0x80	/* ICH4 only */

/* insmod parameters */

/* If force_addr is set to anything different from 0, we forcibly enable
   the I801 at the given address. VERY DANGEROUS! */
static u16 force_addr;
module_param(force_addr, ushort, 0);
MODULE_PARM_DESC(force_addr,
		 "Forcibly enable the I801 at the given address. "
		 "EXTREMELY DANGEROUS!");

static int i801_transaction(void);
static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
				  int command, int hwpec);

static unsigned short i801_smba;
static struct pci_driver i801_driver;
static struct pci_dev *I801_dev;
static int isich4;

static int i801_setup(struct pci_dev *dev)
{
	int error_return = 0;
	unsigned char temp;

	/* Note: we keep on searching until we have found 'function 3' */
	if(PCI_FUNC(dev->devfn) != 3)
		return -ENODEV;

	I801_dev = dev;
	if ((dev->device == PCI_DEVICE_ID_INTEL_82801DB_3) ||
	    (dev->device == PCI_DEVICE_ID_INTEL_82801EB_3) ||
	    (dev->device == PCI_DEVICE_ID_INTEL_ESB_4))
		isich4 = 1;
	else
		isich4 = 0;

	/* Determine the address of the SMBus areas */
	if (force_addr) {
		i801_smba = force_addr & 0xfff0;
	} else {
		pci_read_config_word(I801_dev, SMBBA, &i801_smba);
		i801_smba &= 0xfff0;
		if(i801_smba == 0) {
			dev_err(&dev->dev, "SMB base address uninitialized "
				"- upgrade BIOS or use force_addr=0xaddr\n");
			return -ENODEV;
		}
	}

	if (!request_region(i801_smba, (isich4 ? 16 : 8), i801_driver.name)) {
		dev_err(&dev->dev, "I801_smb region 0x%x already in use!\n",
			i801_smba);
		error_return = -EBUSY;
		goto END;
	}

	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
	temp &= ~SMBHSTCFG_I2C_EN;	/* SMBus timing */
	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);

	/* If force_addr is set, we program the new address here. Just to make
	   sure, we disable the device first. */
	if (force_addr) {
		pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
		pci_write_config_word(I801_dev, SMBBA, i801_smba);
		pci_write_config_byte(I801_dev, SMBHSTCFG, temp | 0x01);
		dev_warn(&dev->dev, "WARNING: I801 SMBus interface set to "
			"new address %04x!\n", i801_smba);
	} else if ((temp & 1) == 0) {
		pci_write_config_byte(I801_dev, SMBHSTCFG, temp | 1);
		dev_warn(&dev->dev, "enabling SMBus device\n");
	}

	if (temp & 0x02)
		dev_dbg(&dev->dev, "I801 using Interrupt SMI# for SMBus.\n");
	else
		dev_dbg(&dev->dev, "I801 using PCI Interrupt for SMBus.\n");

	pci_read_config_byte(I801_dev, SMBREV, &temp);
	dev_dbg(&dev->dev, "SMBREV = 0x%X\n", temp);
	dev_dbg(&dev->dev, "I801_smba = 0x%X\n", i801_smba);

END:
	return error_return;
}

static int i801_transaction(void)
{
	int temp;
	int result = 0;
	int timeout = 0;

	dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
		inb_p(SMBHSTDAT1));

	/* Make sure the SMBus host is ready to start transmitting */
	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
		dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
			temp);
		outb_p(temp, SMBHSTSTS);
		if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
			dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
			return -1;
		} else {
			dev_dbg(&I801_dev->dev, "Successfull!\n");
		}
	}

	outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);

	/* We will always wait for a fraction of a second! */
	do {
		msleep(1);
		temp = inb_p(SMBHSTSTS);
	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));

	/* If the SMBus is still busy, we give up */
	if (timeout >= MAX_TIMEOUT) {
		dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
		result = -1;
	}

	if (temp & 0x10) {
		result = -1;
		dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
	}

	if (temp & 0x08) {
		result = -1;
		dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
			"until next hard reset. (sorry!)\n");
		/* Clock stops and slave is stuck in mid-transmission */
	}

	if (temp & 0x04) {
		result = -1;
		dev_dbg(&I801_dev->dev, "Error: no response!\n");
	}

	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
		outb_p(inb(SMBHSTSTS), SMBHSTSTS);

	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
		dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
			"(%02x)\n", temp);
	}
	dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
		inb_p(SMBHSTDAT1));
	return result;
}

/* All-inclusive block transaction function */
static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
				  int command, int hwpec)
{
	int i, len;
	int smbcmd;
	int temp;
	int result = 0;
	int timeout;
	unsigned char hostc, errmask;

	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
		if (read_write == I2C_SMBUS_WRITE) {
			/* set I2C_EN bit in configuration register */
			pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
			pci_write_config_byte(I801_dev, SMBHSTCFG,
					      hostc | SMBHSTCFG_I2C_EN);
		} else {
			dev_err(&I801_dev->dev,
				"I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
			return -1;
		}
	}

	if (read_write == I2C_SMBUS_WRITE) {
		len = data->block[0];
		if (len < 1)
			len = 1;
		if (len > 32)
			len = 32;
		outb_p(len, SMBHSTDAT0);
		outb_p(data->block[1], SMBBLKDAT);
	} else {
		len = 32;	/* max for reads */
	}

	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
		/* set 32 byte buffer */
	}

	for (i = 1; i <= len; i++) {
		if (i == len && read_write == I2C_SMBUS_READ)
			smbcmd = I801_BLOCK_LAST;
		else
			smbcmd = I801_BLOCK_DATA;
		outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);

		dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
			"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
			inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
			inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));

		/* Make sure the SMBus host is ready to start transmitting */
		temp = inb_p(SMBHSTSTS);
		if (i == 1) {
			/* Erronenous conditions before transaction: 
			 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
			errmask=0x9f; 
		} else {
			/* Erronenous conditions during transaction: 
			 * Failed, Bus_Err, Dev_Err, Intr */
			errmask=0x1e; 
		}
		if (temp & errmask) {
			dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
				"Resetting...\n", temp);
			outb_p(temp, SMBHSTSTS);
			if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
				dev_err(&I801_dev->dev,
					"Reset failed! (%02x)\n", temp);
				result = -1;
                                goto END;
			}
			if (i != 1) {
				/* if die in middle of block transaction, fail */
				result = -1;
				goto END;
			}
		}

		if (i == 1)
			outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);

		/* We will always wait for a fraction of a second! */
		timeout = 0;
		do {
			temp = inb_p(SMBHSTSTS);
			msleep(1);
		}
		    while ((!(temp & 0x80))
			   && (timeout++ < MAX_TIMEOUT));

		/* If the SMBus is still busy, we give up */
		if (timeout >= MAX_TIMEOUT) {
			result = -1;
			dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
		}

		if (temp & 0x10) {
			result = -1;
			dev_dbg(&I801_dev->dev,
				"Error: Failed bus transaction\n");
		} else if (temp & 0x08) {
			result = -1;
			dev_err(&I801_dev->dev, "Bus collision!\n");
		} else if (temp & 0x04) {
			result = -1;
			dev_dbg(&I801_dev->dev, "Error: no response!\n");
		}

		if (i == 1 && read_write == I2C_SMBUS_READ) {
			len = inb_p(SMBHSTDAT0);
			if (len < 1)
				len = 1;
			if (len > 32)
				len = 32;
			data->block[0] = len;
		}

		/* Retrieve/store value in SMBBLKDAT */
		if (read_write == I2C_SMBUS_READ)
			data->block[i] = inb_p(SMBBLKDAT);
		if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
			outb_p(data->block[i+1], SMBBLKDAT);
		if ((temp & 0x9e) != 0x00)
			outb_p(temp, SMBHSTSTS);  /* signals SMBBLKDAT ready */

		if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
			dev_dbg(&I801_dev->dev,
				"Bad status (%02x) at end of transaction\n",
				temp);
		}
		dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
			"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
			inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
			inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));

		if (result < 0)
			goto END;
	}

	if (hwpec) {
		/* wait for INTR bit as advised by Intel */
		timeout = 0;
		do {
			temp = inb_p(SMBHSTSTS);
			msleep(1);
		} while ((!(temp & 0x02))
			   && (timeout++ < MAX_TIMEOUT));

		if (timeout >= MAX_TIMEOUT) {
			dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
		}
		outb_p(temp, SMBHSTSTS); 
	}
	result = 0;
END:
	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
		/* restore saved configuration register value */
		pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
	}
	return result;
}

/* Return -1 on error. */
static s32 i801_access(struct i2c_adapter * adap, u16 addr,
		       unsigned short flags, char read_write, u8 command,
		       int size, union i2c_smbus_data * data)
{
	int hwpec;
	int block = 0;
	int ret, xact = 0;

	hwpec = isich4 && (flags & I2C_CLIENT_PEC)
		&& size != I2C_SMBUS_QUICK
		&& size != I2C_SMBUS_I2C_BLOCK_DATA;

	switch (size) {
	case I2C_SMBUS_QUICK:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		xact = I801_QUICK;
		break;
	case I2C_SMBUS_BYTE:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(command, SMBHSTCMD);
		xact = I801_BYTE;
		break;
	case I2C_SMBUS_BYTE_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(data->byte, SMBHSTDAT0);
		xact = I801_BYTE_DATA;
		break;
	case I2C_SMBUS_WORD_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE) {
			outb_p(data->word & 0xff, SMBHSTDAT0);
			outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
		}
		xact = I801_WORD_DATA;
		break;
	case I2C_SMBUS_BLOCK_DATA:
	case I2C_SMBUS_I2C_BLOCK_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		block = 1;
		break;
	case I2C_SMBUS_PROC_CALL:
	default:
		dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
		return -1;
	}

	outb_p(hwpec, SMBAUXCTL);	/* enable/disable hardware PEC */

	if(block)
		ret = i801_block_transaction(data, read_write, size, hwpec);
	else {
		outb_p(xact | ENABLE_INT9, SMBHSTCNT);
		ret = i801_transaction();
	}

	if(block)
		return ret;
	if(ret)
		return -1;
	if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
		return 0;

	switch (xact & 0x7f) {
	case I801_BYTE:	/* Result put in SMBHSTDAT0 */
	case I801_BYTE_DATA:
		data->byte = inb_p(SMBHSTDAT0);
		break;
	case I801_WORD_DATA:
		data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
		break;
	}
	return 0;
}


static u32 i801_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
	    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
	    I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
	     | (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0);
}

static struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer	= i801_access,
	.functionality	= i801_func,
};

static struct i2c_adapter i801_adapter = {
	.owner		= THIS_MODULE,
	.class		= I2C_CLASS_HWMON,
	.algo		= &smbus_algorithm,
};

static struct pci_device_id i801_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
	{ 0, }
};

MODULE_DEVICE_TABLE (pci, i801_ids);

static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
{

	if (i801_setup(dev)) {
		dev_warn(&dev->dev,
			"I801 not detected, module not inserted.\n");
		return -ENODEV;
	}

	/* set up the driverfs linkage to our parent device */
	i801_adapter.dev.parent = &dev->dev;

	snprintf(i801_adapter.name, I2C_NAME_SIZE,
		"SMBus I801 adapter at %04x", i801_smba);
	return i2c_add_adapter(&i801_adapter);
}

static void __devexit i801_remove(struct pci_dev *dev)
{
	i2c_del_adapter(&i801_adapter);
	release_region(i801_smba, (isich4 ? 16 : 8));
}

static struct pci_driver i801_driver = {
	.name		= "i801_smbus",
	.id_table	= i801_ids,
	.probe		= i801_probe,
	.remove		= __devexit_p(i801_remove),
};

static int __init i2c_i801_init(void)
{
	return pci_register_driver(&i801_driver);
}

static void __exit i2c_i801_exit(void)
{
	pci_unregister_driver(&i801_driver);
}

MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
		"Philip Edelbrock <phil@netroedge.com>, "
		"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
MODULE_DESCRIPTION("I801 SMBus driver");
MODULE_LICENSE("GPL");

module_init(i2c_i801_init);
module_exit(i2c_i801_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	i801.c - Part of lm_sensors, Linux kernel modules for hardware
	3	monitoring
	4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
	5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
	6	<mdsxyz123@yahoo.com>
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	/*
	24	SUPPORTED DEVICES PCI ID
	25	82801AA 2413
	26	82801AB 2423
	27	82801BA 2443
	28	82801CA/CAM 2483
	29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
	30	82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
	31	6300ESB 25A4
	32	ICH6 266A
	33	ICH7 27DA
b0a70b57	34	ESB2 269B
1da177e4 LT	35	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
	36	For SMBus support, they are similar to the PIIX4 and are part
	37	of Intel's '810' and other chipsets.
	38	See the doc/busses/i2c-i801 file for details.
	39	I2C Block Read and Process Call are not supported.
	40	*/
	41
	42	/* Note: we assume there can only be one I801, with one SMBus interface */
	43
1da177e4 LT	44	#include <linux/module.h>
	45	#include <linux/pci.h>
	46	#include <linux/kernel.h>
	47	#include <linux/stddef.h>
	48	#include <linux/delay.h>
	49	#include <linux/sched.h>
	50	#include <linux/ioport.h>
	51	#include <linux/init.h>
	52	#include <linux/i2c.h>
	53	#include <asm/io.h>
	54
1da177e4 LT	55	/* I801 SMBus address offsets */
	56	#define SMBHSTSTS (0 + i801_smba)
	57	#define SMBHSTCNT (2 + i801_smba)
	58	#define SMBHSTCMD (3 + i801_smba)
	59	#define SMBHSTADD (4 + i801_smba)
	60	#define SMBHSTDAT0 (5 + i801_smba)
	61	#define SMBHSTDAT1 (6 + i801_smba)
	62	#define SMBBLKDAT (7 + i801_smba)
	63	#define SMBPEC (8 + i801_smba) /* ICH4 only */
	64	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
	65	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
	66
	67	/* PCI Address Constants */
	68	#define SMBBA 0x020
	69	#define SMBHSTCFG 0x040
	70	#define SMBREV 0x008
	71
	72	/* Host configuration bits for SMBHSTCFG */
	73	#define SMBHSTCFG_HST_EN 1
	74	#define SMBHSTCFG_SMB_SMI_EN 2
	75	#define SMBHSTCFG_I2C_EN 4
	76
	77	/* Other settings */
	78	#define MAX_TIMEOUT 100
	79	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
	80
	81	/* I801 command constants */
	82	#define I801_QUICK 0x00
	83	#define I801_BYTE 0x04
	84	#define I801_BYTE_DATA 0x08
	85	#define I801_WORD_DATA 0x0C
	86	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
	87	#define I801_BLOCK_DATA 0x14
	88	#define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */
	89	#define I801_BLOCK_LAST 0x34
	90	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
	91	#define I801_START 0x40
	92	#define I801_PEC_EN 0x80 /* ICH4 only */
	93
	94	/* insmod parameters */
	95
	96	/* If force_addr is set to anything different from 0, we forcibly enable
	97	the I801 at the given address. VERY DANGEROUS! */
	98	static u16 force_addr;
	99	module_param(force_addr, ushort, 0);
	100	MODULE_PARM_DESC(force_addr,
	101	"Forcibly enable the I801 at the given address. "
	102	"EXTREMELY DANGEROUS!");
	103
	104	static int i801_transaction(void);
585b3160 JD	105	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
585b3160 JD	106	int command, int hwpec);
1da177e4 LT	107
1da177e4 LT	108	static unsigned short i801_smba;
d6072f84	109	static struct pci_driver i801_driver;
1da177e4 LT	110	static struct pci_dev *I801_dev;
	111	static int isich4;
	112
	113	static int i801_setup(struct pci_dev *dev)
	114	{
	115	int error_return = 0;
	116	unsigned char temp;
	117
	118	/* Note: we keep on searching until we have found 'function 3' */
	119	if(PCI_FUNC(dev->devfn) != 3)
	120	return -ENODEV;
	121
	122	I801_dev = dev;
	123	if ((dev->device == PCI_DEVICE_ID_INTEL_82801DB_3) \|\|
	124	(dev->device == PCI_DEVICE_ID_INTEL_82801EB_3) \|\|
	125	(dev->device == PCI_DEVICE_ID_INTEL_ESB_4))
	126	isich4 = 1;
	127	else
	128	isich4 = 0;
	129
	130	/* Determine the address of the SMBus areas */
	131	if (force_addr) {
	132	i801_smba = force_addr & 0xfff0;
	133	} else {
	134	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
	135	i801_smba &= 0xfff0;
	136	if(i801_smba == 0) {
368609c5	137	dev_err(&dev->dev, "SMB base address uninitialized "
1da177e4 LT	138	"- upgrade BIOS or use force_addr=0xaddr\n");
	139	return -ENODEV;
	140	}
	141	}
	142
d6072f84	143	if (!request_region(i801_smba, (isich4 ? 16 : 8), i801_driver.name)) {
1da177e4 LT	144	dev_err(&dev->dev, "I801_smb region 0x%x already in use!\n",
	145	i801_smba);
	146	error_return = -EBUSY;
	147	goto END;
	148	}
	149
	150	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
	151	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
	152	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
	153
	154	/* If force_addr is set, we program the new address here. Just to make
	155	sure, we disable the device first. */
	156	if (force_addr) {
	157	pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
	158	pci_write_config_word(I801_dev, SMBBA, i801_smba);
	159	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 0x01);
	160	dev_warn(&dev->dev, "WARNING: I801 SMBus interface set to "
	161	"new address %04x!\n", i801_smba);
	162	} else if ((temp & 1) == 0) {
	163	pci_write_config_byte(I801_dev, SMBHSTCFG, temp \| 1);
	164	dev_warn(&dev->dev, "enabling SMBus device\n");
	165	}
	166
	167	if (temp & 0x02)
	168	dev_dbg(&dev->dev, "I801 using Interrupt SMI# for SMBus.\n");
	169	else
	170	dev_dbg(&dev->dev, "I801 using PCI Interrupt for SMBus.\n");
	171
	172	pci_read_config_byte(I801_dev, SMBREV, &temp);
	173	dev_dbg(&dev->dev, "SMBREV = 0x%X\n", temp);
	174	dev_dbg(&dev->dev, "I801_smba = 0x%X\n", i801_smba);
	175
	176	END:
	177	return error_return;
	178	}
	179
	180	static int i801_transaction(void)
	181	{
	182	int temp;
	183	int result = 0;
	184	int timeout = 0;
	185
368609c5	186	dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
1da177e4 LT	187	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
	188	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
	189	inb_p(SMBHSTDAT1));
	190
	191	/* Make sure the SMBus host is ready to start transmitting */
	192	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
	193	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
541e6a02	194	dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
1da177e4 LT	195	temp);
	196	outb_p(temp, SMBHSTSTS);
	197	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
	198	dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
	199	return -1;
	200	} else {
	201	dev_dbg(&I801_dev->dev, "Successfull!\n");
	202	}
	203	}
	204
	205	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
	206
	207	/* We will always wait for a fraction of a second! */
	208	do {
	209	msleep(1);
	210	temp = inb_p(SMBHSTSTS);
	211	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
	212
	213	/* If the SMBus is still busy, we give up */
	214	if (timeout >= MAX_TIMEOUT) {
	215	dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
	216	result = -1;
	217	}
	218
	219	if (temp & 0x10) {
	220	result = -1;
	221	dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
	222	}
	223
	224	if (temp & 0x08) {
	225	result = -1;
	226	dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
	227	"until next hard reset. (sorry!)\n");
	228	/* Clock stops and slave is stuck in mid-transmission */
	229	}
	230
	231	if (temp & 0x04) {
	232	result = -1;
	233	dev_dbg(&I801_dev->dev, "Error: no response!\n");
	234	}
	235
	236	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
	237	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
	238
	239	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
368609c5	240	dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
1da177e4 LT	241	"(%02x)\n", temp);
	242	}
	243	dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
	244	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
	245	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
	246	inb_p(SMBHSTDAT1));
	247	return result;
	248	}
	249
	250	/* All-inclusive block transaction function */
	251	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
585b3160	252	int command, int hwpec)
1da177e4 LT	253	{
	254	int i, len;
	255	int smbcmd;
	256	int temp;
	257	int result = 0;
	258	int timeout;
	259	unsigned char hostc, errmask;
	260
	261	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
	262	if (read_write == I2C_SMBUS_WRITE) {
	263	/* set I2C_EN bit in configuration register */
	264	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
	265	pci_write_config_byte(I801_dev, SMBHSTCFG,
	266	hostc \| SMBHSTCFG_I2C_EN);
	267	} else {
	268	dev_err(&I801_dev->dev,
	269	"I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
	270	return -1;
	271	}
	272	}
	273
	274	if (read_write == I2C_SMBUS_WRITE) {
	275	len = data->block[0];
	276	if (len < 1)
	277	len = 1;
	278	if (len > 32)
	279	len = 32;
	280	outb_p(len, SMBHSTDAT0);
	281	outb_p(data->block[1], SMBBLKDAT);
	282	} else {
	283	len = 32; /* max for reads */
	284	}
	285
	286	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
	287	/* set 32 byte buffer */
	288	}
	289
	290	for (i = 1; i <= len; i++) {
	291	if (i == len && read_write == I2C_SMBUS_READ)
	292	smbcmd = I801_BLOCK_LAST;
	293	else
	294	smbcmd = I801_BLOCK_DATA;
	295	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
	296
	297	dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
	298	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
	299	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
	300	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
	301
	302	/* Make sure the SMBus host is ready to start transmitting */
	303	temp = inb_p(SMBHSTSTS);
	304	if (i == 1) {
	305	/* Erronenous conditions before transaction:
	306	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
	307	errmask=0x9f;
	308	} else {
	309	/* Erronenous conditions during transaction:
	310	* Failed, Bus_Err, Dev_Err, Intr */
	311	errmask=0x1e;
	312	}
	313	if (temp & errmask) {
	314	dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
541e6a02	315	"Resetting...\n", temp);
1da177e4 LT	316	outb_p(temp, SMBHSTSTS);
	317	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
	318	dev_err(&I801_dev->dev,
	319	"Reset failed! (%02x)\n", temp);
	320	result = -1;
	321	goto END;
	322	}
	323	if (i != 1) {
	324	/* if die in middle of block transaction, fail */
	325	result = -1;
	326	goto END;
	327	}
	328	}
	329
	330	if (i == 1)
	331	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
	332
	333	/* We will always wait for a fraction of a second! */
	334	timeout = 0;
	335	do {
	336	temp = inb_p(SMBHSTSTS);
	337	msleep(1);
	338	}
	339	while ((!(temp & 0x80))
	340	&& (timeout++ < MAX_TIMEOUT));
	341
	342	/* If the SMBus is still busy, we give up */
	343	if (timeout >= MAX_TIMEOUT) {
	344	result = -1;
	345	dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
	346	}
	347
	348	if (temp & 0x10) {
	349	result = -1;
	350	dev_dbg(&I801_dev->dev,
	351	"Error: Failed bus transaction\n");
	352	} else if (temp & 0x08) {
	353	result = -1;
	354	dev_err(&I801_dev->dev, "Bus collision!\n");
	355	} else if (temp & 0x04) {
	356	result = -1;
	357	dev_dbg(&I801_dev->dev, "Error: no response!\n");
	358	}
	359
	360	if (i == 1 && read_write == I2C_SMBUS_READ) {
	361	len = inb_p(SMBHSTDAT0);
	362	if (len < 1)
	363	len = 1;
	364	if (len > 32)
	365	len = 32;
	366	data->block[0] = len;
	367	}
	368
	369	/* Retrieve/store value in SMBBLKDAT */
	370	if (read_write == I2C_SMBUS_READ)
	371	data->block[i] = inb_p(SMBBLKDAT);
	372	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
	373	outb_p(data->block[i+1], SMBBLKDAT);
	374	if ((temp & 0x9e) != 0x00)
	375	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
	376
	377	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
	378	dev_dbg(&I801_dev->dev,
	379	"Bad status (%02x) at end of transaction\n",
380	temp);
381	}
382	dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
383	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
384	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
385	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
386
387	if (result < 0)
388	goto END;
389	}
390
e8aac4a9	391	if (hwpec) {
1da177e4 LT	392	/* wait for INTR bit as advised by Intel */
	393	timeout = 0;
	394	do {
	395	temp = inb_p(SMBHSTSTS);
	396	msleep(1);
	397	} while ((!(temp & 0x02))
	398	&& (timeout++ < MAX_TIMEOUT));
	399
	400	if (timeout >= MAX_TIMEOUT) {
	401	dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
	402	}
	403	outb_p(temp, SMBHSTSTS);
	404	}
1da177e4 LT	405	result = 0;
	406	END:
	407	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
	408	/* restore saved configuration register value */
	409	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
	410	}
	411	return result;
	412	}
	413
	414	/* Return -1 on error. */
	415	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
	416	unsigned short flags, char read_write, u8 command,
	417	int size, union i2c_smbus_data * data)
	418	{
e8aac4a9	419	int hwpec;
1da177e4 LT	420	int block = 0;
	421	int ret, xact = 0;
	422
e8aac4a9 JD	423	hwpec = isich4 && (flags & I2C_CLIENT_PEC)
	424	&& size != I2C_SMBUS_QUICK
	425	&& size != I2C_SMBUS_I2C_BLOCK_DATA;
1da177e4 LT	426
	427	switch (size) {
	428	case I2C_SMBUS_QUICK:
	429	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	430	SMBHSTADD);
	431	xact = I801_QUICK;
	432	break;
	433	case I2C_SMBUS_BYTE:
	434	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	435	SMBHSTADD);
	436	if (read_write == I2C_SMBUS_WRITE)
	437	outb_p(command, SMBHSTCMD);
	438	xact = I801_BYTE;
	439	break;
	440	case I2C_SMBUS_BYTE_DATA:
	441	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	442	SMBHSTADD);
	443	outb_p(command, SMBHSTCMD);
	444	if (read_write == I2C_SMBUS_WRITE)
	445	outb_p(data->byte, SMBHSTDAT0);
	446	xact = I801_BYTE_DATA;
	447	break;
	448	case I2C_SMBUS_WORD_DATA:
	449	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	450	SMBHSTADD);
	451	outb_p(command, SMBHSTCMD);
	452	if (read_write == I2C_SMBUS_WRITE) {
	453	outb_p(data->word & 0xff, SMBHSTDAT0);
	454	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
	455	}
	456	xact = I801_WORD_DATA;
	457	break;
	458	case I2C_SMBUS_BLOCK_DATA:
	459	case I2C_SMBUS_I2C_BLOCK_DATA:
1da177e4 LT	460	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	461	SMBHSTADD);
	462	outb_p(command, SMBHSTCMD);
	463	block = 1;
	464	break;
	465	case I2C_SMBUS_PROC_CALL:
	466	default:
	467	dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
	468	return -1;
	469	}
	470
2e3e13f8	471	outb_p(hwpec, SMBAUXCTL); /* enable/disable hardware PEC */
e8aac4a9	472
1da177e4	473	if(block)
585b3160	474	ret = i801_block_transaction(data, read_write, size, hwpec);
1da177e4 LT	475	else {
	476	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
	477	ret = i801_transaction();
	478	}
	479
1da177e4 LT	480	if(block)
	481	return ret;
	482	if(ret)
	483	return -1;
	484	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
	485	return 0;
	486
	487	switch (xact & 0x7f) {
	488	case I801_BYTE: /* Result put in SMBHSTDAT0 */
	489	case I801_BYTE_DATA:
	490	data->byte = inb_p(SMBHSTDAT0);
	491	break;
	492	case I801_WORD_DATA:
	493	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
	494	break;
	495	}
	496	return 0;
	497	}
	498
	499
	500	static u32 i801_func(struct i2c_adapter *adapter)
	501	{
	502	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
	503	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
	504	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
b8095544	505	\| (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0);
1da177e4 LT	506	}
	507
	508	static struct i2c_algorithm smbus_algorithm = {
1da177e4 LT	509	.smbus_xfer = i801_access,
	510	.functionality = i801_func,
	511	};
	512
	513	static struct i2c_adapter i801_adapter = {
	514	.owner = THIS_MODULE,
	515	.class = I2C_CLASS_HWMON,
	516	.algo = &smbus_algorithm,
1da177e4 LT	517	};
	518
	519	static struct pci_device_id i801_ids[] = {
	520	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
	521	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
	522	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
	523	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
	524	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
	525	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
	526	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
	527	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
	528	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
b0a70b57	529	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1da177e4 LT	530	{ 0, }
	531	};
	532
	533	MODULE_DEVICE_TABLE (pci, i801_ids);
	534
	535	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
	536	{
	537
	538	if (i801_setup(dev)) {
	539	dev_warn(&dev->dev,
	540	"I801 not detected, module not inserted.\n");
	541	return -ENODEV;
	542	}
	543
	544	/* set up the driverfs linkage to our parent device */
	545	i801_adapter.dev.parent = &dev->dev;
	546
	547	snprintf(i801_adapter.name, I2C_NAME_SIZE,
	548	"SMBus I801 adapter at %04x", i801_smba);
	549	return i2c_add_adapter(&i801_adapter);
	550	}
	551
	552	static void __devexit i801_remove(struct pci_dev *dev)
	553	{
	554	i2c_del_adapter(&i801_adapter);
	555	release_region(i801_smba, (isich4 ? 16 : 8));
	556	}
	557
	558	static struct pci_driver i801_driver = {
	559	.name = "i801_smbus",
	560	.id_table = i801_ids,
	561	.probe = i801_probe,
	562	.remove = __devexit_p(i801_remove),
	563	};
	564
	565	static int __init i2c_i801_init(void)
	566	{
	567	return pci_register_driver(&i801_driver);
	568	}
	569
	570	static void __exit i2c_i801_exit(void)
	571	{
	572	pci_unregister_driver(&i801_driver);
	573	}
	574
	575	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
	576	"Philip Edelbrock <phil@netroedge.com>, "
	577	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
	578	MODULE_DESCRIPTION("I801 SMBus driver");
	579	MODULE_LICENSE("GPL");
	580
	581	module_init(i2c_i801_init);
	582	module_exit(i2c_i801_exit);