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i2c-powermac: Be less verbose in the absence of real errors.
[net-next-2.6.git] / drivers / i2c / busses / i2c-i801.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
cf898dc5 5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
1da177e4
LT		 6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22/*
ae7b0497
JD		 23 Supports the following Intel I/O Controller Hubs (ICH):
24
25 I/O Block I2C
26 region SMBus Block proc. block
27 Chip name PCI ID size PEC buffer call read
28 ----------------------------------------------------------------------
29 82801AA (ICH) 0x2413 16 no no no no
30 82801AB (ICH0) 0x2423 16 no no no no
31 82801BA (ICH2) 0x2443 16 no no no no
32 82801CA (ICH3) 0x2483 32 soft no no no
33 82801DB (ICH4) 0x24c3 32 hard yes no no
34 82801E (ICH5) 0x24d3 32 hard yes yes yes
35 6300ESB 0x25a4 32 hard yes yes yes
36 82801F (ICH6) 0x266a 32 hard yes yes yes
37 6310ESB/6320ESB 0x269b 32 hard yes yes yes
38 82801G (ICH7) 0x27da 32 hard yes yes yes
39 82801H (ICH8) 0x283e 32 hard yes yes yes
40 82801I (ICH9) 0x2930 32 hard yes yes yes
d28dc711
GJ		 41 Tolapai 0x5032 32 hard yes yes yes
42 ICH10 0x3a30 32 hard yes yes yes
43 ICH10 0x3a60 32 hard yes yes yes
39376434
SH		 44 3400/5 Series (PCH) 0x3b30 32 hard yes yes yes
45 Cougar Point (PCH) 0x1c22 32 hard yes yes yes
ae7b0497
JD		 46
47 Features supported by this driver:
48 Software PEC no
49 Hardware PEC yes
50 Block buffer yes
51 Block process call transaction no
6342064c 52 I2C block read transaction yes (doesn't use the block buffer)
ae7b0497
JD		 53
54 See the file Documentation/i2c/busses/i2c-i801 for details.
1da177e4
LT		 55*/
56
57/* Note: we assume there can only be one I801, with one SMBus interface */
58
1da177e4
LT		 59#include <linux/module.h>
60#include <linux/pci.h>
61#include <linux/kernel.h>
62#include <linux/stddef.h>
63#include <linux/delay.h>
1da177e4
LT		 64#include <linux/ioport.h>
65#include <linux/init.h>
66#include <linux/i2c.h>
54fb4a05 67#include <linux/acpi.h>
1561bfe5 68#include <linux/io.h>
fa5bfab7 69#include <linux/dmi.h>
1da177e4 70
1da177e4
LT		 71/* I801 SMBus address offsets */
72#define SMBHSTSTS (0 + i801_smba)
73#define SMBHSTCNT (2 + i801_smba)
74#define SMBHSTCMD (3 + i801_smba)
75#define SMBHSTADD (4 + i801_smba)
76#define SMBHSTDAT0 (5 + i801_smba)
77#define SMBHSTDAT1 (6 + i801_smba)
78#define SMBBLKDAT (7 + i801_smba)
ae7b0497
JD		 79#define SMBPEC (8 + i801_smba) /* ICH3 and later */
80#define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
81#define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
1da177e4
LT		 82
83/* PCI Address Constants */
6dcc19df 84#define SMBBAR 4
1da177e4 85#define SMBHSTCFG 0x040
1da177e4
LT		 86
87/* Host configuration bits for SMBHSTCFG */
88#define SMBHSTCFG_HST_EN 1
89#define SMBHSTCFG_SMB_SMI_EN 2
90#define SMBHSTCFG_I2C_EN 4
91
ca8b9e32
OR		 92/* Auxillary control register bits, ICH4+ only */
93#define SMBAUXCTL_CRC 1
94#define SMBAUXCTL_E32B 2
95
96/* kill bit for SMBHSTCNT */
97#define SMBHSTCNT_KILL 2
98
1da177e4
LT		 99/* Other settings */
100#define MAX_TIMEOUT 100
101#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
102
103/* I801 command constants */
104#define I801_QUICK 0x00
105#define I801_BYTE 0x04
106#define I801_BYTE_DATA 0x08
107#define I801_WORD_DATA 0x0C
ae7b0497 108#define I801_PROC_CALL 0x10 /* unimplemented */
1da177e4 109#define I801_BLOCK_DATA 0x14
6342064c 110#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
1da177e4 111#define I801_BLOCK_LAST 0x34
6342064c 112#define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
1da177e4 113#define I801_START 0x40
ae7b0497 114#define I801_PEC_EN 0x80 /* ICH3 and later */
1da177e4 115
ca8b9e32
OR		 116/* I801 Hosts Status register bits */
117#define SMBHSTSTS_BYTE_DONE 0x80
118#define SMBHSTSTS_INUSE_STS 0x40
119#define SMBHSTSTS_SMBALERT_STS 0x20
120#define SMBHSTSTS_FAILED 0x10
121#define SMBHSTSTS_BUS_ERR 0x08
122#define SMBHSTSTS_DEV_ERR 0x04
123#define SMBHSTSTS_INTR 0x02
124#define SMBHSTSTS_HOST_BUSY 0x01
1da177e4 125
cf898dc5
JD		 126#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
127 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
128 SMBHSTSTS_INTR)
129
6dcc19df 130static unsigned long i801_smba;
a5aaea37 131static unsigned char i801_original_hstcfg;
d6072f84 132static struct pci_driver i801_driver;
1da177e4 133static struct pci_dev *I801_dev;
369f6f4a
JD		 134
135#define FEATURE_SMBUS_PEC (1 << 0)
136#define FEATURE_BLOCK_BUFFER (1 << 1)
137#define FEATURE_BLOCK_PROC (1 << 2)
138#define FEATURE_I2C_BLOCK_READ (1 << 3)
139static unsigned int i801_features;
1da177e4 140
cf898dc5
JD		 141/* Make sure the SMBus host is ready to start transmitting.
142 Return 0 if it is, -EBUSY if it is not. */
143static int i801_check_pre(void)
1da177e4 144{
2b73809d 145 int status;
1da177e4 146
cf898dc5
JD		 147 status = inb_p(SMBHSTSTS);
148 if (status & SMBHSTSTS_HOST_BUSY) {
149 dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n");
150 return -EBUSY;
151 }
152
153 status &= STATUS_FLAGS;
154 if (status) {
155 dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n",
2b73809d
JD		 156 status);
157 outb_p(status, SMBHSTSTS);
cf898dc5
JD		 158 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
159 if (status) {
160 dev_err(&I801_dev->dev,
161 "Failed clearing status flags (%02x)\n",
162 status);
97140342 163 return -EBUSY;
1da177e4
LT		 164 }
165 }
166
cf898dc5
JD		 167 return 0;
168}
1da177e4 169
cf898dc5
JD		 170/* Convert the status register to an error code, and clear it. */
171static int i801_check_post(int status, int timeout)
172{
173 int result = 0;
1da177e4
LT		 174
175 /* If the SMBus is still busy, we give up */
cf898dc5
JD		 176 if (timeout) {
177 dev_err(&I801_dev->dev, "Transaction timeout\n");
ca8b9e32
OR		 178 /* try to stop the current command */
179 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
180 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
181 msleep(1);
182 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
cf898dc5
JD		 183
184 /* Check if it worked */
185 status = inb_p(SMBHSTSTS);
186 if ((status & SMBHSTSTS_HOST_BUSY) ||
187 !(status & SMBHSTSTS_FAILED))
188 dev_err(&I801_dev->dev,
189 "Failed terminating the transaction\n");
190 outb_p(STATUS_FLAGS, SMBHSTSTS);
191 return -ETIMEDOUT;
1da177e4
LT		 192 }
193
2b73809d 194 if (status & SMBHSTSTS_FAILED) {
97140342 195 result = -EIO;
cf898dc5
JD		 196 dev_err(&I801_dev->dev, "Transaction failed\n");
197 }
198 if (status & SMBHSTSTS_DEV_ERR) {
199 result = -ENXIO;
200 dev_dbg(&I801_dev->dev, "No response\n");
1da177e4 201 }
2b73809d 202 if (status & SMBHSTSTS_BUS_ERR) {
dcb5c923
JD		 203 result = -EAGAIN;
204 dev_dbg(&I801_dev->dev, "Lost arbitration\n");
1da177e4
LT		 205 }
206
cf898dc5
JD		 207 if (result) {
208 /* Clear error flags */
209 outb_p(status & STATUS_FLAGS, SMBHSTSTS);
210 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
211 if (status) {
212 dev_warn(&I801_dev->dev, "Failed clearing status "
213 "flags at end of transaction (%02x)\n",
214 status);
215 }
1da177e4
LT		 216 }
217
1da177e4
LT		 218 return result;
219}
220
cf898dc5
JD		 221static int i801_transaction(int xact)
222{
223 int status;
224 int result;
225 int timeout = 0;
226
227 result = i801_check_pre();
228 if (result < 0)
229 return result;
230
231 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
232 * INTREN, SMBSCMD are passed in xact */
233 outb_p(xact | I801_START, SMBHSTCNT);
234
235 /* We will always wait for a fraction of a second! */
236 do {
237 msleep(1);
238 status = inb_p(SMBHSTSTS);
239 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
240
4ccc28f7 241 result = i801_check_post(status, timeout > MAX_TIMEOUT);
cf898dc5
JD		 242 if (result < 0)
243 return result;
244
245 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
246 return 0;
247}
248
ca8b9e32
OR		 249/* wait for INTR bit as advised by Intel */
250static void i801_wait_hwpec(void)
251{
252 int timeout = 0;
2b73809d 253 int status;
ca8b9e32
OR		 254
255 do {
256 msleep(1);
2b73809d
JD		 257 status = inb_p(SMBHSTSTS);
258 } while ((!(status & SMBHSTSTS_INTR))
ca8b9e32
OR		 259 && (timeout++ < MAX_TIMEOUT));
260
4ccc28f7 261 if (timeout > MAX_TIMEOUT)
ca8b9e32 262 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
4ccc28f7 263
2b73809d 264 outb_p(status, SMBHSTSTS);
ca8b9e32
OR		 265}
266
7edcb9ab
OR		 267static int i801_block_transaction_by_block(union i2c_smbus_data *data,
268 char read_write, int hwpec)
269{
270 int i, len;
97140342 271 int status;
7edcb9ab
OR		 272
273 inb_p(SMBHSTCNT); /* reset the data buffer index */
274
275 /* Use 32-byte buffer to process this transaction */
276 if (read_write == I2C_SMBUS_WRITE) {
277 len = data->block[0];
278 outb_p(len, SMBHSTDAT0);
279 for (i = 0; i < len; i++)
280 outb_p(data->block[i+1], SMBBLKDAT);
281 }
282
97140342
DB		 283 status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
284 I801_PEC_EN * hwpec);
285 if (status)
286 return status;
7edcb9ab
OR		 287
288 if (read_write == I2C_SMBUS_READ) {
289 len = inb_p(SMBHSTDAT0);
290 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
97140342 291 return -EPROTO;
7edcb9ab
OR		 292
293 data->block[0] = len;
294 for (i = 0; i < len; i++)
295 data->block[i + 1] = inb_p(SMBBLKDAT);
296 }
297 return 0;
298}
299
300static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
6342064c
JD		 301 char read_write, int command,
302 int hwpec)
1da177e4
LT		 303{
304 int i, len;
305 int smbcmd;
2b73809d 306 int status;
cf898dc5 307 int result;
1da177e4 308 int timeout;
cf898dc5
JD		 309
310 result = i801_check_pre();
311 if (result < 0)
312 return result;
1da177e4 313
7edcb9ab 314 len = data->block[0];
1da177e4
LT		 315
316 if (read_write == I2C_SMBUS_WRITE) {
1da177e4
LT		 317 outb_p(len, SMBHSTDAT0);
318 outb_p(data->block[1], SMBBLKDAT);
1da177e4
LT		 319 }
320
321 for (i = 1; i <= len; i++) {
6342064c
JD		 322 if (i == len && read_write == I2C_SMBUS_READ) {
323 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
324 smbcmd = I801_I2C_BLOCK_LAST;
325 else
326 smbcmd = I801_BLOCK_LAST;
327 } else {
328 if (command == I2C_SMBUS_I2C_BLOCK_DATA
329 && read_write == I2C_SMBUS_READ)
330 smbcmd = I801_I2C_BLOCK_DATA;
331 else
332 smbcmd = I801_BLOCK_DATA;
333 }
1da177e4
LT		 334 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
335
1da177e4
LT		 336 if (i == 1)
337 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
338
339 /* We will always wait for a fraction of a second! */
340 timeout = 0;
341 do {
1da177e4 342 msleep(1);
2b73809d 343 status = inb_p(SMBHSTSTS);
1da177e4 344 }
2b73809d 345 while ((!(status & SMBHSTSTS_BYTE_DONE))
ca8b9e32 346 && (timeout++ < MAX_TIMEOUT));
1da177e4 347
4ccc28f7 348 result = i801_check_post(status, timeout > MAX_TIMEOUT);
cf898dc5
JD		 349 if (result < 0)
350 return result;
1da177e4 351
6342064c
JD		 352 if (i == 1 && read_write == I2C_SMBUS_READ
353 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
1da177e4 354 len = inb_p(SMBHSTDAT0);
cf898dc5
JD		 355 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
356 dev_err(&I801_dev->dev,
357 "Illegal SMBus block read size %d\n",
358 len);
359 /* Recover */
360 while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
361 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS);
362 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
97140342 363 return -EPROTO;
cf898dc5 364 }
1da177e4
LT		 365 data->block[0] = len;
366 }
367
368 /* Retrieve/store value in SMBBLKDAT */
369 if (read_write == I2C_SMBUS_READ)
370 data->block[i] = inb_p(SMBBLKDAT);
371 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
372 outb_p(data->block[i+1], SMBBLKDAT);
1da177e4 373
cf898dc5
JD		 374 /* signals SMBBLKDAT ready */
375 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS);
1da177e4 376 }
cf898dc5
JD		 377
378 return 0;
7edcb9ab 379}
1da177e4 380
7edcb9ab
OR		 381static int i801_set_block_buffer_mode(void)
382{
383 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
384 if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
97140342 385 return -EIO;
7edcb9ab
OR		 386 return 0;
387}
388
389/* Block transaction function */
390static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
391 int command, int hwpec)
392{
393 int result = 0;
394 unsigned char hostc;
395
396 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
397 if (read_write == I2C_SMBUS_WRITE) {
398 /* set I2C_EN bit in configuration register */
399 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
400 pci_write_config_byte(I801_dev, SMBHSTCFG,
401 hostc | SMBHSTCFG_I2C_EN);
6342064c 402 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
7edcb9ab 403 dev_err(&I801_dev->dev,
6342064c 404 "I2C block read is unsupported!\n");
97140342 405 return -EOPNOTSUPP;
7edcb9ab
OR		 406 }
407 }
408
6342064c
JD		 409 if (read_write == I2C_SMBUS_WRITE
410 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
7edcb9ab
OR		 411 if (data->block[0] < 1)
412 data->block[0] = 1;
413 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
414 data->block[0] = I2C_SMBUS_BLOCK_MAX;
415 } else {
6342064c 416 data->block[0] = 32; /* max for SMBus block reads */
7edcb9ab
OR		 417 }
418
369f6f4a 419 if ((i801_features & FEATURE_BLOCK_BUFFER)
6342064c
JD		 420 && !(command == I2C_SMBUS_I2C_BLOCK_DATA
421 && read_write == I2C_SMBUS_READ)
369f6f4a 422 && i801_set_block_buffer_mode() == 0)
7edcb9ab
OR		 423 result = i801_block_transaction_by_block(data, read_write,
424 hwpec);
425 else
426 result = i801_block_transaction_byte_by_byte(data, read_write,
6342064c 427 command, hwpec);
7edcb9ab
OR		 428
429 if (result == 0 && hwpec)
ca8b9e32 430 i801_wait_hwpec();
1da177e4 431
6342064c
JD		 432 if (command == I2C_SMBUS_I2C_BLOCK_DATA
433 && read_write == I2C_SMBUS_WRITE) {
1da177e4
LT		 434 /* restore saved configuration register value */
435 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
436 }
437 return result;
438}
439
97140342 440/* Return negative errno on error. */
1da177e4
LT		 441static s32 i801_access(struct i2c_adapter * adap, u16 addr,
442 unsigned short flags, char read_write, u8 command,
443 int size, union i2c_smbus_data * data)
444{
e8aac4a9 445 int hwpec;
1da177e4
LT		 446 int block = 0;
447 int ret, xact = 0;
448
369f6f4a 449 hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
e8aac4a9
JD		 450 && size != I2C_SMBUS_QUICK
451 && size != I2C_SMBUS_I2C_BLOCK_DATA;
1da177e4
LT		 452
453 switch (size) {
454 case I2C_SMBUS_QUICK:
455 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
456 SMBHSTADD);
457 xact = I801_QUICK;
458 break;
459 case I2C_SMBUS_BYTE:
460 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
461 SMBHSTADD);
462 if (read_write == I2C_SMBUS_WRITE)
463 outb_p(command, SMBHSTCMD);
464 xact = I801_BYTE;
465 break;
466 case I2C_SMBUS_BYTE_DATA:
467 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
468 SMBHSTADD);
469 outb_p(command, SMBHSTCMD);
470 if (read_write == I2C_SMBUS_WRITE)
471 outb_p(data->byte, SMBHSTDAT0);
472 xact = I801_BYTE_DATA;
473 break;
474 case I2C_SMBUS_WORD_DATA:
475 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
476 SMBHSTADD);
477 outb_p(command, SMBHSTCMD);
478 if (read_write == I2C_SMBUS_WRITE) {
479 outb_p(data->word & 0xff, SMBHSTDAT0);
480 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
481 }
482 xact = I801_WORD_DATA;
483 break;
484 case I2C_SMBUS_BLOCK_DATA:
1da177e4
LT		 485 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
486 SMBHSTADD);
487 outb_p(command, SMBHSTCMD);
488 block = 1;
489 break;
6342064c
JD		 490 case I2C_SMBUS_I2C_BLOCK_DATA:
491 /* NB: page 240 of ICH5 datasheet shows that the R/#W
492 * bit should be cleared here, even when reading */
493 outb_p((addr & 0x7f) << 1, SMBHSTADD);
494 if (read_write == I2C_SMBUS_READ) {
495 /* NB: page 240 of ICH5 datasheet also shows
496 * that DATA1 is the cmd field when reading */
497 outb_p(command, SMBHSTDAT1);
498 } else
499 outb_p(command, SMBHSTCMD);
500 block = 1;
501 break;
1da177e4
LT		 502 default:
503 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
97140342 504 return -EOPNOTSUPP;
1da177e4
LT		 505 }
506
ca8b9e32
OR		 507 if (hwpec) /* enable/disable hardware PEC */
508 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
509 else
510 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
e8aac4a9 511
1da177e4 512 if(block)
585b3160 513 ret = i801_block_transaction(data, read_write, size, hwpec);
7edcb9ab
OR		 514 else
515 ret = i801_transaction(xact | ENABLE_INT9);
1da177e4 516
c79cfbac 517 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
7edcb9ab
OR		 518 time, so we forcibly disable it after every transaction. Turn off
519 E32B for the same reason. */
a0921b6c 520 if (hwpec || block)
7edcb9ab
OR		 521 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
522 SMBAUXCTL);
c79cfbac 523
1da177e4
LT		 524 if(block)
525 return ret;
526 if(ret)
97140342 527 return ret;
1da177e4
LT		 528 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
529 return 0;
530
531 switch (xact & 0x7f) {
532 case I801_BYTE: /* Result put in SMBHSTDAT0 */
533 case I801_BYTE_DATA:
534 data->byte = inb_p(SMBHSTDAT0);
535 break;
536 case I801_WORD_DATA:
537 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
538 break;
539 }
540 return 0;
541}
542
543
544static u32 i801_func(struct i2c_adapter *adapter)
545{
546 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
369f6f4a
JD		 547 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
548 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
6342064c
JD		 549 ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
550 ((i801_features & FEATURE_I2C_BLOCK_READ) ?
551 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
1da177e4
LT		 552}
553
8f9082c5 554static const struct i2c_algorithm smbus_algorithm = {
1da177e4
LT		 555 .smbus_xfer = i801_access,
556 .functionality = i801_func,
557};
558
559static struct i2c_adapter i801_adapter = {
560 .owner = THIS_MODULE,
3401b2ff 561 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
1da177e4 562 .algo = &smbus_algorithm,
1da177e4
LT		 563};
564
4111ecd2 565static const struct pci_device_id i801_ids[] = {
1da177e4
LT		 566 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
567 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
568 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
569 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
570 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
571 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
572 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
573 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
574 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
b0a70b57 575 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
8254fc4a 576 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
adbc2a10 577 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
e07bc679 578 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
d28dc711
GJ		 579 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
580 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
c429a247 581 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PCH_SMBUS) },
39376434 582 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CPT_SMBUS) },
1da177e4
LT		 583 { 0, }
584};
585
586MODULE_DEVICE_TABLE (pci, i801_ids);
587
1561bfe5
JD		 588#if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
589static unsigned char apanel_addr;
590
591/* Scan the system ROM for the signature "FJKEYINF" */
592static __init const void __iomem *bios_signature(const void __iomem *bios)
593{
594 ssize_t offset;
595 const unsigned char signature[] = "FJKEYINF";
596
597 for (offset = 0; offset < 0x10000; offset += 0x10) {
598 if (check_signature(bios + offset, signature,
599 sizeof(signature)-1))
600 return bios + offset;
601 }
602 return NULL;
603}
604
605static void __init input_apanel_init(void)
606{
607 void __iomem *bios;
608 const void __iomem *p;
609
610 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
611 p = bios_signature(bios);
612 if (p) {
613 /* just use the first address */
614 apanel_addr = readb(p + 8 + 3) >> 1;
615 }
616 iounmap(bios);
617}
618#else
619static void __init input_apanel_init(void) {}
620#endif
621
fa5bfab7
HG		 622#if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
623struct dmi_onboard_device_info {
624 const char *name;
625 u8 type;
626 unsigned short i2c_addr;
627 const char *i2c_type;
628};
629
630static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
631 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
632 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
633 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
634};
635
636static void __devinit dmi_check_onboard_device(u8 type, const char *name,
637 struct i2c_adapter *adap)
638{
639 int i;
640 struct i2c_board_info info;
641
642 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
643 /* & ~0x80, ignore enabled/disabled bit */
644 if ((type & ~0x80) != dmi_devices[i].type)
645 continue;
646 if (strcmp(name, dmi_devices[i].name))
647 continue;
648
649 memset(&info, 0, sizeof(struct i2c_board_info));
650 info.addr = dmi_devices[i].i2c_addr;
651 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
652 i2c_new_device(adap, &info);
653 break;
654 }
655}
656
657/* We use our own function to check for onboard devices instead of
658 dmi_find_device() as some buggy BIOS's have the devices we are interested
659 in marked as disabled */
660static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
661 void *adap)
662{
663 int i, count;
664
665 if (dm->type != 10)
666 return;
667
668 count = (dm->length - sizeof(struct dmi_header)) / 2;
669 for (i = 0; i < count; i++) {
670 const u8 *d = (char *)(dm + 1) + (i * 2);
671 const char *name = ((char *) dm) + dm->length;
672 u8 type = d[0];
673 u8 s = d[1];
674
675 if (!s)
676 continue;
677 s--;
678 while (s > 0 && name[0]) {
679 name += strlen(name) + 1;
680 s--;
681 }
682 if (name[0] == 0) /* Bogus string reference */
683 continue;
684
685 dmi_check_onboard_device(type, name, adap);
686 }
687}
688#endif
689
1da177e4
LT		 690static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
691{
02dd7ae2 692 unsigned char temp;
455f3323 693 int err;
fa5bfab7
HG		 694#if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
695 const char *vendor;
696#endif
1da177e4 697
02dd7ae2 698 I801_dev = dev;
369f6f4a 699 i801_features = 0;
250d1bd3 700 switch (dev->device) {
250d1bd3
JD		 701 case PCI_DEVICE_ID_INTEL_82801EB_3:
702 case PCI_DEVICE_ID_INTEL_ESB_4:
703 case PCI_DEVICE_ID_INTEL_ICH6_16:
704 case PCI_DEVICE_ID_INTEL_ICH7_17:
705 case PCI_DEVICE_ID_INTEL_ESB2_17:
706 case PCI_DEVICE_ID_INTEL_ICH8_5:
707 case PCI_DEVICE_ID_INTEL_ICH9_6:
d28dc711
GJ		 708 case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
709 case PCI_DEVICE_ID_INTEL_ICH10_4:
710 case PCI_DEVICE_ID_INTEL_ICH10_5:
c429a247 711 case PCI_DEVICE_ID_INTEL_PCH_SMBUS:
39376434 712 case PCI_DEVICE_ID_INTEL_CPT_SMBUS:
6342064c
JD		 713 i801_features |= FEATURE_I2C_BLOCK_READ;
714 /* fall through */
715 case PCI_DEVICE_ID_INTEL_82801DB_3:
369f6f4a
JD		 716 i801_features |= FEATURE_SMBUS_PEC;
717 i801_features |= FEATURE_BLOCK_BUFFER;
250d1bd3 718 break;
250d1bd3 719 }
02dd7ae2
JD		 720
721 err = pci_enable_device(dev);
722 if (err) {
723 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
724 err);
725 goto exit;
726 }
727
728 /* Determine the address of the SMBus area */
729 i801_smba = pci_resource_start(dev, SMBBAR);
730 if (!i801_smba) {
731 dev_err(&dev->dev, "SMBus base address uninitialized, "
732 "upgrade BIOS\n");
733 err = -ENODEV;
d6fcb3b9 734 goto exit;
02dd7ae2
JD		 735 }
736
54fb4a05 737 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
18669eab
JD		 738 if (err) {
739 err = -ENODEV;
54fb4a05 740 goto exit;
18669eab 741 }
54fb4a05 742
02dd7ae2
JD		 743 err = pci_request_region(dev, SMBBAR, i801_driver.name);
744 if (err) {
745 dev_err(&dev->dev, "Failed to request SMBus region "
598736c5
AM		 746 "0x%lx-0x%Lx\n", i801_smba,
747 (unsigned long long)pci_resource_end(dev, SMBBAR));
d6fcb3b9 748 goto exit;
02dd7ae2
JD		 749 }
750
751 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
a5aaea37 752 i801_original_hstcfg = temp;
02dd7ae2
JD		 753 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
754 if (!(temp & SMBHSTCFG_HST_EN)) {
755 dev_info(&dev->dev, "Enabling SMBus device\n");
756 temp |= SMBHSTCFG_HST_EN;
757 }
758 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
759
760 if (temp & SMBHSTCFG_SMB_SMI_EN)
761 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
762 else
763 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
1da177e4 764
a0921b6c
JD		 765 /* Clear special mode bits */
766 if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
767 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
768 SMBAUXCTL);
769
405ae7d3 770 /* set up the sysfs linkage to our parent device */
1da177e4
LT		 771 i801_adapter.dev.parent = &dev->dev;
772
7e2193a8
JD		 773 /* Retry up to 3 times on lost arbitration */
774 i801_adapter.retries = 3;
775
2096b956 776 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
6dcc19df 777 "SMBus I801 adapter at %04lx", i801_smba);
02dd7ae2
JD		 778 err = i2c_add_adapter(&i801_adapter);
779 if (err) {
780 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
d6fcb3b9 781 goto exit_release;
02dd7ae2 782 }
1561bfe5
JD		 783
784 /* Register optional slaves */
785#if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
786 if (apanel_addr) {
787 struct i2c_board_info info;
788
789 memset(&info, 0, sizeof(struct i2c_board_info));
790 info.addr = apanel_addr;
791 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
792 i2c_new_device(&i801_adapter, &info);
793 }
794#endif
fa5bfab7
HG		 795#if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
796 vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
797 if (vendor && !strcmp(vendor, "FUJITSU SIEMENS"))
798 dmi_walk(dmi_check_onboard_devices, &i801_adapter);
799#endif
1561bfe5 800
d6fcb3b9 801 return 0;
02dd7ae2 802
d6fcb3b9
DR		 803exit_release:
804 pci_release_region(dev, SMBBAR);
02dd7ae2
JD		 805exit:
806 return err;
1da177e4
LT		 807}
808
809static void __devexit i801_remove(struct pci_dev *dev)
810{
811 i2c_del_adapter(&i801_adapter);
a5aaea37 812 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
6dcc19df 813 pci_release_region(dev, SMBBAR);
d6fcb3b9
DR		 814 /*
815 * do not call pci_disable_device(dev) since it can cause hard hangs on
816 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
817 */
1da177e4
LT		 818}
819
a5aaea37
JD		 820#ifdef CONFIG_PM
821static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
822{
823 pci_save_state(dev);
824 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
825 pci_set_power_state(dev, pci_choose_state(dev, mesg));
826 return 0;
827}
828
829static int i801_resume(struct pci_dev *dev)
830{
831 pci_set_power_state(dev, PCI_D0);
832 pci_restore_state(dev);
833 return pci_enable_device(dev);
834}
835#else
836#define i801_suspend NULL
837#define i801_resume NULL
838#endif
839
1da177e4
LT		 840static struct pci_driver i801_driver = {
841 .name = "i801_smbus",
842 .id_table = i801_ids,
843 .probe = i801_probe,
844 .remove = __devexit_p(i801_remove),
a5aaea37
JD		 845 .suspend = i801_suspend,
846 .resume = i801_resume,
1da177e4
LT		 847};
848
849static int __init i2c_i801_init(void)
850{
1561bfe5 851 input_apanel_init();
1da177e4
LT		 852 return pci_register_driver(&i801_driver);
853}
854
855static void __exit i2c_i801_exit(void)
856{
857 pci_unregister_driver(&i801_driver);
858}
859
6342064c
JD		 860MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
861 "Jean Delvare <khali@linux-fr.org>");
1da177e4
LT		 862MODULE_DESCRIPTION("I801 SMBus driver");
863MODULE_LICENSE("GPL");
864
865module_init(i2c_i801_init);
866module_exit(i2c_i801_exit);
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