[net-next-2.6.git] / drivers / i2c / busses / i2c-i801.c

/*
    i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
              monitoring
    Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
    Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
    <mdsxyz123@yahoo.com>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

/*
    SUPPORTED DEVICES	PCI ID
    82801AA		2413           
    82801AB		2423           
    82801BA		2443           
    82801CA/CAM		2483           
    82801DB		24C3   (HW PEC supported, 32 byte buffer not supported)
    82801EB		24D3   (HW PEC supported, 32 byte buffer not supported)
    6300ESB		25A4
    ICH6		266A
    ICH7		27DA
    ESB2		269B
    ICH8		283E
    This driver supports several versions of Intel's I/O Controller Hubs (ICH).
    For SMBus support, they are similar to the PIIX4 and are part
    of Intel's '810' and other chipsets.
    See the file Documentation/i2c/busses/i2c-i801 for details.
    I2C Block Read and Process Call are not supported.
*/

/* Note: we assume there can only be one I801, with one SMBus interface */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <asm/io.h>

/* I801 SMBus address offsets */
#define SMBHSTSTS	(0 + i801_smba)
#define SMBHSTCNT	(2 + i801_smba)
#define SMBHSTCMD	(3 + i801_smba)
#define SMBHSTADD	(4 + i801_smba)
#define SMBHSTDAT0	(5 + i801_smba)
#define SMBHSTDAT1	(6 + i801_smba)
#define SMBBLKDAT	(7 + i801_smba)
#define SMBPEC		(8 + i801_smba)	/* ICH4 only */
#define SMBAUXSTS	(12 + i801_smba)	/* ICH4 only */
#define SMBAUXCTL	(13 + i801_smba)	/* ICH4 only */

/* PCI Address Constants */
#define SMBBA		0x020
#define SMBHSTCFG	0x040
#define SMBREV		0x008

/* Host configuration bits for SMBHSTCFG */
#define SMBHSTCFG_HST_EN	1
#define SMBHSTCFG_SMB_SMI_EN	2
#define SMBHSTCFG_I2C_EN	4

/* Other settings */
#define MAX_TIMEOUT		100
#define ENABLE_INT9		0	/* set to 0x01 to enable - untested */

/* I801 command constants */
#define I801_QUICK		0x00
#define I801_BYTE		0x04
#define I801_BYTE_DATA		0x08
#define I801_WORD_DATA		0x0C
#define I801_PROC_CALL		0x10	/* later chips only, unimplemented */
#define I801_BLOCK_DATA		0x14
#define I801_I2C_BLOCK_DATA	0x18	/* unimplemented */
#define I801_BLOCK_LAST		0x34
#define I801_I2C_BLOCK_LAST	0x38	/* unimplemented */
#define I801_START		0x40
#define I801_PEC_EN		0x80	/* ICH4 only */


static int i801_transaction(void);
static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
				  int command, int hwpec);

static unsigned short i801_smba;
static struct pci_driver i801_driver;
static struct pci_dev *I801_dev;
static int isich4;

static int __devinit i801_setup(struct pci_dev *dev)
{
	unsigned char temp;

	I801_dev = dev;
	if ((dev->device == PCI_DEVICE_ID_INTEL_82801DB_3) ||
	    (dev->device == PCI_DEVICE_ID_INTEL_82801EB_3) ||
	    (dev->device == PCI_DEVICE_ID_INTEL_ESB_4))
		isich4 = 1;
	else
		isich4 = 0;

	/* Determine the address of the SMBus area */
	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
	i801_smba &= 0xfff0;
	if (!i801_smba) {
		dev_err(&dev->dev, "SMBus base address uninitialized, "
			"upgrade BIOS\n");
		return -ENODEV;
	}

	if (!request_region(i801_smba, (isich4 ? 16 : 8), i801_driver.name)) {
		dev_err(&dev->dev, "I801_smb region 0x%x already in use!\n",
			i801_smba);
		return -EBUSY;
	}

	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
	temp &= ~SMBHSTCFG_I2C_EN;	/* SMBus timing */
	if (!(temp & SMBHSTCFG_HST_EN)) {
		dev_warn(&dev->dev, "enabling SMBus device\n");
		temp |= SMBHSTCFG_HST_EN;
	}
	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);

	if (temp & SMBHSTCFG_SMB_SMI_EN)
		dev_dbg(&dev->dev, "I801 using Interrupt SMI# for SMBus.\n");
	else
		dev_dbg(&dev->dev, "I801 using PCI Interrupt for SMBus.\n");

	pci_read_config_byte(I801_dev, SMBREV, &temp);
	dev_dbg(&dev->dev, "SMBREV = 0x%X\n", temp);
	dev_dbg(&dev->dev, "I801_smba = 0x%X\n", i801_smba);

	return 0;
}

static int i801_transaction(void)
{
	int temp;
	int result = 0;
	int timeout = 0;

	dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
		inb_p(SMBHSTDAT1));

	/* Make sure the SMBus host is ready to start transmitting */
	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
		dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
			temp);
		outb_p(temp, SMBHSTSTS);
		if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
			dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
			return -1;
		} else {
			dev_dbg(&I801_dev->dev, "Successfull!\n");
		}
	}

	outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);

	/* We will always wait for a fraction of a second! */
	do {
		msleep(1);
		temp = inb_p(SMBHSTSTS);
	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));

	/* If the SMBus is still busy, we give up */
	if (timeout >= MAX_TIMEOUT) {
		dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
		result = -1;
	}

	if (temp & 0x10) {
		result = -1;
		dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
	}

	if (temp & 0x08) {
		result = -1;
		dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
			"until next hard reset. (sorry!)\n");
		/* Clock stops and slave is stuck in mid-transmission */
	}

	if (temp & 0x04) {
		result = -1;
		dev_dbg(&I801_dev->dev, "Error: no response!\n");
	}

	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
		outb_p(inb(SMBHSTSTS), SMBHSTSTS);

	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
		dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
			"(%02x)\n", temp);
	}
	dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
		"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
		inb_p(SMBHSTDAT1));
	return result;
}

/* All-inclusive block transaction function */
static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
				  int command, int hwpec)
{
	int i, len;
	int smbcmd;
	int temp;
	int result = 0;
	int timeout;
	unsigned char hostc, errmask;

	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
		if (read_write == I2C_SMBUS_WRITE) {
			/* set I2C_EN bit in configuration register */
			pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
			pci_write_config_byte(I801_dev, SMBHSTCFG,
					      hostc | SMBHSTCFG_I2C_EN);
		} else {
			dev_err(&I801_dev->dev,
				"I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
			return -1;
		}
	}

	if (read_write == I2C_SMBUS_WRITE) {
		len = data->block[0];
		if (len < 1)
			len = 1;
		if (len > 32)
			len = 32;
		outb_p(len, SMBHSTDAT0);
		outb_p(data->block[1], SMBBLKDAT);
	} else {
		len = 32;	/* max for reads */
	}

	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
		/* set 32 byte buffer */
	}

	for (i = 1; i <= len; i++) {
		if (i == len && read_write == I2C_SMBUS_READ)
			smbcmd = I801_BLOCK_LAST;
		else
			smbcmd = I801_BLOCK_DATA;
		outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);

		dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
			"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
			inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
			inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));

		/* Make sure the SMBus host is ready to start transmitting */
		temp = inb_p(SMBHSTSTS);
		if (i == 1) {
			/* Erronenous conditions before transaction: 
			 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
			errmask=0x9f; 
		} else {
			/* Erronenous conditions during transaction: 
			 * Failed, Bus_Err, Dev_Err, Intr */
			errmask=0x1e; 
		}
		if (temp & errmask) {
			dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
				"Resetting...\n", temp);
			outb_p(temp, SMBHSTSTS);
			if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
				dev_err(&I801_dev->dev,
					"Reset failed! (%02x)\n", temp);
				result = -1;
                                goto END;
			}
			if (i != 1) {
				/* if die in middle of block transaction, fail */
				result = -1;
				goto END;
			}
		}

		if (i == 1)
			outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);

		/* We will always wait for a fraction of a second! */
		timeout = 0;
		do {
			msleep(1);
			temp = inb_p(SMBHSTSTS);
		}
		    while ((!(temp & 0x80))
			   && (timeout++ < MAX_TIMEOUT));

		/* If the SMBus is still busy, we give up */
		if (timeout >= MAX_TIMEOUT) {
			result = -1;
			dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
		}

		if (temp & 0x10) {
			result = -1;
			dev_dbg(&I801_dev->dev,
				"Error: Failed bus transaction\n");
		} else if (temp & 0x08) {
			result = -1;
			dev_err(&I801_dev->dev, "Bus collision!\n");
		} else if (temp & 0x04) {
			result = -1;
			dev_dbg(&I801_dev->dev, "Error: no response!\n");
		}

		if (i == 1 && read_write == I2C_SMBUS_READ) {
			len = inb_p(SMBHSTDAT0);
			if (len < 1)
				len = 1;
			if (len > 32)
				len = 32;
			data->block[0] = len;
		}

		/* Retrieve/store value in SMBBLKDAT */
		if (read_write == I2C_SMBUS_READ)
			data->block[i] = inb_p(SMBBLKDAT);
		if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
			outb_p(data->block[i+1], SMBBLKDAT);
		if ((temp & 0x9e) != 0x00)
			outb_p(temp, SMBHSTSTS);  /* signals SMBBLKDAT ready */

		if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
			dev_dbg(&I801_dev->dev,
				"Bad status (%02x) at end of transaction\n",
				temp);
		}
		dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
			"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
			inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
			inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));

		if (result < 0)
			goto END;
	}

	if (hwpec) {
		/* wait for INTR bit as advised by Intel */
		timeout = 0;
		do {
			msleep(1);
			temp = inb_p(SMBHSTSTS);
		} while ((!(temp & 0x02))
			   && (timeout++ < MAX_TIMEOUT));

		if (timeout >= MAX_TIMEOUT) {
			dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
		}
		outb_p(temp, SMBHSTSTS); 
	}
	result = 0;
END:
	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
		/* restore saved configuration register value */
		pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
	}
	return result;
}

/* Return -1 on error. */
static s32 i801_access(struct i2c_adapter * adap, u16 addr,
		       unsigned short flags, char read_write, u8 command,
		       int size, union i2c_smbus_data * data)
{
	int hwpec;
	int block = 0;
	int ret, xact = 0;

	hwpec = isich4 && (flags & I2C_CLIENT_PEC)
		&& size != I2C_SMBUS_QUICK
		&& size != I2C_SMBUS_I2C_BLOCK_DATA;

	switch (size) {
	case I2C_SMBUS_QUICK:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		xact = I801_QUICK;
		break;
	case I2C_SMBUS_BYTE:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(command, SMBHSTCMD);
		xact = I801_BYTE;
		break;
	case I2C_SMBUS_BYTE_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE)
			outb_p(data->byte, SMBHSTDAT0);
		xact = I801_BYTE_DATA;
		break;
	case I2C_SMBUS_WORD_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		if (read_write == I2C_SMBUS_WRITE) {
			outb_p(data->word & 0xff, SMBHSTDAT0);
			outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
		}
		xact = I801_WORD_DATA;
		break;
	case I2C_SMBUS_BLOCK_DATA:
	case I2C_SMBUS_I2C_BLOCK_DATA:
		outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
		       SMBHSTADD);
		outb_p(command, SMBHSTCMD);
		block = 1;
		break;
	case I2C_SMBUS_PROC_CALL:
	default:
		dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
		return -1;
	}

	outb_p(hwpec, SMBAUXCTL);	/* enable/disable hardware PEC */

	if(block)
		ret = i801_block_transaction(data, read_write, size, hwpec);
	else {
		outb_p(xact | ENABLE_INT9, SMBHSTCNT);
		ret = i801_transaction();
	}

	/* Some BIOSes don't like it when PEC is enabled at reboot or resume
	   time, so we forcibly disable it after every transaction. */
	if (hwpec)
		outb_p(0, SMBAUXCTL);

	if(block)
		return ret;
	if(ret)
		return -1;
	if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
		return 0;

	switch (xact & 0x7f) {
	case I801_BYTE:	/* Result put in SMBHSTDAT0 */
	case I801_BYTE_DATA:
		data->byte = inb_p(SMBHSTDAT0);
		break;
	case I801_WORD_DATA:
		data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
		break;
	}
	return 0;
}


static u32 i801_func(struct i2c_adapter *adapter)
{
	return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
	    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
	    I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
	     | (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0);
}

static struct i2c_algorithm smbus_algorithm = {
	.smbus_xfer	= i801_access,
	.functionality	= i801_func,
};

static struct i2c_adapter i801_adapter = {
	.owner		= THIS_MODULE,
	.class		= I2C_CLASS_HWMON,
	.algo		= &smbus_algorithm,
};

static struct pci_device_id i801_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
	{ 0, }
};

MODULE_DEVICE_TABLE (pci, i801_ids);

static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int err;

	if ((err = i801_setup(dev)))
		return err;

	/* set up the driverfs linkage to our parent device */
	i801_adapter.dev.parent = &dev->dev;

	snprintf(i801_adapter.name, I2C_NAME_SIZE,
		"SMBus I801 adapter at %04x", i801_smba);
	return i2c_add_adapter(&i801_adapter);
}

static void __devexit i801_remove(struct pci_dev *dev)
{
	i2c_del_adapter(&i801_adapter);
	release_region(i801_smba, (isich4 ? 16 : 8));
}

static struct pci_driver i801_driver = {
	.name		= "i801_smbus",
	.id_table	= i801_ids,
	.probe		= i801_probe,
	.remove		= __devexit_p(i801_remove),
};

static int __init i2c_i801_init(void)
{
	return pci_register_driver(&i801_driver);
}

static void __exit i2c_i801_exit(void)
{
	pci_unregister_driver(&i801_driver);
}

MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
		"Philip Edelbrock <phil@netroedge.com>, "
		"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
MODULE_DESCRIPTION("I801 SMBus driver");
MODULE_LICENSE("GPL");

module_init(i2c_i801_init);
module_exit(i2c_i801_exit);
Commit	Line	Data
1da177e4	1	/*
455f3323	2	i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
1da177e4 LT	3	monitoring
	4	Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
	5	Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
	6	<mdsxyz123@yahoo.com>
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program; if not, write to the Free Software
	20	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	/*
	24	SUPPORTED DEVICES PCI ID
	25	82801AA 2413
	26	82801AB 2423
	27	82801BA 2443
	28	82801CA/CAM 2483
	29	82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
	30	82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
	31	6300ESB 25A4
	32	ICH6 266A
	33	ICH7 27DA
b0a70b57	34	ESB2 269B
8254fc4a	35	ICH8 283E
1da177e4 LT	36	This driver supports several versions of Intel's I/O Controller Hubs (ICH).
	37	For SMBus support, they are similar to the PIIX4 and are part
	38	of Intel's '810' and other chipsets.
455f3323	39	See the file Documentation/i2c/busses/i2c-i801 for details.
1da177e4 LT	40	I2C Block Read and Process Call are not supported.
	41	*/
	42
	43	/* Note: we assume there can only be one I801, with one SMBus interface */
	44
1da177e4 LT	45	#include <linux/module.h>
	46	#include <linux/pci.h>
	47	#include <linux/kernel.h>
	48	#include <linux/stddef.h>
	49	#include <linux/delay.h>
	50	#include <linux/sched.h>
	51	#include <linux/ioport.h>
	52	#include <linux/init.h>
	53	#include <linux/i2c.h>
	54	#include <asm/io.h>
	55
1da177e4 LT	56	/* I801 SMBus address offsets */
	57	#define SMBHSTSTS (0 + i801_smba)
	58	#define SMBHSTCNT (2 + i801_smba)
	59	#define SMBHSTCMD (3 + i801_smba)
	60	#define SMBHSTADD (4 + i801_smba)
	61	#define SMBHSTDAT0 (5 + i801_smba)
	62	#define SMBHSTDAT1 (6 + i801_smba)
	63	#define SMBBLKDAT (7 + i801_smba)
	64	#define SMBPEC (8 + i801_smba) /* ICH4 only */
	65	#define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
	66	#define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
	67
	68	/* PCI Address Constants */
	69	#define SMBBA 0x020
	70	#define SMBHSTCFG 0x040
	71	#define SMBREV 0x008
	72
	73	/* Host configuration bits for SMBHSTCFG */
	74	#define SMBHSTCFG_HST_EN 1
	75	#define SMBHSTCFG_SMB_SMI_EN 2
	76	#define SMBHSTCFG_I2C_EN 4
	77
	78	/* Other settings */
	79	#define MAX_TIMEOUT 100
	80	#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
	81
	82	/* I801 command constants */
	83	#define I801_QUICK 0x00
	84	#define I801_BYTE 0x04
	85	#define I801_BYTE_DATA 0x08
	86	#define I801_WORD_DATA 0x0C
	87	#define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
	88	#define I801_BLOCK_DATA 0x14
	89	#define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */
	90	#define I801_BLOCK_LAST 0x34
	91	#define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
	92	#define I801_START 0x40
	93	#define I801_PEC_EN 0x80 /* ICH4 only */
	94
1da177e4 LT	95
1da177e4 LT	96	static int i801_transaction(void);
585b3160 JD	97	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
585b3160 JD	98	int command, int hwpec);
1da177e4 LT	99
1da177e4 LT	100	static unsigned short i801_smba;
d6072f84	101	static struct pci_driver i801_driver;
1da177e4 LT	102	static struct pci_dev *I801_dev;
	103	static int isich4;
	104
455f3323	105	static int __devinit i801_setup(struct pci_dev *dev)
1da177e4	106	{
1da177e4 LT	107	unsigned char temp;
1da177e4 LT	108
1da177e4 LT	109	I801_dev = dev;
	110	if ((dev->device == PCI_DEVICE_ID_INTEL_82801DB_3) \|\|
	111	(dev->device == PCI_DEVICE_ID_INTEL_82801EB_3) \|\|
	112	(dev->device == PCI_DEVICE_ID_INTEL_ESB_4))
	113	isich4 = 1;
	114	else
	115	isich4 = 0;
	116
455f3323	117	/* Determine the address of the SMBus area */
d8db8f98 JD	118	pci_read_config_word(I801_dev, SMBBA, &i801_smba);
	119	i801_smba &= 0xfff0;
	120	if (!i801_smba) {
	121	dev_err(&dev->dev, "SMBus base address uninitialized, "
	122	"upgrade BIOS\n");
	123	return -ENODEV;
1da177e4 LT	124	}
1da177e4 LT	125
d6072f84	126	if (!request_region(i801_smba, (isich4 ? 16 : 8), i801_driver.name)) {
1da177e4 LT	127	dev_err(&dev->dev, "I801_smb region 0x%x already in use!\n",
1da177e4 LT	128	i801_smba);
455f3323	129	return -EBUSY;
1da177e4 LT	130	}
	131
	132	pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
	133	temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
455f3323	134	if (!(temp & SMBHSTCFG_HST_EN)) {
1da177e4	135	dev_warn(&dev->dev, "enabling SMBus device\n");
455f3323	136	temp \|= SMBHSTCFG_HST_EN;
1da177e4	137	}
455f3323	138	pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
1da177e4	139
455f3323	140	if (temp & SMBHSTCFG_SMB_SMI_EN)
1da177e4 LT	141	dev_dbg(&dev->dev, "I801 using Interrupt SMI# for SMBus.\n");
	142	else
	143	dev_dbg(&dev->dev, "I801 using PCI Interrupt for SMBus.\n");
	144
	145	pci_read_config_byte(I801_dev, SMBREV, &temp);
	146	dev_dbg(&dev->dev, "SMBREV = 0x%X\n", temp);
	147	dev_dbg(&dev->dev, "I801_smba = 0x%X\n", i801_smba);
	148
455f3323	149	return 0;
1da177e4 LT	150	}
	151
	152	static int i801_transaction(void)
	153	{
	154	int temp;
	155	int result = 0;
	156	int timeout = 0;
	157
368609c5	158	dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
1da177e4 LT	159	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
	160	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
	161	inb_p(SMBHSTDAT1));
	162
	163	/* Make sure the SMBus host is ready to start transmitting */
	164	/* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
	165	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
541e6a02	166	dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
1da177e4 LT	167	temp);
	168	outb_p(temp, SMBHSTSTS);
	169	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
	170	dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
	171	return -1;
	172	} else {
	173	dev_dbg(&I801_dev->dev, "Successfull!\n");
	174	}
	175	}
	176
	177	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
	178
	179	/* We will always wait for a fraction of a second! */
	180	do {
	181	msleep(1);
	182	temp = inb_p(SMBHSTSTS);
	183	} while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
	184
	185	/* If the SMBus is still busy, we give up */
	186	if (timeout >= MAX_TIMEOUT) {
	187	dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
	188	result = -1;
	189	}
	190
	191	if (temp & 0x10) {
	192	result = -1;
	193	dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
	194	}
	195
	196	if (temp & 0x08) {
	197	result = -1;
	198	dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
	199	"until next hard reset. (sorry!)\n");
	200	/* Clock stops and slave is stuck in mid-transmission */
	201	}
	202
	203	if (temp & 0x04) {
	204	result = -1;
	205	dev_dbg(&I801_dev->dev, "Error: no response!\n");
	206	}
	207
	208	if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
	209	outb_p(inb(SMBHSTSTS), SMBHSTSTS);
	210
	211	if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
368609c5	212	dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
1da177e4 LT	213	"(%02x)\n", temp);
	214	}
	215	dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
	216	"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
	217	inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
	218	inb_p(SMBHSTDAT1));
	219	return result;
	220	}
	221
	222	/* All-inclusive block transaction function */
	223	static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
585b3160	224	int command, int hwpec)
1da177e4 LT	225	{
	226	int i, len;
	227	int smbcmd;
	228	int temp;
	229	int result = 0;
	230	int timeout;
	231	unsigned char hostc, errmask;
	232
	233	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
	234	if (read_write == I2C_SMBUS_WRITE) {
	235	/* set I2C_EN bit in configuration register */
	236	pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
	237	pci_write_config_byte(I801_dev, SMBHSTCFG,
	238	hostc \| SMBHSTCFG_I2C_EN);
	239	} else {
	240	dev_err(&I801_dev->dev,
	241	"I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
	242	return -1;
	243	}
	244	}
	245
	246	if (read_write == I2C_SMBUS_WRITE) {
	247	len = data->block[0];
	248	if (len < 1)
	249	len = 1;
	250	if (len > 32)
	251	len = 32;
	252	outb_p(len, SMBHSTDAT0);
	253	outb_p(data->block[1], SMBBLKDAT);
	254	} else {
	255	len = 32; /* max for reads */
	256	}
	257
	258	if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
	259	/* set 32 byte buffer */
	260	}
	261
	262	for (i = 1; i <= len; i++) {
	263	if (i == len && read_write == I2C_SMBUS_READ)
	264	smbcmd = I801_BLOCK_LAST;
	265	else
	266	smbcmd = I801_BLOCK_DATA;
	267	outb_p(smbcmd \| ENABLE_INT9, SMBHSTCNT);
	268
	269	dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
	270	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
	271	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
	272	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
	273
	274	/* Make sure the SMBus host is ready to start transmitting */
	275	temp = inb_p(SMBHSTSTS);
	276	if (i == 1) {
	277	/* Erronenous conditions before transaction:
	278	* Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
	279	errmask=0x9f;
	280	} else {
	281	/* Erronenous conditions during transaction:
	282	* Failed, Bus_Err, Dev_Err, Intr */
	283	errmask=0x1e;
	284	}
	285	if (temp & errmask) {
	286	dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
541e6a02	287	"Resetting...\n", temp);
1da177e4 LT	288	outb_p(temp, SMBHSTSTS);
	289	if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
	290	dev_err(&I801_dev->dev,
	291	"Reset failed! (%02x)\n", temp);
	292	result = -1;
	293	goto END;
	294	}
	295	if (i != 1) {
	296	/* if die in middle of block transaction, fail */
	297	result = -1;
	298	goto END;
	299	}
	300	}
	301
	302	if (i == 1)
	303	outb_p(inb(SMBHSTCNT) \| I801_START, SMBHSTCNT);
	304
	305	/* We will always wait for a fraction of a second! */
	306	timeout = 0;
	307	do {
1da177e4	308	msleep(1);
397e2f66	309	temp = inb_p(SMBHSTSTS);
1da177e4 LT	310	}
	311	while ((!(temp & 0x80))
	312	&& (timeout++ < MAX_TIMEOUT));
	313
	314	/* If the SMBus is still busy, we give up */
	315	if (timeout >= MAX_TIMEOUT) {
	316	result = -1;
	317	dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
	318	}
	319
	320	if (temp & 0x10) {
	321	result = -1;
	322	dev_dbg(&I801_dev->dev,
	323	"Error: Failed bus transaction\n");
	324	} else if (temp & 0x08) {
	325	result = -1;
	326	dev_err(&I801_dev->dev, "Bus collision!\n");
	327	} else if (temp & 0x04) {
	328	result = -1;
	329	dev_dbg(&I801_dev->dev, "Error: no response!\n");
	330	}
	331
	332	if (i == 1 && read_write == I2C_SMBUS_READ) {
	333	len = inb_p(SMBHSTDAT0);
	334	if (len < 1)
	335	len = 1;
	336	if (len > 32)
	337	len = 32;
	338	data->block[0] = len;
	339	}
	340
	341	/* Retrieve/store value in SMBBLKDAT */
	342	if (read_write == I2C_SMBUS_READ)
	343	data->block[i] = inb_p(SMBBLKDAT);
	344	if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
	345	outb_p(data->block[i+1], SMBBLKDAT);
	346	if ((temp & 0x9e) != 0x00)
	347	outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
	348
	349	if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
	350	dev_dbg(&I801_dev->dev,
	351	"Bad status (%02x) at end of transaction\n",
	352	temp);
	353	}
	354	dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
	355	"ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
	356	inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
	357	inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
	358
	359	if (result < 0)
	360	goto END;
	361	}
	362
e8aac4a9	363	if (hwpec) {
1da177e4 LT	364	/* wait for INTR bit as advised by Intel */
	365	timeout = 0;
	366	do {
1da177e4	367	msleep(1);
397e2f66	368	temp = inb_p(SMBHSTSTS);
1da177e4 LT	369	} while ((!(temp & 0x02))
	370	&& (timeout++ < MAX_TIMEOUT));
	371
	372	if (timeout >= MAX_TIMEOUT) {
	373	dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
	374	}
	375	outb_p(temp, SMBHSTSTS);
	376	}
1da177e4 LT	377	result = 0;
	378	END:
	379	if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
	380	/* restore saved configuration register value */
	381	pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
	382	}
	383	return result;
	384	}
	385
	386	/* Return -1 on error. */
	387	static s32 i801_access(struct i2c_adapter * adap, u16 addr,
	388	unsigned short flags, char read_write, u8 command,
	389	int size, union i2c_smbus_data * data)
	390	{
e8aac4a9	391	int hwpec;
1da177e4 LT	392	int block = 0;
	393	int ret, xact = 0;
	394
e8aac4a9 JD	395	hwpec = isich4 && (flags & I2C_CLIENT_PEC)
	396	&& size != I2C_SMBUS_QUICK
	397	&& size != I2C_SMBUS_I2C_BLOCK_DATA;
1da177e4 LT	398
	399	switch (size) {
	400	case I2C_SMBUS_QUICK:
	401	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	402	SMBHSTADD);
	403	xact = I801_QUICK;
	404	break;
	405	case I2C_SMBUS_BYTE:
	406	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	407	SMBHSTADD);
	408	if (read_write == I2C_SMBUS_WRITE)
	409	outb_p(command, SMBHSTCMD);
	410	xact = I801_BYTE;
	411	break;
	412	case I2C_SMBUS_BYTE_DATA:
	413	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	414	SMBHSTADD);
	415	outb_p(command, SMBHSTCMD);
	416	if (read_write == I2C_SMBUS_WRITE)
	417	outb_p(data->byte, SMBHSTDAT0);
	418	xact = I801_BYTE_DATA;
	419	break;
	420	case I2C_SMBUS_WORD_DATA:
	421	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	422	SMBHSTADD);
	423	outb_p(command, SMBHSTCMD);
	424	if (read_write == I2C_SMBUS_WRITE) {
	425	outb_p(data->word & 0xff, SMBHSTDAT0);
	426	outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
	427	}
	428	xact = I801_WORD_DATA;
	429	break;
	430	case I2C_SMBUS_BLOCK_DATA:
	431	case I2C_SMBUS_I2C_BLOCK_DATA:
1da177e4 LT	432	outb_p(((addr & 0x7f) << 1) \| (read_write & 0x01),
	433	SMBHSTADD);
	434	outb_p(command, SMBHSTCMD);
	435	block = 1;
	436	break;
	437	case I2C_SMBUS_PROC_CALL:
	438	default:
	439	dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
	440	return -1;
	441	}
	442
2e3e13f8	443	outb_p(hwpec, SMBAUXCTL); /* enable/disable hardware PEC */
e8aac4a9	444
1da177e4	445	if(block)
585b3160	446	ret = i801_block_transaction(data, read_write, size, hwpec);
1da177e4 LT	447	else {
	448	outb_p(xact \| ENABLE_INT9, SMBHSTCNT);
	449	ret = i801_transaction();
	450	}
	451
c79cfbac JD	452	/* Some BIOSes don't like it when PEC is enabled at reboot or resume
	453	time, so we forcibly disable it after every transaction. */
	454	if (hwpec)
	455	outb_p(0, SMBAUXCTL);
	456
1da177e4 LT	457	if(block)
	458	return ret;
	459	if(ret)
	460	return -1;
	461	if ((read_write == I2C_SMBUS_WRITE) \|\| (xact == I801_QUICK))
	462	return 0;
	463
	464	switch (xact & 0x7f) {
	465	case I801_BYTE: /* Result put in SMBHSTDAT0 */
	466	case I801_BYTE_DATA:
	467	data->byte = inb_p(SMBHSTDAT0);
	468	break;
	469	case I801_WORD_DATA:
	470	data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
	471	break;
	472	}
	473	return 0;
	474	}
	475
	476
	477	static u32 i801_func(struct i2c_adapter *adapter)
	478	{
	479	return I2C_FUNC_SMBUS_QUICK \| I2C_FUNC_SMBUS_BYTE \|
	480	I2C_FUNC_SMBUS_BYTE_DATA \| I2C_FUNC_SMBUS_WORD_DATA \|
	481	I2C_FUNC_SMBUS_BLOCK_DATA \| I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
b8095544	482	\| (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0);
1da177e4 LT	483	}
	484
	485	static struct i2c_algorithm smbus_algorithm = {
1da177e4 LT	486	.smbus_xfer = i801_access,
	487	.functionality = i801_func,
	488	};
	489
	490	static struct i2c_adapter i801_adapter = {
	491	.owner = THIS_MODULE,
	492	.class = I2C_CLASS_HWMON,
	493	.algo = &smbus_algorithm,
1da177e4 LT	494	};
	495
	496	static struct pci_device_id i801_ids[] = {
	497	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
	498	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
	499	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
	500	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
	501	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
	502	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
	503	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
	504	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
	505	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
b0a70b57	506	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
8254fc4a	507	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1da177e4 LT	508	{ 0, }
	509	};
	510
	511	MODULE_DEVICE_TABLE (pci, i801_ids);
	512
	513	static int __devinit i801_probe(struct pci_dev dev, const struct pci_device_id id)
	514	{
455f3323	515	int err;
1da177e4	516
455f3323 JD	517	if ((err = i801_setup(dev)))
455f3323 JD	518	return err;
1da177e4 LT	519
	520	/* set up the driverfs linkage to our parent device */
	521	i801_adapter.dev.parent = &dev->dev;
	522
	523	snprintf(i801_adapter.name, I2C_NAME_SIZE,
	524	"SMBus I801 adapter at %04x", i801_smba);
	525	return i2c_add_adapter(&i801_adapter);
	526	}
	527
	528	static void __devexit i801_remove(struct pci_dev *dev)
	529	{
	530	i2c_del_adapter(&i801_adapter);
	531	release_region(i801_smba, (isich4 ? 16 : 8));
	532	}
	533
	534	static struct pci_driver i801_driver = {
	535	.name = "i801_smbus",
	536	.id_table = i801_ids,
	537	.probe = i801_probe,
	538	.remove = __devexit_p(i801_remove),
	539	};
	540
	541	static int __init i2c_i801_init(void)
	542	{
	543	return pci_register_driver(&i801_driver);
	544	}
	545
	546	static void __exit i2c_i801_exit(void)
	547	{
	548	pci_unregister_driver(&i801_driver);
	549	}
	550
	551	MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
	552	"Philip Edelbrock <phil@netroedge.com>, "
	553	"and Mark D. Studebaker <mdsxyz123@yahoo.com>");
	554	MODULE_DESCRIPTION("I801 SMBus driver");
	555	MODULE_LICENSE("GPL");
	556
	557	module_init(i2c_i801_init);
	558	module_exit(i2c_i801_exit);