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i2c: Make i2c_register_board_info() a NOP when CONFIG_I2C_BOARDINFO=n
[net-next-2.6.git] / drivers / i2c / busses / i2c-i801.c
CommitLineData
1da177e4 1/*
455f3323 2 i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
1da177e4
LT		 3 monitoring
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
6 <mdsxyz123@yahoo.com>
6342064c 7 Copyright (C) 2007 Jean Delvare <khali@linux-fr.org>
1da177e4
LT		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22*/
23
24/*
ae7b0497
JD		 25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 Tolapai 0x5032 32 hard yes ? ?
44
45 Features supported by this driver:
46 Software PEC no
47 Hardware PEC yes
48 Block buffer yes
49 Block process call transaction no
6342064c 50 I2C block read transaction yes (doesn't use the block buffer)
ae7b0497
JD		 51
52 See the file Documentation/i2c/busses/i2c-i801 for details.
1da177e4
LT		 53*/
54
55/* Note: we assume there can only be one I801, with one SMBus interface */
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/pci.h>
59#include <linux/kernel.h>
60#include <linux/stddef.h>
61#include <linux/delay.h>
1da177e4
LT		 62#include <linux/ioport.h>
63#include <linux/init.h>
64#include <linux/i2c.h>
65#include <asm/io.h>
66
1da177e4
LT		 67/* I801 SMBus address offsets */
68#define SMBHSTSTS (0 + i801_smba)
69#define SMBHSTCNT (2 + i801_smba)
70#define SMBHSTCMD (3 + i801_smba)
71#define SMBHSTADD (4 + i801_smba)
72#define SMBHSTDAT0 (5 + i801_smba)
73#define SMBHSTDAT1 (6 + i801_smba)
74#define SMBBLKDAT (7 + i801_smba)
ae7b0497
JD		 75#define SMBPEC (8 + i801_smba) /* ICH3 and later */
76#define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
77#define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
1da177e4
LT		 78
79/* PCI Address Constants */
6dcc19df 80#define SMBBAR 4
1da177e4 81#define SMBHSTCFG 0x040
1da177e4
LT		 82
83/* Host configuration bits for SMBHSTCFG */
84#define SMBHSTCFG_HST_EN 1
85#define SMBHSTCFG_SMB_SMI_EN 2
86#define SMBHSTCFG_I2C_EN 4
87
ca8b9e32
OR		 88/* Auxillary control register bits, ICH4+ only */
89#define SMBAUXCTL_CRC 1
90#define SMBAUXCTL_E32B 2
91
92/* kill bit for SMBHSTCNT */
93#define SMBHSTCNT_KILL 2
94
1da177e4
LT		 95/* Other settings */
96#define MAX_TIMEOUT 100
97#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
98
99/* I801 command constants */
100#define I801_QUICK 0x00
101#define I801_BYTE 0x04
102#define I801_BYTE_DATA 0x08
103#define I801_WORD_DATA 0x0C
ae7b0497 104#define I801_PROC_CALL 0x10 /* unimplemented */
1da177e4 105#define I801_BLOCK_DATA 0x14
6342064c 106#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
1da177e4 107#define I801_BLOCK_LAST 0x34
6342064c 108#define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
1da177e4 109#define I801_START 0x40
ae7b0497 110#define I801_PEC_EN 0x80 /* ICH3 and later */
1da177e4 111
ca8b9e32
OR		 112/* I801 Hosts Status register bits */
113#define SMBHSTSTS_BYTE_DONE 0x80
114#define SMBHSTSTS_INUSE_STS 0x40
115#define SMBHSTSTS_SMBALERT_STS 0x20
116#define SMBHSTSTS_FAILED 0x10
117#define SMBHSTSTS_BUS_ERR 0x08
118#define SMBHSTSTS_DEV_ERR 0x04
119#define SMBHSTSTS_INTR 0x02
120#define SMBHSTSTS_HOST_BUSY 0x01
1da177e4 121
6dcc19df 122static unsigned long i801_smba;
a5aaea37 123static unsigned char i801_original_hstcfg;
d6072f84 124static struct pci_driver i801_driver;
1da177e4 125static struct pci_dev *I801_dev;
369f6f4a
JD		 126
127#define FEATURE_SMBUS_PEC (1 << 0)
128#define FEATURE_BLOCK_BUFFER (1 << 1)
129#define FEATURE_BLOCK_PROC (1 << 2)
130#define FEATURE_I2C_BLOCK_READ (1 << 3)
131static unsigned int i801_features;
1da177e4 132
7edcb9ab 133static int i801_transaction(int xact)
1da177e4
LT		 134{
135 int temp;
136 int result = 0;
137 int timeout = 0;
138
368609c5 139 dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
1da177e4
LT		 140 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
141 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
142 inb_p(SMBHSTDAT1));
143
144 /* Make sure the SMBus host is ready to start transmitting */
145 /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
146 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
541e6a02 147 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
1da177e4
LT		 148 temp);
149 outb_p(temp, SMBHSTSTS);
150 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
151 dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
152 return -1;
153 } else {
fcdd96ec 154 dev_dbg(&I801_dev->dev, "Successful!\n");
1da177e4
LT		 155 }
156 }
157
7edcb9ab
OR		 158 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
159 * INTREN, SMBSCMD are passed in xact */
160 outb_p(xact | I801_START, SMBHSTCNT);
1da177e4
LT		 161
162 /* We will always wait for a fraction of a second! */
163 do {
164 msleep(1);
165 temp = inb_p(SMBHSTSTS);
ca8b9e32 166 } while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
1da177e4
LT		 167
168 /* If the SMBus is still busy, we give up */
169 if (timeout >= MAX_TIMEOUT) {
170 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
171 result = -1;
ca8b9e32
OR		 172 /* try to stop the current command */
173 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
174 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
175 msleep(1);
176 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
1da177e4
LT		 177 }
178
ca8b9e32 179 if (temp & SMBHSTSTS_FAILED) {
1da177e4
LT		 180 result = -1;
181 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
182 }
183
ca8b9e32 184 if (temp & SMBHSTSTS_BUS_ERR) {
1da177e4
LT		 185 result = -1;
186 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
187 "until next hard reset. (sorry!)\n");
188 /* Clock stops and slave is stuck in mid-transmission */
189 }
190
ca8b9e32 191 if (temp & SMBHSTSTS_DEV_ERR) {
1da177e4
LT		 192 result = -1;
193 dev_dbg(&I801_dev->dev, "Error: no response!\n");
194 }
195
196 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
197 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
198
199 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
368609c5 200 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
1da177e4
LT		 201 "(%02x)\n", temp);
202 }
203 dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
204 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
205 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
206 inb_p(SMBHSTDAT1));
207 return result;
208}
209
ca8b9e32
OR		 210/* wait for INTR bit as advised by Intel */
211static void i801_wait_hwpec(void)
212{
213 int timeout = 0;
214 int temp;
215
216 do {
217 msleep(1);
218 temp = inb_p(SMBHSTSTS);
219 } while ((!(temp & SMBHSTSTS_INTR))
220 && (timeout++ < MAX_TIMEOUT));
221
222 if (timeout >= MAX_TIMEOUT) {
223 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
224 }
225 outb_p(temp, SMBHSTSTS);
226}
227
7edcb9ab
OR		 228static int i801_block_transaction_by_block(union i2c_smbus_data *data,
229 char read_write, int hwpec)
230{
231 int i, len;
232
233 inb_p(SMBHSTCNT); /* reset the data buffer index */
234
235 /* Use 32-byte buffer to process this transaction */
236 if (read_write == I2C_SMBUS_WRITE) {
237 len = data->block[0];
238 outb_p(len, SMBHSTDAT0);
239 for (i = 0; i < len; i++)
240 outb_p(data->block[i+1], SMBBLKDAT);
241 }
242
243 if (i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
244 I801_PEC_EN * hwpec))
245 return -1;
246
247 if (read_write == I2C_SMBUS_READ) {
248 len = inb_p(SMBHSTDAT0);
249 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
250 return -1;
251
252 data->block[0] = len;
253 for (i = 0; i < len; i++)
254 data->block[i + 1] = inb_p(SMBBLKDAT);
255 }
256 return 0;
257}
258
259static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
6342064c
JD		 260 char read_write, int command,
261 int hwpec)
1da177e4
LT		 262{
263 int i, len;
264 int smbcmd;
265 int temp;
266 int result = 0;
267 int timeout;
7edcb9ab 268 unsigned char errmask;
1da177e4 269
7edcb9ab 270 len = data->block[0];
1da177e4
LT		 271
272 if (read_write == I2C_SMBUS_WRITE) {
1da177e4
LT		 273 outb_p(len, SMBHSTDAT0);
274 outb_p(data->block[1], SMBBLKDAT);
1da177e4
LT		 275 }
276
277 for (i = 1; i <= len; i++) {
6342064c
JD		 278 if (i == len && read_write == I2C_SMBUS_READ) {
279 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
280 smbcmd = I801_I2C_BLOCK_LAST;
281 else
282 smbcmd = I801_BLOCK_LAST;
283 } else {
284 if (command == I2C_SMBUS_I2C_BLOCK_DATA
285 && read_write == I2C_SMBUS_READ)
286 smbcmd = I801_I2C_BLOCK_DATA;
287 else
288 smbcmd = I801_BLOCK_DATA;
289 }
1da177e4
LT		 290 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
291
292 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
6342064c 293 "ADD=%02x, DAT0=%02x, DAT1=%02x, BLKDAT=%02x\n", i,
1da177e4 294 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
6342064c 295 inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1), inb_p(SMBBLKDAT));
1da177e4
LT		 296
297 /* Make sure the SMBus host is ready to start transmitting */
298 temp = inb_p(SMBHSTSTS);
299 if (i == 1) {
002cf631 300 /* Erroneous conditions before transaction:
1da177e4 301 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
ca8b9e32 302 errmask = 0x9f;
1da177e4 303 } else {
002cf631 304 /* Erroneous conditions during transaction:
1da177e4 305 * Failed, Bus_Err, Dev_Err, Intr */
ca8b9e32 306 errmask = 0x1e;
1da177e4
LT		 307 }
308 if (temp & errmask) {
309 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
541e6a02 310 "Resetting...\n", temp);
1da177e4
LT		 311 outb_p(temp, SMBHSTSTS);
312 if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
313 dev_err(&I801_dev->dev,
314 "Reset failed! (%02x)\n", temp);
7edcb9ab 315 return -1;
1da177e4 316 }
7edcb9ab 317 if (i != 1)
1da177e4 318 /* if die in middle of block transaction, fail */
7edcb9ab 319 return -1;
1da177e4
LT		 320 }
321
322 if (i == 1)
323 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
324
325 /* We will always wait for a fraction of a second! */
326 timeout = 0;
327 do {
1da177e4 328 msleep(1);
397e2f66 329 temp = inb_p(SMBHSTSTS);
1da177e4 330 }
ca8b9e32
OR		 331 while ((!(temp & SMBHSTSTS_BYTE_DONE))
332 && (timeout++ < MAX_TIMEOUT));
1da177e4
LT		 333
334 /* If the SMBus is still busy, we give up */
335 if (timeout >= MAX_TIMEOUT) {
ca8b9e32
OR		 336 /* try to stop the current command */
337 dev_dbg(&I801_dev->dev, "Terminating the current "
338 "operation\n");
339 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
340 msleep(1);
341 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL),
342 SMBHSTCNT);
1da177e4
LT		 343 result = -1;
344 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
345 }
346
ca8b9e32 347 if (temp & SMBHSTSTS_FAILED) {
1da177e4
LT		 348 result = -1;
349 dev_dbg(&I801_dev->dev,
350 "Error: Failed bus transaction\n");
ca8b9e32 351 } else if (temp & SMBHSTSTS_BUS_ERR) {
1da177e4
LT		 352 result = -1;
353 dev_err(&I801_dev->dev, "Bus collision!\n");
ca8b9e32 354 } else if (temp & SMBHSTSTS_DEV_ERR) {
1da177e4
LT		 355 result = -1;
356 dev_dbg(&I801_dev->dev, "Error: no response!\n");
357 }
358
6342064c
JD		 359 if (i == 1 && read_write == I2C_SMBUS_READ
360 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
1da177e4 361 len = inb_p(SMBHSTDAT0);
7edcb9ab
OR		 362 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
363 return -1;
1da177e4
LT		 364 data->block[0] = len;
365 }
366
367 /* Retrieve/store value in SMBBLKDAT */
368 if (read_write == I2C_SMBUS_READ)
369 data->block[i] = inb_p(SMBBLKDAT);
370 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
371 outb_p(data->block[i+1], SMBBLKDAT);
372 if ((temp & 0x9e) != 0x00)
373 outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
374
375 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
376 dev_dbg(&I801_dev->dev,
377 "Bad status (%02x) at end of transaction\n",
378 temp);
379 }
380 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
6342064c 381 "ADD=%02x, DAT0=%02x, DAT1=%02x, BLKDAT=%02x\n", i,
1da177e4 382 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
6342064c 383 inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1), inb_p(SMBBLKDAT));
1da177e4
LT		 384
385 if (result < 0)
7edcb9ab 386 return result;
1da177e4 387 }
7edcb9ab
OR		 388 return result;
389}
1da177e4 390
7edcb9ab
OR		 391static int i801_set_block_buffer_mode(void)
392{
393 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
394 if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
395 return -1;
396 return 0;
397}
398
399/* Block transaction function */
400static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
401 int command, int hwpec)
402{
403 int result = 0;
404 unsigned char hostc;
405
406 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
407 if (read_write == I2C_SMBUS_WRITE) {
408 /* set I2C_EN bit in configuration register */
409 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
410 pci_write_config_byte(I801_dev, SMBHSTCFG,
411 hostc | SMBHSTCFG_I2C_EN);
6342064c 412 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
7edcb9ab 413 dev_err(&I801_dev->dev,
6342064c 414 "I2C block read is unsupported!\n");
7edcb9ab
OR		 415 return -1;
416 }
417 }
418
6342064c
JD		 419 if (read_write == I2C_SMBUS_WRITE
420 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
7edcb9ab
OR		 421 if (data->block[0] < 1)
422 data->block[0] = 1;
423 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
424 data->block[0] = I2C_SMBUS_BLOCK_MAX;
425 } else {
6342064c 426 data->block[0] = 32; /* max for SMBus block reads */
7edcb9ab
OR		 427 }
428
369f6f4a 429 if ((i801_features & FEATURE_BLOCK_BUFFER)
6342064c
JD		 430 && !(command == I2C_SMBUS_I2C_BLOCK_DATA
431 && read_write == I2C_SMBUS_READ)
369f6f4a 432 && i801_set_block_buffer_mode() == 0)
7edcb9ab
OR		 433 result = i801_block_transaction_by_block(data, read_write,
434 hwpec);
435 else
436 result = i801_block_transaction_byte_by_byte(data, read_write,
6342064c 437 command, hwpec);
7edcb9ab
OR		 438
439 if (result == 0 && hwpec)
ca8b9e32 440 i801_wait_hwpec();
1da177e4 441
6342064c
JD		 442 if (command == I2C_SMBUS_I2C_BLOCK_DATA
443 && read_write == I2C_SMBUS_WRITE) {
1da177e4
LT		 444 /* restore saved configuration register value */
445 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
446 }
447 return result;
448}
449
450/* Return -1 on error. */
451static s32 i801_access(struct i2c_adapter * adap, u16 addr,
452 unsigned short flags, char read_write, u8 command,
453 int size, union i2c_smbus_data * data)
454{
e8aac4a9 455 int hwpec;
1da177e4
LT		 456 int block = 0;
457 int ret, xact = 0;
458
369f6f4a 459 hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
e8aac4a9
JD		 460 && size != I2C_SMBUS_QUICK
461 && size != I2C_SMBUS_I2C_BLOCK_DATA;
1da177e4
LT		 462
463 switch (size) {
464 case I2C_SMBUS_QUICK:
465 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
466 SMBHSTADD);
467 xact = I801_QUICK;
468 break;
469 case I2C_SMBUS_BYTE:
470 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
471 SMBHSTADD);
472 if (read_write == I2C_SMBUS_WRITE)
473 outb_p(command, SMBHSTCMD);
474 xact = I801_BYTE;
475 break;
476 case I2C_SMBUS_BYTE_DATA:
477 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
478 SMBHSTADD);
479 outb_p(command, SMBHSTCMD);
480 if (read_write == I2C_SMBUS_WRITE)
481 outb_p(data->byte, SMBHSTDAT0);
482 xact = I801_BYTE_DATA;
483 break;
484 case I2C_SMBUS_WORD_DATA:
485 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
486 SMBHSTADD);
487 outb_p(command, SMBHSTCMD);
488 if (read_write == I2C_SMBUS_WRITE) {
489 outb_p(data->word & 0xff, SMBHSTDAT0);
490 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
491 }
492 xact = I801_WORD_DATA;
493 break;
494 case I2C_SMBUS_BLOCK_DATA:
1da177e4
LT		 495 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
496 SMBHSTADD);
497 outb_p(command, SMBHSTCMD);
498 block = 1;
499 break;
6342064c
JD		 500 case I2C_SMBUS_I2C_BLOCK_DATA:
501 /* NB: page 240 of ICH5 datasheet shows that the R/#W
502 * bit should be cleared here, even when reading */
503 outb_p((addr & 0x7f) << 1, SMBHSTADD);
504 if (read_write == I2C_SMBUS_READ) {
505 /* NB: page 240 of ICH5 datasheet also shows
506 * that DATA1 is the cmd field when reading */
507 outb_p(command, SMBHSTDAT1);
508 } else
509 outb_p(command, SMBHSTCMD);
510 block = 1;
511 break;
1da177e4
LT		 512 case I2C_SMBUS_PROC_CALL:
513 default:
514 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
515 return -1;
516 }
517
ca8b9e32
OR		 518 if (hwpec) /* enable/disable hardware PEC */
519 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
520 else
521 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
e8aac4a9 522
1da177e4 523 if(block)
585b3160 524 ret = i801_block_transaction(data, read_write, size, hwpec);
7edcb9ab
OR		 525 else
526 ret = i801_transaction(xact | ENABLE_INT9);
1da177e4 527
c79cfbac 528 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
7edcb9ab
OR		 529 time, so we forcibly disable it after every transaction. Turn off
530 E32B for the same reason. */
a0921b6c 531 if (hwpec || block)
7edcb9ab
OR		 532 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
533 SMBAUXCTL);
c79cfbac 534
1da177e4
LT		 535 if(block)
536 return ret;
537 if(ret)
538 return -1;
539 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
540 return 0;
541
542 switch (xact & 0x7f) {
543 case I801_BYTE: /* Result put in SMBHSTDAT0 */
544 case I801_BYTE_DATA:
545 data->byte = inb_p(SMBHSTDAT0);
546 break;
547 case I801_WORD_DATA:
548 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
549 break;
550 }
551 return 0;
552}
553
554
555static u32 i801_func(struct i2c_adapter *adapter)
556{
557 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
369f6f4a
JD		 558 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
559 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
6342064c
JD		 560 ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
561 ((i801_features & FEATURE_I2C_BLOCK_READ) ?
562 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
1da177e4
LT		 563}
564
8f9082c5 565static const struct i2c_algorithm smbus_algorithm = {
1da177e4
LT		 566 .smbus_xfer = i801_access,
567 .functionality = i801_func,
568};
569
570static struct i2c_adapter i801_adapter = {
571 .owner = THIS_MODULE,
9ace555d 572 .id = I2C_HW_SMBUS_I801,
1da177e4
LT		 573 .class = I2C_CLASS_HWMON,
574 .algo = &smbus_algorithm,
1da177e4
LT		 575};
576
577static struct pci_device_id i801_ids[] = {
578 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
579 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
580 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
581 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
582 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
583 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
584 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
585 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
586 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
b0a70b57 587 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
8254fc4a 588 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
adbc2a10 589 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
e07bc679 590 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
1da177e4
LT		 591 { 0, }
592};
593
594MODULE_DEVICE_TABLE (pci, i801_ids);
595
596static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
597{
02dd7ae2 598 unsigned char temp;
455f3323 599 int err;
1da177e4 600
02dd7ae2 601 I801_dev = dev;
369f6f4a 602 i801_features = 0;
250d1bd3 603 switch (dev->device) {
250d1bd3
JD		 604 case PCI_DEVICE_ID_INTEL_82801EB_3:
605 case PCI_DEVICE_ID_INTEL_ESB_4:
606 case PCI_DEVICE_ID_INTEL_ICH6_16:
607 case PCI_DEVICE_ID_INTEL_ICH7_17:
608 case PCI_DEVICE_ID_INTEL_ESB2_17:
609 case PCI_DEVICE_ID_INTEL_ICH8_5:
610 case PCI_DEVICE_ID_INTEL_ICH9_6:
6342064c
JD		 611 i801_features |= FEATURE_I2C_BLOCK_READ;
612 /* fall through */
613 case PCI_DEVICE_ID_INTEL_82801DB_3:
e07bc679 614 case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
369f6f4a
JD		 615 i801_features |= FEATURE_SMBUS_PEC;
616 i801_features |= FEATURE_BLOCK_BUFFER;
250d1bd3 617 break;
250d1bd3 618 }
02dd7ae2
JD		 619
620 err = pci_enable_device(dev);
621 if (err) {
622 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
623 err);
624 goto exit;
625 }
626
627 /* Determine the address of the SMBus area */
628 i801_smba = pci_resource_start(dev, SMBBAR);
629 if (!i801_smba) {
630 dev_err(&dev->dev, "SMBus base address uninitialized, "
631 "upgrade BIOS\n");
632 err = -ENODEV;
d6fcb3b9 633 goto exit;
02dd7ae2
JD		 634 }
635
636 err = pci_request_region(dev, SMBBAR, i801_driver.name);
637 if (err) {
638 dev_err(&dev->dev, "Failed to request SMBus region "
598736c5
AM		 639 "0x%lx-0x%Lx\n", i801_smba,
640 (unsigned long long)pci_resource_end(dev, SMBBAR));
d6fcb3b9 641 goto exit;
02dd7ae2
JD		 642 }
643
644 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
a5aaea37 645 i801_original_hstcfg = temp;
02dd7ae2
JD		 646 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
647 if (!(temp & SMBHSTCFG_HST_EN)) {
648 dev_info(&dev->dev, "Enabling SMBus device\n");
649 temp |= SMBHSTCFG_HST_EN;
650 }
651 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
652
653 if (temp & SMBHSTCFG_SMB_SMI_EN)
654 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
655 else
656 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
1da177e4 657
a0921b6c
JD		 658 /* Clear special mode bits */
659 if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
660 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
661 SMBAUXCTL);
662
405ae7d3 663 /* set up the sysfs linkage to our parent device */
1da177e4
LT		 664 i801_adapter.dev.parent = &dev->dev;
665
2096b956 666 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
6dcc19df 667 "SMBus I801 adapter at %04lx", i801_smba);
02dd7ae2
JD		 668 err = i2c_add_adapter(&i801_adapter);
669 if (err) {
670 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
d6fcb3b9 671 goto exit_release;
02dd7ae2 672 }
d6fcb3b9 673 return 0;
02dd7ae2 674
d6fcb3b9
DR		 675exit_release:
676 pci_release_region(dev, SMBBAR);
02dd7ae2
JD		 677exit:
678 return err;
1da177e4
LT		 679}
680
681static void __devexit i801_remove(struct pci_dev *dev)
682{
683 i2c_del_adapter(&i801_adapter);
a5aaea37 684 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
6dcc19df 685 pci_release_region(dev, SMBBAR);
d6fcb3b9
DR		 686 /*
687 * do not call pci_disable_device(dev) since it can cause hard hangs on
688 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
689 */
1da177e4
LT		 690}
691
a5aaea37
JD		 692#ifdef CONFIG_PM
693static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
694{
695 pci_save_state(dev);
696 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
697 pci_set_power_state(dev, pci_choose_state(dev, mesg));
698 return 0;
699}
700
701static int i801_resume(struct pci_dev *dev)
702{
703 pci_set_power_state(dev, PCI_D0);
704 pci_restore_state(dev);
705 return pci_enable_device(dev);
706}
707#else
708#define i801_suspend NULL
709#define i801_resume NULL
710#endif
711
1da177e4
LT		 712static struct pci_driver i801_driver = {
713 .name = "i801_smbus",
714 .id_table = i801_ids,
715 .probe = i801_probe,
716 .remove = __devexit_p(i801_remove),
a5aaea37
JD		 717 .suspend = i801_suspend,
718 .resume = i801_resume,
1da177e4
LT		 719};
720
721static int __init i2c_i801_init(void)
722{
723 return pci_register_driver(&i801_driver);
724}
725
726static void __exit i2c_i801_exit(void)
727{
728 pci_unregister_driver(&i801_driver);
729}
730
6342064c
JD		 731MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
732 "Jean Delvare <khali@linux-fr.org>");
1da177e4
LT		 733MODULE_DESCRIPTION("I801 SMBus driver");
734MODULE_LICENSE("GPL");
735
736module_init(i2c_i801_init);
737module_exit(i2c_i801_exit);
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