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hwmon/w83627ehf: Enable VBAT monitoring
[net-next-2.6.git] / drivers / hwmon / w83627ehf.c
CommitLineData
08e7e278
JD		 1/*
2 w83627ehf - Driver for the hardware monitoring functionality of
3 the Winbond W83627EHF Super-I/O chip
4 Copyright (C) 2005 Jean Delvare <khali@linux-fr.org>
3379ceee 5 Copyright (C) 2006 Yuan Mu (Winbond),
7188cc66 6 Rudolf Marek <r.marek@assembler.cz>
c18beb5b 7 David Hubbard <david.c.hubbard@gmail.com>
08e7e278
JD		 8
9 Shamelessly ripped from the w83627hf driver
10 Copyright (C) 2003 Mark Studebaker
11
12 Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
13 in testing and debugging this driver.
14
8dd2d2ca
JD		 15 This driver also supports the W83627EHG, which is the lead-free
16 version of the W83627EHF.
17
08e7e278
JD		 18 This program is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
22
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
27
28 You should have received a copy of the GNU General Public License
29 along with this program; if not, write to the Free Software
30 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31
32
33 Supports the following chips:
34
657c93b1
DH		 35 Chip #vin #fan #pwm #temp chip IDs man ID
36 w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
37 0x8860 0xa1
38 w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
08e7e278
JD		 39*/
40
41#include <linux/module.h>
42#include <linux/init.h>
43#include <linux/slab.h>
1ea6dd38
DH		 44#include <linux/jiffies.h>
45#include <linux/platform_device.h>
943b0830 46#include <linux/hwmon.h>
412fec82 47#include <linux/hwmon-sysfs.h>
fc18d6c0 48#include <linux/hwmon-vid.h>
943b0830 49#include <linux/err.h>
9a61bf63 50#include <linux/mutex.h>
08e7e278
JD		 51#include <asm/io.h>
52#include "lm75.h"
53
1ea6dd38 54enum kinds { w83627ehf, w83627dhg };
08e7e278 55
1ea6dd38
DH		 56/* used to set data->name = w83627ehf_device_names[data->sio_kind] */
57static const char * w83627ehf_device_names[] = {
58 "w83627ehf",
59 "w83627dhg",
60};
61
62#define DRVNAME "w83627ehf"
08e7e278 63
657c93b1 64/*
1ea6dd38 65 * Super-I/O constants and functions
657c93b1 66 */
08e7e278
JD		 67
68#define W83627EHF_LD_HWM 0x0b
69
70#define SIO_REG_LDSEL 0x07 /* Logical device select */
71#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
fc18d6c0 72#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
08e7e278
JD		 73#define SIO_REG_ENABLE 0x30 /* Logical device enable */
74#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
fc18d6c0
JD		 75#define SIO_REG_VID_CTRL 0xF0 /* VID control */
76#define SIO_REG_VID_DATA 0xF1 /* VID data */
08e7e278 77
657c93b1
DH		 78#define SIO_W83627EHF_ID 0x8850
79#define SIO_W83627EHG_ID 0x8860
80#define SIO_W83627DHG_ID 0xa020
81#define SIO_ID_MASK 0xFFF0
08e7e278
JD		 82
83static inline void
1ea6dd38 84superio_outb(int ioreg, int reg, int val)
08e7e278 85{
1ea6dd38
DH		 86 outb(reg, ioreg);
87 outb(val, ioreg + 1);
08e7e278
JD		 88}
89
90static inline int
1ea6dd38 91superio_inb(int ioreg, int reg)
08e7e278 92{
1ea6dd38
DH		 93 outb(reg, ioreg);
94 return inb(ioreg + 1);
08e7e278
JD		 95}
96
97static inline void
1ea6dd38 98superio_select(int ioreg, int ld)
08e7e278 99{
1ea6dd38
DH		 100 outb(SIO_REG_LDSEL, ioreg);
101 outb(ld, ioreg + 1);
08e7e278
JD		 102}
103
104static inline void
1ea6dd38 105superio_enter(int ioreg)
08e7e278 106{
1ea6dd38
DH		 107 outb(0x87, ioreg);
108 outb(0x87, ioreg);
08e7e278
JD		 109}
110
111static inline void
1ea6dd38 112superio_exit(int ioreg)
08e7e278 113{
1ea6dd38
DH		 114 outb(0x02, ioreg);
115 outb(0x02, ioreg + 1);
08e7e278
JD		 116}
117
118/*
119 * ISA constants
120 */
121
1a641fce
JD		 122#define IOREGION_ALIGNMENT ~7
123#define IOREGION_OFFSET 5
124#define IOREGION_LENGTH 2
1ea6dd38
DH		 125#define ADDR_REG_OFFSET 0
126#define DATA_REG_OFFSET 1
08e7e278
JD		 127
128#define W83627EHF_REG_BANK 0x4E
129#define W83627EHF_REG_CONFIG 0x40
657c93b1
DH		 130
131/* Not currently used:
132 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
133 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
134 * REG_MAN_ID is at port 0x4f
135 * REG_CHIP_ID is at port 0x58 */
08e7e278
JD		 136
137static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
138static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
139
cf0676fe
RM		 140/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
141#define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
142 (0x554 + (((nr) - 7) * 2)))
143#define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
144 (0x555 + (((nr) - 7) * 2)))
145#define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
146 (0x550 + (nr) - 7))
147
08e7e278
JD		 148#define W83627EHF_REG_TEMP1 0x27
149#define W83627EHF_REG_TEMP1_HYST 0x3a
150#define W83627EHF_REG_TEMP1_OVER 0x39
151static const u16 W83627EHF_REG_TEMP[] = { 0x150, 0x250 };
152static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x153, 0x253 };
153static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x155, 0x255 };
154static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0x152, 0x252 };
155
156/* Fan clock dividers are spread over the following five registers */
157#define W83627EHF_REG_FANDIV1 0x47
158#define W83627EHF_REG_FANDIV2 0x4B
159#define W83627EHF_REG_VBAT 0x5D
160#define W83627EHF_REG_DIODE 0x59
161#define W83627EHF_REG_SMI_OVT 0x4C
162
a4589dbb
JD		 163#define W83627EHF_REG_ALARM1 0x459
164#define W83627EHF_REG_ALARM2 0x45A
165#define W83627EHF_REG_ALARM3 0x45B
166
08c79950
RM		 167/* SmartFan registers */
168/* DC or PWM output fan configuration */
169static const u8 W83627EHF_REG_PWM_ENABLE[] = {
170 0x04, /* SYS FAN0 output mode and PWM mode */
171 0x04, /* CPU FAN0 output mode and PWM mode */
172 0x12, /* AUX FAN mode */
173 0x62, /* CPU fan1 mode */
174};
175
176static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
177static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
178
179/* FAN Duty Cycle, be used to control */
180static const u8 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
181static const u8 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
182static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
183
184
185/* Advanced Fan control, some values are common for all fans */
186static const u8 W83627EHF_REG_FAN_MIN_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
187static const u8 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0C, 0x0D, 0x17, 0x66 };
188
08e7e278
JD		 189/*
190 * Conversions
191 */
192
08c79950
RM		 193/* 1 is PWM mode, output in ms */
194static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
195{
196 return mode ? 100 * reg : 400 * reg;
197}
198
199static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
200{
201 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
202 (msec + 200) / 400), 1, 255);
203}
204
08e7e278
JD		 205static inline unsigned int
206fan_from_reg(u8 reg, unsigned int div)
207{
208 if (reg == 0 || reg == 255)
209 return 0;
210 return 1350000U / (reg * div);
211}
212
213static inline unsigned int
214div_from_reg(u8 reg)
215{
216 return 1 << reg;
217}
218
219static inline int
220temp1_from_reg(s8 reg)
221{
222 return reg * 1000;
223}
224
225static inline s8
08c79950 226temp1_to_reg(int temp, int min, int max)
08e7e278 227{
08c79950
RM		 228 if (temp <= min)
229 return min / 1000;
230 if (temp >= max)
231 return max / 1000;
08e7e278
JD		 232 if (temp < 0)
233 return (temp - 500) / 1000;
234 return (temp + 500) / 1000;
235}
236
cf0676fe
RM		 237/* Some of analog inputs have internal scaling (2x), 8mV is ADC LSB */
238
239static u8 scale_in[10] = { 8, 8, 16, 16, 8, 8, 8, 16, 16, 8 };
240
241static inline long in_from_reg(u8 reg, u8 nr)
242{
243 return reg * scale_in[nr];
244}
245
246static inline u8 in_to_reg(u32 val, u8 nr)
247{
248 return SENSORS_LIMIT(((val + (scale_in[nr] / 2)) / scale_in[nr]), 0, 255);
249}
250
08e7e278
JD		 251/*
252 * Data structures and manipulation thereof
253 */
254
255struct w83627ehf_data {
1ea6dd38
DH		 256 int addr; /* IO base of hw monitor block */
257 const char *name;
258
943b0830 259 struct class_device *class_dev;
9a61bf63 260 struct mutex lock;
08e7e278 261
9a61bf63 262 struct mutex update_lock;
08e7e278
JD		 263 char valid; /* !=0 if following fields are valid */
264 unsigned long last_updated; /* In jiffies */
265
266 /* Register values */
1ea6dd38 267 u8 in_num; /* number of in inputs we have */
cf0676fe
RM		 268 u8 in[10]; /* Register value */
269 u8 in_max[10]; /* Register value */
270 u8 in_min[10]; /* Register value */
08e7e278
JD		 271 u8 fan[5];
272 u8 fan_min[5];
273 u8 fan_div[5];
274 u8 has_fan; /* some fan inputs can be disabled */
275 s8 temp1;
276 s8 temp1_max;
277 s8 temp1_max_hyst;
278 s16 temp[2];
279 s16 temp_max[2];
280 s16 temp_max_hyst[2];
a4589dbb 281 u32 alarms;
08c79950
RM		 282
283 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
284 u8 pwm_enable[4]; /* 1->manual
285 2->thermal cruise (also called SmartFan I) */
286 u8 pwm[4];
287 u8 target_temp[4];
288 u8 tolerance[4];
289
290 u8 fan_min_output[4]; /* minimum fan speed */
291 u8 fan_stop_time[4];
fc18d6c0
JD		 292
293 u8 vid;
294 u8 vrm;
08e7e278
JD		 295};
296
1ea6dd38
DH		 297struct w83627ehf_sio_data {
298 int sioreg;
299 enum kinds kind;
300};
301
08e7e278
JD		 302static inline int is_word_sized(u16 reg)
303{
304 return (((reg & 0xff00) == 0x100
305 || (reg & 0xff00) == 0x200)
306 && ((reg & 0x00ff) == 0x50
307 || (reg & 0x00ff) == 0x53
308 || (reg & 0x00ff) == 0x55));
309}
310
311/* We assume that the default bank is 0, thus the following two functions do
312 nothing for registers which live in bank 0. For others, they respectively
313 set the bank register to the correct value (before the register is
314 accessed), and back to 0 (afterwards). */
1ea6dd38 315static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
08e7e278
JD		 316{
317 if (reg & 0xff00) {
1ea6dd38
DH		 318 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
319 outb_p(reg >> 8, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 320 }
321}
322
1ea6dd38 323static inline void w83627ehf_reset_bank(struct w83627ehf_data *data, u16 reg)
08e7e278
JD		 324{
325 if (reg & 0xff00) {
1ea6dd38
DH		 326 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
327 outb_p(0, data->addr + DATA_REG_OFFSET);
08e7e278
JD		 328 }
329}
330
1ea6dd38 331static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
08e7e278 332{
08e7e278
JD		 333 int res, word_sized = is_word_sized(reg);
334
9a61bf63 335 mutex_lock(&data->lock);
08e7e278 336
1ea6dd38
DH		 337 w83627ehf_set_bank(data, reg);
338 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
339 res = inb_p(data->addr + DATA_REG_OFFSET);
08e7e278
JD		 340 if (word_sized) {
341 outb_p((reg & 0xff) + 1,
1ea6dd38
DH		 342 data->addr + ADDR_REG_OFFSET);
343 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
08e7e278 344 }
1ea6dd38 345 w83627ehf_reset_bank(data, reg);
08e7e278 346
9a61bf63 347 mutex_unlock(&data->lock);
08e7e278
JD		 348
349 return res;
350}
351
1ea6dd38 352static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg, u16 value)
08e7e278 353{
08e7e278
JD		 354 int word_sized = is_word_sized(reg);
355
9a61bf63 356 mutex_lock(&data->lock);
08e7e278 357
1ea6dd38
DH		 358 w83627ehf_set_bank(data, reg);
359 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
08e7e278 360 if (word_sized) {
1ea6dd38 361 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
08e7e278 362 outb_p((reg & 0xff) + 1,
1ea6dd38 363 data->addr + ADDR_REG_OFFSET);
08e7e278 364 }
1ea6dd38
DH		 365 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
366 w83627ehf_reset_bank(data, reg);
08e7e278 367
9a61bf63 368 mutex_unlock(&data->lock);
08e7e278
JD		 369 return 0;
370}
371
372/* This function assumes that the caller holds data->update_lock */
1ea6dd38 373static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
08e7e278 374{
08e7e278
JD		 375 u8 reg;
376
377 switch (nr) {
378 case 0:
1ea6dd38 379 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
08e7e278 380 | ((data->fan_div[0] & 0x03) << 4);
14992c7e
RM		 381 /* fan5 input control bit is write only, compute the value */
382 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 383 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
384 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
08e7e278 385 | ((data->fan_div[0] & 0x04) << 3);
1ea6dd38 386 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 387 break;
388 case 1:
1ea6dd38 389 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
08e7e278 390 | ((data->fan_div[1] & 0x03) << 6);
14992c7e
RM		 391 /* fan5 input control bit is write only, compute the value */
392 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
1ea6dd38
DH		 393 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
394 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
08e7e278 395 | ((data->fan_div[1] & 0x04) << 4);
1ea6dd38 396 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 397 break;
398 case 2:
1ea6dd38 399 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
08e7e278 400 | ((data->fan_div[2] & 0x03) << 6);
1ea6dd38
DH		 401 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
402 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
08e7e278 403 | ((data->fan_div[2] & 0x04) << 5);
1ea6dd38 404 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
08e7e278
JD		 405 break;
406 case 3:
1ea6dd38 407 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
08e7e278 408 | (data->fan_div[3] & 0x03);
1ea6dd38
DH		 409 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
410 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
08e7e278 411 | ((data->fan_div[3] & 0x04) << 5);
1ea6dd38 412 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
08e7e278
JD		 413 break;
414 case 4:
1ea6dd38 415 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
33725ad3 416 | ((data->fan_div[4] & 0x03) << 2)
08e7e278 417 | ((data->fan_div[4] & 0x04) << 5);
1ea6dd38 418 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
08e7e278
JD		 419 break;
420 }
421}
422
423static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
424{
1ea6dd38 425 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950 426 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
08e7e278
JD		 427 int i;
428
9a61bf63 429 mutex_lock(&data->update_lock);
08e7e278 430
6b3e4645 431 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
08e7e278
JD		 432 || !data->valid) {
433 /* Fan clock dividers */
1ea6dd38 434 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
08e7e278
JD		 435 data->fan_div[0] = (i >> 4) & 0x03;
436 data->fan_div[1] = (i >> 6) & 0x03;
1ea6dd38 437 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
08e7e278 438 data->fan_div[2] = (i >> 6) & 0x03;
1ea6dd38 439 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
08e7e278
JD		 440 data->fan_div[0] |= (i >> 3) & 0x04;
441 data->fan_div[1] |= (i >> 4) & 0x04;
442 data->fan_div[2] |= (i >> 5) & 0x04;
443 if (data->has_fan & ((1 << 3) | (1 << 4))) {
1ea6dd38 444 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
08e7e278
JD		 445 data->fan_div[3] = i & 0x03;
446 data->fan_div[4] = ((i >> 2) & 0x03)
447 | ((i >> 5) & 0x04);
448 }
449 if (data->has_fan & (1 << 3)) {
1ea6dd38 450 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
08e7e278
JD		 451 data->fan_div[3] |= (i >> 5) & 0x04;
452 }
453
cf0676fe 454 /* Measured voltages and limits */
1ea6dd38
DH		 455 for (i = 0; i < data->in_num; i++) {
456 data->in[i] = w83627ehf_read_value(data,
cf0676fe 457 W83627EHF_REG_IN(i));
1ea6dd38 458 data->in_min[i] = w83627ehf_read_value(data,
cf0676fe 459 W83627EHF_REG_IN_MIN(i));
1ea6dd38 460 data->in_max[i] = w83627ehf_read_value(data,
cf0676fe
RM		 461 W83627EHF_REG_IN_MAX(i));
462 }
463
08e7e278
JD		 464 /* Measured fan speeds and limits */
465 for (i = 0; i < 5; i++) {
466 if (!(data->has_fan & (1 << i)))
467 continue;
468
1ea6dd38 469 data->fan[i] = w83627ehf_read_value(data,
08e7e278 470 W83627EHF_REG_FAN[i]);
1ea6dd38 471 data->fan_min[i] = w83627ehf_read_value(data,
08e7e278
JD		 472 W83627EHF_REG_FAN_MIN[i]);
473
474 /* If we failed to measure the fan speed and clock
475 divider can be increased, let's try that for next
476 time */
477 if (data->fan[i] == 0xff
478 && data->fan_div[i] < 0x07) {
1ea6dd38 479 dev_dbg(dev, "Increasing fan%d "
08e7e278 480 "clock divider from %u to %u\n",
33725ad3 481 i + 1, div_from_reg(data->fan_div[i]),
08e7e278
JD		 482 div_from_reg(data->fan_div[i] + 1));
483 data->fan_div[i]++;
1ea6dd38 484 w83627ehf_write_fan_div(data, i);
08e7e278
JD		 485 /* Preserve min limit if possible */
486 if (data->fan_min[i] >= 2
487 && data->fan_min[i] != 255)
1ea6dd38 488 w83627ehf_write_value(data,
08e7e278
JD		 489 W83627EHF_REG_FAN_MIN[i],
490 (data->fan_min[i] /= 2));
491 }
492 }
493
08c79950
RM		 494 for (i = 0; i < 4; i++) {
495 /* pwmcfg, tolarance mapped for i=0, i=1 to same reg */
496 if (i != 1) {
1ea6dd38 497 pwmcfg = w83627ehf_read_value(data,
08c79950 498 W83627EHF_REG_PWM_ENABLE[i]);
1ea6dd38 499 tolerance = w83627ehf_read_value(data,
08c79950
RM		 500 W83627EHF_REG_TOLERANCE[i]);
501 }
502 data->pwm_mode[i] =
503 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1)
504 ? 0 : 1;
505 data->pwm_enable[i] =
506 ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
507 & 3) + 1;
1ea6dd38 508 data->pwm[i] = w83627ehf_read_value(data,
08c79950 509 W83627EHF_REG_PWM[i]);
1ea6dd38 510 data->fan_min_output[i] = w83627ehf_read_value(data,
08c79950 511 W83627EHF_REG_FAN_MIN_OUTPUT[i]);
1ea6dd38 512 data->fan_stop_time[i] = w83627ehf_read_value(data,
08c79950
RM		 513 W83627EHF_REG_FAN_STOP_TIME[i]);
514 data->target_temp[i] =
1ea6dd38 515 w83627ehf_read_value(data,
08c79950
RM		 516 W83627EHF_REG_TARGET[i]) &
517 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
518 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0))
519 & 0x0f;
520 }
521
08e7e278 522 /* Measured temperatures and limits */
1ea6dd38 523 data->temp1 = w83627ehf_read_value(data,
08e7e278 524 W83627EHF_REG_TEMP1);
1ea6dd38 525 data->temp1_max = w83627ehf_read_value(data,
08e7e278 526 W83627EHF_REG_TEMP1_OVER);
1ea6dd38 527 data->temp1_max_hyst = w83627ehf_read_value(data,
08e7e278
JD		 528 W83627EHF_REG_TEMP1_HYST);
529 for (i = 0; i < 2; i++) {
1ea6dd38 530 data->temp[i] = w83627ehf_read_value(data,
08e7e278 531 W83627EHF_REG_TEMP[i]);
1ea6dd38 532 data->temp_max[i] = w83627ehf_read_value(data,
08e7e278 533 W83627EHF_REG_TEMP_OVER[i]);
1ea6dd38 534 data->temp_max_hyst[i] = w83627ehf_read_value(data,
08e7e278
JD		 535 W83627EHF_REG_TEMP_HYST[i]);
536 }
537
1ea6dd38 538 data->alarms = w83627ehf_read_value(data,
a4589dbb 539 W83627EHF_REG_ALARM1) |
1ea6dd38 540 (w83627ehf_read_value(data,
a4589dbb 541 W83627EHF_REG_ALARM2) << 8) |
1ea6dd38 542 (w83627ehf_read_value(data,
a4589dbb
JD		 543 W83627EHF_REG_ALARM3) << 16);
544
08e7e278
JD		 545 data->last_updated = jiffies;
546 data->valid = 1;
547 }
548
9a61bf63 549 mutex_unlock(&data->update_lock);
08e7e278
JD		 550 return data;
551}
552
553/*
554 * Sysfs callback functions
555 */
cf0676fe
RM		 556#define show_in_reg(reg) \
557static ssize_t \
558show_##reg(struct device *dev, struct device_attribute *attr, \
559 char *buf) \
560{ \
561 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
562 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
563 int nr = sensor_attr->index; \
564 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr)); \
565}
566show_in_reg(in)
567show_in_reg(in_min)
568show_in_reg(in_max)
569
570#define store_in_reg(REG, reg) \
571static ssize_t \
572store_in_##reg (struct device *dev, struct device_attribute *attr, \
573 const char *buf, size_t count) \
574{ \
1ea6dd38 575 struct w83627ehf_data *data = dev_get_drvdata(dev); \
cf0676fe
RM		 576 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
577 int nr = sensor_attr->index; \
578 u32 val = simple_strtoul(buf, NULL, 10); \
579 \
580 mutex_lock(&data->update_lock); \
581 data->in_##reg[nr] = in_to_reg(val, nr); \
1ea6dd38 582 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
cf0676fe
RM		 583 data->in_##reg[nr]); \
584 mutex_unlock(&data->update_lock); \
585 return count; \
586}
587
588store_in_reg(MIN, min)
589store_in_reg(MAX, max)
590
a4589dbb
JD		 591static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
592{
593 struct w83627ehf_data *data = w83627ehf_update_device(dev);
594 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
595 int nr = sensor_attr->index;
596 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
597}
598
cf0676fe
RM		 599static struct sensor_device_attribute sda_in_input[] = {
600 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
601 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
602 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
603 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
604 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
605 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
606 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
607 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
608 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
609 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
610};
611
a4589dbb
JD		 612static struct sensor_device_attribute sda_in_alarm[] = {
613 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
614 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
615 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
616 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
617 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
618 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
619 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
620 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
621 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
622 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
623};
624
cf0676fe
RM		 625static struct sensor_device_attribute sda_in_min[] = {
626 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
627 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
628 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
629 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
630 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
631 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
632 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
633 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
634 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
635 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
636};
637
638static struct sensor_device_attribute sda_in_max[] = {
639 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
640 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
641 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
642 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
643 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
644 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
645 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
646 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
647 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
648 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
649};
650
08e7e278
JD		 651#define show_fan_reg(reg) \
652static ssize_t \
412fec82
YM		 653show_##reg(struct device *dev, struct device_attribute *attr, \
654 char *buf) \
08e7e278
JD		 655{ \
656 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 657 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
658 int nr = sensor_attr->index; \
08e7e278
JD		 659 return sprintf(buf, "%d\n", \
660 fan_from_reg(data->reg[nr], \
661 div_from_reg(data->fan_div[nr]))); \
662}
663show_fan_reg(fan);
664show_fan_reg(fan_min);
665
666static ssize_t
412fec82
YM		 667show_fan_div(struct device *dev, struct device_attribute *attr,
668 char *buf)
08e7e278
JD		 669{
670 struct w83627ehf_data *data = w83627ehf_update_device(dev);
412fec82
YM		 671 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
672 int nr = sensor_attr->index;
673 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
08e7e278
JD		 674}
675
676static ssize_t
412fec82
YM		 677store_fan_min(struct device *dev, struct device_attribute *attr,
678 const char *buf, size_t count)
08e7e278 679{
1ea6dd38 680 struct w83627ehf_data *data = dev_get_drvdata(dev);
412fec82
YM		 681 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
682 int nr = sensor_attr->index;
08e7e278
JD		 683 unsigned int val = simple_strtoul(buf, NULL, 10);
684 unsigned int reg;
685 u8 new_div;
686
9a61bf63 687 mutex_lock(&data->update_lock);
08e7e278
JD		 688 if (!val) {
689 /* No min limit, alarm disabled */
690 data->fan_min[nr] = 255;
691 new_div = data->fan_div[nr]; /* No change */
692 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
693 } else if ((reg = 1350000U / val) >= 128 * 255) {
694 /* Speed below this value cannot possibly be represented,
695 even with the highest divider (128) */
696 data->fan_min[nr] = 254;
697 new_div = 7; /* 128 == (1 << 7) */
698 dev_warn(dev, "fan%u low limit %u below minimum %u, set to "
699 "minimum\n", nr + 1, val, fan_from_reg(254, 128));
700 } else if (!reg) {
701 /* Speed above this value cannot possibly be represented,
702 even with the lowest divider (1) */
703 data->fan_min[nr] = 1;
704 new_div = 0; /* 1 == (1 << 0) */
705 dev_warn(dev, "fan%u low limit %u above maximum %u, set to "
b9110b1c 706 "maximum\n", nr + 1, val, fan_from_reg(1, 1));
08e7e278
JD		 707 } else {
708 /* Automatically pick the best divider, i.e. the one such
709 that the min limit will correspond to a register value
710 in the 96..192 range */
711 new_div = 0;
712 while (reg > 192 && new_div < 7) {
713 reg >>= 1;
714 new_div++;
715 }
716 data->fan_min[nr] = reg;
717 }
718
719 /* Write both the fan clock divider (if it changed) and the new
720 fan min (unconditionally) */
721 if (new_div != data->fan_div[nr]) {
158ce075
JD		 722 /* Preserve the fan speed reading */
723 if (data->fan[nr] != 0xff) {
724 if (new_div > data->fan_div[nr])
725 data->fan[nr] >>= new_div - data->fan_div[nr];
726 else if (data->fan[nr] & 0x80)
727 data->fan[nr] = 0xff;
728 else
729 data->fan[nr] <<= data->fan_div[nr] - new_div;
730 }
08e7e278
JD		 731
732 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
733 nr + 1, div_from_reg(data->fan_div[nr]),
734 div_from_reg(new_div));
735 data->fan_div[nr] = new_div;
1ea6dd38 736 w83627ehf_write_fan_div(data, nr);
6b3e4645
JD		 737 /* Give the chip time to sample a new speed value */
738 data->last_updated = jiffies;
08e7e278 739 }
1ea6dd38 740 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[nr],
08e7e278 741 data->fan_min[nr]);
9a61bf63 742 mutex_unlock(&data->update_lock);
08e7e278
JD		 743
744 return count;
745}
746
412fec82
YM		 747static struct sensor_device_attribute sda_fan_input[] = {
748 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
749 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
750 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
751 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
752 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
753};
08e7e278 754
a4589dbb
JD		 755static struct sensor_device_attribute sda_fan_alarm[] = {
756 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
757 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
758 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
759 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
760 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
761};
762
412fec82
YM		 763static struct sensor_device_attribute sda_fan_min[] = {
764 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
765 store_fan_min, 0),
766 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
767 store_fan_min, 1),
768 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
769 store_fan_min, 2),
770 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
771 store_fan_min, 3),
772 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
773 store_fan_min, 4),
774};
08e7e278 775
412fec82
YM		 776static struct sensor_device_attribute sda_fan_div[] = {
777 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
778 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
779 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
780 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
781 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
782};
783
08e7e278
JD		 784#define show_temp1_reg(reg) \
785static ssize_t \
6f637a64
GKH		 786show_##reg(struct device *dev, struct device_attribute *attr, \
787 char *buf) \
08e7e278
JD		 788{ \
789 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
790 return sprintf(buf, "%d\n", temp1_from_reg(data->reg)); \
791}
792show_temp1_reg(temp1);
793show_temp1_reg(temp1_max);
794show_temp1_reg(temp1_max_hyst);
795
796#define store_temp1_reg(REG, reg) \
797static ssize_t \
6f637a64
GKH		 798store_temp1_##reg(struct device *dev, struct device_attribute *attr, \
799 const char *buf, size_t count) \
08e7e278 800{ \
1ea6dd38 801 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08e7e278
JD		 802 u32 val = simple_strtoul(buf, NULL, 10); \
803 \
9a61bf63 804 mutex_lock(&data->update_lock); \
08c79950 805 data->temp1_##reg = temp1_to_reg(val, -128000, 127000); \
1ea6dd38 806 w83627ehf_write_value(data, W83627EHF_REG_TEMP1_##REG, \
08e7e278 807 data->temp1_##reg); \
9a61bf63 808 mutex_unlock(&data->update_lock); \
08e7e278
JD		 809 return count; \
810}
811store_temp1_reg(OVER, max);
812store_temp1_reg(HYST, max_hyst);
813
08e7e278
JD		 814#define show_temp_reg(reg) \
815static ssize_t \
412fec82
YM		 816show_##reg(struct device *dev, struct device_attribute *attr, \
817 char *buf) \
08e7e278
JD		 818{ \
819 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
412fec82
YM		 820 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
821 int nr = sensor_attr->index; \
08e7e278
JD		 822 return sprintf(buf, "%d\n", \
823 LM75_TEMP_FROM_REG(data->reg[nr])); \
824}
825show_temp_reg(temp);
826show_temp_reg(temp_max);
827show_temp_reg(temp_max_hyst);
828
829#define store_temp_reg(REG, reg) \
830static ssize_t \
412fec82
YM		 831store_##reg(struct device *dev, struct device_attribute *attr, \
832 const char *buf, size_t count) \
08e7e278 833{ \
1ea6dd38 834 struct w83627ehf_data *data = dev_get_drvdata(dev); \
412fec82
YM		 835 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
836 int nr = sensor_attr->index; \
08e7e278
JD		 837 u32 val = simple_strtoul(buf, NULL, 10); \
838 \
9a61bf63 839 mutex_lock(&data->update_lock); \
08e7e278 840 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1ea6dd38 841 w83627ehf_write_value(data, W83627EHF_REG_TEMP_##REG[nr], \
08e7e278 842 data->reg[nr]); \
9a61bf63 843 mutex_unlock(&data->update_lock); \
08e7e278
JD		 844 return count; \
845}
846store_temp_reg(OVER, temp_max);
847store_temp_reg(HYST, temp_max_hyst);
848
412fec82
YM		 849static struct sensor_device_attribute sda_temp[] = {
850 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp1, NULL, 0),
851 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 0),
852 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 1),
853 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp1_max,
854 store_temp1_max, 0),
855 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
856 store_temp_max, 0),
857 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
858 store_temp_max, 1),
859 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp1_max_hyst,
860 store_temp1_max_hyst, 0),
861 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
862 store_temp_max_hyst, 0),
863 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
864 store_temp_max_hyst, 1),
a4589dbb
JD		 865 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
866 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
867 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
412fec82 868};
08e7e278 869
08c79950
RM		 870#define show_pwm_reg(reg) \
871static ssize_t show_##reg (struct device *dev, struct device_attribute *attr, \
872 char *buf) \
873{ \
874 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
875 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
876 int nr = sensor_attr->index; \
877 return sprintf(buf, "%d\n", data->reg[nr]); \
878}
879
880show_pwm_reg(pwm_mode)
881show_pwm_reg(pwm_enable)
882show_pwm_reg(pwm)
883
884static ssize_t
885store_pwm_mode(struct device *dev, struct device_attribute *attr,
886 const char *buf, size_t count)
887{
1ea6dd38 888 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 889 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
890 int nr = sensor_attr->index;
891 u32 val = simple_strtoul(buf, NULL, 10);
892 u16 reg;
893
894 if (val > 1)
895 return -EINVAL;
896 mutex_lock(&data->update_lock);
1ea6dd38 897 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 898 data->pwm_mode[nr] = val;
899 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
900 if (!val)
901 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1ea6dd38 902 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 903 mutex_unlock(&data->update_lock);
904 return count;
905}
906
907static ssize_t
908store_pwm(struct device *dev, struct device_attribute *attr,
909 const char *buf, size_t count)
910{
1ea6dd38 911 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 912 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
913 int nr = sensor_attr->index;
914 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 0, 255);
915
916 mutex_lock(&data->update_lock);
917 data->pwm[nr] = val;
1ea6dd38 918 w83627ehf_write_value(data, W83627EHF_REG_PWM[nr], val);
08c79950
RM		 919 mutex_unlock(&data->update_lock);
920 return count;
921}
922
923static ssize_t
924store_pwm_enable(struct device *dev, struct device_attribute *attr,
925 const char *buf, size_t count)
926{
1ea6dd38 927 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 928 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
929 int nr = sensor_attr->index;
930 u32 val = simple_strtoul(buf, NULL, 10);
931 u16 reg;
932
933 if (!val || (val > 2)) /* only modes 1 and 2 are supported */
934 return -EINVAL;
935 mutex_lock(&data->update_lock);
1ea6dd38 936 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
08c79950
RM		 937 data->pwm_enable[nr] = val;
938 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
939 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1ea6dd38 940 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
08c79950
RM		 941 mutex_unlock(&data->update_lock);
942 return count;
943}
944
945
946#define show_tol_temp(reg) \
947static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
948 char *buf) \
949{ \
950 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
951 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
952 int nr = sensor_attr->index; \
953 return sprintf(buf, "%d\n", temp1_from_reg(data->reg[nr])); \
954}
955
956show_tol_temp(tolerance)
957show_tol_temp(target_temp)
958
959static ssize_t
960store_target_temp(struct device *dev, struct device_attribute *attr,
961 const char *buf, size_t count)
962{
1ea6dd38 963 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 964 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
965 int nr = sensor_attr->index;
966 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 127000);
967
968 mutex_lock(&data->update_lock);
969 data->target_temp[nr] = val;
1ea6dd38 970 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
08c79950
RM		 971 mutex_unlock(&data->update_lock);
972 return count;
973}
974
975static ssize_t
976store_tolerance(struct device *dev, struct device_attribute *attr,
977 const char *buf, size_t count)
978{
1ea6dd38 979 struct w83627ehf_data *data = dev_get_drvdata(dev);
08c79950
RM		 980 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
981 int nr = sensor_attr->index;
982 u16 reg;
983 /* Limit the temp to 0C - 15C */
984 u8 val = temp1_to_reg(simple_strtoul(buf, NULL, 10), 0, 15000);
985
986 mutex_lock(&data->update_lock);
1ea6dd38 987 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
08c79950
RM		 988 data->tolerance[nr] = val;
989 if (nr == 1)
990 reg = (reg & 0x0f) | (val << 4);
991 else
992 reg = (reg & 0xf0) | val;
1ea6dd38 993 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
08c79950
RM		 994 mutex_unlock(&data->update_lock);
995 return count;
996}
997
998static struct sensor_device_attribute sda_pwm[] = {
999 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1000 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1001 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1002 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1003};
1004
1005static struct sensor_device_attribute sda_pwm_mode[] = {
1006 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1007 store_pwm_mode, 0),
1008 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1009 store_pwm_mode, 1),
1010 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1011 store_pwm_mode, 2),
1012 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1013 store_pwm_mode, 3),
1014};
1015
1016static struct sensor_device_attribute sda_pwm_enable[] = {
1017 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1018 store_pwm_enable, 0),
1019 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1020 store_pwm_enable, 1),
1021 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1022 store_pwm_enable, 2),
1023 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1024 store_pwm_enable, 3),
1025};
1026
1027static struct sensor_device_attribute sda_target_temp[] = {
1028 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1029 store_target_temp, 0),
1030 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1031 store_target_temp, 1),
1032 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1033 store_target_temp, 2),
1034 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1035 store_target_temp, 3),
1036};
1037
1038static struct sensor_device_attribute sda_tolerance[] = {
1039 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1040 store_tolerance, 0),
1041 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1042 store_tolerance, 1),
1043 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1044 store_tolerance, 2),
1045 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1046 store_tolerance, 3),
1047};
1048
08c79950
RM		 1049/* Smart Fan registers */
1050
1051#define fan_functions(reg, REG) \
1052static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1053 char *buf) \
1054{ \
1055 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1056 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1057 int nr = sensor_attr->index; \
1058 return sprintf(buf, "%d\n", data->reg[nr]); \
1059}\
1060static ssize_t \
1061store_##reg(struct device *dev, struct device_attribute *attr, \
1062 const char *buf, size_t count) \
1063{\
1ea6dd38 1064 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1065 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1066 int nr = sensor_attr->index; \
1067 u32 val = SENSORS_LIMIT(simple_strtoul(buf, NULL, 10), 1, 255); \
1068 mutex_lock(&data->update_lock); \
1069 data->reg[nr] = val; \
1ea6dd38 1070 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1071 mutex_unlock(&data->update_lock); \
1072 return count; \
1073}
1074
1075fan_functions(fan_min_output, FAN_MIN_OUTPUT)
1076
1077#define fan_time_functions(reg, REG) \
1078static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1079 char *buf) \
1080{ \
1081 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1082 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1083 int nr = sensor_attr->index; \
1084 return sprintf(buf, "%d\n", \
1085 step_time_from_reg(data->reg[nr], data->pwm_mode[nr])); \
1086} \
1087\
1088static ssize_t \
1089store_##reg(struct device *dev, struct device_attribute *attr, \
1090 const char *buf, size_t count) \
1091{ \
1ea6dd38 1092 struct w83627ehf_data *data = dev_get_drvdata(dev); \
08c79950
RM		 1093 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); \
1094 int nr = sensor_attr->index; \
1095 u8 val = step_time_to_reg(simple_strtoul(buf, NULL, 10), \
1096 data->pwm_mode[nr]); \
1097 mutex_lock(&data->update_lock); \
1098 data->reg[nr] = val; \
1ea6dd38 1099 w83627ehf_write_value(data, W83627EHF_REG_##REG[nr], val); \
08c79950
RM		 1100 mutex_unlock(&data->update_lock); \
1101 return count; \
1102} \
1103
1104fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1105
1ea6dd38
DH		 1106static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1107 char *buf)
1108{
1109 struct w83627ehf_data *data = dev_get_drvdata(dev);
1110
1111 return sprintf(buf, "%s\n", data->name);
1112}
1113static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
08c79950
RM		 1114
1115static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1116 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1117 store_fan_stop_time, 3),
1118 SENSOR_ATTR(pwm4_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1119 store_fan_min_output, 3),
1120};
1121
1122static struct sensor_device_attribute sda_sf3_arrays[] = {
1123 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1124 store_fan_stop_time, 0),
1125 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1126 store_fan_stop_time, 1),
1127 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1128 store_fan_stop_time, 2),
1129 SENSOR_ATTR(pwm1_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1130 store_fan_min_output, 0),
1131 SENSOR_ATTR(pwm2_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1132 store_fan_min_output, 1),
1133 SENSOR_ATTR(pwm3_min_output, S_IWUSR | S_IRUGO, show_fan_min_output,
1134 store_fan_min_output, 2),
1135};
1136
fc18d6c0
JD		 1137static ssize_t
1138show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1139{
1140 struct w83627ehf_data *data = dev_get_drvdata(dev);
1141 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1142}
1143static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1144
08e7e278 1145/*
1ea6dd38 1146 * Driver and device management
08e7e278
JD		 1147 */
1148
c18beb5b
DH		 1149static void w83627ehf_device_remove_files(struct device *dev)
1150{
1151 /* some entries in the following arrays may not have been used in
1152 * device_create_file(), but device_remove_file() will ignore them */
1153 int i;
1ea6dd38 1154 struct w83627ehf_data *data = dev_get_drvdata(dev);
c18beb5b
DH		 1155
1156 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1157 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
1158 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1159 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1ea6dd38 1160 for (i = 0; i < data->in_num; i++) {
c18beb5b
DH		 1161 device_remove_file(dev, &sda_in_input[i].dev_attr);
1162 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1163 device_remove_file(dev, &sda_in_min[i].dev_attr);
1164 device_remove_file(dev, &sda_in_max[i].dev_attr);
1165 }
1166 for (i = 0; i < 5; i++) {
1167 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1168 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1169 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1170 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1171 }
1172 for (i = 0; i < 4; i++) {
1173 device_remove_file(dev, &sda_pwm[i].dev_attr);
1174 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1175 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1176 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1177 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1178 }
1179 for (i = 0; i < ARRAY_SIZE(sda_temp); i++)
1180 device_remove_file(dev, &sda_temp[i].dev_attr);
c18beb5b 1181
1ea6dd38 1182 device_remove_file(dev, &dev_attr_name);
fc18d6c0
JD		 1183 if (data->vid != 0x3f)
1184 device_remove_file(dev, &dev_attr_cpu0_vid);
1ea6dd38 1185}
08e7e278 1186
1ea6dd38
DH		 1187/* Get the monitoring functions started */
1188static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
08e7e278
JD		 1189{
1190 int i;
1191 u8 tmp;
1192
1193 /* Start monitoring is needed */
1ea6dd38 1194 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
08e7e278 1195 if (!(tmp & 0x01))
1ea6dd38 1196 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
08e7e278
JD		 1197 tmp | 0x01);
1198
1199 /* Enable temp2 and temp3 if needed */
1200 for (i = 0; i < 2; i++) {
1ea6dd38 1201 tmp = w83627ehf_read_value(data,
08e7e278
JD		 1202 W83627EHF_REG_TEMP_CONFIG[i]);
1203 if (tmp & 0x01)
1ea6dd38 1204 w83627ehf_write_value(data,
08e7e278
JD		 1205 W83627EHF_REG_TEMP_CONFIG[i],
1206 tmp & 0xfe);
1207 }
d3130f0e
JD		 1208
1209 /* Enable VBAT monitoring if needed */
1210 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1211 if (!(tmp & 0x01))
1212 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
08e7e278
JD		 1213}
1214
1ea6dd38 1215static int __devinit w83627ehf_probe(struct platform_device *pdev)
08e7e278 1216{
1ea6dd38
DH		 1217 struct device *dev = &pdev->dev;
1218 struct w83627ehf_sio_data *sio_data = dev->platform_data;
08e7e278 1219 struct w83627ehf_data *data;
1ea6dd38 1220 struct resource *res;
fc18d6c0 1221 u8 fan4pin, fan5pin, en_vrm10;
08e7e278
JD		 1222 int i, err = 0;
1223
1ea6dd38
DH		 1224 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1225 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
08e7e278 1226 err = -EBUSY;
1ea6dd38
DH		 1227 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1228 (unsigned long)res->start,
1229 (unsigned long)res->start + IOREGION_LENGTH - 1);
08e7e278
JD		 1230 goto exit;
1231 }
1232
ba9c2e8d 1233 if (!(data = kzalloc(sizeof(struct w83627ehf_data), GFP_KERNEL))) {
08e7e278
JD		 1234 err = -ENOMEM;
1235 goto exit_release;
1236 }
08e7e278 1237
1ea6dd38 1238 data->addr = res->start;
9a61bf63 1239 mutex_init(&data->lock);
9a61bf63 1240 mutex_init(&data->update_lock);
1ea6dd38
DH		 1241 data->name = w83627ehf_device_names[sio_data->kind];
1242 platform_set_drvdata(pdev, data);
08e7e278 1243
1ea6dd38
DH		 1244 /* 627EHG and 627EHF have 10 voltage inputs; DHG has 9 */
1245 data->in_num = (sio_data->kind == w83627dhg) ? 9 : 10;
08e7e278
JD		 1246
1247 /* Initialize the chip */
1ea6dd38 1248 w83627ehf_init_device(data);
08e7e278
JD		 1249
1250 /* A few vars need to be filled upon startup */
1251 for (i = 0; i < 5; i++)
1ea6dd38 1252 data->fan_min[i] = w83627ehf_read_value(data,
08e7e278
JD		 1253 W83627EHF_REG_FAN_MIN[i]);
1254
fc18d6c0
JD		 1255 data->vrm = vid_which_vrm();
1256 superio_enter(sio_data->sioreg);
1257 /* Set VID input sensibility if needed. In theory the BIOS should
1258 have set it, but in practice it's not always the case. */
1259 en_vrm10 = superio_inb(sio_data->sioreg, SIO_REG_EN_VRM10);
1260 if ((en_vrm10 & 0x08) && data->vrm != 100) {
1261 dev_warn(dev, "Setting VID input voltage to TTL\n");
1262 superio_outb(sio_data->sioreg, SIO_REG_EN_VRM10,
1263 en_vrm10 & ~0x08);
1264 } else if (!(en_vrm10 & 0x08) && data->vrm == 100) {
1265 dev_warn(dev, "Setting VID input voltage to VRM10\n");
1266 superio_outb(sio_data->sioreg, SIO_REG_EN_VRM10,
1267 en_vrm10 | 0x08);
1268 }
1269 /* Read VID value */
1270 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1271 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80)
1272 data->vid = superio_inb(sio_data->sioreg, SIO_REG_VID_DATA) & 0x3f;
1273 else {
1274 dev_info(dev, "VID pins in output mode, CPU VID not "
1275 "available\n");
1276 data->vid = 0x3f;
1277 }
1278
08c79950
RM		 1279 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1280
1ea6dd38
DH		 1281 fan5pin = superio_inb(sio_data->sioreg, 0x24) & 0x2;
1282 fan4pin = superio_inb(sio_data->sioreg, 0x29) & 0x6;
1283 superio_exit(sio_data->sioreg);
08c79950 1284
08e7e278 1285 /* It looks like fan4 and fan5 pins can be alternatively used
14992c7e
RM		 1286 as fan on/off switches, but fan5 control is write only :/
1287 We assume that if the serial interface is disabled, designers
1288 connected fan5 as input unless they are emitting log 1, which
1289 is not the default. */
08c79950 1290
08e7e278 1291 data->has_fan = 0x07; /* fan1, fan2 and fan3 */
1ea6dd38 1292 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
08c79950 1293 if ((i & (1 << 2)) && (!fan4pin))
08e7e278 1294 data->has_fan |= (1 << 3);
14992c7e 1295 if (!(i & (1 << 1)) && (!fan5pin))
08e7e278
JD		 1296 data->has_fan |= (1 << 4);
1297
1298 /* Register sysfs hooks */
08c79950 1299 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
c18beb5b
DH		 1300 if ((err = device_create_file(dev,
1301 &sda_sf3_arrays[i].dev_attr)))
1302 goto exit_remove;
08c79950
RM		 1303
1304 /* if fan4 is enabled create the sf3 files for it */
1305 if (data->has_fan & (1 << 3))
c18beb5b
DH		 1306 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
1307 if ((err = device_create_file(dev,
1308 &sda_sf3_arrays_fan4[i].dev_attr)))
1309 goto exit_remove;
1310 }
08c79950 1311
1ea6dd38 1312 for (i = 0; i < data->in_num; i++)
c18beb5b
DH		 1313 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
1314 || (err = device_create_file(dev,
1315 &sda_in_alarm[i].dev_attr))
1316 || (err = device_create_file(dev,
1317 &sda_in_min[i].dev_attr))
1318 || (err = device_create_file(dev,
1319 &sda_in_max[i].dev_attr)))
1320 goto exit_remove;
cf0676fe 1321
412fec82 1322 for (i = 0; i < 5; i++) {
08c79950 1323 if (data->has_fan & (1 << i)) {
c18beb5b
DH		 1324 if ((err = device_create_file(dev,
1325 &sda_fan_input[i].dev_attr))
1326 || (err = device_create_file(dev,
1327 &sda_fan_alarm[i].dev_attr))
1328 || (err = device_create_file(dev,
1329 &sda_fan_div[i].dev_attr))
1330 || (err = device_create_file(dev,
1331 &sda_fan_min[i].dev_attr)))
1332 goto exit_remove;
1333 if (i < 4 && /* w83627ehf only has 4 pwm */
1334 ((err = device_create_file(dev,
1335 &sda_pwm[i].dev_attr))
1336 || (err = device_create_file(dev,
1337 &sda_pwm_mode[i].dev_attr))
1338 || (err = device_create_file(dev,
1339 &sda_pwm_enable[i].dev_attr))
1340 || (err = device_create_file(dev,
1341 &sda_target_temp[i].dev_attr))
1342 || (err = device_create_file(dev,
1343 &sda_tolerance[i].dev_attr))))
1344 goto exit_remove;
08c79950 1345 }
08e7e278 1346 }
08c79950 1347
412fec82 1348 for (i = 0; i < ARRAY_SIZE(sda_temp); i++)
c18beb5b
DH		 1349 if ((err = device_create_file(dev, &sda_temp[i].dev_attr)))
1350 goto exit_remove;
1351
1ea6dd38
DH		 1352 err = device_create_file(dev, &dev_attr_name);
1353 if (err)
1354 goto exit_remove;
1355
fc18d6c0
JD		 1356 if (data->vid != 0x3f) {
1357 err = device_create_file(dev, &dev_attr_cpu0_vid);
1358 if (err)
1359 goto exit_remove;
1360 }
1361
c18beb5b
DH		 1362 data->class_dev = hwmon_device_register(dev);
1363 if (IS_ERR(data->class_dev)) {
1364 err = PTR_ERR(data->class_dev);
1365 goto exit_remove;
1366 }
08e7e278
JD		 1367
1368 return 0;
1369
c18beb5b
DH		 1370exit_remove:
1371 w83627ehf_device_remove_files(dev);
08e7e278 1372 kfree(data);
1ea6dd38 1373 platform_set_drvdata(pdev, NULL);
08e7e278 1374exit_release:
1ea6dd38 1375 release_region(res->start, IOREGION_LENGTH);
08e7e278
JD		 1376exit:
1377 return err;
1378}
1379
1ea6dd38 1380static int __devexit w83627ehf_remove(struct platform_device *pdev)
08e7e278 1381{
1ea6dd38 1382 struct w83627ehf_data *data = platform_get_drvdata(pdev);
08e7e278 1383
943b0830 1384 hwmon_device_unregister(data->class_dev);
1ea6dd38
DH		 1385 w83627ehf_device_remove_files(&pdev->dev);
1386 release_region(data->addr, IOREGION_LENGTH);
1387 platform_set_drvdata(pdev, NULL);
943b0830 1388 kfree(data);
08e7e278
JD		 1389
1390 return 0;
1391}
1392
1ea6dd38 1393static struct platform_driver w83627ehf_driver = {
cdaf7934 1394 .driver = {
87218842 1395 .owner = THIS_MODULE,
1ea6dd38 1396 .name = DRVNAME,
cdaf7934 1397 },
1ea6dd38
DH		 1398 .probe = w83627ehf_probe,
1399 .remove = __devexit_p(w83627ehf_remove),
08e7e278
JD		 1400};
1401
1ea6dd38
DH		 1402/* w83627ehf_find() looks for a '627 in the Super-I/O config space */
1403static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
1404 struct w83627ehf_sio_data *sio_data)
08e7e278 1405{
1ea6dd38
DH		 1406 static const char __initdata sio_name_W83627EHF[] = "W83627EHF";
1407 static const char __initdata sio_name_W83627EHG[] = "W83627EHG";
1408 static const char __initdata sio_name_W83627DHG[] = "W83627DHG";
1409
08e7e278 1410 u16 val;
1ea6dd38 1411 const char *sio_name;
08e7e278 1412
1ea6dd38 1413 superio_enter(sioaddr);
08e7e278 1414
1ea6dd38
DH		 1415 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
1416 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
657c93b1 1417 switch (val & SIO_ID_MASK) {
657c93b1 1418 case SIO_W83627EHF_ID:
1ea6dd38
DH		 1419 sio_data->kind = w83627ehf;
1420 sio_name = sio_name_W83627EHF;
1421 break;
657c93b1 1422 case SIO_W83627EHG_ID:
1ea6dd38
DH		 1423 sio_data->kind = w83627ehf;
1424 sio_name = sio_name_W83627EHG;
1425 break;
1426 case SIO_W83627DHG_ID:
1427 sio_data->kind = w83627dhg;
1428 sio_name = sio_name_W83627DHG;
657c93b1
DH		 1429 break;
1430 default:
1ea6dd38 1431 pr_info(DRVNAME ": unsupported chip ID: 0x%04x\n",
657c93b1 1432 val);
1ea6dd38 1433 superio_exit(sioaddr);
08e7e278
JD		 1434 return -ENODEV;
1435 }
1436
1ea6dd38
DH		 1437 /* We have a known chip, find the HWM I/O address */
1438 superio_select(sioaddr, W83627EHF_LD_HWM);
1439 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
1440 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
1a641fce 1441 *addr = val & IOREGION_ALIGNMENT;
2d8672c5 1442 if (*addr == 0) {
475ef855
DH		 1443 printk(KERN_ERR DRVNAME ": Refusing to enable a Super-I/O "
1444 "device with a base I/O port 0.\n");
1ea6dd38 1445 superio_exit(sioaddr);
08e7e278
JD		 1446 return -ENODEV;
1447 }
1448
1449 /* Activate logical device if needed */
1ea6dd38 1450 val = superio_inb(sioaddr, SIO_REG_ENABLE);
475ef855
DH		 1451 if (!(val & 0x01)) {
1452 printk(KERN_WARNING DRVNAME ": Forcibly enabling Super-I/O. "
1453 "Sensor is probably unusable.\n");
1ea6dd38 1454 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
475ef855 1455 }
1ea6dd38
DH		 1456
1457 superio_exit(sioaddr);
1458 pr_info(DRVNAME ": Found %s chip at %#x\n", sio_name, *addr);
1459 sio_data->sioreg = sioaddr;
08e7e278 1460
08e7e278
JD		 1461 return 0;
1462}
1463
1ea6dd38
DH		 1464/* when Super-I/O functions move to a separate file, the Super-I/O
1465 * bus will manage the lifetime of the device and this module will only keep
1466 * track of the w83627ehf driver. But since we platform_device_alloc(), we
1467 * must keep track of the device */
1468static struct platform_device *pdev;
1469
08e7e278
JD		 1470static int __init sensors_w83627ehf_init(void)
1471{
1ea6dd38
DH		 1472 int err;
1473 unsigned short address;
1474 struct resource res;
1475 struct w83627ehf_sio_data sio_data;
1476
1477 /* initialize sio_data->kind and sio_data->sioreg.
1478 *
1479 * when Super-I/O functions move to a separate file, the Super-I/O
1480 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
1481 * w83627ehf hardware monitor, and call probe() */
1482 if (w83627ehf_find(0x2e, &address, &sio_data) &&
1483 w83627ehf_find(0x4e, &address, &sio_data))
08e7e278
JD		 1484 return -ENODEV;
1485
1ea6dd38
DH		 1486 err = platform_driver_register(&w83627ehf_driver);
1487 if (err)
1488 goto exit;
1489
1490 if (!(pdev = platform_device_alloc(DRVNAME, address))) {
1491 err = -ENOMEM;
1492 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
1493 goto exit_unregister;
1494 }
1495
1496 err = platform_device_add_data(pdev, &sio_data,
1497 sizeof(struct w83627ehf_sio_data));
1498 if (err) {
1499 printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
1500 goto exit_device_put;
1501 }
1502
1503 memset(&res, 0, sizeof(res));
1504 res.name = DRVNAME;
1505 res.start = address + IOREGION_OFFSET;
1506 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
1507 res.flags = IORESOURCE_IO;
1508 err = platform_device_add_resources(pdev, &res, 1);
1509 if (err) {
1510 printk(KERN_ERR DRVNAME ": Device resource addition failed "
1511 "(%d)\n", err);
1512 goto exit_device_put;
1513 }
1514
1515 /* platform_device_add calls probe() */
1516 err = platform_device_add(pdev);
1517 if (err) {
1518 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
1519 err);
1520 goto exit_device_put;
1521 }
1522
1523 return 0;
1524
1525exit_device_put:
1526 platform_device_put(pdev);
1527exit_unregister:
1528 platform_driver_unregister(&w83627ehf_driver);
1529exit:
1530 return err;
08e7e278
JD		 1531}
1532
1533static void __exit sensors_w83627ehf_exit(void)
1534{
1ea6dd38
DH		 1535 platform_device_unregister(pdev);
1536 platform_driver_unregister(&w83627ehf_driver);
08e7e278
JD		 1537}
1538
1539MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
1540MODULE_DESCRIPTION("W83627EHF driver");
1541MODULE_LICENSE("GPL");
1542
1543module_init(sensors_w83627ehf_init);
1544module_exit(sensors_w83627ehf_exit);
Clone of davem's net-next-2.6 tree