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771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/firmware.h>
29#include <linux/platform_device.h>
5a0e3ad6 30#include <linux/slab.h>
771fe6b9 31#include "drmP.h"
771fe6b9 32#include "radeon.h"
e6990375 33#include "radeon_asic.h"
4153e584 34#include "radeon_drm.h"
3ce0a23d 35#include "rv770d.h"
3ce0a23d 36#include "atom.h"
d39c3b89 37#include "avivod.h"
771fe6b9 38
3ce0a23d
JG		 39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
771fe6b9 41
3ce0a23d
JG		 42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
771fe6b9 44
21a8122a
AD		 45/* get temperature in millidegrees */
46u32 rv770_get_temp(struct radeon_device *rdev)
47{
48 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
49 ASIC_T_SHIFT;
50 u32 actual_temp = 0;
51
52 if ((temp >> 9) & 1)
53 actual_temp = 0;
54 else
55 actual_temp = (temp >> 1) & 0xff;
56
57 return actual_temp * 1000;
58}
59
49e02b73
AD		 60void rv770_pm_misc(struct radeon_device *rdev)
61{
a081a9d6
RM		 62 int req_ps_idx = rdev->pm.requested_power_state_index;
63 int req_cm_idx = rdev->pm.requested_clock_mode_index;
64 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
65 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
4d60173f
AD		 66
67 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
68 if (voltage->voltage != rdev->pm.current_vddc) {
69 radeon_atom_set_voltage(rdev, voltage->voltage);
70 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 71 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 72 }
73 }
49e02b73 74}
771fe6b9
JG		 75
76/*
3ce0a23d 77 * GART
771fe6b9 78 */
3ce0a23d 79int rv770_pcie_gart_enable(struct radeon_device *rdev)
771fe6b9 80{
3ce0a23d
JG		 81 u32 tmp;
82 int r, i;
771fe6b9 83
4aac0473
JG		 84 if (rdev->gart.table.vram.robj == NULL) {
85 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
86 return -EINVAL;
3ce0a23d 87 }
4aac0473
JG		 88 r = radeon_gart_table_vram_pin(rdev);
89 if (r)
3ce0a23d 90 return r;
82568565 91 radeon_gart_restore(rdev);
3ce0a23d
JG		 92 /* Setup L2 cache */
93 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
94 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
95 EFFECTIVE_L2_QUEUE_SIZE(7));
96 WREG32(VM_L2_CNTL2, 0);
97 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
98 /* Setup TLB control */
99 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
100 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
101 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
102 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
103 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
104 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
105 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
106 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
107 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
108 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
109 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
110 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 111 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 112 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
113 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
114 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
115 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
116 (u32)(rdev->dummy_page.addr >> 12));
117 for (i = 1; i < 7; i++)
118 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 119
3ce0a23d
JG		 120 r600_pcie_gart_tlb_flush(rdev);
121 rdev->gart.ready = true;
771fe6b9
JG		 122 return 0;
123}
124
3ce0a23d 125void rv770_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 126{
3ce0a23d 127 u32 tmp;
4c788679 128 int i, r;
3ce0a23d 129
3ce0a23d
JG		 130 /* Disable all tables */
131 for (i = 0; i < 7; i++)
132 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
133
134 /* Setup L2 cache */
135 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
136 EFFECTIVE_L2_QUEUE_SIZE(7));
137 WREG32(VM_L2_CNTL2, 0);
138 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
139 /* Setup TLB control */
140 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
141 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
142 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
143 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
144 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
145 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
146 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
147 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
4aac0473 148 if (rdev->gart.table.vram.robj) {
4c788679
JG		 149 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
150 if (likely(r == 0)) {
151 radeon_bo_kunmap(rdev->gart.table.vram.robj);
152 radeon_bo_unpin(rdev->gart.table.vram.robj);
153 radeon_bo_unreserve(rdev->gart.table.vram.robj);
154 }
4aac0473
JG		 155 }
156}
157
158void rv770_pcie_gart_fini(struct radeon_device *rdev)
159{
f9274562 160 radeon_gart_fini(rdev);
4aac0473
JG		 161 rv770_pcie_gart_disable(rdev);
162 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 163}
164
165
1a029b76
JG		 166void rv770_agp_enable(struct radeon_device *rdev)
167{
168 u32 tmp;
169 int i;
170
171 /* Setup L2 cache */
172 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
173 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
174 EFFECTIVE_L2_QUEUE_SIZE(7));
175 WREG32(VM_L2_CNTL2, 0);
176 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
177 /* Setup TLB control */
178 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
179 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
180 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
181 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
182 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
183 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
184 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
185 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
186 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
187 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
188 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
189 for (i = 0; i < 7; i++)
190 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
191}
192
a3c1945a 193static void rv770_mc_program(struct radeon_device *rdev)
771fe6b9 194{
a3c1945a 195 struct rv515_mc_save save;
3ce0a23d
JG		 196 u32 tmp;
197 int i, j;
198
199 /* Initialize HDP */
200 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
201 WREG32((0x2c14 + j), 0x00000000);
202 WREG32((0x2c18 + j), 0x00000000);
203 WREG32((0x2c1c + j), 0x00000000);
204 WREG32((0x2c20 + j), 0x00000000);
205 WREG32((0x2c24 + j), 0x00000000);
206 }
812d0469
AD		 207 /* r7xx hw bug. Read from HDP_DEBUG1 rather
208 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
209 */
210 tmp = RREG32(HDP_DEBUG1);
3ce0a23d 211
a3c1945a 212 rv515_mc_stop(rdev, &save);
3ce0a23d 213 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 214 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 215 }
3ce0a23d
JG		 216 /* Lockout access through VGA aperture*/
217 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 218 /* Update configuration */
1a029b76
JG		 219 if (rdev->flags & RADEON_IS_AGP) {
220 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
221 /* VRAM before AGP */
222 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
223 rdev->mc.vram_start >> 12);
224 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
225 rdev->mc.gtt_end >> 12);
226 } else {
227 /* VRAM after AGP */
228 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
229 rdev->mc.gtt_start >> 12);
230 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
231 rdev->mc.vram_end >> 12);
232 }
233 } else {
234 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
235 rdev->mc.vram_start >> 12);
236 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
237 rdev->mc.vram_end >> 12);
238 }
3ce0a23d 239 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 240 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 241 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
242 WREG32(MC_VM_FB_LOCATION, tmp);
243 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
244 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 245 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 246 if (rdev->flags & RADEON_IS_AGP) {
1a029b76 247 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
3ce0a23d
JG		 248 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
249 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
250 } else {
251 WREG32(MC_VM_AGP_BASE, 0);
252 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
253 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
254 }
3ce0a23d 255 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 256 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 257 }
a3c1945a 258 rv515_mc_resume(rdev, &save);
698443d9
DA		 259 /* we need to own VRAM, so turn off the VGA renderer here
260 * to stop it overwriting our objects */
d39c3b89 261 rv515_vga_render_disable(rdev);
771fe6b9
JG		 262}
263
3ce0a23d
JG		 264
265/*
266 * CP.
267 */
268void r700_cp_stop(struct radeon_device *rdev)
771fe6b9 269{
c919b371 270 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
3ce0a23d 271 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
724c80e1 272 WREG32(SCRATCH_UMSK, 0);
771fe6b9
JG		 273}
274
3ce0a23d 275static int rv770_cp_load_microcode(struct radeon_device *rdev)
771fe6b9 276{
3ce0a23d
JG		 277 const __be32 *fw_data;
278 int i;
279
280 if (!rdev->me_fw || !rdev->pfp_fw)
281 return -EINVAL;
282
283 r700_cp_stop(rdev);
284 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
285
286 /* Reset cp */
287 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
288 RREG32(GRBM_SOFT_RESET);
289 mdelay(15);
290 WREG32(GRBM_SOFT_RESET, 0);
291
292 fw_data = (const __be32 *)rdev->pfp_fw->data;
293 WREG32(CP_PFP_UCODE_ADDR, 0);
294 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
295 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
296 WREG32(CP_PFP_UCODE_ADDR, 0);
297
298 fw_data = (const __be32 *)rdev->me_fw->data;
299 WREG32(CP_ME_RAM_WADDR, 0);
300 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
301 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
302
303 WREG32(CP_PFP_UCODE_ADDR, 0);
304 WREG32(CP_ME_RAM_WADDR, 0);
305 WREG32(CP_ME_RAM_RADDR, 0);
306 return 0;
771fe6b9
JG		 307}
308
fe251e2f
AD		 309void r700_cp_fini(struct radeon_device *rdev)
310{
311 r700_cp_stop(rdev);
312 radeon_ring_fini(rdev);
313}
771fe6b9
JG		 314
315/*
3ce0a23d 316 * Core functions
771fe6b9 317 */
d03f5d59
AD		 318static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
319 u32 num_tile_pipes,
320 u32 num_backends,
321 u32 backend_disable_mask)
771fe6b9 322{
3ce0a23d
JG		 323 u32 backend_map = 0;
324 u32 enabled_backends_mask;
325 u32 enabled_backends_count;
326 u32 cur_pipe;
327 u32 swizzle_pipe[R7XX_MAX_PIPES];
328 u32 cur_backend;
329 u32 i;
d03f5d59 330 bool force_no_swizzle;
3ce0a23d
JG		 331
332 if (num_tile_pipes > R7XX_MAX_PIPES)
333 num_tile_pipes = R7XX_MAX_PIPES;
334 if (num_tile_pipes < 1)
335 num_tile_pipes = 1;
336 if (num_backends > R7XX_MAX_BACKENDS)
337 num_backends = R7XX_MAX_BACKENDS;
338 if (num_backends < 1)
339 num_backends = 1;
340
341 enabled_backends_mask = 0;
342 enabled_backends_count = 0;
343 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
344 if (((backend_disable_mask >> i) & 1) == 0) {
345 enabled_backends_mask |= (1 << i);
346 ++enabled_backends_count;
347 }
348 if (enabled_backends_count == num_backends)
349 break;
350 }
351
352 if (enabled_backends_count == 0) {
353 enabled_backends_mask = 1;
354 enabled_backends_count = 1;
355 }
356
357 if (enabled_backends_count != num_backends)
358 num_backends = enabled_backends_count;
359
d03f5d59
AD		 360 switch (rdev->family) {
361 case CHIP_RV770:
362 case CHIP_RV730:
363 force_no_swizzle = false;
364 break;
365 case CHIP_RV710:
366 case CHIP_RV740:
367 default:
368 force_no_swizzle = true;
369 break;
370 }
371
3ce0a23d
JG		 372 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
373 switch (num_tile_pipes) {
374 case 1:
375 swizzle_pipe[0] = 0;
376 break;
377 case 2:
378 swizzle_pipe[0] = 0;
379 swizzle_pipe[1] = 1;
380 break;
381 case 3:
d03f5d59
AD		 382 if (force_no_swizzle) {
383 swizzle_pipe[0] = 0;
384 swizzle_pipe[1] = 1;
385 swizzle_pipe[2] = 2;
386 } else {
387 swizzle_pipe[0] = 0;
388 swizzle_pipe[1] = 2;
389 swizzle_pipe[2] = 1;
390 }
3ce0a23d
JG		 391 break;
392 case 4:
d03f5d59
AD		 393 if (force_no_swizzle) {
394 swizzle_pipe[0] = 0;
395 swizzle_pipe[1] = 1;
396 swizzle_pipe[2] = 2;
397 swizzle_pipe[3] = 3;
398 } else {
399 swizzle_pipe[0] = 0;
400 swizzle_pipe[1] = 2;
401 swizzle_pipe[2] = 3;
402 swizzle_pipe[3] = 1;
403 }
3ce0a23d
JG		 404 break;
405 case 5:
d03f5d59
AD		 406 if (force_no_swizzle) {
407 swizzle_pipe[0] = 0;
408 swizzle_pipe[1] = 1;
409 swizzle_pipe[2] = 2;
410 swizzle_pipe[3] = 3;
411 swizzle_pipe[4] = 4;
412 } else {
413 swizzle_pipe[0] = 0;
414 swizzle_pipe[1] = 2;
415 swizzle_pipe[2] = 4;
416 swizzle_pipe[3] = 1;
417 swizzle_pipe[4] = 3;
418 }
3ce0a23d
JG		 419 break;
420 case 6:
d03f5d59
AD		 421 if (force_no_swizzle) {
422 swizzle_pipe[0] = 0;
423 swizzle_pipe[1] = 1;
424 swizzle_pipe[2] = 2;
425 swizzle_pipe[3] = 3;
426 swizzle_pipe[4] = 4;
427 swizzle_pipe[5] = 5;
428 } else {
429 swizzle_pipe[0] = 0;
430 swizzle_pipe[1] = 2;
431 swizzle_pipe[2] = 4;
432 swizzle_pipe[3] = 5;
433 swizzle_pipe[4] = 3;
434 swizzle_pipe[5] = 1;
435 }
3ce0a23d
JG		 436 break;
437 case 7:
d03f5d59
AD		 438 if (force_no_swizzle) {
439 swizzle_pipe[0] = 0;
440 swizzle_pipe[1] = 1;
441 swizzle_pipe[2] = 2;
442 swizzle_pipe[3] = 3;
443 swizzle_pipe[4] = 4;
444 swizzle_pipe[5] = 5;
445 swizzle_pipe[6] = 6;
446 } else {
447 swizzle_pipe[0] = 0;
448 swizzle_pipe[1] = 2;
449 swizzle_pipe[2] = 4;
450 swizzle_pipe[3] = 6;
451 swizzle_pipe[4] = 3;
452 swizzle_pipe[5] = 1;
453 swizzle_pipe[6] = 5;
454 }
3ce0a23d
JG		 455 break;
456 case 8:
d03f5d59
AD		 457 if (force_no_swizzle) {
458 swizzle_pipe[0] = 0;
459 swizzle_pipe[1] = 1;
460 swizzle_pipe[2] = 2;
461 swizzle_pipe[3] = 3;
462 swizzle_pipe[4] = 4;
463 swizzle_pipe[5] = 5;
464 swizzle_pipe[6] = 6;
465 swizzle_pipe[7] = 7;
466 } else {
467 swizzle_pipe[0] = 0;
468 swizzle_pipe[1] = 2;
469 swizzle_pipe[2] = 4;
470 swizzle_pipe[3] = 6;
471 swizzle_pipe[4] = 3;
472 swizzle_pipe[5] = 1;
473 swizzle_pipe[6] = 7;
474 swizzle_pipe[7] = 5;
475 }
3ce0a23d
JG		 476 break;
477 }
478
479 cur_backend = 0;
480 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
481 while (((1 << cur_backend) & enabled_backends_mask) == 0)
482 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
483
484 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
485
486 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
487 }
488
489 return backend_map;
771fe6b9
JG		 490}
491
3ce0a23d 492static void rv770_gpu_init(struct radeon_device *rdev)
771fe6b9 493{
3ce0a23d 494 int i, j, num_qd_pipes;
d03f5d59 495 u32 ta_aux_cntl;
3ce0a23d
JG		 496 u32 sx_debug_1;
497 u32 smx_dc_ctl0;
d03f5d59 498 u32 db_debug3;
3ce0a23d
JG		 499 u32 num_gs_verts_per_thread;
500 u32 vgt_gs_per_es;
501 u32 gs_prim_buffer_depth = 0;
502 u32 sq_ms_fifo_sizes;
503 u32 sq_config;
504 u32 sq_thread_resource_mgmt;
505 u32 hdp_host_path_cntl;
506 u32 sq_dyn_gpr_size_simd_ab_0;
507 u32 backend_map;
508 u32 gb_tiling_config = 0;
509 u32 cc_rb_backend_disable = 0;
510 u32 cc_gc_shader_pipe_config = 0;
511 u32 mc_arb_ramcfg;
512 u32 db_debug4;
771fe6b9 513
3ce0a23d
JG		 514 /* setup chip specs */
515 switch (rdev->family) {
516 case CHIP_RV770:
517 rdev->config.rv770.max_pipes = 4;
518 rdev->config.rv770.max_tile_pipes = 8;
519 rdev->config.rv770.max_simds = 10;
520 rdev->config.rv770.max_backends = 4;
521 rdev->config.rv770.max_gprs = 256;
522 rdev->config.rv770.max_threads = 248;
523 rdev->config.rv770.max_stack_entries = 512;
524 rdev->config.rv770.max_hw_contexts = 8;
525 rdev->config.rv770.max_gs_threads = 16 * 2;
526 rdev->config.rv770.sx_max_export_size = 128;
527 rdev->config.rv770.sx_max_export_pos_size = 16;
528 rdev->config.rv770.sx_max_export_smx_size = 112;
529 rdev->config.rv770.sq_num_cf_insts = 2;
530
531 rdev->config.rv770.sx_num_of_sets = 7;
532 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
533 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
534 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
535 break;
536 case CHIP_RV730:
537 rdev->config.rv770.max_pipes = 2;
538 rdev->config.rv770.max_tile_pipes = 4;
539 rdev->config.rv770.max_simds = 8;
540 rdev->config.rv770.max_backends = 2;
541 rdev->config.rv770.max_gprs = 128;
542 rdev->config.rv770.max_threads = 248;
543 rdev->config.rv770.max_stack_entries = 256;
544 rdev->config.rv770.max_hw_contexts = 8;
545 rdev->config.rv770.max_gs_threads = 16 * 2;
546 rdev->config.rv770.sx_max_export_size = 256;
547 rdev->config.rv770.sx_max_export_pos_size = 32;
548 rdev->config.rv770.sx_max_export_smx_size = 224;
549 rdev->config.rv770.sq_num_cf_insts = 2;
550
551 rdev->config.rv770.sx_num_of_sets = 7;
552 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
553 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
554 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
555 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
556 rdev->config.rv770.sx_max_export_pos_size -= 16;
557 rdev->config.rv770.sx_max_export_smx_size += 16;
558 }
559 break;
560 case CHIP_RV710:
561 rdev->config.rv770.max_pipes = 2;
562 rdev->config.rv770.max_tile_pipes = 2;
563 rdev->config.rv770.max_simds = 2;
564 rdev->config.rv770.max_backends = 1;
565 rdev->config.rv770.max_gprs = 256;
566 rdev->config.rv770.max_threads = 192;
567 rdev->config.rv770.max_stack_entries = 256;
568 rdev->config.rv770.max_hw_contexts = 4;
569 rdev->config.rv770.max_gs_threads = 8 * 2;
570 rdev->config.rv770.sx_max_export_size = 128;
571 rdev->config.rv770.sx_max_export_pos_size = 16;
572 rdev->config.rv770.sx_max_export_smx_size = 112;
573 rdev->config.rv770.sq_num_cf_insts = 1;
574
575 rdev->config.rv770.sx_num_of_sets = 7;
576 rdev->config.rv770.sc_prim_fifo_size = 0x40;
577 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
578 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
579 break;
580 case CHIP_RV740:
581 rdev->config.rv770.max_pipes = 4;
582 rdev->config.rv770.max_tile_pipes = 4;
583 rdev->config.rv770.max_simds = 8;
584 rdev->config.rv770.max_backends = 4;
585 rdev->config.rv770.max_gprs = 256;
586 rdev->config.rv770.max_threads = 248;
587 rdev->config.rv770.max_stack_entries = 512;
588 rdev->config.rv770.max_hw_contexts = 8;
589 rdev->config.rv770.max_gs_threads = 16 * 2;
590 rdev->config.rv770.sx_max_export_size = 256;
591 rdev->config.rv770.sx_max_export_pos_size = 32;
592 rdev->config.rv770.sx_max_export_smx_size = 224;
593 rdev->config.rv770.sq_num_cf_insts = 2;
594
595 rdev->config.rv770.sx_num_of_sets = 7;
596 rdev->config.rv770.sc_prim_fifo_size = 0x100;
597 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
598 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
599
600 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
601 rdev->config.rv770.sx_max_export_pos_size -= 16;
602 rdev->config.rv770.sx_max_export_smx_size += 16;
603 }
604 break;
605 default:
606 break;
607 }
608
609 /* Initialize HDP */
610 j = 0;
611 for (i = 0; i < 32; i++) {
612 WREG32((0x2c14 + j), 0x00000000);
613 WREG32((0x2c18 + j), 0x00000000);
614 WREG32((0x2c1c + j), 0x00000000);
615 WREG32((0x2c20 + j), 0x00000000);
616 WREG32((0x2c24 + j), 0x00000000);
617 j += 0x18;
618 }
619
620 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
621
622 /* setup tiling, simd, pipe config */
623 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
624
625 switch (rdev->config.rv770.max_tile_pipes) {
626 case 1:
d03f5d59 627 default:
3ce0a23d
JG		 628 gb_tiling_config |= PIPE_TILING(0);
629 break;
630 case 2:
631 gb_tiling_config |= PIPE_TILING(1);
632 break;
633 case 4:
634 gb_tiling_config |= PIPE_TILING(2);
635 break;
636 case 8:
637 gb_tiling_config |= PIPE_TILING(3);
3ce0a23d
JG		 638 break;
639 }
d03f5d59 640 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
3ce0a23d
JG		 641
642 if (rdev->family == CHIP_RV770)
643 gb_tiling_config |= BANK_TILING(1);
644 else
e29649db 645 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
961fb597 646 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
881fe6c1
AD		 647 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
648 if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
649 rdev->config.rv770.tiling_group_size = 512;
650 else
651 rdev->config.rv770.tiling_group_size = 256;
e29649db 652 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
3ce0a23d
JG		 653 gb_tiling_config |= ROW_TILING(3);
654 gb_tiling_config |= SAMPLE_SPLIT(3);
655 } else {
656 gb_tiling_config |=
657 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
658 gb_tiling_config |=
659 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
660 }
661
662 gb_tiling_config |= BANK_SWAPS(1);
663
d03f5d59
AD		 664 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
665 cc_rb_backend_disable |=
666 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
3ce0a23d 667
d03f5d59
AD		 668 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
669 cc_gc_shader_pipe_config |=
3ce0a23d
JG		 670 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
671 cc_gc_shader_pipe_config |=
672 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
673
d03f5d59
AD		 674 if (rdev->family == CHIP_RV740)
675 backend_map = 0x28;
676 else
677 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
678 rdev->config.rv770.max_tile_pipes,
679 (R7XX_MAX_BACKENDS -
680 r600_count_pipe_bits((cc_rb_backend_disable &
681 R7XX_MAX_BACKENDS_MASK) >> 16)),
682 (cc_rb_backend_disable >> 16));
d03f5d59 683
e7aeeba6
AD		 684 rdev->config.rv770.tile_config = gb_tiling_config;
685 gb_tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 686
687 WREG32(GB_TILING_CONFIG, gb_tiling_config);
688 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
689 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
690
691 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
692 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 693 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
d03f5d59 694 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
3ce0a23d 695
3ce0a23d
JG		 696 WREG32(CGTS_SYS_TCC_DISABLE, 0);
697 WREG32(CGTS_TCC_DISABLE, 0);
f867c60d
AD		 698 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
699 WREG32(CGTS_USER_TCC_DISABLE, 0);
3ce0a23d
JG		 700
701 num_qd_pipes =
d03f5d59 702 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 703 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
704 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
705
706 /* set HW defaults for 3D engine */
707 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
e29649db 708 ROQ_IB2_START(0x2b)));
3ce0a23d
JG		 709
710 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
711
d03f5d59
AD		 712 ta_aux_cntl = RREG32(TA_CNTL_AUX);
713 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
3ce0a23d
JG		 714
715 sx_debug_1 = RREG32(SX_DEBUG_1);
716 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
717 WREG32(SX_DEBUG_1, sx_debug_1);
718
719 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
720 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
721 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
722 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
723
d03f5d59
AD		 724 if (rdev->family != CHIP_RV740)
725 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
726 GS_FLUSH_CTL(4) |
727 ACK_FLUSH_CTL(3) |
728 SYNC_FLUSH_CTL));
3ce0a23d 729
d03f5d59
AD		 730 db_debug3 = RREG32(DB_DEBUG3);
731 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
732 switch (rdev->family) {
733 case CHIP_RV770:
734 case CHIP_RV740:
735 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
736 break;
737 case CHIP_RV710:
738 case CHIP_RV730:
739 default:
740 db_debug3 |= DB_CLK_OFF_DELAY(2);
741 break;
742 }
743 WREG32(DB_DEBUG3, db_debug3);
744
745 if (rdev->family != CHIP_RV770) {
3ce0a23d
JG		 746 db_debug4 = RREG32(DB_DEBUG4);
747 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
748 WREG32(DB_DEBUG4, db_debug4);
749 }
750
751 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
e29649db
AD		 752 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
753 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
3ce0a23d
JG		 754
755 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
e29649db
AD		 756 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
757 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
3ce0a23d
JG		 758
759 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
760
761 WREG32(VGT_NUM_INSTANCES, 1);
762
763 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
764
765 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
766
767 WREG32(CP_PERFMON_CNTL, 0);
768
769 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
770 DONE_FIFO_HIWATER(0xe0) |
771 ALU_UPDATE_FIFO_HIWATER(0x8));
772 switch (rdev->family) {
773 case CHIP_RV770:
3ce0a23d
JG		 774 case CHIP_RV730:
775 case CHIP_RV710:
d03f5d59
AD		 776 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
777 break;
3ce0a23d
JG		 778 case CHIP_RV740:
779 default:
780 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
781 break;
782 }
783 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
784
785 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
786 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
787 */
788 sq_config = RREG32(SQ_CONFIG);
789 sq_config &= ~(PS_PRIO(3) |
790 VS_PRIO(3) |
791 GS_PRIO(3) |
792 ES_PRIO(3));
793 sq_config |= (DX9_CONSTS |
794 VC_ENABLE |
795 EXPORT_SRC_C |
796 PS_PRIO(0) |
797 VS_PRIO(1) |
798 GS_PRIO(2) |
799 ES_PRIO(3));
800 if (rdev->family == CHIP_RV710)
801 /* no vertex cache */
802 sq_config &= ~VC_ENABLE;
803
804 WREG32(SQ_CONFIG, sq_config);
805
806 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
fe62e1a4
DA		 807 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
808 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
3ce0a23d
JG		 809
810 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
fe62e1a4 811 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
3ce0a23d
JG		 812
813 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
814 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
815 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
816 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
817 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
818 else
819 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
820 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
821
822 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
823 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
824
825 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
826 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
827
828 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
829 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
830 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
831 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
832
833 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
834 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
835 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
836 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
837 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
838 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
839 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
840 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
841
842 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
fe62e1a4 843 FORCE_EOV_MAX_REZ_CNT(255)));
3ce0a23d
JG		 844
845 if (rdev->family == CHIP_RV710)
846 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
fe62e1a4 847 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 848 else
849 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
fe62e1a4 850 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 851
852 switch (rdev->family) {
853 case CHIP_RV770:
854 case CHIP_RV730:
855 case CHIP_RV740:
856 gs_prim_buffer_depth = 384;
857 break;
858 case CHIP_RV710:
859 gs_prim_buffer_depth = 128;
860 break;
861 default:
862 break;
863 }
864
865 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
866 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
867 /* Max value for this is 256 */
868 if (vgt_gs_per_es > 256)
869 vgt_gs_per_es = 256;
870
871 WREG32(VGT_ES_PER_GS, 128);
872 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
873 WREG32(VGT_GS_PER_VS, 2);
874
875 /* more default values. 2D/3D driver should adjust as needed */
876 WREG32(VGT_GS_VERTEX_REUSE, 16);
877 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
878 WREG32(VGT_STRMOUT_EN, 0);
879 WREG32(SX_MISC, 0);
880 WREG32(PA_SC_MODE_CNTL, 0);
881 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
882 WREG32(PA_SC_AA_CONFIG, 0);
883 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
884 WREG32(PA_SC_LINE_STIPPLE, 0);
885 WREG32(SPI_INPUT_Z, 0);
886 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
887 WREG32(CB_COLOR7_FRAG, 0);
888
889 /* clear render buffer base addresses */
890 WREG32(CB_COLOR0_BASE, 0);
891 WREG32(CB_COLOR1_BASE, 0);
892 WREG32(CB_COLOR2_BASE, 0);
893 WREG32(CB_COLOR3_BASE, 0);
894 WREG32(CB_COLOR4_BASE, 0);
895 WREG32(CB_COLOR5_BASE, 0);
896 WREG32(CB_COLOR6_BASE, 0);
897 WREG32(CB_COLOR7_BASE, 0);
898
899 WREG32(TCP_CNTL, 0);
900
901 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
902 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
903
904 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
905
906 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
907 NUM_CLIP_SEQ(3)));
908
909}
910
87cbf8f2
AD		 911static int rv770_vram_scratch_init(struct radeon_device *rdev)
912{
913 int r;
914 u64 gpu_addr;
915
916 if (rdev->vram_scratch.robj == NULL) {
917 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
918 true, RADEON_GEM_DOMAIN_VRAM,
919 &rdev->vram_scratch.robj);
920 if (r) {
921 return r;
922 }
923 }
924
925 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
926 if (unlikely(r != 0))
927 return r;
928 r = radeon_bo_pin(rdev->vram_scratch.robj,
929 RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
930 if (r) {
931 radeon_bo_unreserve(rdev->vram_scratch.robj);
932 return r;
933 }
934 r = radeon_bo_kmap(rdev->vram_scratch.robj,
935 (void **)&rdev->vram_scratch.ptr);
936 if (r)
937 radeon_bo_unpin(rdev->vram_scratch.robj);
938 radeon_bo_unreserve(rdev->vram_scratch.robj);
939
940 return r;
941}
942
943static void rv770_vram_scratch_fini(struct radeon_device *rdev)
944{
945 int r;
946
947 if (rdev->vram_scratch.robj == NULL) {
948 return;
949 }
950 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
951 if (likely(r == 0)) {
952 radeon_bo_kunmap(rdev->vram_scratch.robj);
953 radeon_bo_unpin(rdev->vram_scratch.robj);
954 radeon_bo_unreserve(rdev->vram_scratch.robj);
955 }
956 radeon_bo_unref(&rdev->vram_scratch.robj);
957}
958
3ce0a23d
JG		 959int rv770_mc_init(struct radeon_device *rdev)
960{
3ce0a23d 961 u32 tmp;
5885b7a9 962 int chansize, numchan;
3ce0a23d
JG		 963
964 /* Get VRAM informations */
3ce0a23d 965 rdev->mc.vram_is_ddr = true;
5885b7a9
AD		 966 tmp = RREG32(MC_ARB_RAMCFG);
967 if (tmp & CHANSIZE_OVERRIDE) {
968 chansize = 16;
969 } else if (tmp & CHANSIZE_MASK) {
970 chansize = 64;
971 } else {
972 chansize = 32;
973 }
974 tmp = RREG32(MC_SHARED_CHMAP);
975 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
976 case 0:
977 default:
978 numchan = 1;
979 break;
980 case 1:
981 numchan = 2;
982 break;
983 case 2:
984 numchan = 4;
985 break;
986 case 3:
987 numchan = 8;
988 break;
989 }
990 rdev->mc.vram_width = numchan * chansize;
771fe6b9 991 /* Could aper size report 0 ? */
01d73a69
JC		 992 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
993 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 994 /* Setup GPU memory space */
995 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
996 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 997 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 998 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
d594e46a 999 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 1000 radeon_update_bandwidth_info(rdev);
1001
3ce0a23d
JG		 1002 return 0;
1003}
d594e46a 1004
fc30b8ef 1005static int rv770_startup(struct radeon_device *rdev)
3ce0a23d
JG		 1006{
1007 int r;
1008
779720a3
AD		 1009 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1010 r = r600_init_microcode(rdev);
1011 if (r) {
1012 DRM_ERROR("Failed to load firmware!\n");
1013 return r;
1014 }
1015 }
1016
a3c1945a 1017 rv770_mc_program(rdev);
1a029b76
JG		 1018 if (rdev->flags & RADEON_IS_AGP) {
1019 rv770_agp_enable(rdev);
1020 } else {
1021 r = rv770_pcie_gart_enable(rdev);
1022 if (r)
1023 return r;
1024 }
87cbf8f2
AD		 1025 r = rv770_vram_scratch_init(rdev);
1026 if (r)
1027 return r;
3ce0a23d 1028 rv770_gpu_init(rdev);
c38c7b64
JG		 1029 r = r600_blit_init(rdev);
1030 if (r) {
1031 r600_blit_fini(rdev);
1032 rdev->asic->copy = NULL;
1033 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1034 }
b70d6bb3 1035
724c80e1
AD		 1036 /* allocate wb buffer */
1037 r = radeon_wb_init(rdev);
1038 if (r)
1039 return r;
1040
d8f60cfc 1041 /* Enable IRQ */
d8f60cfc
AD		 1042 r = r600_irq_init(rdev);
1043 if (r) {
1044 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1045 radeon_irq_kms_fini(rdev);
1046 return r;
1047 }
1048 r600_irq_set(rdev);
1049
3ce0a23d
JG		 1050 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1051 if (r)
1052 return r;
1053 r = rv770_cp_load_microcode(rdev);
1054 if (r)
1055 return r;
1056 r = r600_cp_resume(rdev);
1057 if (r)
1058 return r;
724c80e1 1059
3ce0a23d
JG		 1060 return 0;
1061}
1062
fc30b8ef
DA		 1063int rv770_resume(struct radeon_device *rdev)
1064{
1065 int r;
1066
1a029b76
JG		 1067 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1068 * posting will perform necessary task to bring back GPU into good
1069 * shape.
1070 */
fc30b8ef 1071 /* post card */
e7d40b9a 1072 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 1073
1074 r = rv770_startup(rdev);
1075 if (r) {
1076 DRM_ERROR("r600 startup failed on resume\n");
1077 return r;
1078 }
1079
62a8ea3f 1080 r = r600_ib_test(rdev);
fc30b8ef
DA		 1081 if (r) {
1082 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1083 return r;
1084 }
8a8c6e7c
RM		 1085
1086 r = r600_audio_init(rdev);
1087 if (r) {
1088 dev_err(rdev->dev, "radeon: audio init failed\n");
1089 return r;
1090 }
1091
fc30b8ef
DA		 1092 return r;
1093
1094}
1095
3ce0a23d
JG		 1096int rv770_suspend(struct radeon_device *rdev)
1097{
4c788679
JG		 1098 int r;
1099
8a8c6e7c 1100 r600_audio_fini(rdev);
3ce0a23d
JG		 1101 /* FIXME: we should wait for ring to be empty */
1102 r700_cp_stop(rdev);
4153e584 1103 rdev->cp.ready = false;
0c45249f 1104 r600_irq_suspend(rdev);
724c80e1 1105 radeon_wb_disable(rdev);
4aac0473 1106 rv770_pcie_gart_disable(rdev);
4153e584 1107 /* unpin shaders bo */
30d2d9a5
JG		 1108 if (rdev->r600_blit.shader_obj) {
1109 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1110 if (likely(r == 0)) {
1111 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1112 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1113 }
4c788679 1114 }
3ce0a23d
JG		 1115 return 0;
1116}
1117
1118/* Plan is to move initialization in that function and use
1119 * helper function so that radeon_device_init pretty much
1120 * do nothing more than calling asic specific function. This
1121 * should also allow to remove a bunch of callback function
1122 * like vram_info.
1123 */
1124int rv770_init(struct radeon_device *rdev)
1125{
1126 int r;
1127
3ce0a23d
JG		 1128 r = radeon_dummy_page_init(rdev);
1129 if (r)
1130 return r;
1131 /* This don't do much */
1132 r = radeon_gem_init(rdev);
1133 if (r)
1134 return r;
1135 /* Read BIOS */
1136 if (!radeon_get_bios(rdev)) {
1137 if (ASIC_IS_AVIVO(rdev))
1138 return -EINVAL;
1139 }
1140 /* Must be an ATOMBIOS */
e7d40b9a
JG		 1141 if (!rdev->is_atom_bios) {
1142 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 1143 return -EINVAL;
e7d40b9a 1144 }
3ce0a23d
JG		 1145 r = radeon_atombios_init(rdev);
1146 if (r)
1147 return r;
1148 /* Post card if necessary */
72542d77
DA		 1149 if (!r600_card_posted(rdev)) {
1150 if (!rdev->bios) {
1151 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1152 return -EINVAL;
1153 }
3ce0a23d
JG		 1154 DRM_INFO("GPU not posted. posting now...\n");
1155 atom_asic_init(rdev->mode_info.atom_context);
1156 }
1157 /* Initialize scratch registers */
1158 r600_scratch_init(rdev);
1159 /* Initialize surface registers */
1160 radeon_surface_init(rdev);
7433874e 1161 /* Initialize clocks */
5e6dde7e 1162 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 1163 /* Fence driver */
1164 r = radeon_fence_driver_init(rdev);
1165 if (r)
1166 return r;
d594e46a 1167 /* initialize AGP */
700a0cc0
JG		 1168 if (rdev->flags & RADEON_IS_AGP) {
1169 r = radeon_agp_init(rdev);
1170 if (r)
1171 radeon_agp_disable(rdev);
1172 }
3ce0a23d 1173 r = rv770_mc_init(rdev);
b574f251 1174 if (r)
3ce0a23d 1175 return r;
3ce0a23d 1176 /* Memory manager */
4c788679 1177 r = radeon_bo_init(rdev);
3ce0a23d
JG		 1178 if (r)
1179 return r;
d8f60cfc
AD		 1180
1181 r = radeon_irq_kms_init(rdev);
1182 if (r)
1183 return r;
1184
3ce0a23d
JG		 1185 rdev->cp.ring_obj = NULL;
1186 r600_ring_init(rdev, 1024 * 1024);
1187
d8f60cfc
AD		 1188 rdev->ih.ring_obj = NULL;
1189 r600_ih_ring_init(rdev, 64 * 1024);
1190
4aac0473
JG		 1191 r = r600_pcie_gart_init(rdev);
1192 if (r)
1193 return r;
1194
779720a3 1195 rdev->accel_working = true;
fc30b8ef 1196 r = rv770_startup(rdev);
3ce0a23d 1197 if (r) {
655efd3d 1198 dev_err(rdev->dev, "disabling GPU acceleration\n");
fe251e2f 1199 r700_cp_fini(rdev);
655efd3d 1200 r600_irq_fini(rdev);
724c80e1 1201 radeon_wb_fini(rdev);
655efd3d 1202 radeon_irq_kms_fini(rdev);
75c81298 1203 rv770_pcie_gart_fini(rdev);
733289c2 1204 rdev->accel_working = false;
3ce0a23d 1205 }
733289c2 1206 if (rdev->accel_working) {
733289c2
JG		 1207 r = radeon_ib_pool_init(rdev);
1208 if (r) {
db96380e 1209 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 1210 rdev->accel_working = false;
db96380e
JG		 1211 } else {
1212 r = r600_ib_test(rdev);
1213 if (r) {
1214 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1215 rdev->accel_working = false;
1216 }
733289c2 1217 }
3ce0a23d 1218 }
8a8c6e7c
RM		 1219
1220 r = r600_audio_init(rdev);
1221 if (r) {
1222 dev_err(rdev->dev, "radeon: audio init failed\n");
1223 return r;
1224 }
1225
3ce0a23d
JG		 1226 return 0;
1227}
1228
1229void rv770_fini(struct radeon_device *rdev)
1230{
1231 r600_blit_fini(rdev);
fe251e2f 1232 r700_cp_fini(rdev);
d8f60cfc 1233 r600_irq_fini(rdev);
724c80e1 1234 radeon_wb_fini(rdev);
d8f60cfc 1235 radeon_irq_kms_fini(rdev);
4aac0473 1236 rv770_pcie_gart_fini(rdev);
87cbf8f2 1237 rv770_vram_scratch_fini(rdev);
3ce0a23d
JG		 1238 radeon_gem_fini(rdev);
1239 radeon_fence_driver_fini(rdev);
d0269ed8 1240 radeon_agp_fini(rdev);
4c788679 1241 radeon_bo_fini(rdev);
e7d40b9a 1242 radeon_atombios_fini(rdev);
3ce0a23d
JG		 1243 kfree(rdev->bios);
1244 rdev->bios = NULL;
1245 radeon_dummy_page_fini(rdev);
771fe6b9 1246}
Clone of davem's net-next-2.6 tree