]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/radeon/rv770.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/r600: fix some issues with suspend/resume.
[net-next-2.6.git] / drivers / gpu / drm / radeon / rv770.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/firmware.h>
29#include <linux/platform_device.h>
771fe6b9 30#include "drmP.h"
771fe6b9 31#include "radeon.h"
3ce0a23d
JG		 32#include "rv770d.h"
33#include "avivod.h"
34#include "atom.h"
771fe6b9 35
3ce0a23d
JG		 36#define R700_PFP_UCODE_SIZE 848
37#define R700_PM4_UCODE_SIZE 1360
771fe6b9 38
3ce0a23d
JG		 39static void rv770_gpu_init(struct radeon_device *rdev);
40void rv770_fini(struct radeon_device *rdev);
771fe6b9
JG		 41
42
43/*
3ce0a23d 44 * GART
771fe6b9 45 */
3ce0a23d 46int rv770_pcie_gart_enable(struct radeon_device *rdev)
771fe6b9 47{
3ce0a23d
JG		 48 u32 tmp;
49 int r, i;
771fe6b9 50
4aac0473
JG		 51 if (rdev->gart.table.vram.robj == NULL) {
52 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
53 return -EINVAL;
3ce0a23d 54 }
4aac0473
JG		 55 r = radeon_gart_table_vram_pin(rdev);
56 if (r)
3ce0a23d 57 return r;
3ce0a23d
JG		 58 for (i = 0; i < rdev->gart.num_gpu_pages; i++)
59 r600_gart_clear_page(rdev, i);
60 /* Setup L2 cache */
61 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
62 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
63 EFFECTIVE_L2_QUEUE_SIZE(7));
64 WREG32(VM_L2_CNTL2, 0);
65 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
66 /* Setup TLB control */
67 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
68 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
69 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
70 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
71 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
72 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
73 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
74 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
75 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
76 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
77 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
78 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
79 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
80 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
81 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
82 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
83 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
84 (u32)(rdev->dummy_page.addr >> 12));
85 for (i = 1; i < 7; i++)
86 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 87
3ce0a23d
JG		 88 r600_pcie_gart_tlb_flush(rdev);
89 rdev->gart.ready = true;
771fe6b9
JG		 90 return 0;
91}
92
3ce0a23d 93void rv770_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 94{
3ce0a23d
JG		 95 u32 tmp;
96 int i;
97
3ce0a23d
JG		 98 /* Disable all tables */
99 for (i = 0; i < 7; i++)
100 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
101
102 /* Setup L2 cache */
103 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
104 EFFECTIVE_L2_QUEUE_SIZE(7));
105 WREG32(VM_L2_CNTL2, 0);
106 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
107 /* Setup TLB control */
108 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
109 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
110 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
111 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
112 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
113 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
114 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
115 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
4aac0473
JG		 116 if (rdev->gart.table.vram.robj) {
117 radeon_object_kunmap(rdev->gart.table.vram.robj);
118 radeon_object_unpin(rdev->gart.table.vram.robj);
119 }
120}
121
122void rv770_pcie_gart_fini(struct radeon_device *rdev)
123{
124 rv770_pcie_gart_disable(rdev);
125 radeon_gart_table_vram_free(rdev);
126 radeon_gart_fini(rdev);
771fe6b9
JG		 127}
128
129
130/*
3ce0a23d 131 * MC
771fe6b9 132 */
3ce0a23d 133static void rv770_mc_resume(struct radeon_device *rdev)
771fe6b9 134{
3ce0a23d
JG		 135 u32 d1vga_control, d2vga_control;
136 u32 vga_render_control, vga_hdp_control;
137 u32 d1crtc_control, d2crtc_control;
138 u32 new_d1grph_primary, new_d1grph_secondary;
139 u32 new_d2grph_primary, new_d2grph_secondary;
140 u64 old_vram_start;
141 u32 tmp;
142 int i, j;
143
144 /* Initialize HDP */
145 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
146 WREG32((0x2c14 + j), 0x00000000);
147 WREG32((0x2c18 + j), 0x00000000);
148 WREG32((0x2c1c + j), 0x00000000);
149 WREG32((0x2c20 + j), 0x00000000);
150 WREG32((0x2c24 + j), 0x00000000);
151 }
152 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
153
154 d1vga_control = RREG32(D1VGA_CONTROL);
155 d2vga_control = RREG32(D2VGA_CONTROL);
156 vga_render_control = RREG32(VGA_RENDER_CONTROL);
157 vga_hdp_control = RREG32(VGA_HDP_CONTROL);
158 d1crtc_control = RREG32(D1CRTC_CONTROL);
159 d2crtc_control = RREG32(D2CRTC_CONTROL);
160 old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
161 new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
162 new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
163 new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
164 new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
165 new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
166 new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
167 new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
168 new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
169
170 /* Stop all video */
171 WREG32(D1VGA_CONTROL, 0);
172 WREG32(D2VGA_CONTROL, 0);
173 WREG32(VGA_RENDER_CONTROL, 0);
174 WREG32(D1CRTC_UPDATE_LOCK, 1);
175 WREG32(D2CRTC_UPDATE_LOCK, 1);
176 WREG32(D1CRTC_CONTROL, 0);
177 WREG32(D2CRTC_CONTROL, 0);
178 WREG32(D1CRTC_UPDATE_LOCK, 0);
179 WREG32(D2CRTC_UPDATE_LOCK, 0);
180
181 mdelay(1);
182 if (r600_mc_wait_for_idle(rdev)) {
183 printk(KERN_WARNING "[drm] MC not idle !\n");
184 }
185
186 /* Lockout access through VGA aperture*/
187 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
188
189 /* Update configuration */
190 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
191 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
192 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
193 tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
194 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
195 WREG32(MC_VM_FB_LOCATION, tmp);
196 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
197 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
198 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
199 if (rdev->flags & RADEON_IS_AGP) {
200 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
201 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
202 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
203 } else {
204 WREG32(MC_VM_AGP_BASE, 0);
205 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
206 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
207 }
208 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
209 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
210 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
211 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
212 WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
213
214 /* Unlock host access */
215 WREG32(VGA_HDP_CONTROL, vga_hdp_control);
216
217 mdelay(1);
218 if (r600_mc_wait_for_idle(rdev)) {
219 printk(KERN_WARNING "[drm] MC not idle !\n");
220 }
221
222 /* Restore video state */
223 WREG32(D1CRTC_UPDATE_LOCK, 1);
224 WREG32(D2CRTC_UPDATE_LOCK, 1);
225 WREG32(D1CRTC_CONTROL, d1crtc_control);
226 WREG32(D2CRTC_CONTROL, d2crtc_control);
227 WREG32(D1CRTC_UPDATE_LOCK, 0);
228 WREG32(D2CRTC_UPDATE_LOCK, 0);
229 WREG32(D1VGA_CONTROL, d1vga_control);
230 WREG32(D2VGA_CONTROL, d2vga_control);
231 WREG32(VGA_RENDER_CONTROL, vga_render_control);
698443d9
DA		 232
233 /* we need to own VRAM, so turn off the VGA renderer here
234 * to stop it overwriting our objects */
235 radeon_avivo_vga_render_disable(rdev);
771fe6b9
JG		 236}
237
3ce0a23d
JG		 238
239/*
240 * CP.
241 */
242void r700_cp_stop(struct radeon_device *rdev)
771fe6b9 243{
3ce0a23d 244 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
771fe6b9
JG		 245}
246
3ce0a23d
JG		 247
248static int rv770_cp_load_microcode(struct radeon_device *rdev)
771fe6b9 249{
3ce0a23d
JG		 250 const __be32 *fw_data;
251 int i;
252
253 if (!rdev->me_fw || !rdev->pfp_fw)
254 return -EINVAL;
255
256 r700_cp_stop(rdev);
257 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
258
259 /* Reset cp */
260 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
261 RREG32(GRBM_SOFT_RESET);
262 mdelay(15);
263 WREG32(GRBM_SOFT_RESET, 0);
264
265 fw_data = (const __be32 *)rdev->pfp_fw->data;
266 WREG32(CP_PFP_UCODE_ADDR, 0);
267 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
268 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
269 WREG32(CP_PFP_UCODE_ADDR, 0);
270
271 fw_data = (const __be32 *)rdev->me_fw->data;
272 WREG32(CP_ME_RAM_WADDR, 0);
273 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
274 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
275
276 WREG32(CP_PFP_UCODE_ADDR, 0);
277 WREG32(CP_ME_RAM_WADDR, 0);
278 WREG32(CP_ME_RAM_RADDR, 0);
279 return 0;
771fe6b9
JG		 280}
281
282
283/*
3ce0a23d 284 * Core functions
771fe6b9 285 */
3ce0a23d
JG		 286static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
287 u32 num_backends,
288 u32 backend_disable_mask)
771fe6b9 289{
3ce0a23d
JG		 290 u32 backend_map = 0;
291 u32 enabled_backends_mask;
292 u32 enabled_backends_count;
293 u32 cur_pipe;
294 u32 swizzle_pipe[R7XX_MAX_PIPES];
295 u32 cur_backend;
296 u32 i;
297
298 if (num_tile_pipes > R7XX_MAX_PIPES)
299 num_tile_pipes = R7XX_MAX_PIPES;
300 if (num_tile_pipes < 1)
301 num_tile_pipes = 1;
302 if (num_backends > R7XX_MAX_BACKENDS)
303 num_backends = R7XX_MAX_BACKENDS;
304 if (num_backends < 1)
305 num_backends = 1;
306
307 enabled_backends_mask = 0;
308 enabled_backends_count = 0;
309 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
310 if (((backend_disable_mask >> i) & 1) == 0) {
311 enabled_backends_mask |= (1 << i);
312 ++enabled_backends_count;
313 }
314 if (enabled_backends_count == num_backends)
315 break;
316 }
317
318 if (enabled_backends_count == 0) {
319 enabled_backends_mask = 1;
320 enabled_backends_count = 1;
321 }
322
323 if (enabled_backends_count != num_backends)
324 num_backends = enabled_backends_count;
325
326 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
327 switch (num_tile_pipes) {
328 case 1:
329 swizzle_pipe[0] = 0;
330 break;
331 case 2:
332 swizzle_pipe[0] = 0;
333 swizzle_pipe[1] = 1;
334 break;
335 case 3:
336 swizzle_pipe[0] = 0;
337 swizzle_pipe[1] = 2;
338 swizzle_pipe[2] = 1;
339 break;
340 case 4:
341 swizzle_pipe[0] = 0;
342 swizzle_pipe[1] = 2;
343 swizzle_pipe[2] = 3;
344 swizzle_pipe[3] = 1;
345 break;
346 case 5:
347 swizzle_pipe[0] = 0;
348 swizzle_pipe[1] = 2;
349 swizzle_pipe[2] = 4;
350 swizzle_pipe[3] = 1;
351 swizzle_pipe[4] = 3;
352 break;
353 case 6:
354 swizzle_pipe[0] = 0;
355 swizzle_pipe[1] = 2;
356 swizzle_pipe[2] = 4;
357 swizzle_pipe[3] = 5;
358 swizzle_pipe[4] = 3;
359 swizzle_pipe[5] = 1;
360 break;
361 case 7:
362 swizzle_pipe[0] = 0;
363 swizzle_pipe[1] = 2;
364 swizzle_pipe[2] = 4;
365 swizzle_pipe[3] = 6;
366 swizzle_pipe[4] = 3;
367 swizzle_pipe[5] = 1;
368 swizzle_pipe[6] = 5;
369 break;
370 case 8:
371 swizzle_pipe[0] = 0;
372 swizzle_pipe[1] = 2;
373 swizzle_pipe[2] = 4;
374 swizzle_pipe[3] = 6;
375 swizzle_pipe[4] = 3;
376 swizzle_pipe[5] = 1;
377 swizzle_pipe[6] = 7;
378 swizzle_pipe[7] = 5;
379 break;
380 }
381
382 cur_backend = 0;
383 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
384 while (((1 << cur_backend) & enabled_backends_mask) == 0)
385 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
386
387 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
388
389 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
390 }
391
392 return backend_map;
771fe6b9
JG		 393}
394
3ce0a23d 395static void rv770_gpu_init(struct radeon_device *rdev)
771fe6b9 396{
3ce0a23d
JG		 397 int i, j, num_qd_pipes;
398 u32 sx_debug_1;
399 u32 smx_dc_ctl0;
400 u32 num_gs_verts_per_thread;
401 u32 vgt_gs_per_es;
402 u32 gs_prim_buffer_depth = 0;
403 u32 sq_ms_fifo_sizes;
404 u32 sq_config;
405 u32 sq_thread_resource_mgmt;
406 u32 hdp_host_path_cntl;
407 u32 sq_dyn_gpr_size_simd_ab_0;
408 u32 backend_map;
409 u32 gb_tiling_config = 0;
410 u32 cc_rb_backend_disable = 0;
411 u32 cc_gc_shader_pipe_config = 0;
412 u32 mc_arb_ramcfg;
413 u32 db_debug4;
771fe6b9 414
3ce0a23d
JG		 415 /* setup chip specs */
416 switch (rdev->family) {
417 case CHIP_RV770:
418 rdev->config.rv770.max_pipes = 4;
419 rdev->config.rv770.max_tile_pipes = 8;
420 rdev->config.rv770.max_simds = 10;
421 rdev->config.rv770.max_backends = 4;
422 rdev->config.rv770.max_gprs = 256;
423 rdev->config.rv770.max_threads = 248;
424 rdev->config.rv770.max_stack_entries = 512;
425 rdev->config.rv770.max_hw_contexts = 8;
426 rdev->config.rv770.max_gs_threads = 16 * 2;
427 rdev->config.rv770.sx_max_export_size = 128;
428 rdev->config.rv770.sx_max_export_pos_size = 16;
429 rdev->config.rv770.sx_max_export_smx_size = 112;
430 rdev->config.rv770.sq_num_cf_insts = 2;
431
432 rdev->config.rv770.sx_num_of_sets = 7;
433 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
434 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
435 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
436 break;
437 case CHIP_RV730:
438 rdev->config.rv770.max_pipes = 2;
439 rdev->config.rv770.max_tile_pipes = 4;
440 rdev->config.rv770.max_simds = 8;
441 rdev->config.rv770.max_backends = 2;
442 rdev->config.rv770.max_gprs = 128;
443 rdev->config.rv770.max_threads = 248;
444 rdev->config.rv770.max_stack_entries = 256;
445 rdev->config.rv770.max_hw_contexts = 8;
446 rdev->config.rv770.max_gs_threads = 16 * 2;
447 rdev->config.rv770.sx_max_export_size = 256;
448 rdev->config.rv770.sx_max_export_pos_size = 32;
449 rdev->config.rv770.sx_max_export_smx_size = 224;
450 rdev->config.rv770.sq_num_cf_insts = 2;
451
452 rdev->config.rv770.sx_num_of_sets = 7;
453 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
454 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
455 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
456 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
457 rdev->config.rv770.sx_max_export_pos_size -= 16;
458 rdev->config.rv770.sx_max_export_smx_size += 16;
459 }
460 break;
461 case CHIP_RV710:
462 rdev->config.rv770.max_pipes = 2;
463 rdev->config.rv770.max_tile_pipes = 2;
464 rdev->config.rv770.max_simds = 2;
465 rdev->config.rv770.max_backends = 1;
466 rdev->config.rv770.max_gprs = 256;
467 rdev->config.rv770.max_threads = 192;
468 rdev->config.rv770.max_stack_entries = 256;
469 rdev->config.rv770.max_hw_contexts = 4;
470 rdev->config.rv770.max_gs_threads = 8 * 2;
471 rdev->config.rv770.sx_max_export_size = 128;
472 rdev->config.rv770.sx_max_export_pos_size = 16;
473 rdev->config.rv770.sx_max_export_smx_size = 112;
474 rdev->config.rv770.sq_num_cf_insts = 1;
475
476 rdev->config.rv770.sx_num_of_sets = 7;
477 rdev->config.rv770.sc_prim_fifo_size = 0x40;
478 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
479 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
480 break;
481 case CHIP_RV740:
482 rdev->config.rv770.max_pipes = 4;
483 rdev->config.rv770.max_tile_pipes = 4;
484 rdev->config.rv770.max_simds = 8;
485 rdev->config.rv770.max_backends = 4;
486 rdev->config.rv770.max_gprs = 256;
487 rdev->config.rv770.max_threads = 248;
488 rdev->config.rv770.max_stack_entries = 512;
489 rdev->config.rv770.max_hw_contexts = 8;
490 rdev->config.rv770.max_gs_threads = 16 * 2;
491 rdev->config.rv770.sx_max_export_size = 256;
492 rdev->config.rv770.sx_max_export_pos_size = 32;
493 rdev->config.rv770.sx_max_export_smx_size = 224;
494 rdev->config.rv770.sq_num_cf_insts = 2;
495
496 rdev->config.rv770.sx_num_of_sets = 7;
497 rdev->config.rv770.sc_prim_fifo_size = 0x100;
498 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
499 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
500
501 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
502 rdev->config.rv770.sx_max_export_pos_size -= 16;
503 rdev->config.rv770.sx_max_export_smx_size += 16;
504 }
505 break;
506 default:
507 break;
508 }
509
510 /* Initialize HDP */
511 j = 0;
512 for (i = 0; i < 32; i++) {
513 WREG32((0x2c14 + j), 0x00000000);
514 WREG32((0x2c18 + j), 0x00000000);
515 WREG32((0x2c1c + j), 0x00000000);
516 WREG32((0x2c20 + j), 0x00000000);
517 WREG32((0x2c24 + j), 0x00000000);
518 j += 0x18;
519 }
520
521 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
522
523 /* setup tiling, simd, pipe config */
524 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
525
526 switch (rdev->config.rv770.max_tile_pipes) {
527 case 1:
528 gb_tiling_config |= PIPE_TILING(0);
529 break;
530 case 2:
531 gb_tiling_config |= PIPE_TILING(1);
532 break;
533 case 4:
534 gb_tiling_config |= PIPE_TILING(2);
535 break;
536 case 8:
537 gb_tiling_config |= PIPE_TILING(3);
538 break;
539 default:
540 break;
541 }
542
543 if (rdev->family == CHIP_RV770)
544 gb_tiling_config |= BANK_TILING(1);
545 else
546 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK);
547
548 gb_tiling_config |= GROUP_SIZE(0);
549
550 if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) {
551 gb_tiling_config |= ROW_TILING(3);
552 gb_tiling_config |= SAMPLE_SPLIT(3);
553 } else {
554 gb_tiling_config |=
555 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
556 gb_tiling_config |=
557 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
558 }
559
560 gb_tiling_config |= BANK_SWAPS(1);
561
562 backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
563 rdev->config.rv770.max_backends,
564 (0xff << rdev->config.rv770.max_backends) & 0xff);
565 gb_tiling_config |= BACKEND_MAP(backend_map);
566
567 cc_gc_shader_pipe_config =
568 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
569 cc_gc_shader_pipe_config |=
570 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
571
572 cc_rb_backend_disable =
573 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
574
575 WREG32(GB_TILING_CONFIG, gb_tiling_config);
576 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
577 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
578
579 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
580 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
581 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
582
583 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
584 WREG32(CGTS_SYS_TCC_DISABLE, 0);
585 WREG32(CGTS_TCC_DISABLE, 0);
586 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
587 WREG32(CGTS_USER_TCC_DISABLE, 0);
588
589 num_qd_pipes =
590 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
591 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
592 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
593
594 /* set HW defaults for 3D engine */
595 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
596 ROQ_IB2_START(0x2b)));
597
598 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
599
600 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
601 SYNC_GRADIENT |
602 SYNC_WALKER |
603 SYNC_ALIGNER));
604
605 sx_debug_1 = RREG32(SX_DEBUG_1);
606 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
607 WREG32(SX_DEBUG_1, sx_debug_1);
608
609 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
610 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
611 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
612 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
613
614 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
615 GS_FLUSH_CTL(4) |
616 ACK_FLUSH_CTL(3) |
617 SYNC_FLUSH_CTL));
618
619 if (rdev->family == CHIP_RV770)
620 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
621 else {
622 db_debug4 = RREG32(DB_DEBUG4);
623 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
624 WREG32(DB_DEBUG4, db_debug4);
625 }
626
627 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
628 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
629 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
630
631 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
632 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
633 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
634
635 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
636
637 WREG32(VGT_NUM_INSTANCES, 1);
638
639 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
640
641 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
642
643 WREG32(CP_PERFMON_CNTL, 0);
644
645 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
646 DONE_FIFO_HIWATER(0xe0) |
647 ALU_UPDATE_FIFO_HIWATER(0x8));
648 switch (rdev->family) {
649 case CHIP_RV770:
650 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
651 break;
652 case CHIP_RV730:
653 case CHIP_RV710:
654 case CHIP_RV740:
655 default:
656 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
657 break;
658 }
659 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
660
661 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
662 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
663 */
664 sq_config = RREG32(SQ_CONFIG);
665 sq_config &= ~(PS_PRIO(3) |
666 VS_PRIO(3) |
667 GS_PRIO(3) |
668 ES_PRIO(3));
669 sq_config |= (DX9_CONSTS |
670 VC_ENABLE |
671 EXPORT_SRC_C |
672 PS_PRIO(0) |
673 VS_PRIO(1) |
674 GS_PRIO(2) |
675 ES_PRIO(3));
676 if (rdev->family == CHIP_RV710)
677 /* no vertex cache */
678 sq_config &= ~VC_ENABLE;
679
680 WREG32(SQ_CONFIG, sq_config);
681
682 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
683 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
684 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
685
686 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
687 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
688
689 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
690 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
691 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
692 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
693 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
694 else
695 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
696 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
697
698 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
699 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
700
701 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
702 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
703
704 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
705 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
706 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
707 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
708
709 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
710 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
711 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
712 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
713 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
714 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
715 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
716 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
717
718 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
719 FORCE_EOV_MAX_REZ_CNT(255)));
720
721 if (rdev->family == CHIP_RV710)
722 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
723 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
724 else
725 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
726 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
727
728 switch (rdev->family) {
729 case CHIP_RV770:
730 case CHIP_RV730:
731 case CHIP_RV740:
732 gs_prim_buffer_depth = 384;
733 break;
734 case CHIP_RV710:
735 gs_prim_buffer_depth = 128;
736 break;
737 default:
738 break;
739 }
740
741 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
742 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
743 /* Max value for this is 256 */
744 if (vgt_gs_per_es > 256)
745 vgt_gs_per_es = 256;
746
747 WREG32(VGT_ES_PER_GS, 128);
748 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
749 WREG32(VGT_GS_PER_VS, 2);
750
751 /* more default values. 2D/3D driver should adjust as needed */
752 WREG32(VGT_GS_VERTEX_REUSE, 16);
753 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
754 WREG32(VGT_STRMOUT_EN, 0);
755 WREG32(SX_MISC, 0);
756 WREG32(PA_SC_MODE_CNTL, 0);
757 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
758 WREG32(PA_SC_AA_CONFIG, 0);
759 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
760 WREG32(PA_SC_LINE_STIPPLE, 0);
761 WREG32(SPI_INPUT_Z, 0);
762 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
763 WREG32(CB_COLOR7_FRAG, 0);
764
765 /* clear render buffer base addresses */
766 WREG32(CB_COLOR0_BASE, 0);
767 WREG32(CB_COLOR1_BASE, 0);
768 WREG32(CB_COLOR2_BASE, 0);
769 WREG32(CB_COLOR3_BASE, 0);
770 WREG32(CB_COLOR4_BASE, 0);
771 WREG32(CB_COLOR5_BASE, 0);
772 WREG32(CB_COLOR6_BASE, 0);
773 WREG32(CB_COLOR7_BASE, 0);
774
775 WREG32(TCP_CNTL, 0);
776
777 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
778 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
779
780 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
781
782 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
783 NUM_CLIP_SEQ(3)));
784
785}
786
787int rv770_mc_init(struct radeon_device *rdev)
788{
789 fixed20_12 a;
790 u32 tmp;
791 int r;
792
793 /* Get VRAM informations */
794 /* FIXME: Don't know how to determine vram width, need to check
795 * vram_width usage
796 */
797 rdev->mc.vram_width = 128;
798 rdev->mc.vram_is_ddr = true;
771fe6b9
JG		 799 /* Could aper size report 0 ? */
800 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
801 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
3ce0a23d
JG		 802 /* Setup GPU memory space */
803 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
804 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
805 if (rdev->flags & RADEON_IS_AGP) {
806 r = radeon_agp_init(rdev);
807 if (r)
808 return r;
809 /* gtt_size is setup by radeon_agp_init */
810 rdev->mc.gtt_location = rdev->mc.agp_base;
811 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
812 /* Try to put vram before or after AGP because we
813 * we want SYSTEM_APERTURE to cover both VRAM and
814 * AGP so that GPU can catch out of VRAM/AGP access
815 */
816 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
817 /* Enought place before */
818 rdev->mc.vram_location = rdev->mc.gtt_location -
819 rdev->mc.mc_vram_size;
820 } else if (tmp > rdev->mc.mc_vram_size) {
821 /* Enought place after */
822 rdev->mc.vram_location = rdev->mc.gtt_location +
823 rdev->mc.gtt_size;
824 } else {
825 /* Try to setup VRAM then AGP might not
826 * not work on some card
827 */
828 rdev->mc.vram_location = 0x00000000UL;
829 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
830 }
831 } else {
832 rdev->mc.vram_location = 0x00000000UL;
833 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
834 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
835 }
836 rdev->mc.vram_start = rdev->mc.vram_location;
837 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
838 rdev->mc.gtt_start = rdev->mc.gtt_location;
839 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
840 /* FIXME: we should enforce default clock in case GPU is not in
841 * default setup
842 */
843 a.full = rfixed_const(100);
844 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
845 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
846 return 0;
847}
848int rv770_gpu_reset(struct radeon_device *rdev)
849{
850 /* FIXME: implement */
851 return 0;
852}
853
854int rv770_resume(struct radeon_device *rdev)
855{
856 int r;
857
858 rv770_mc_resume(rdev);
859 r = rv770_pcie_gart_enable(rdev);
860 if (r)
861 return r;
862 rv770_gpu_init(rdev);
863 r = radeon_ring_init(rdev, rdev->cp.ring_size);
864 if (r)
865 return r;
866 r = rv770_cp_load_microcode(rdev);
867 if (r)
868 return r;
869 r = r600_cp_resume(rdev);
870 if (r)
871 return r;
872 r = r600_wb_init(rdev);
873 if (r)
874 return r;
875 return 0;
876}
877
878int rv770_suspend(struct radeon_device *rdev)
879{
880 /* FIXME: we should wait for ring to be empty */
881 r700_cp_stop(rdev);
4aac0473 882 rv770_pcie_gart_disable(rdev);
3ce0a23d
JG		 883 return 0;
884}
885
886/* Plan is to move initialization in that function and use
887 * helper function so that radeon_device_init pretty much
888 * do nothing more than calling asic specific function. This
889 * should also allow to remove a bunch of callback function
890 * like vram_info.
891 */
892int rv770_init(struct radeon_device *rdev)
893{
894 int r;
895
896 rdev->new_init_path = true;
897 r = radeon_dummy_page_init(rdev);
898 if (r)
899 return r;
900 /* This don't do much */
901 r = radeon_gem_init(rdev);
902 if (r)
903 return r;
904 /* Read BIOS */
905 if (!radeon_get_bios(rdev)) {
906 if (ASIC_IS_AVIVO(rdev))
907 return -EINVAL;
908 }
909 /* Must be an ATOMBIOS */
910 if (!rdev->is_atom_bios)
911 return -EINVAL;
912 r = radeon_atombios_init(rdev);
913 if (r)
914 return r;
915 /* Post card if necessary */
916 if (!r600_card_posted(rdev) && rdev->bios) {
917 DRM_INFO("GPU not posted. posting now...\n");
918 atom_asic_init(rdev->mode_info.atom_context);
919 }
920 /* Initialize scratch registers */
921 r600_scratch_init(rdev);
922 /* Initialize surface registers */
923 radeon_surface_init(rdev);
5e6dde7e 924 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 925 r = radeon_clocks_init(rdev);
926 if (r)
927 return r;
928 /* Fence driver */
929 r = radeon_fence_driver_init(rdev);
930 if (r)
931 return r;
932 r = rv770_mc_init(rdev);
933 if (r) {
934 if (rdev->flags & RADEON_IS_AGP) {
935 /* Retry with disabling AGP */
936 rv770_fini(rdev);
937 rdev->flags &= ~RADEON_IS_AGP;
938 return rv770_init(rdev);
939 }
940 return r;
941 }
942 /* Memory manager */
943 r = radeon_object_init(rdev);
944 if (r)
945 return r;
946 rdev->cp.ring_obj = NULL;
947 r600_ring_init(rdev, 1024 * 1024);
948
949 if (!rdev->me_fw || !rdev->pfp_fw) {
950 r = r600_cp_init_microcode(rdev);
951 if (r) {
952 DRM_ERROR("Failed to load firmware!\n");
953 return r;
954 }
955 }
956
4aac0473
JG		 957 r = r600_pcie_gart_init(rdev);
958 if (r)
959 return r;
960
733289c2 961 rdev->accel_working = true;
3ce0a23d
JG		 962 r = rv770_resume(rdev);
963 if (r) {
964 if (rdev->flags & RADEON_IS_AGP) {
965 /* Retry with disabling AGP */
966 rv770_fini(rdev);
967 rdev->flags &= ~RADEON_IS_AGP;
968 return rv770_init(rdev);
969 }
733289c2 970 rdev->accel_working = false;
3ce0a23d 971 }
733289c2
JG		 972 if (rdev->accel_working) {
973 r = r600_blit_init(rdev);
974 if (r) {
975 DRM_ERROR("radeon: failled blitter (%d).\n", r);
976 rdev->accel_working = false;
977 }
978 r = radeon_ib_pool_init(rdev);
979 if (r) {
980 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
981 rdev->accel_working = false;
982 }
983 r = radeon_ib_test(rdev);
984 if (r) {
985 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
986 rdev->accel_working = false;
987 }
3ce0a23d
JG		 988 }
989 return 0;
990}
991
992void rv770_fini(struct radeon_device *rdev)
993{
994 r600_blit_fini(rdev);
995 radeon_ring_fini(rdev);
4aac0473 996 rv770_pcie_gart_fini(rdev);
3ce0a23d
JG		 997 radeon_gem_fini(rdev);
998 radeon_fence_driver_fini(rdev);
999 radeon_clocks_fini(rdev);
1000#if __OS_HAS_AGP
1001 if (rdev->flags & RADEON_IS_AGP)
1002 radeon_agp_fini(rdev);
1003#endif
1004 radeon_object_fini(rdev);
1005 if (rdev->is_atom_bios) {
1006 radeon_atombios_fini(rdev);
1007 } else {
1008 radeon_combios_fini(rdev);
1009 }
1010 kfree(rdev->bios);
1011 rdev->bios = NULL;
1012 radeon_dummy_page_fini(rdev);
771fe6b9 1013}
Clone of davem's net-next-2.6 tree