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drm/radeon: fix a couple of array index errors
[net-next-2.6.git] / drivers / gpu / drm / radeon / rs690.c
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771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
771fe6b9 29#include "radeon.h"
c93bb85b 30#include "atom.h"
3bc68535 31#include "rs690d.h"
771fe6b9 32
3bc68535 33static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9
JG		 34{
35 unsigned i;
36 uint32_t tmp;
37
38 for (i = 0; i < rdev->usec_timeout; i++) {
39 /* read MC_STATUS */
3bc68535
JG		 40 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
41 if (G_000090_MC_SYSTEM_IDLE(tmp))
771fe6b9 42 return 0;
3bc68535 43 udelay(1);
771fe6b9
JG		 44 }
45 return -1;
46}
47
3bc68535 48static void rs690_gpu_init(struct radeon_device *rdev)
771fe6b9
JG		 49{
50 /* FIXME: HDP same place on rs690 ? */
51 r100_hdp_reset(rdev);
771fe6b9
JG		 52 /* FIXME: is this correct ? */
53 r420_pipes_init(rdev);
54 if (rs690_mc_wait_for_idle(rdev)) {
55 printk(KERN_WARNING "Failed to wait MC idle while "
56 "programming pipes. Bad things might happen.\n");
57 }
58}
59
c93bb85b
JG		 60void rs690_pm_info(struct radeon_device *rdev)
61{
62 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
63 struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
64 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
65 void *ptr;
66 uint16_t data_offset;
67 uint8_t frev, crev;
68 fixed20_12 tmp;
69
70 atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
71 &frev, &crev, &data_offset);
72 ptr = rdev->mode_info.atom_context->bios + data_offset;
73 info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
74 info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
75 /* Get various system informations from bios */
76 switch (crev) {
77 case 1:
78 tmp.full = rfixed_const(100);
79 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
80 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
81 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
82 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
83 rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
84 break;
85 case 2:
86 tmp.full = rfixed_const(100);
87 rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
88 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
89 rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
90 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
91 rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
92 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
93 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
94 break;
95 default:
96 tmp.full = rfixed_const(100);
97 /* We assume the slower possible clock ie worst case */
98 /* DDR 333Mhz */
99 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
100 /* FIXME: system clock ? */
101 rdev->pm.igp_system_mclk.full = rfixed_const(100);
102 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
103 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
104 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
105 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
106 break;
107 }
108 /* Compute various bandwidth */
109 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
110 tmp.full = rfixed_const(4);
111 rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
112 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
113 * = ht_clk * ht_width / 5
114 */
115 tmp.full = rfixed_const(5);
116 rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
117 rdev->pm.igp_ht_link_width);
118 rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
119 if (tmp.full < rdev->pm.max_bandwidth.full) {
120 /* HT link is a limiting factor */
121 rdev->pm.max_bandwidth.full = tmp.full;
122 }
123 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
124 * = (sideport_clk * 14) / 10
125 */
126 tmp.full = rfixed_const(14);
127 rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
128 tmp.full = rfixed_const(10);
129 rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
130}
131
771fe6b9
JG		 132void rs690_vram_info(struct radeon_device *rdev)
133{
c93bb85b 134 fixed20_12 a;
771fe6b9
JG		 135
136 rs400_gart_adjust_size(rdev);
0088dbdb 137
771fe6b9 138 rdev->mc.vram_is_ddr = true;
722f2943
AD		 139 rdev->mc.vram_width = 128;
140
7a50f01a
DA		 141 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
142 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 143
144 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
145 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
0088dbdb
AD		 146
147 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
148 rdev->mc.mc_vram_size = rdev->mc.aper_size;
149
150 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
151 rdev->mc.real_vram_size = rdev->mc.aper_size;
152
c93bb85b
JG		 153 rs690_pm_info(rdev);
154 /* FIXME: we should enforce default clock in case GPU is not in
155 * default setup
156 */
157 a.full = rfixed_const(100);
158 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
159 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
160 a.full = rfixed_const(16);
161 /* core_bandwidth = sclk(Mhz) * 16 */
162 rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
163}
164
22dd5013
AD		 165static int rs690_mc_init(struct radeon_device *rdev)
166{
167 int r;
168 u32 tmp;
169
170 /* Setup GPU memory space */
171 tmp = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
172 rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
173 rdev->mc.gtt_location = 0xFFFFFFFFUL;
174 r = radeon_mc_setup(rdev);
175 if (r)
176 return r;
177 return 0;
178}
179
c93bb85b
JG		 180void rs690_line_buffer_adjust(struct radeon_device *rdev,
181 struct drm_display_mode *mode1,
182 struct drm_display_mode *mode2)
183{
184 u32 tmp;
185
186 /*
187 * Line Buffer Setup
188 * There is a single line buffer shared by both display controllers.
3bc68535 189 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
c93bb85b
JG		 190 * the display controllers. The paritioning can either be done
191 * manually or via one of four preset allocations specified in bits 1:0:
192 * 0 - line buffer is divided in half and shared between crtc
193 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
194 * 2 - D1 gets the whole buffer
195 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
3bc68535 196 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
c93bb85b
JG		 197 * allocation mode. In manual allocation mode, D1 always starts at 0,
198 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
199 */
3bc68535
JG		 200 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
201 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
c93bb85b
JG		 202 /* auto */
203 if (mode1 && mode2) {
204 if (mode1->hdisplay > mode2->hdisplay) {
205 if (mode1->hdisplay > 2560)
3bc68535 206 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
c93bb85b 207 else
3bc68535 208 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b
JG		 209 } else if (mode2->hdisplay > mode1->hdisplay) {
210 if (mode2->hdisplay > 2560)
3bc68535 211 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
c93bb85b 212 else
3bc68535 213 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b 214 } else
3bc68535 215 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b 216 } else if (mode1) {
3bc68535 217 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
c93bb85b 218 } else if (mode2) {
3bc68535 219 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
c93bb85b 220 }
3bc68535 221 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
771fe6b9
JG		 222}
223
c93bb85b
JG		 224struct rs690_watermark {
225 u32 lb_request_fifo_depth;
226 fixed20_12 num_line_pair;
227 fixed20_12 estimated_width;
228 fixed20_12 worst_case_latency;
229 fixed20_12 consumption_rate;
230 fixed20_12 active_time;
231 fixed20_12 dbpp;
232 fixed20_12 priority_mark_max;
233 fixed20_12 priority_mark;
234 fixed20_12 sclk;
235};
236
237void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
238 struct radeon_crtc *crtc,
239 struct rs690_watermark *wm)
240{
241 struct drm_display_mode *mode = &crtc->base.mode;
242 fixed20_12 a, b, c;
243 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
244 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
245 /* FIXME: detect IGP with sideport memory, i don't think there is any
246 * such product available
247 */
248 bool sideport = false;
249
250 if (!crtc->base.enabled) {
251 /* FIXME: wouldn't it better to set priority mark to maximum */
252 wm->lb_request_fifo_depth = 4;
253 return;
254 }
255
256 if (crtc->vsc.full > rfixed_const(2))
257 wm->num_line_pair.full = rfixed_const(2);
258 else
259 wm->num_line_pair.full = rfixed_const(1);
260
261 b.full = rfixed_const(mode->crtc_hdisplay);
262 c.full = rfixed_const(256);
69b3b5e5
AD		 263 a.full = rfixed_div(b, c);
264 request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
265 request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
c93bb85b
JG		 266 if (a.full < rfixed_const(4)) {
267 wm->lb_request_fifo_depth = 4;
268 } else {
269 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
270 }
271
272 /* Determine consumption rate
273 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
274 * vtaps = number of vertical taps,
275 * vsc = vertical scaling ratio, defined as source/destination
276 * hsc = horizontal scaling ration, defined as source/destination
277 */
278 a.full = rfixed_const(mode->clock);
279 b.full = rfixed_const(1000);
280 a.full = rfixed_div(a, b);
281 pclk.full = rfixed_div(b, a);
282 if (crtc->rmx_type != RMX_OFF) {
283 b.full = rfixed_const(2);
284 if (crtc->vsc.full > b.full)
285 b.full = crtc->vsc.full;
286 b.full = rfixed_mul(b, crtc->hsc);
287 c.full = rfixed_const(2);
288 b.full = rfixed_div(b, c);
289 consumption_time.full = rfixed_div(pclk, b);
290 } else {
291 consumption_time.full = pclk.full;
292 }
293 a.full = rfixed_const(1);
294 wm->consumption_rate.full = rfixed_div(a, consumption_time);
295
296
297 /* Determine line time
298 * LineTime = total time for one line of displayhtotal
299 * LineTime = total number of horizontal pixels
300 * pclk = pixel clock period(ns)
301 */
302 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
303 line_time.full = rfixed_mul(a, pclk);
304
305 /* Determine active time
306 * ActiveTime = time of active region of display within one line,
307 * hactive = total number of horizontal active pixels
308 * htotal = total number of horizontal pixels
309 */
310 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
311 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
312 wm->active_time.full = rfixed_mul(line_time, b);
313 wm->active_time.full = rfixed_div(wm->active_time, a);
314
315 /* Maximun bandwidth is the minimun bandwidth of all component */
316 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
317 if (sideport) {
318 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
319 rdev->pm.sideport_bandwidth.full)
320 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
321 read_delay_latency.full = rfixed_const(370 * 800 * 1000);
322 read_delay_latency.full = rfixed_div(read_delay_latency,
323 rdev->pm.igp_sideport_mclk);
324 } else {
325 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
326 rdev->pm.k8_bandwidth.full)
327 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
328 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
329 rdev->pm.ht_bandwidth.full)
330 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
331 read_delay_latency.full = rfixed_const(5000);
332 }
333
334 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
335 a.full = rfixed_const(16);
336 rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
337 a.full = rfixed_const(1000);
338 rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
339 /* Determine chunk time
340 * ChunkTime = the time it takes the DCP to send one chunk of data
341 * to the LB which consists of pipeline delay and inter chunk gap
342 * sclk = system clock(ns)
343 */
344 a.full = rfixed_const(256 * 13);
345 chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
346 a.full = rfixed_const(10);
347 chunk_time.full = rfixed_div(chunk_time, a);
348
349 /* Determine the worst case latency
350 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
351 * WorstCaseLatency = worst case time from urgent to when the MC starts
352 * to return data
353 * READ_DELAY_IDLE_MAX = constant of 1us
354 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
355 * which consists of pipeline delay and inter chunk gap
356 */
357 if (rfixed_trunc(wm->num_line_pair) > 1) {
358 a.full = rfixed_const(3);
359 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
360 wm->worst_case_latency.full += read_delay_latency.full;
361 } else {
362 a.full = rfixed_const(2);
363 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
364 wm->worst_case_latency.full += read_delay_latency.full;
365 }
366
367 /* Determine the tolerable latency
368 * TolerableLatency = Any given request has only 1 line time
369 * for the data to be returned
370 * LBRequestFifoDepth = Number of chunk requests the LB can
371 * put into the request FIFO for a display
372 * LineTime = total time for one line of display
373 * ChunkTime = the time it takes the DCP to send one chunk
374 * of data to the LB which consists of
375 * pipeline delay and inter chunk gap
376 */
377 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
378 tolerable_latency.full = line_time.full;
379 } else {
380 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
381 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
382 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
383 tolerable_latency.full = line_time.full - tolerable_latency.full;
384 }
385 /* We assume worst case 32bits (4 bytes) */
386 wm->dbpp.full = rfixed_const(4 * 8);
387
388 /* Determine the maximum priority mark
389 * width = viewport width in pixels
390 */
391 a.full = rfixed_const(16);
392 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
393 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
69b3b5e5 394 wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
c93bb85b
JG		 395
396 /* Determine estimated width */
397 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
398 estimated_width.full = rfixed_div(estimated_width, consumption_time);
399 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
400 wm->priority_mark.full = rfixed_const(10);
401 } else {
402 a.full = rfixed_const(16);
403 wm->priority_mark.full = rfixed_div(estimated_width, a);
69b3b5e5 404 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
c93bb85b
JG		 405 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
406 }
407}
408
409void rs690_bandwidth_update(struct radeon_device *rdev)
410{
411 struct drm_display_mode *mode0 = NULL;
412 struct drm_display_mode *mode1 = NULL;
413 struct rs690_watermark wm0;
414 struct rs690_watermark wm1;
415 u32 tmp;
416 fixed20_12 priority_mark02, priority_mark12, fill_rate;
417 fixed20_12 a, b;
418
419 if (rdev->mode_info.crtcs[0]->base.enabled)
420 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
421 if (rdev->mode_info.crtcs[1]->base.enabled)
422 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
423 /*
424 * Set display0/1 priority up in the memory controller for
425 * modes if the user specifies HIGH for displaypriority
426 * option.
427 */
428 if (rdev->disp_priority == 2) {
3bc68535
JG		 429 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
430 tmp &= C_000104_MC_DISP0R_INIT_LAT;
431 tmp &= C_000104_MC_DISP1R_INIT_LAT;
c93bb85b 432 if (mode0)
3bc68535
JG		 433 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
434 if (mode1)
435 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
436 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
c93bb85b
JG		 437 }
438 rs690_line_buffer_adjust(rdev, mode0, mode1);
439
440 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
3bc68535 441 WREG32(R_006C9C_DCP_CONTROL, 0);
c93bb85b 442 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
3bc68535 443 WREG32(R_006C9C_DCP_CONTROL, 2);
c93bb85b
JG		 444
445 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
446 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
447
448 tmp = (wm0.lb_request_fifo_depth - 1);
449 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
3bc68535 450 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
c93bb85b
JG		 451
452 if (mode0 && mode1) {
453 if (rfixed_trunc(wm0.dbpp) > 64)
454 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
455 else
456 a.full = wm0.num_line_pair.full;
457 if (rfixed_trunc(wm1.dbpp) > 64)
458 b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
459 else
460 b.full = wm1.num_line_pair.full;
461 a.full += b.full;
462 fill_rate.full = rfixed_div(wm0.sclk, a);
463 if (wm0.consumption_rate.full > fill_rate.full) {
464 b.full = wm0.consumption_rate.full - fill_rate.full;
465 b.full = rfixed_mul(b, wm0.active_time);
466 a.full = rfixed_mul(wm0.worst_case_latency,
467 wm0.consumption_rate);
468 a.full = a.full + b.full;
469 b.full = rfixed_const(16 * 1000);
470 priority_mark02.full = rfixed_div(a, b);
471 } else {
472 a.full = rfixed_mul(wm0.worst_case_latency,
473 wm0.consumption_rate);
474 b.full = rfixed_const(16 * 1000);
475 priority_mark02.full = rfixed_div(a, b);
476 }
477 if (wm1.consumption_rate.full > fill_rate.full) {
478 b.full = wm1.consumption_rate.full - fill_rate.full;
479 b.full = rfixed_mul(b, wm1.active_time);
480 a.full = rfixed_mul(wm1.worst_case_latency,
481 wm1.consumption_rate);
482 a.full = a.full + b.full;
483 b.full = rfixed_const(16 * 1000);
484 priority_mark12.full = rfixed_div(a, b);
485 } else {
486 a.full = rfixed_mul(wm1.worst_case_latency,
487 wm1.consumption_rate);
488 b.full = rfixed_const(16 * 1000);
489 priority_mark12.full = rfixed_div(a, b);
490 }
491 if (wm0.priority_mark.full > priority_mark02.full)
492 priority_mark02.full = wm0.priority_mark.full;
493 if (rfixed_trunc(priority_mark02) < 0)
494 priority_mark02.full = 0;
495 if (wm0.priority_mark_max.full > priority_mark02.full)
496 priority_mark02.full = wm0.priority_mark_max.full;
497 if (wm1.priority_mark.full > priority_mark12.full)
498 priority_mark12.full = wm1.priority_mark.full;
499 if (rfixed_trunc(priority_mark12) < 0)
500 priority_mark12.full = 0;
501 if (wm1.priority_mark_max.full > priority_mark12.full)
502 priority_mark12.full = wm1.priority_mark_max.full;
3bc68535
JG		 503 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
504 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
505 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
506 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
c93bb85b
JG		 507 } else if (mode0) {
508 if (rfixed_trunc(wm0.dbpp) > 64)
509 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
510 else
511 a.full = wm0.num_line_pair.full;
512 fill_rate.full = rfixed_div(wm0.sclk, a);
513 if (wm0.consumption_rate.full > fill_rate.full) {
514 b.full = wm0.consumption_rate.full - fill_rate.full;
515 b.full = rfixed_mul(b, wm0.active_time);
516 a.full = rfixed_mul(wm0.worst_case_latency,
517 wm0.consumption_rate);
518 a.full = a.full + b.full;
519 b.full = rfixed_const(16 * 1000);
520 priority_mark02.full = rfixed_div(a, b);
521 } else {
522 a.full = rfixed_mul(wm0.worst_case_latency,
523 wm0.consumption_rate);
524 b.full = rfixed_const(16 * 1000);
525 priority_mark02.full = rfixed_div(a, b);
526 }
527 if (wm0.priority_mark.full > priority_mark02.full)
528 priority_mark02.full = wm0.priority_mark.full;
529 if (rfixed_trunc(priority_mark02) < 0)
530 priority_mark02.full = 0;
531 if (wm0.priority_mark_max.full > priority_mark02.full)
532 priority_mark02.full = wm0.priority_mark_max.full;
3bc68535
JG		 533 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
534 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
535 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
536 S_006D48_D2MODE_PRIORITY_A_OFF(1));
537 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
538 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
c93bb85b
JG		 539 } else {
540 if (rfixed_trunc(wm1.dbpp) > 64)
541 a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
542 else
543 a.full = wm1.num_line_pair.full;
544 fill_rate.full = rfixed_div(wm1.sclk, a);
545 if (wm1.consumption_rate.full > fill_rate.full) {
546 b.full = wm1.consumption_rate.full - fill_rate.full;
547 b.full = rfixed_mul(b, wm1.active_time);
548 a.full = rfixed_mul(wm1.worst_case_latency,
549 wm1.consumption_rate);
550 a.full = a.full + b.full;
551 b.full = rfixed_const(16 * 1000);
552 priority_mark12.full = rfixed_div(a, b);
553 } else {
554 a.full = rfixed_mul(wm1.worst_case_latency,
555 wm1.consumption_rate);
556 b.full = rfixed_const(16 * 1000);
557 priority_mark12.full = rfixed_div(a, b);
558 }
559 if (wm1.priority_mark.full > priority_mark12.full)
560 priority_mark12.full = wm1.priority_mark.full;
561 if (rfixed_trunc(priority_mark12) < 0)
562 priority_mark12.full = 0;
563 if (wm1.priority_mark_max.full > priority_mark12.full)
564 priority_mark12.full = wm1.priority_mark_max.full;
3bc68535
JG		 565 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
566 S_006548_D1MODE_PRIORITY_A_OFF(1));
567 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
568 S_00654C_D1MODE_PRIORITY_B_OFF(1));
569 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
570 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
c93bb85b
JG		 571 }
572}
771fe6b9 573
771fe6b9
JG		 574uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
575{
576 uint32_t r;
577
3bc68535
JG		 578 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
579 r = RREG32(R_00007C_MC_DATA);
580 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
771fe6b9
JG		 581 return r;
582}
583
584void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
585{
3bc68535
JG		 586 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
587 S_000078_MC_IND_WR_EN(1));
588 WREG32(R_00007C_MC_DATA, v);
589 WREG32(R_000078_MC_INDEX, 0x7F);
590}
591
592void rs690_mc_program(struct radeon_device *rdev)
593{
594 struct rv515_mc_save save;
595
596 /* Stops all mc clients */
597 rv515_mc_stop(rdev, &save);
598
599 /* Wait for mc idle */
600 if (rs690_mc_wait_for_idle(rdev))
601 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
602 /* Program MC, should be a 32bits limited address space */
603 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
604 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
605 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
606 WREG32(R_000134_HDP_FB_LOCATION,
607 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
608
609 rv515_mc_resume(rdev, &save);
610}
611
612static int rs690_startup(struct radeon_device *rdev)
613{
614 int r;
615
616 rs690_mc_program(rdev);
617 /* Resume clock */
618 rv515_clock_startup(rdev);
619 /* Initialize GPU configuration (# pipes, ...) */
620 rs690_gpu_init(rdev);
621 /* Initialize GART (initialize after TTM so we can allocate
622 * memory through TTM but finalize after TTM) */
623 r = rs400_gart_enable(rdev);
624 if (r)
625 return r;
626 /* Enable IRQ */
ac447df4 627 rs600_irq_set(rdev);
3bc68535
JG		 628 /* 1M ring buffer */
629 r = r100_cp_init(rdev, 1024 * 1024);
630 if (r) {
631 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
632 return r;
633 }
634 r = r100_wb_init(rdev);
635 if (r)
636 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
637 r = r100_ib_init(rdev);
638 if (r) {
639 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
640 return r;
641 }
642 return 0;
643}
644
645int rs690_resume(struct radeon_device *rdev)
646{
647 /* Make sur GART are not working */
648 rs400_gart_disable(rdev);
649 /* Resume clock before doing reset */
650 rv515_clock_startup(rdev);
651 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
652 if (radeon_gpu_reset(rdev)) {
653 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
654 RREG32(R_000E40_RBBM_STATUS),
655 RREG32(R_0007C0_CP_STAT));
656 }
657 /* post */
658 atom_asic_init(rdev->mode_info.atom_context);
659 /* Resume clock after posting */
660 rv515_clock_startup(rdev);
550e2d92
DA		 661 /* Initialize surface registers */
662 radeon_surface_init(rdev);
3bc68535
JG		 663 return rs690_startup(rdev);
664}
665
666int rs690_suspend(struct radeon_device *rdev)
667{
668 r100_cp_disable(rdev);
669 r100_wb_disable(rdev);
ac447df4 670 rs600_irq_disable(rdev);
3bc68535
JG		 671 rs400_gart_disable(rdev);
672 return 0;
673}
674
675void rs690_fini(struct radeon_device *rdev)
676{
677 rs690_suspend(rdev);
678 r100_cp_fini(rdev);
679 r100_wb_fini(rdev);
680 r100_ib_fini(rdev);
681 radeon_gem_fini(rdev);
682 rs400_gart_fini(rdev);
683 radeon_irq_kms_fini(rdev);
684 radeon_fence_driver_fini(rdev);
4c788679 685 radeon_bo_fini(rdev);
3bc68535
JG		 686 radeon_atombios_fini(rdev);
687 kfree(rdev->bios);
688 rdev->bios = NULL;
689}
690
691int rs690_init(struct radeon_device *rdev)
692{
693 int r;
694
3bc68535
JG		 695 /* Disable VGA */
696 rv515_vga_render_disable(rdev);
697 /* Initialize scratch registers */
698 radeon_scratch_init(rdev);
699 /* Initialize surface registers */
700 radeon_surface_init(rdev);
701 /* TODO: disable VGA need to use VGA request */
702 /* BIOS*/
703 if (!radeon_get_bios(rdev)) {
704 if (ASIC_IS_AVIVO(rdev))
705 return -EINVAL;
706 }
707 if (rdev->is_atom_bios) {
708 r = radeon_atombios_init(rdev);
709 if (r)
710 return r;
711 } else {
712 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
713 return -EINVAL;
714 }
715 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
716 if (radeon_gpu_reset(rdev)) {
717 dev_warn(rdev->dev,
718 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
719 RREG32(R_000E40_RBBM_STATUS),
720 RREG32(R_0007C0_CP_STAT));
721 }
722 /* check if cards are posted or not */
72542d77
DA		 723 if (radeon_boot_test_post_card(rdev) == false)
724 return -EINVAL;
725
3bc68535
JG		 726 /* Initialize clocks */
727 radeon_get_clock_info(rdev->ddev);
7433874e
RM		 728 /* Initialize power management */
729 radeon_pm_init(rdev);
3bc68535
JG		 730 /* Get vram informations */
731 rs690_vram_info(rdev);
732 /* Initialize memory controller (also test AGP) */
22dd5013 733 r = rs690_mc_init(rdev);
3bc68535
JG		 734 if (r)
735 return r;
736 rv515_debugfs(rdev);
737 /* Fence driver */
738 r = radeon_fence_driver_init(rdev);
739 if (r)
740 return r;
741 r = radeon_irq_kms_init(rdev);
742 if (r)
743 return r;
744 /* Memory manager */
4c788679 745 r = radeon_bo_init(rdev);
3bc68535
JG		 746 if (r)
747 return r;
748 r = rs400_gart_init(rdev);
749 if (r)
750 return r;
751 rs600_set_safe_registers(rdev);
752 rdev->accel_working = true;
753 r = rs690_startup(rdev);
754 if (r) {
755 /* Somethings want wront with the accel init stop accel */
756 dev_err(rdev->dev, "Disabling GPU acceleration\n");
757 rs690_suspend(rdev);
758 r100_cp_fini(rdev);
759 r100_wb_fini(rdev);
760 r100_ib_fini(rdev);
761 rs400_gart_fini(rdev);
762 radeon_irq_kms_fini(rdev);
763 rdev->accel_working = false;
764 }
765 return 0;
771fe6b9 766}
Clone of davem's net-next-2.6 tree