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drm/radeon/kms: fix gtt MC base alignment on rs4xx/rs690/rs740 asics
[net-next-2.6.git] / drivers / gpu / drm / radeon / rs690.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
771fe6b9 29#include "radeon.h"
e6990375 30#include "radeon_asic.h"
c93bb85b 31#include "atom.h"
3bc68535 32#include "rs690d.h"
771fe6b9 33
3bc68535 34static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9
JG		 35{
36 unsigned i;
37 uint32_t tmp;
38
39 for (i = 0; i < rdev->usec_timeout; i++) {
40 /* read MC_STATUS */
3bc68535
JG		 41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
771fe6b9 43 return 0;
3bc68535 44 udelay(1);
771fe6b9
JG		 45 }
46 return -1;
47}
48
3bc68535 49static void rs690_gpu_init(struct radeon_device *rdev)
771fe6b9 50{
771fe6b9
JG		 51 /* FIXME: is this correct ? */
52 r420_pipes_init(rdev);
53 if (rs690_mc_wait_for_idle(rdev)) {
54 printk(KERN_WARNING "Failed to wait MC idle while "
55 "programming pipes. Bad things might happen.\n");
56 }
57}
58
a084e6ee
AD		 59union igp_info {
60 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
62};
63
c93bb85b
JG		 64void rs690_pm_info(struct radeon_device *rdev)
65{
66 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
a084e6ee 67 union igp_info *info;
c93bb85b
JG		 68 uint16_t data_offset;
69 uint8_t frev, crev;
70 fixed20_12 tmp;
71
a084e6ee
AD		 72 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73 &frev, &crev, &data_offset)) {
74 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
75
76 /* Get various system informations from bios */
77 switch (crev) {
78 case 1:
68adac5e
BS		 79 tmp.full = dfixed_const(100);
80 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock);
81 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
f892034a
AD		 82 if (info->info.usK8MemoryClock)
83 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
84 else if (rdev->clock.default_mclk) {
85 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
86 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
87 } else
88 rdev->pm.igp_system_mclk.full = dfixed_const(400);
68adac5e
BS		 89 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
90 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
a084e6ee
AD		 91 break;
92 case 2:
68adac5e
BS		 93 tmp.full = dfixed_const(100);
94 rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock);
95 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
f892034a
AD		 96 if (info->info_v2.ulBootUpUMAClock)
97 rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
98 else if (rdev->clock.default_mclk)
99 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
100 else
101 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
68adac5e
BS		 102 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
103 rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq);
104 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
105 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
a084e6ee
AD		 106 break;
107 default:
a084e6ee 108 /* We assume the slower possible clock ie worst case */
f892034a
AD		 109 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
110 rdev->pm.igp_system_mclk.full = dfixed_const(200);
111 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
68adac5e 112 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
a084e6ee
AD		 113 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
114 break;
115 }
116 } else {
c93bb85b 117 /* We assume the slower possible clock ie worst case */
f892034a
AD		 118 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
119 rdev->pm.igp_system_mclk.full = dfixed_const(200);
120 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
68adac5e 121 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
c93bb85b 122 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
c93bb85b
JG		 123 }
124 /* Compute various bandwidth */
125 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
68adac5e
BS		 126 tmp.full = dfixed_const(4);
127 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
c93bb85b
JG		 128 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
129 * = ht_clk * ht_width / 5
130 */
68adac5e
BS		 131 tmp.full = dfixed_const(5);
132 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
c93bb85b 133 rdev->pm.igp_ht_link_width);
68adac5e 134 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
c93bb85b
JG		 135 if (tmp.full < rdev->pm.max_bandwidth.full) {
136 /* HT link is a limiting factor */
137 rdev->pm.max_bandwidth.full = tmp.full;
138 }
139 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
140 * = (sideport_clk * 14) / 10
141 */
68adac5e
BS		 142 tmp.full = dfixed_const(14);
143 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
144 tmp.full = dfixed_const(10);
145 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
c93bb85b
JG		 146}
147
d594e46a 148void rs690_mc_init(struct radeon_device *rdev)
771fe6b9 149{
d594e46a 150 u64 base;
771fe6b9
JG		 151
152 rs400_gart_adjust_size(rdev);
771fe6b9 153 rdev->mc.vram_is_ddr = true;
722f2943 154 rdev->mc.vram_width = 128;
7a50f01a
DA		 155 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
156 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 157 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
158 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
51e5fcd3 159 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a
JG		 160 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
161 base = G_000100_MC_FB_START(base) << 16;
c93bb85b 162 rs690_pm_info(rdev);
06b6476d 163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
d594e46a 164 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 165 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
d594e46a 166 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 167 radeon_update_bandwidth_info(rdev);
22dd5013
AD		 168}
169
c93bb85b
JG		 170void rs690_line_buffer_adjust(struct radeon_device *rdev,
171 struct drm_display_mode *mode1,
172 struct drm_display_mode *mode2)
173{
174 u32 tmp;
175
176 /*
177 * Line Buffer Setup
178 * There is a single line buffer shared by both display controllers.
3bc68535 179 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
c93bb85b
JG		 180 * the display controllers. The paritioning can either be done
181 * manually or via one of four preset allocations specified in bits 1:0:
182 * 0 - line buffer is divided in half and shared between crtc
183 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
184 * 2 - D1 gets the whole buffer
185 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
3bc68535 186 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
c93bb85b
JG		 187 * allocation mode. In manual allocation mode, D1 always starts at 0,
188 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
189 */
3bc68535
JG		 190 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
191 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
c93bb85b
JG		 192 /* auto */
193 if (mode1 && mode2) {
194 if (mode1->hdisplay > mode2->hdisplay) {
195 if (mode1->hdisplay > 2560)
3bc68535 196 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
c93bb85b 197 else
3bc68535 198 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b
JG		 199 } else if (mode2->hdisplay > mode1->hdisplay) {
200 if (mode2->hdisplay > 2560)
3bc68535 201 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
c93bb85b 202 else
3bc68535 203 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b 204 } else
3bc68535 205 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b 206 } else if (mode1) {
3bc68535 207 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
c93bb85b 208 } else if (mode2) {
3bc68535 209 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
c93bb85b 210 }
3bc68535 211 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
771fe6b9
JG		 212}
213
c93bb85b
JG		 214struct rs690_watermark {
215 u32 lb_request_fifo_depth;
216 fixed20_12 num_line_pair;
217 fixed20_12 estimated_width;
218 fixed20_12 worst_case_latency;
219 fixed20_12 consumption_rate;
220 fixed20_12 active_time;
221 fixed20_12 dbpp;
222 fixed20_12 priority_mark_max;
223 fixed20_12 priority_mark;
224 fixed20_12 sclk;
225};
226
227void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
228 struct radeon_crtc *crtc,
229 struct rs690_watermark *wm)
230{
231 struct drm_display_mode *mode = &crtc->base.mode;
232 fixed20_12 a, b, c;
233 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
234 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
c93bb85b
JG		 235
236 if (!crtc->base.enabled) {
237 /* FIXME: wouldn't it better to set priority mark to maximum */
238 wm->lb_request_fifo_depth = 4;
239 return;
240 }
241
68adac5e
BS		 242 if (crtc->vsc.full > dfixed_const(2))
243 wm->num_line_pair.full = dfixed_const(2);
c93bb85b 244 else
68adac5e
BS		 245 wm->num_line_pair.full = dfixed_const(1);
246
247 b.full = dfixed_const(mode->crtc_hdisplay);
248 c.full = dfixed_const(256);
249 a.full = dfixed_div(b, c);
250 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
251 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
252 if (a.full < dfixed_const(4)) {
c93bb85b
JG		 253 wm->lb_request_fifo_depth = 4;
254 } else {
68adac5e 255 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
c93bb85b
JG		 256 }
257
258 /* Determine consumption rate
259 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
260 * vtaps = number of vertical taps,
261 * vsc = vertical scaling ratio, defined as source/destination
262 * hsc = horizontal scaling ration, defined as source/destination
263 */
68adac5e
BS		 264 a.full = dfixed_const(mode->clock);
265 b.full = dfixed_const(1000);
266 a.full = dfixed_div(a, b);
267 pclk.full = dfixed_div(b, a);
c93bb85b 268 if (crtc->rmx_type != RMX_OFF) {
68adac5e 269 b.full = dfixed_const(2);
c93bb85b
JG		 270 if (crtc->vsc.full > b.full)
271 b.full = crtc->vsc.full;
68adac5e
BS		 272 b.full = dfixed_mul(b, crtc->hsc);
273 c.full = dfixed_const(2);
274 b.full = dfixed_div(b, c);
275 consumption_time.full = dfixed_div(pclk, b);
c93bb85b
JG		 276 } else {
277 consumption_time.full = pclk.full;
278 }
68adac5e
BS		 279 a.full = dfixed_const(1);
280 wm->consumption_rate.full = dfixed_div(a, consumption_time);
c93bb85b
JG		 281
282
283 /* Determine line time
284 * LineTime = total time for one line of displayhtotal
285 * LineTime = total number of horizontal pixels
286 * pclk = pixel clock period(ns)
287 */
68adac5e
BS		 288 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
289 line_time.full = dfixed_mul(a, pclk);
c93bb85b
JG		 290
291 /* Determine active time
292 * ActiveTime = time of active region of display within one line,
293 * hactive = total number of horizontal active pixels
294 * htotal = total number of horizontal pixels
295 */
68adac5e
BS		 296 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
297 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
298 wm->active_time.full = dfixed_mul(line_time, b);
299 wm->active_time.full = dfixed_div(wm->active_time, a);
c93bb85b
JG		 300
301 /* Maximun bandwidth is the minimun bandwidth of all component */
302 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
0888e883 303 if (rdev->mc.igp_sideport_enabled) {
c93bb85b
JG		 304 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
305 rdev->pm.sideport_bandwidth.full)
306 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
68adac5e
BS		 307 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
308 read_delay_latency.full = dfixed_div(read_delay_latency,
c93bb85b
JG		 309 rdev->pm.igp_sideport_mclk);
310 } else {
311 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
312 rdev->pm.k8_bandwidth.full)
313 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
314 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
315 rdev->pm.ht_bandwidth.full)
316 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
68adac5e 317 read_delay_latency.full = dfixed_const(5000);
c93bb85b
JG		 318 }
319
320 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
68adac5e
BS		 321 a.full = dfixed_const(16);
322 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
323 a.full = dfixed_const(1000);
324 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
c93bb85b
JG		 325 /* Determine chunk time
326 * ChunkTime = the time it takes the DCP to send one chunk of data
327 * to the LB which consists of pipeline delay and inter chunk gap
328 * sclk = system clock(ns)
329 */
68adac5e
BS		 330 a.full = dfixed_const(256 * 13);
331 chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
332 a.full = dfixed_const(10);
333 chunk_time.full = dfixed_div(chunk_time, a);
c93bb85b
JG		 334
335 /* Determine the worst case latency
336 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
337 * WorstCaseLatency = worst case time from urgent to when the MC starts
338 * to return data
339 * READ_DELAY_IDLE_MAX = constant of 1us
340 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
341 * which consists of pipeline delay and inter chunk gap
342 */
68adac5e
BS		 343 if (dfixed_trunc(wm->num_line_pair) > 1) {
344 a.full = dfixed_const(3);
345 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
c93bb85b
JG		 346 wm->worst_case_latency.full += read_delay_latency.full;
347 } else {
68adac5e
BS		 348 a.full = dfixed_const(2);
349 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
c93bb85b
JG		 350 wm->worst_case_latency.full += read_delay_latency.full;
351 }
352
353 /* Determine the tolerable latency
354 * TolerableLatency = Any given request has only 1 line time
355 * for the data to be returned
356 * LBRequestFifoDepth = Number of chunk requests the LB can
357 * put into the request FIFO for a display
358 * LineTime = total time for one line of display
359 * ChunkTime = the time it takes the DCP to send one chunk
360 * of data to the LB which consists of
361 * pipeline delay and inter chunk gap
362 */
68adac5e 363 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
c93bb85b
JG		 364 tolerable_latency.full = line_time.full;
365 } else {
68adac5e 366 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
c93bb85b 367 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
68adac5e 368 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
c93bb85b
JG		 369 tolerable_latency.full = line_time.full - tolerable_latency.full;
370 }
371 /* We assume worst case 32bits (4 bytes) */
68adac5e 372 wm->dbpp.full = dfixed_const(4 * 8);
c93bb85b
JG		 373
374 /* Determine the maximum priority mark
375 * width = viewport width in pixels
376 */
68adac5e
BS		 377 a.full = dfixed_const(16);
378 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
379 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
380 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
c93bb85b
JG		 381
382 /* Determine estimated width */
383 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
68adac5e
BS		 384 estimated_width.full = dfixed_div(estimated_width, consumption_time);
385 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
386 wm->priority_mark.full = dfixed_const(10);
c93bb85b 387 } else {
68adac5e
BS		 388 a.full = dfixed_const(16);
389 wm->priority_mark.full = dfixed_div(estimated_width, a);
390 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
c93bb85b
JG		 391 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
392 }
393}
394
395void rs690_bandwidth_update(struct radeon_device *rdev)
396{
397 struct drm_display_mode *mode0 = NULL;
398 struct drm_display_mode *mode1 = NULL;
399 struct rs690_watermark wm0;
400 struct rs690_watermark wm1;
f46c0120 401 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
c93bb85b
JG		 402 fixed20_12 priority_mark02, priority_mark12, fill_rate;
403 fixed20_12 a, b;
404
f46c0120
AD		 405 radeon_update_display_priority(rdev);
406
c93bb85b
JG		 407 if (rdev->mode_info.crtcs[0]->base.enabled)
408 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
409 if (rdev->mode_info.crtcs[1]->base.enabled)
410 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
411 /*
412 * Set display0/1 priority up in the memory controller for
413 * modes if the user specifies HIGH for displaypriority
414 * option.
415 */
f46c0120
AD		 416 if ((rdev->disp_priority == 2) &&
417 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
3bc68535
JG		 418 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
419 tmp &= C_000104_MC_DISP0R_INIT_LAT;
420 tmp &= C_000104_MC_DISP1R_INIT_LAT;
c93bb85b 421 if (mode0)
3bc68535
JG		 422 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
423 if (mode1)
424 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
425 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
c93bb85b
JG		 426 }
427 rs690_line_buffer_adjust(rdev, mode0, mode1);
428
429 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
3bc68535 430 WREG32(R_006C9C_DCP_CONTROL, 0);
c93bb85b 431 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
3bc68535 432 WREG32(R_006C9C_DCP_CONTROL, 2);
c93bb85b
JG		 433
434 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
435 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
436
437 tmp = (wm0.lb_request_fifo_depth - 1);
438 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
3bc68535 439 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
c93bb85b
JG		 440
441 if (mode0 && mode1) {
68adac5e
BS		 442 if (dfixed_trunc(wm0.dbpp) > 64)
443 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
c93bb85b
JG		 444 else
445 a.full = wm0.num_line_pair.full;
68adac5e
BS		 446 if (dfixed_trunc(wm1.dbpp) > 64)
447 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
c93bb85b
JG		 448 else
449 b.full = wm1.num_line_pair.full;
450 a.full += b.full;
68adac5e 451 fill_rate.full = dfixed_div(wm0.sclk, a);
c93bb85b
JG		 452 if (wm0.consumption_rate.full > fill_rate.full) {
453 b.full = wm0.consumption_rate.full - fill_rate.full;
68adac5e
BS		 454 b.full = dfixed_mul(b, wm0.active_time);
455 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b
JG		 456 wm0.consumption_rate);
457 a.full = a.full + b.full;
68adac5e
BS		 458 b.full = dfixed_const(16 * 1000);
459 priority_mark02.full = dfixed_div(a, b);
c93bb85b 460 } else {
68adac5e 461 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b 462 wm0.consumption_rate);
68adac5e
BS		 463 b.full = dfixed_const(16 * 1000);
464 priority_mark02.full = dfixed_div(a, b);
c93bb85b
JG		 465 }
466 if (wm1.consumption_rate.full > fill_rate.full) {
467 b.full = wm1.consumption_rate.full - fill_rate.full;
68adac5e
BS		 468 b.full = dfixed_mul(b, wm1.active_time);
469 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b
JG		 470 wm1.consumption_rate);
471 a.full = a.full + b.full;
68adac5e
BS		 472 b.full = dfixed_const(16 * 1000);
473 priority_mark12.full = dfixed_div(a, b);
c93bb85b 474 } else {
68adac5e 475 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b 476 wm1.consumption_rate);
68adac5e
BS		 477 b.full = dfixed_const(16 * 1000);
478 priority_mark12.full = dfixed_div(a, b);
c93bb85b
JG		 479 }
480 if (wm0.priority_mark.full > priority_mark02.full)
481 priority_mark02.full = wm0.priority_mark.full;
68adac5e 482 if (dfixed_trunc(priority_mark02) < 0)
c93bb85b
JG		 483 priority_mark02.full = 0;
484 if (wm0.priority_mark_max.full > priority_mark02.full)
485 priority_mark02.full = wm0.priority_mark_max.full;
486 if (wm1.priority_mark.full > priority_mark12.full)
487 priority_mark12.full = wm1.priority_mark.full;
68adac5e 488 if (dfixed_trunc(priority_mark12) < 0)
c93bb85b
JG		 489 priority_mark12.full = 0;
490 if (wm1.priority_mark_max.full > priority_mark12.full)
491 priority_mark12.full = wm1.priority_mark_max.full;
68adac5e
BS		 492 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
493 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
f46c0120
AD		 494 if (rdev->disp_priority == 2) {
495 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
496 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
497 }
498 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
499 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
500 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
501 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
c93bb85b 502 } else if (mode0) {
68adac5e
BS		 503 if (dfixed_trunc(wm0.dbpp) > 64)
504 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
c93bb85b
JG		 505 else
506 a.full = wm0.num_line_pair.full;
68adac5e 507 fill_rate.full = dfixed_div(wm0.sclk, a);
c93bb85b
JG		 508 if (wm0.consumption_rate.full > fill_rate.full) {
509 b.full = wm0.consumption_rate.full - fill_rate.full;
68adac5e
BS		 510 b.full = dfixed_mul(b, wm0.active_time);
511 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b
JG		 512 wm0.consumption_rate);
513 a.full = a.full + b.full;
68adac5e
BS		 514 b.full = dfixed_const(16 * 1000);
515 priority_mark02.full = dfixed_div(a, b);
c93bb85b 516 } else {
68adac5e 517 a.full = dfixed_mul(wm0.worst_case_latency,
c93bb85b 518 wm0.consumption_rate);
68adac5e
BS		 519 b.full = dfixed_const(16 * 1000);
520 priority_mark02.full = dfixed_div(a, b);
c93bb85b
JG		 521 }
522 if (wm0.priority_mark.full > priority_mark02.full)
523 priority_mark02.full = wm0.priority_mark.full;
68adac5e 524 if (dfixed_trunc(priority_mark02) < 0)
c93bb85b
JG		 525 priority_mark02.full = 0;
526 if (wm0.priority_mark_max.full > priority_mark02.full)
527 priority_mark02.full = wm0.priority_mark_max.full;
68adac5e 528 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
f46c0120
AD		 529 if (rdev->disp_priority == 2)
530 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
531 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
532 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
3bc68535
JG		 533 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
534 S_006D48_D2MODE_PRIORITY_A_OFF(1));
535 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
536 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
c93bb85b 537 } else {
68adac5e
BS		 538 if (dfixed_trunc(wm1.dbpp) > 64)
539 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
c93bb85b
JG		 540 else
541 a.full = wm1.num_line_pair.full;
68adac5e 542 fill_rate.full = dfixed_div(wm1.sclk, a);
c93bb85b
JG		 543 if (wm1.consumption_rate.full > fill_rate.full) {
544 b.full = wm1.consumption_rate.full - fill_rate.full;
68adac5e
BS		 545 b.full = dfixed_mul(b, wm1.active_time);
546 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b
JG		 547 wm1.consumption_rate);
548 a.full = a.full + b.full;
68adac5e
BS		 549 b.full = dfixed_const(16 * 1000);
550 priority_mark12.full = dfixed_div(a, b);
c93bb85b 551 } else {
68adac5e 552 a.full = dfixed_mul(wm1.worst_case_latency,
c93bb85b 553 wm1.consumption_rate);
68adac5e
BS		 554 b.full = dfixed_const(16 * 1000);
555 priority_mark12.full = dfixed_div(a, b);
c93bb85b
JG		 556 }
557 if (wm1.priority_mark.full > priority_mark12.full)
558 priority_mark12.full = wm1.priority_mark.full;
68adac5e 559 if (dfixed_trunc(priority_mark12) < 0)
c93bb85b
JG		 560 priority_mark12.full = 0;
561 if (wm1.priority_mark_max.full > priority_mark12.full)
562 priority_mark12.full = wm1.priority_mark_max.full;
68adac5e 563 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
f46c0120
AD		 564 if (rdev->disp_priority == 2)
565 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
3bc68535
JG		 566 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
567 S_006548_D1MODE_PRIORITY_A_OFF(1));
568 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
569 S_00654C_D1MODE_PRIORITY_B_OFF(1));
f46c0120
AD		 570 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
571 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
c93bb85b
JG		 572 }
573}
771fe6b9 574
771fe6b9
JG		 575uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
576{
577 uint32_t r;
578
3bc68535
JG		 579 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
580 r = RREG32(R_00007C_MC_DATA);
581 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
771fe6b9
JG		 582 return r;
583}
584
585void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
586{
3bc68535
JG		 587 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
588 S_000078_MC_IND_WR_EN(1));
589 WREG32(R_00007C_MC_DATA, v);
590 WREG32(R_000078_MC_INDEX, 0x7F);
591}
592
593void rs690_mc_program(struct radeon_device *rdev)
594{
595 struct rv515_mc_save save;
596
597 /* Stops all mc clients */
598 rv515_mc_stop(rdev, &save);
599
600 /* Wait for mc idle */
601 if (rs690_mc_wait_for_idle(rdev))
602 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
603 /* Program MC, should be a 32bits limited address space */
604 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
605 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
606 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
607 WREG32(R_000134_HDP_FB_LOCATION,
608 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
609
610 rv515_mc_resume(rdev, &save);
611}
612
613static int rs690_startup(struct radeon_device *rdev)
614{
615 int r;
616
617 rs690_mc_program(rdev);
618 /* Resume clock */
619 rv515_clock_startup(rdev);
620 /* Initialize GPU configuration (# pipes, ...) */
621 rs690_gpu_init(rdev);
622 /* Initialize GART (initialize after TTM so we can allocate
623 * memory through TTM but finalize after TTM) */
624 r = rs400_gart_enable(rdev);
625 if (r)
626 return r;
627 /* Enable IRQ */
ac447df4 628 rs600_irq_set(rdev);
cafe6609 629 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3bc68535
JG		 630 /* 1M ring buffer */
631 r = r100_cp_init(rdev, 1024 * 1024);
632 if (r) {
633 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
634 return r;
635 }
636 r = r100_wb_init(rdev);
637 if (r)
638 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
639 r = r100_ib_init(rdev);
640 if (r) {
641 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
642 return r;
643 }
644 return 0;
645}
646
647int rs690_resume(struct radeon_device *rdev)
648{
649 /* Make sur GART are not working */
650 rs400_gart_disable(rdev);
651 /* Resume clock before doing reset */
652 rv515_clock_startup(rdev);
653 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 654 if (radeon_asic_reset(rdev)) {
3bc68535
JG		 655 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
656 RREG32(R_000E40_RBBM_STATUS),
657 RREG32(R_0007C0_CP_STAT));
658 }
659 /* post */
660 atom_asic_init(rdev->mode_info.atom_context);
661 /* Resume clock after posting */
662 rv515_clock_startup(rdev);
550e2d92
DA		 663 /* Initialize surface registers */
664 radeon_surface_init(rdev);
3bc68535
JG		 665 return rs690_startup(rdev);
666}
667
668int rs690_suspend(struct radeon_device *rdev)
669{
670 r100_cp_disable(rdev);
671 r100_wb_disable(rdev);
ac447df4 672 rs600_irq_disable(rdev);
3bc68535
JG		 673 rs400_gart_disable(rdev);
674 return 0;
675}
676
677void rs690_fini(struct radeon_device *rdev)
678{
3bc68535
JG		 679 r100_cp_fini(rdev);
680 r100_wb_fini(rdev);
681 r100_ib_fini(rdev);
682 radeon_gem_fini(rdev);
683 rs400_gart_fini(rdev);
684 radeon_irq_kms_fini(rdev);
685 radeon_fence_driver_fini(rdev);
4c788679 686 radeon_bo_fini(rdev);
3bc68535
JG		 687 radeon_atombios_fini(rdev);
688 kfree(rdev->bios);
689 rdev->bios = NULL;
690}
691
692int rs690_init(struct radeon_device *rdev)
693{
694 int r;
695
3bc68535
JG		 696 /* Disable VGA */
697 rv515_vga_render_disable(rdev);
698 /* Initialize scratch registers */
699 radeon_scratch_init(rdev);
700 /* Initialize surface registers */
701 radeon_surface_init(rdev);
702 /* TODO: disable VGA need to use VGA request */
703 /* BIOS*/
704 if (!radeon_get_bios(rdev)) {
705 if (ASIC_IS_AVIVO(rdev))
706 return -EINVAL;
707 }
708 if (rdev->is_atom_bios) {
709 r = radeon_atombios_init(rdev);
710 if (r)
711 return r;
712 } else {
713 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
714 return -EINVAL;
715 }
716 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 717 if (radeon_asic_reset(rdev)) {
3bc68535
JG		 718 dev_warn(rdev->dev,
719 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
720 RREG32(R_000E40_RBBM_STATUS),
721 RREG32(R_0007C0_CP_STAT));
722 }
723 /* check if cards are posted or not */
72542d77
DA		 724 if (radeon_boot_test_post_card(rdev) == false)
725 return -EINVAL;
726
3bc68535
JG		 727 /* Initialize clocks */
728 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 729 /* initialize memory controller */
730 rs690_mc_init(rdev);
3bc68535
JG		 731 rv515_debugfs(rdev);
732 /* Fence driver */
733 r = radeon_fence_driver_init(rdev);
734 if (r)
735 return r;
736 r = radeon_irq_kms_init(rdev);
737 if (r)
738 return r;
739 /* Memory manager */
4c788679 740 r = radeon_bo_init(rdev);
3bc68535
JG		 741 if (r)
742 return r;
743 r = rs400_gart_init(rdev);
744 if (r)
745 return r;
746 rs600_set_safe_registers(rdev);
747 rdev->accel_working = true;
748 r = rs690_startup(rdev);
749 if (r) {
750 /* Somethings want wront with the accel init stop accel */
751 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3bc68535
JG		 752 r100_cp_fini(rdev);
753 r100_wb_fini(rdev);
754 r100_ib_fini(rdev);
755 rs400_gart_fini(rdev);
756 radeon_irq_kms_fini(rdev);
757 rdev->accel_working = false;
758 }
759 return 0;
771fe6b9 760}
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