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drm/radeon/kms: fix return value from fence function.
[net-next-2.6.git] / drivers / gpu / drm / radeon / rs690.c
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771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
771fe6b9 29#include "radeon.h"
c93bb85b 30#include "atom.h"
3bc68535 31#include "rs690d.h"
771fe6b9 32
3bc68535 33static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9
JG		 34{
35 unsigned i;
36 uint32_t tmp;
37
38 for (i = 0; i < rdev->usec_timeout; i++) {
39 /* read MC_STATUS */
3bc68535
JG		 40 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
41 if (G_000090_MC_SYSTEM_IDLE(tmp))
771fe6b9 42 return 0;
3bc68535 43 udelay(1);
771fe6b9
JG		 44 }
45 return -1;
46}
47
3bc68535 48static void rs690_gpu_init(struct radeon_device *rdev)
771fe6b9
JG		 49{
50 /* FIXME: HDP same place on rs690 ? */
51 r100_hdp_reset(rdev);
771fe6b9
JG		 52 /* FIXME: is this correct ? */
53 r420_pipes_init(rdev);
54 if (rs690_mc_wait_for_idle(rdev)) {
55 printk(KERN_WARNING "Failed to wait MC idle while "
56 "programming pipes. Bad things might happen.\n");
57 }
58}
59
c93bb85b
JG		 60void rs690_pm_info(struct radeon_device *rdev)
61{
62 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
63 struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
64 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
65 void *ptr;
66 uint16_t data_offset;
67 uint8_t frev, crev;
68 fixed20_12 tmp;
69
70 atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
71 &frev, &crev, &data_offset);
72 ptr = rdev->mode_info.atom_context->bios + data_offset;
73 info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
74 info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
75 /* Get various system informations from bios */
76 switch (crev) {
77 case 1:
78 tmp.full = rfixed_const(100);
79 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
80 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
81 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
82 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
83 rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
84 break;
85 case 2:
86 tmp.full = rfixed_const(100);
87 rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
88 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
89 rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
90 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
91 rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
92 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
93 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
94 break;
95 default:
96 tmp.full = rfixed_const(100);
97 /* We assume the slower possible clock ie worst case */
98 /* DDR 333Mhz */
99 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
100 /* FIXME: system clock ? */
101 rdev->pm.igp_system_mclk.full = rfixed_const(100);
102 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
103 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
104 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
105 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
106 break;
107 }
108 /* Compute various bandwidth */
109 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
110 tmp.full = rfixed_const(4);
111 rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
112 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
113 * = ht_clk * ht_width / 5
114 */
115 tmp.full = rfixed_const(5);
116 rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
117 rdev->pm.igp_ht_link_width);
118 rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
119 if (tmp.full < rdev->pm.max_bandwidth.full) {
120 /* HT link is a limiting factor */
121 rdev->pm.max_bandwidth.full = tmp.full;
122 }
123 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
124 * = (sideport_clk * 14) / 10
125 */
126 tmp.full = rfixed_const(14);
127 rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
128 tmp.full = rfixed_const(10);
129 rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
130}
131
771fe6b9
JG		 132void rs690_vram_info(struct radeon_device *rdev)
133{
c93bb85b 134 fixed20_12 a;
771fe6b9
JG		 135
136 rs400_gart_adjust_size(rdev);
0088dbdb 137
771fe6b9 138 rdev->mc.vram_is_ddr = true;
722f2943
AD		 139 rdev->mc.vram_width = 128;
140
7a50f01a
DA		 141 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
142 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 143
144 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
145 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
0088dbdb
AD		 146
147 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
148 rdev->mc.mc_vram_size = rdev->mc.aper_size;
149
150 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
151 rdev->mc.real_vram_size = rdev->mc.aper_size;
152
c93bb85b
JG		 153 rs690_pm_info(rdev);
154 /* FIXME: we should enforce default clock in case GPU is not in
155 * default setup
156 */
157 a.full = rfixed_const(100);
158 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
159 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
160 a.full = rfixed_const(16);
161 /* core_bandwidth = sclk(Mhz) * 16 */
162 rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
163}
164
22dd5013
AD		 165static int rs690_mc_init(struct radeon_device *rdev)
166{
167 int r;
168 u32 tmp;
169
170 /* Setup GPU memory space */
171 tmp = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
172 rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
173 rdev->mc.gtt_location = 0xFFFFFFFFUL;
174 r = radeon_mc_setup(rdev);
175 if (r)
176 return r;
177 return 0;
178}
179
c93bb85b
JG		 180void rs690_line_buffer_adjust(struct radeon_device *rdev,
181 struct drm_display_mode *mode1,
182 struct drm_display_mode *mode2)
183{
184 u32 tmp;
185
186 /*
187 * Line Buffer Setup
188 * There is a single line buffer shared by both display controllers.
3bc68535 189 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
c93bb85b
JG		 190 * the display controllers. The paritioning can either be done
191 * manually or via one of four preset allocations specified in bits 1:0:
192 * 0 - line buffer is divided in half and shared between crtc
193 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
194 * 2 - D1 gets the whole buffer
195 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
3bc68535 196 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
c93bb85b
JG		 197 * allocation mode. In manual allocation mode, D1 always starts at 0,
198 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
199 */
3bc68535
JG		 200 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
201 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
c93bb85b
JG		 202 /* auto */
203 if (mode1 && mode2) {
204 if (mode1->hdisplay > mode2->hdisplay) {
205 if (mode1->hdisplay > 2560)
3bc68535 206 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
c93bb85b 207 else
3bc68535 208 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b
JG		 209 } else if (mode2->hdisplay > mode1->hdisplay) {
210 if (mode2->hdisplay > 2560)
3bc68535 211 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
c93bb85b 212 else
3bc68535 213 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b 214 } else
3bc68535 215 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b 216 } else if (mode1) {
3bc68535 217 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
c93bb85b 218 } else if (mode2) {
3bc68535 219 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
c93bb85b 220 }
3bc68535 221 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
771fe6b9
JG		 222}
223
c93bb85b
JG		 224struct rs690_watermark {
225 u32 lb_request_fifo_depth;
226 fixed20_12 num_line_pair;
227 fixed20_12 estimated_width;
228 fixed20_12 worst_case_latency;
229 fixed20_12 consumption_rate;
230 fixed20_12 active_time;
231 fixed20_12 dbpp;
232 fixed20_12 priority_mark_max;
233 fixed20_12 priority_mark;
234 fixed20_12 sclk;
235};
236
237void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
238 struct radeon_crtc *crtc,
239 struct rs690_watermark *wm)
240{
241 struct drm_display_mode *mode = &crtc->base.mode;
242 fixed20_12 a, b, c;
243 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
244 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
245 /* FIXME: detect IGP with sideport memory, i don't think there is any
246 * such product available
247 */
248 bool sideport = false;
249
250 if (!crtc->base.enabled) {
251 /* FIXME: wouldn't it better to set priority mark to maximum */
252 wm->lb_request_fifo_depth = 4;
253 return;
254 }
255
256 if (crtc->vsc.full > rfixed_const(2))
257 wm->num_line_pair.full = rfixed_const(2);
258 else
259 wm->num_line_pair.full = rfixed_const(1);
260
261 b.full = rfixed_const(mode->crtc_hdisplay);
262 c.full = rfixed_const(256);
263 a.full = rfixed_mul(wm->num_line_pair, b);
264 request_fifo_depth.full = rfixed_div(a, c);
265 if (a.full < rfixed_const(4)) {
266 wm->lb_request_fifo_depth = 4;
267 } else {
268 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
269 }
270
271 /* Determine consumption rate
272 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
273 * vtaps = number of vertical taps,
274 * vsc = vertical scaling ratio, defined as source/destination
275 * hsc = horizontal scaling ration, defined as source/destination
276 */
277 a.full = rfixed_const(mode->clock);
278 b.full = rfixed_const(1000);
279 a.full = rfixed_div(a, b);
280 pclk.full = rfixed_div(b, a);
281 if (crtc->rmx_type != RMX_OFF) {
282 b.full = rfixed_const(2);
283 if (crtc->vsc.full > b.full)
284 b.full = crtc->vsc.full;
285 b.full = rfixed_mul(b, crtc->hsc);
286 c.full = rfixed_const(2);
287 b.full = rfixed_div(b, c);
288 consumption_time.full = rfixed_div(pclk, b);
289 } else {
290 consumption_time.full = pclk.full;
291 }
292 a.full = rfixed_const(1);
293 wm->consumption_rate.full = rfixed_div(a, consumption_time);
294
295
296 /* Determine line time
297 * LineTime = total time for one line of displayhtotal
298 * LineTime = total number of horizontal pixels
299 * pclk = pixel clock period(ns)
300 */
301 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
302 line_time.full = rfixed_mul(a, pclk);
303
304 /* Determine active time
305 * ActiveTime = time of active region of display within one line,
306 * hactive = total number of horizontal active pixels
307 * htotal = total number of horizontal pixels
308 */
309 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
310 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
311 wm->active_time.full = rfixed_mul(line_time, b);
312 wm->active_time.full = rfixed_div(wm->active_time, a);
313
314 /* Maximun bandwidth is the minimun bandwidth of all component */
315 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
316 if (sideport) {
317 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
318 rdev->pm.sideport_bandwidth.full)
319 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
320 read_delay_latency.full = rfixed_const(370 * 800 * 1000);
321 read_delay_latency.full = rfixed_div(read_delay_latency,
322 rdev->pm.igp_sideport_mclk);
323 } else {
324 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
325 rdev->pm.k8_bandwidth.full)
326 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
327 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
328 rdev->pm.ht_bandwidth.full)
329 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
330 read_delay_latency.full = rfixed_const(5000);
331 }
332
333 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
334 a.full = rfixed_const(16);
335 rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
336 a.full = rfixed_const(1000);
337 rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
338 /* Determine chunk time
339 * ChunkTime = the time it takes the DCP to send one chunk of data
340 * to the LB which consists of pipeline delay and inter chunk gap
341 * sclk = system clock(ns)
342 */
343 a.full = rfixed_const(256 * 13);
344 chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
345 a.full = rfixed_const(10);
346 chunk_time.full = rfixed_div(chunk_time, a);
347
348 /* Determine the worst case latency
349 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
350 * WorstCaseLatency = worst case time from urgent to when the MC starts
351 * to return data
352 * READ_DELAY_IDLE_MAX = constant of 1us
353 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
354 * which consists of pipeline delay and inter chunk gap
355 */
356 if (rfixed_trunc(wm->num_line_pair) > 1) {
357 a.full = rfixed_const(3);
358 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
359 wm->worst_case_latency.full += read_delay_latency.full;
360 } else {
361 a.full = rfixed_const(2);
362 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
363 wm->worst_case_latency.full += read_delay_latency.full;
364 }
365
366 /* Determine the tolerable latency
367 * TolerableLatency = Any given request has only 1 line time
368 * for the data to be returned
369 * LBRequestFifoDepth = Number of chunk requests the LB can
370 * put into the request FIFO for a display
371 * LineTime = total time for one line of display
372 * ChunkTime = the time it takes the DCP to send one chunk
373 * of data to the LB which consists of
374 * pipeline delay and inter chunk gap
375 */
376 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
377 tolerable_latency.full = line_time.full;
378 } else {
379 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
380 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
381 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
382 tolerable_latency.full = line_time.full - tolerable_latency.full;
383 }
384 /* We assume worst case 32bits (4 bytes) */
385 wm->dbpp.full = rfixed_const(4 * 8);
386
387 /* Determine the maximum priority mark
388 * width = viewport width in pixels
389 */
390 a.full = rfixed_const(16);
391 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
392 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
393
394 /* Determine estimated width */
395 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
396 estimated_width.full = rfixed_div(estimated_width, consumption_time);
397 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
398 wm->priority_mark.full = rfixed_const(10);
399 } else {
400 a.full = rfixed_const(16);
401 wm->priority_mark.full = rfixed_div(estimated_width, a);
402 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
403 }
404}
405
406void rs690_bandwidth_update(struct radeon_device *rdev)
407{
408 struct drm_display_mode *mode0 = NULL;
409 struct drm_display_mode *mode1 = NULL;
410 struct rs690_watermark wm0;
411 struct rs690_watermark wm1;
412 u32 tmp;
413 fixed20_12 priority_mark02, priority_mark12, fill_rate;
414 fixed20_12 a, b;
415
416 if (rdev->mode_info.crtcs[0]->base.enabled)
417 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
418 if (rdev->mode_info.crtcs[1]->base.enabled)
419 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
420 /*
421 * Set display0/1 priority up in the memory controller for
422 * modes if the user specifies HIGH for displaypriority
423 * option.
424 */
425 if (rdev->disp_priority == 2) {
3bc68535
JG		 426 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
427 tmp &= C_000104_MC_DISP0R_INIT_LAT;
428 tmp &= C_000104_MC_DISP1R_INIT_LAT;
c93bb85b 429 if (mode0)
3bc68535
JG		 430 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
431 if (mode1)
432 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
433 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
c93bb85b
JG		 434 }
435 rs690_line_buffer_adjust(rdev, mode0, mode1);
436
437 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
3bc68535 438 WREG32(R_006C9C_DCP_CONTROL, 0);
c93bb85b 439 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
3bc68535 440 WREG32(R_006C9C_DCP_CONTROL, 2);
c93bb85b
JG		 441
442 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
443 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
444
445 tmp = (wm0.lb_request_fifo_depth - 1);
446 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
3bc68535 447 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
c93bb85b
JG		 448
449 if (mode0 && mode1) {
450 if (rfixed_trunc(wm0.dbpp) > 64)
451 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
452 else
453 a.full = wm0.num_line_pair.full;
454 if (rfixed_trunc(wm1.dbpp) > 64)
455 b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
456 else
457 b.full = wm1.num_line_pair.full;
458 a.full += b.full;
459 fill_rate.full = rfixed_div(wm0.sclk, a);
460 if (wm0.consumption_rate.full > fill_rate.full) {
461 b.full = wm0.consumption_rate.full - fill_rate.full;
462 b.full = rfixed_mul(b, wm0.active_time);
463 a.full = rfixed_mul(wm0.worst_case_latency,
464 wm0.consumption_rate);
465 a.full = a.full + b.full;
466 b.full = rfixed_const(16 * 1000);
467 priority_mark02.full = rfixed_div(a, b);
468 } else {
469 a.full = rfixed_mul(wm0.worst_case_latency,
470 wm0.consumption_rate);
471 b.full = rfixed_const(16 * 1000);
472 priority_mark02.full = rfixed_div(a, b);
473 }
474 if (wm1.consumption_rate.full > fill_rate.full) {
475 b.full = wm1.consumption_rate.full - fill_rate.full;
476 b.full = rfixed_mul(b, wm1.active_time);
477 a.full = rfixed_mul(wm1.worst_case_latency,
478 wm1.consumption_rate);
479 a.full = a.full + b.full;
480 b.full = rfixed_const(16 * 1000);
481 priority_mark12.full = rfixed_div(a, b);
482 } else {
483 a.full = rfixed_mul(wm1.worst_case_latency,
484 wm1.consumption_rate);
485 b.full = rfixed_const(16 * 1000);
486 priority_mark12.full = rfixed_div(a, b);
487 }
488 if (wm0.priority_mark.full > priority_mark02.full)
489 priority_mark02.full = wm0.priority_mark.full;
490 if (rfixed_trunc(priority_mark02) < 0)
491 priority_mark02.full = 0;
492 if (wm0.priority_mark_max.full > priority_mark02.full)
493 priority_mark02.full = wm0.priority_mark_max.full;
494 if (wm1.priority_mark.full > priority_mark12.full)
495 priority_mark12.full = wm1.priority_mark.full;
496 if (rfixed_trunc(priority_mark12) < 0)
497 priority_mark12.full = 0;
498 if (wm1.priority_mark_max.full > priority_mark12.full)
499 priority_mark12.full = wm1.priority_mark_max.full;
3bc68535
JG		 500 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
501 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
502 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
503 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
c93bb85b
JG		 504 } else if (mode0) {
505 if (rfixed_trunc(wm0.dbpp) > 64)
506 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
507 else
508 a.full = wm0.num_line_pair.full;
509 fill_rate.full = rfixed_div(wm0.sclk, a);
510 if (wm0.consumption_rate.full > fill_rate.full) {
511 b.full = wm0.consumption_rate.full - fill_rate.full;
512 b.full = rfixed_mul(b, wm0.active_time);
513 a.full = rfixed_mul(wm0.worst_case_latency,
514 wm0.consumption_rate);
515 a.full = a.full + b.full;
516 b.full = rfixed_const(16 * 1000);
517 priority_mark02.full = rfixed_div(a, b);
518 } else {
519 a.full = rfixed_mul(wm0.worst_case_latency,
520 wm0.consumption_rate);
521 b.full = rfixed_const(16 * 1000);
522 priority_mark02.full = rfixed_div(a, b);
523 }
524 if (wm0.priority_mark.full > priority_mark02.full)
525 priority_mark02.full = wm0.priority_mark.full;
526 if (rfixed_trunc(priority_mark02) < 0)
527 priority_mark02.full = 0;
528 if (wm0.priority_mark_max.full > priority_mark02.full)
529 priority_mark02.full = wm0.priority_mark_max.full;
3bc68535
JG		 530 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
531 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
532 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
533 S_006D48_D2MODE_PRIORITY_A_OFF(1));
534 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
535 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
c93bb85b
JG		 536 } else {
537 if (rfixed_trunc(wm1.dbpp) > 64)
538 a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
539 else
540 a.full = wm1.num_line_pair.full;
541 fill_rate.full = rfixed_div(wm1.sclk, a);
542 if (wm1.consumption_rate.full > fill_rate.full) {
543 b.full = wm1.consumption_rate.full - fill_rate.full;
544 b.full = rfixed_mul(b, wm1.active_time);
545 a.full = rfixed_mul(wm1.worst_case_latency,
546 wm1.consumption_rate);
547 a.full = a.full + b.full;
548 b.full = rfixed_const(16 * 1000);
549 priority_mark12.full = rfixed_div(a, b);
550 } else {
551 a.full = rfixed_mul(wm1.worst_case_latency,
552 wm1.consumption_rate);
553 b.full = rfixed_const(16 * 1000);
554 priority_mark12.full = rfixed_div(a, b);
555 }
556 if (wm1.priority_mark.full > priority_mark12.full)
557 priority_mark12.full = wm1.priority_mark.full;
558 if (rfixed_trunc(priority_mark12) < 0)
559 priority_mark12.full = 0;
560 if (wm1.priority_mark_max.full > priority_mark12.full)
561 priority_mark12.full = wm1.priority_mark_max.full;
3bc68535
JG		 562 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
563 S_006548_D1MODE_PRIORITY_A_OFF(1));
564 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
565 S_00654C_D1MODE_PRIORITY_B_OFF(1));
566 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
567 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
c93bb85b
JG		 568 }
569}
771fe6b9 570
771fe6b9
JG		 571uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
572{
573 uint32_t r;
574
3bc68535
JG		 575 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
576 r = RREG32(R_00007C_MC_DATA);
577 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
771fe6b9
JG		 578 return r;
579}
580
581void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
582{
3bc68535
JG		 583 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
584 S_000078_MC_IND_WR_EN(1));
585 WREG32(R_00007C_MC_DATA, v);
586 WREG32(R_000078_MC_INDEX, 0x7F);
587}
588
589void rs690_mc_program(struct radeon_device *rdev)
590{
591 struct rv515_mc_save save;
592
593 /* Stops all mc clients */
594 rv515_mc_stop(rdev, &save);
595
596 /* Wait for mc idle */
597 if (rs690_mc_wait_for_idle(rdev))
598 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
599 /* Program MC, should be a 32bits limited address space */
600 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
601 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
602 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
603 WREG32(R_000134_HDP_FB_LOCATION,
604 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
605
606 rv515_mc_resume(rdev, &save);
607}
608
609static int rs690_startup(struct radeon_device *rdev)
610{
611 int r;
612
613 rs690_mc_program(rdev);
614 /* Resume clock */
615 rv515_clock_startup(rdev);
616 /* Initialize GPU configuration (# pipes, ...) */
617 rs690_gpu_init(rdev);
618 /* Initialize GART (initialize after TTM so we can allocate
619 * memory through TTM but finalize after TTM) */
620 r = rs400_gart_enable(rdev);
621 if (r)
622 return r;
623 /* Enable IRQ */
ac447df4 624 rs600_irq_set(rdev);
3bc68535
JG		 625 /* 1M ring buffer */
626 r = r100_cp_init(rdev, 1024 * 1024);
627 if (r) {
628 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
629 return r;
630 }
631 r = r100_wb_init(rdev);
632 if (r)
633 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
634 r = r100_ib_init(rdev);
635 if (r) {
636 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
637 return r;
638 }
639 return 0;
640}
641
642int rs690_resume(struct radeon_device *rdev)
643{
644 /* Make sur GART are not working */
645 rs400_gart_disable(rdev);
646 /* Resume clock before doing reset */
647 rv515_clock_startup(rdev);
648 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
649 if (radeon_gpu_reset(rdev)) {
650 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
651 RREG32(R_000E40_RBBM_STATUS),
652 RREG32(R_0007C0_CP_STAT));
653 }
654 /* post */
655 atom_asic_init(rdev->mode_info.atom_context);
656 /* Resume clock after posting */
657 rv515_clock_startup(rdev);
658 return rs690_startup(rdev);
659}
660
661int rs690_suspend(struct radeon_device *rdev)
662{
663 r100_cp_disable(rdev);
664 r100_wb_disable(rdev);
ac447df4 665 rs600_irq_disable(rdev);
3bc68535
JG		 666 rs400_gart_disable(rdev);
667 return 0;
668}
669
670void rs690_fini(struct radeon_device *rdev)
671{
672 rs690_suspend(rdev);
673 r100_cp_fini(rdev);
674 r100_wb_fini(rdev);
675 r100_ib_fini(rdev);
676 radeon_gem_fini(rdev);
677 rs400_gart_fini(rdev);
678 radeon_irq_kms_fini(rdev);
679 radeon_fence_driver_fini(rdev);
4c788679 680 radeon_bo_fini(rdev);
3bc68535
JG		 681 radeon_atombios_fini(rdev);
682 kfree(rdev->bios);
683 rdev->bios = NULL;
684}
685
686int rs690_init(struct radeon_device *rdev)
687{
688 int r;
689
3bc68535
JG		 690 /* Disable VGA */
691 rv515_vga_render_disable(rdev);
692 /* Initialize scratch registers */
693 radeon_scratch_init(rdev);
694 /* Initialize surface registers */
695 radeon_surface_init(rdev);
696 /* TODO: disable VGA need to use VGA request */
697 /* BIOS*/
698 if (!radeon_get_bios(rdev)) {
699 if (ASIC_IS_AVIVO(rdev))
700 return -EINVAL;
701 }
702 if (rdev->is_atom_bios) {
703 r = radeon_atombios_init(rdev);
704 if (r)
705 return r;
706 } else {
707 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
708 return -EINVAL;
709 }
710 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
711 if (radeon_gpu_reset(rdev)) {
712 dev_warn(rdev->dev,
713 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
714 RREG32(R_000E40_RBBM_STATUS),
715 RREG32(R_0007C0_CP_STAT));
716 }
717 /* check if cards are posted or not */
72542d77
DA		 718 if (radeon_boot_test_post_card(rdev) == false)
719 return -EINVAL;
720
3bc68535
JG		 721 /* Initialize clocks */
722 radeon_get_clock_info(rdev->ddev);
7433874e
RM		 723 /* Initialize power management */
724 radeon_pm_init(rdev);
3bc68535
JG		 725 /* Get vram informations */
726 rs690_vram_info(rdev);
727 /* Initialize memory controller (also test AGP) */
22dd5013 728 r = rs690_mc_init(rdev);
3bc68535
JG		 729 if (r)
730 return r;
731 rv515_debugfs(rdev);
732 /* Fence driver */
733 r = radeon_fence_driver_init(rdev);
734 if (r)
735 return r;
736 r = radeon_irq_kms_init(rdev);
737 if (r)
738 return r;
739 /* Memory manager */
4c788679 740 r = radeon_bo_init(rdev);
3bc68535
JG		 741 if (r)
742 return r;
743 r = rs400_gart_init(rdev);
744 if (r)
745 return r;
746 rs600_set_safe_registers(rdev);
747 rdev->accel_working = true;
748 r = rs690_startup(rdev);
749 if (r) {
750 /* Somethings want wront with the accel init stop accel */
751 dev_err(rdev->dev, "Disabling GPU acceleration\n");
752 rs690_suspend(rdev);
753 r100_cp_fini(rdev);
754 r100_wb_fini(rdev);
755 r100_ib_fini(rdev);
756 rs400_gart_fini(rdev);
757 radeon_irq_kms_fini(rdev);
758 rdev->accel_working = false;
759 }
760 return 0;
771fe6b9 761}
Clone of davem's net-next-2.6 tree