[net-next-2.6.git] / drivers / gpu / drm / radeon / rs600.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
/* RS600 / Radeon X1250/X1270 integrated GPU
 *
 * This file gather function specific to RS600 which is the IGP of
 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
 * is the X1250/X1270 supporting AMD CPU). The display engine are
 * the avivo one, bios is an atombios, 3D block are the one of the
 * R4XX family. The GART is different from the RS400 one and is very
 * close to the one of the R600 family (R600 likely being an evolution
 * of the RS600 GART block).
 */
#include "drmP.h"
#include "radeon.h"
#include "atom.h"
#include "rs600d.h"

#include "rs600_reg_safe.h"

void rs600_gpu_init(struct radeon_device *rdev);
int rs600_mc_wait_for_idle(struct radeon_device *rdev);

/*
 * GART.
 */
void rs600_gart_tlb_flush(struct radeon_device *rdev)
{
	uint32_t tmp;

	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);

	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);

	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
}

int rs600_gart_init(struct radeon_device *rdev)
{
	int r;

	if (rdev->gart.table.vram.robj) {
		WARN(1, "RS600 GART already initialized.\n");
		return 0;
	}
	/* Initialize common gart structure */
	r = radeon_gart_init(rdev);
	if (r) {
		return r;
	}
	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
	return radeon_gart_table_vram_alloc(rdev);
}

int rs600_gart_enable(struct radeon_device *rdev)
{
	u32 tmp;
	int r, i;

	if (rdev->gart.table.vram.robj == NULL) {
		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
		return -EINVAL;
	}
	r = radeon_gart_table_vram_pin(rdev);
	if (r)
		return r;
	/* Enable bus master */
	tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
	WREG32(R_00004C_BUS_CNTL, tmp);
	/* FIXME: setup default page */
	WREG32_MC(R_000100_MC_PT0_CNTL,
		 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
		  S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
	for (i = 0; i < 19; i++) {
		WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
			S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
			S_00016C_SYSTEM_ACCESS_MODE_MASK(
				V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) |
			S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
				V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) |
			S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) |
			S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
			S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1));
	}

	/* System context map to GART space */
	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start);
	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end);

	/* enable first context */
	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
			S_000102_ENABLE_PAGE_TABLE(1) |
			S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
	/* disable all other contexts */
	for (i = 1; i < 8; i++) {
		WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
	}

	/* setup the page table */
	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
			rdev->gart.table_addr);
	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);

	/* enable page tables */
	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
	tmp = RREG32_MC(R_000009_MC_CNTL1);
	WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
	rs600_gart_tlb_flush(rdev);
	rdev->gart.ready = true;
	return 0;
}

void rs600_gart_disable(struct radeon_device *rdev)
{
	uint32_t tmp;

	/* FIXME: disable out of gart access */
	WREG32_MC(R_000100_MC_PT0_CNTL, 0);
	tmp = RREG32_MC(R_000009_MC_CNTL1);
	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
	if (rdev->gart.table.vram.robj) {
		radeon_object_kunmap(rdev->gart.table.vram.robj);
		radeon_object_unpin(rdev->gart.table.vram.robj);
	}
}

void rs600_gart_fini(struct radeon_device *rdev)
{
	rs600_gart_disable(rdev);
	radeon_gart_table_vram_free(rdev);
	radeon_gart_fini(rdev);
}

#define R600_PTE_VALID     (1 << 0)
#define R600_PTE_SYSTEM    (1 << 1)
#define R600_PTE_SNOOPED   (1 << 2)
#define R600_PTE_READABLE  (1 << 5)
#define R600_PTE_WRITEABLE (1 << 6)

int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
{
	void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;

	if (i < 0 || i > rdev->gart.num_gpu_pages) {
		return -EINVAL;
	}
	addr = addr & 0xFFFFFFFFFFFFF000ULL;
	addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
	addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
	writeq(addr, ((void __iomem *)ptr) + (i * 8));
	return 0;
}

int rs600_irq_set(struct radeon_device *rdev)
{
	uint32_t tmp = 0;
	uint32_t mode_int = 0;

	if (rdev->irq.sw_int) {
		tmp |= S_000040_SW_INT_EN(1);
	}
	if (rdev->irq.crtc_vblank_int[0]) {
		mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
	}
	if (rdev->irq.crtc_vblank_int[1]) {
		mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
	}
	WREG32(R_000040_GEN_INT_CNTL, tmp);
	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
	return 0;
}

static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
{
	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
	uint32_t irq_mask = ~C_000044_SW_INT;

	if (G_000044_DISPLAY_INT_STAT(irqs)) {
		*r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
			WREG32(R_006534_D1MODE_VBLANK_STATUS,
				S_006534_D1MODE_VBLANK_ACK(1));
		}
		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
			WREG32(R_006D34_D2MODE_VBLANK_STATUS,
				S_006D34_D2MODE_VBLANK_ACK(1));
		}
	} else {
		*r500_disp_int = 0;
	}

	if (irqs) {
		WREG32(R_000044_GEN_INT_STATUS, irqs);
	}
	return irqs & irq_mask;
}

void rs600_irq_disable(struct radeon_device *rdev)
{
	u32 tmp;

	WREG32(R_000040_GEN_INT_CNTL, 0);
	WREG32(R_006540_DxMODE_INT_MASK, 0);
	/* Wait and acknowledge irq */
	mdelay(1);
	rs600_irq_ack(rdev, &tmp);
}

int rs600_irq_process(struct radeon_device *rdev)
{
	uint32_t status;
	uint32_t r500_disp_int;

	status = rs600_irq_ack(rdev, &r500_disp_int);
	if (!status && !r500_disp_int) {
		return IRQ_NONE;
	}
	while (status || r500_disp_int) {
		/* SW interrupt */
		if (G_000040_SW_INT_EN(status))
			radeon_fence_process(rdev);
		/* Vertical blank interrupts */
		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
			drm_handle_vblank(rdev->ddev, 0);
		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int))
			drm_handle_vblank(rdev->ddev, 1);
		status = rs600_irq_ack(rdev, &r500_disp_int);
	}
	return IRQ_HANDLED;
}

u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
{
	if (crtc == 0)
		return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
	else
		return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
}

int rs600_mc_wait_for_idle(struct radeon_device *rdev)
{
	unsigned i;

	for (i = 0; i < rdev->usec_timeout; i++) {
		if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
			return 0;
		udelay(1);
	}
	return -1;
}

void rs600_gpu_init(struct radeon_device *rdev)
{
	/* FIXME: HDP same place on rs600 ? */
	r100_hdp_reset(rdev);
	/* FIXME: is this correct ? */
	r420_pipes_init(rdev);
	/* Wait for mc idle */
	if (rs600_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
}

void rs600_vram_info(struct radeon_device *rdev)
{
	/* FIXME: to do or is these values sane ? */
	rdev->mc.vram_is_ddr = true;
	rdev->mc.vram_width = 128;
}

void rs600_bandwidth_update(struct radeon_device *rdev)
{
	/* FIXME: implement, should this be like rs690 ? */
}

uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
{
	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
		S_000070_MC_IND_CITF_ARB0(1));
	return RREG32(R_000074_MC_IND_DATA);
}

void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
		S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
	WREG32(R_000074_MC_IND_DATA, v);
}

void rs600_debugfs(struct radeon_device *rdev)
{
	if (r100_debugfs_rbbm_init(rdev))
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
}

void rs600_set_safe_registers(struct radeon_device *rdev)
{
	rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
}

static void rs600_mc_program(struct radeon_device *rdev)
{
	struct rv515_mc_save save;

	/* Stops all mc clients */
	rv515_mc_stop(rdev, &save);

	/* Wait for mc idle */
	if (rs600_mc_wait_for_idle(rdev))
		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");

	/* FIXME: What does AGP means for such chipset ? */
	WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
	WREG32_MC(R_000006_AGP_BASE, 0);
	WREG32_MC(R_000007_AGP_BASE_2, 0);
	/* Program MC */
	WREG32_MC(R_000004_MC_FB_LOCATION,
			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
	WREG32(R_000134_HDP_FB_LOCATION,
		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));

	rv515_mc_resume(rdev, &save);
}

static int rs600_startup(struct radeon_device *rdev)
{
	int r;

	rs600_mc_program(rdev);
	/* Resume clock */
	rv515_clock_startup(rdev);
	/* Initialize GPU configuration (# pipes, ...) */
	rs600_gpu_init(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	r = rs600_gart_enable(rdev);
	if (r)
		return r;
	/* Enable IRQ */
	rdev->irq.sw_int = true;
	rs600_irq_set(rdev);
	/* 1M ring buffer */
	r = r100_cp_init(rdev, 1024 * 1024);
	if (r) {
		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		return r;
	}
	r = r100_wb_init(rdev);
	if (r)
		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
	r = r100_ib_init(rdev);
	if (r) {
		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		return r;
	}
	return 0;
}

int rs600_resume(struct radeon_device *rdev)
{
	/* Make sur GART are not working */
	rs600_gart_disable(rdev);
	/* Resume clock before doing reset */
	rv515_clock_startup(rdev);
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* post */
	atom_asic_init(rdev->mode_info.atom_context);
	/* Resume clock after posting */
	rv515_clock_startup(rdev);
	return rs600_startup(rdev);
}

int rs600_suspend(struct radeon_device *rdev)
{
	r100_cp_disable(rdev);
	r100_wb_disable(rdev);
	rs600_irq_disable(rdev);
	rs600_gart_disable(rdev);
	return 0;
}

void rs600_fini(struct radeon_device *rdev)
{
	rs600_suspend(rdev);
	r100_cp_fini(rdev);
	r100_wb_fini(rdev);
	r100_ib_fini(rdev);
	radeon_gem_fini(rdev);
	rs600_gart_fini(rdev);
	radeon_irq_kms_fini(rdev);
	radeon_fence_driver_fini(rdev);
	radeon_object_fini(rdev);
	radeon_atombios_fini(rdev);
	kfree(rdev->bios);
	rdev->bios = NULL;
}

int rs600_init(struct radeon_device *rdev)
{
	int r;

	/* Disable VGA */
	rv515_vga_render_disable(rdev);
	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* BIOS */
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r)
			return r;
	} else {
		dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
		return -EINVAL;
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_gpu_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (!radeon_card_posted(rdev) && rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		atom_asic_init(rdev->mode_info.atom_context);
	}
	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* Get vram informations */
	rs600_vram_info(rdev);
	/* Initialize memory controller (also test AGP) */
	r = r420_mc_init(rdev);
	if (r)
		return r;
	rs600_debugfs(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r)
		return r;
	r = radeon_irq_kms_init(rdev);
	if (r)
		return r;
	/* Memory manager */
	r = radeon_object_init(rdev);
	if (r)
		return r;
	r = rs600_gart_init(rdev);
	if (r)
		return r;
	rs600_set_safe_registers(rdev);
	rdev->accel_working = true;
	r = rs600_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
		rs600_suspend(rdev);
		r100_cp_fini(rdev);
		r100_wb_fini(rdev);
		r100_ib_fini(rdev);
		rs600_gart_fini(rdev);
		radeon_irq_kms_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
c010f800 JG	28	/* RS600 / Radeon X1250/X1270 integrated GPU
	29	*
	30	* This file gather function specific to RS600 which is the IGP of
	31	* the X1250/X1270 family supporting intel CPU (while RS690/RS740
	32	* is the X1250/X1270 supporting AMD CPU). The display engine are
	33	* the avivo one, bios is an atombios, 3D block are the one of the
	34	* R4XX family. The GART is different from the RS400 one and is very
	35	* close to the one of the R600 family (R600 likely being an evolution
	36	* of the RS600 GART block).
	37	*/
771fe6b9	38	#include "drmP.h"
771fe6b9	39	#include "radeon.h"
c010f800 JG	40	#include "atom.h"
c010f800 JG	41	#include "rs600d.h"
771fe6b9	42
3f7dc91a DA	43	#include "rs600_reg_safe.h"
3f7dc91a DA	44
771fe6b9 JG	45	void rs600_gpu_init(struct radeon_device *rdev);
771fe6b9 JG	46	int rs600_mc_wait_for_idle(struct radeon_device *rdev);
771fe6b9	47
771fe6b9 JG	48	/*
	49	* GART.
	50	*/
	51	void rs600_gart_tlb_flush(struct radeon_device *rdev)
	52	{
	53	uint32_t tmp;
	54
c010f800 JG	55	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	56	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
	57	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9	58
c010f800 JG	59	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	60	tmp \|= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
	61	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9	62
c010f800 JG	63	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	64	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
	65	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
	66	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
771fe6b9 JG	67	}
771fe6b9 JG	68
4aac0473	69	int rs600_gart_init(struct radeon_device *rdev)
771fe6b9	70	{
771fe6b9 JG	71	int r;
771fe6b9 JG	72
4aac0473 JG	73	if (rdev->gart.table.vram.robj) {
	74	WARN(1, "RS600 GART already initialized.\n");
	75	return 0;
	76	}
771fe6b9 JG	77	/* Initialize common gart structure */
	78	r = radeon_gart_init(rdev);
	79	if (r) {
	80	return r;
	81	}
	82	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473 JG	83	return radeon_gart_table_vram_alloc(rdev);
	84	}
	85
	86	int rs600_gart_enable(struct radeon_device *rdev)
	87	{
c010f800	88	u32 tmp;
4aac0473 JG	89	int r, i;
	90
	91	if (rdev->gart.table.vram.robj == NULL) {
	92	dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
	93	return -EINVAL;
771fe6b9	94	}
4aac0473 JG	95	r = radeon_gart_table_vram_pin(rdev);
	96	if (r)
	97	return r;
c010f800 JG	98	/* Enable bus master */
	99	tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
	100	WREG32(R_00004C_BUS_CNTL, tmp);
771fe6b9	101	/* FIXME: setup default page */
c010f800 JG	102	WREG32_MC(R_000100_MC_PT0_CNTL,
	103	(S_000100_EFFECTIVE_L2_CACHE_SIZE(6) \|
	104	S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
771fe6b9	105	for (i = 0; i < 19; i++) {
c010f800 JG	106	WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
	107	S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) \|
	108	S_00016C_SYSTEM_ACCESS_MODE_MASK(
	109	V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) \|
	110	S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
	111	V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) \|
	112	S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) \|
	113	S_00016C_ENABLE_FRAGMENT_PROCESSING(1) \|
	114	S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1));
771fe6b9 JG	115	}
	116
	117	/* System context map to GART space */
c010f800 JG	118	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start);
c010f800 JG	119	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end);
771fe6b9 JG	120
771fe6b9 JG	121	/* enable first context */
c010f800 JG	122	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
	123	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
	124	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
	125	S_000102_ENABLE_PAGE_TABLE(1) \|
	126	S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
771fe6b9 JG	127	/* disable all other contexts */
771fe6b9 JG	128	for (i = 1; i < 8; i++) {
c010f800	129	WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
771fe6b9 JG	130	}
	131
	132	/* setup the page table */
c010f800 JG	133	WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
	134	rdev->gart.table_addr);
	135	WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
771fe6b9 JG	136
771fe6b9 JG	137	/* enable page tables */
c010f800 JG	138	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
	139	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp \| S_000100_ENABLE_PT(1)));
	140	tmp = RREG32_MC(R_000009_MC_CNTL1);
	141	WREG32_MC(R_000009_MC_CNTL1, (tmp \| S_000009_ENABLE_PAGE_TABLES(1)));
771fe6b9 JG	142	rs600_gart_tlb_flush(rdev);
	143	rdev->gart.ready = true;
	144	return 0;
	145	}
	146
	147	void rs600_gart_disable(struct radeon_device *rdev)
	148	{
	149	uint32_t tmp;
	150
	151	/* FIXME: disable out of gart access */
c010f800 JG	152	WREG32_MC(R_000100_MC_PT0_CNTL, 0);
	153	tmp = RREG32_MC(R_000009_MC_CNTL1);
	154	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
4aac0473 JG	155	if (rdev->gart.table.vram.robj) {
	156	radeon_object_kunmap(rdev->gart.table.vram.robj);
	157	radeon_object_unpin(rdev->gart.table.vram.robj);
	158	}
	159	}
	160
	161	void rs600_gart_fini(struct radeon_device *rdev)
	162	{
	163	rs600_gart_disable(rdev);
	164	radeon_gart_table_vram_free(rdev);
	165	radeon_gart_fini(rdev);
771fe6b9 JG	166	}
	167
	168	#define R600_PTE_VALID (1 << 0)
	169	#define R600_PTE_SYSTEM (1 << 1)
	170	#define R600_PTE_SNOOPED (1 << 2)
	171	#define R600_PTE_READABLE (1 << 5)
	172	#define R600_PTE_WRITEABLE (1 << 6)
	173
	174	int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
	175	{
	176	void __iomem ptr = (void )rdev->gart.table.vram.ptr;
	177
	178	if (i < 0 \|\| i > rdev->gart.num_gpu_pages) {
	179	return -EINVAL;
	180	}
	181	addr = addr & 0xFFFFFFFFFFFFF000ULL;
	182	addr \|= R600_PTE_VALID \| R600_PTE_SYSTEM \| R600_PTE_SNOOPED;
	183	addr \|= R600_PTE_READABLE \| R600_PTE_WRITEABLE;
	184	writeq(addr, ((void __iomem )ptr) + (i 8));
	185	return 0;
	186	}
	187
7ed220d7 MD	188	int rs600_irq_set(struct radeon_device *rdev)
	189	{
	190	uint32_t tmp = 0;
	191	uint32_t mode_int = 0;
	192
	193	if (rdev->irq.sw_int) {
c010f800	194	tmp \|= S_000040_SW_INT_EN(1);
7ed220d7 MD	195	}
7ed220d7 MD	196	if (rdev->irq.crtc_vblank_int[0]) {
c010f800	197	mode_int \|= S_006540_D1MODE_VBLANK_INT_MASK(1);
7ed220d7 MD	198	}
7ed220d7 MD	199	if (rdev->irq.crtc_vblank_int[1]) {
c010f800	200	mode_int \|= S_006540_D2MODE_VBLANK_INT_MASK(1);
7ed220d7	201	}
c010f800 JG	202	WREG32(R_000040_GEN_INT_CNTL, tmp);
c010f800 JG	203	WREG32(R_006540_DxMODE_INT_MASK, mode_int);
7ed220d7 MD	204	return 0;
	205	}
	206
	207	static inline uint32_t rs600_irq_ack(struct radeon_device rdev, u32 r500_disp_int)
	208	{
01ceae8e JG	209	uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
01ceae8e JG	210	uint32_t irq_mask = ~C_000044_SW_INT;
c010f800	211
01ceae8e	212	if (G_000044_DISPLAY_INT_STAT(irqs)) {
c010f800 JG	213	*r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
	214	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
	215	WREG32(R_006534_D1MODE_VBLANK_STATUS,
	216	S_006534_D1MODE_VBLANK_ACK(1));
7ed220d7	217	}
c010f800 JG	218	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
	219	WREG32(R_006D34_D2MODE_VBLANK_STATUS,
	220	S_006D34_D2MODE_VBLANK_ACK(1));
7ed220d7 MD	221	}
	222	} else {
	223	*r500_disp_int = 0;
	224	}
	225
	226	if (irqs) {
01ceae8e	227	WREG32(R_000044_GEN_INT_STATUS, irqs);
7ed220d7 MD	228	}
	229	return irqs & irq_mask;
	230	}
	231
ac447df4 JG	232	void rs600_irq_disable(struct radeon_device *rdev)
	233	{
	234	u32 tmp;
	235
	236	WREG32(R_000040_GEN_INT_CNTL, 0);
	237	WREG32(R_006540_DxMODE_INT_MASK, 0);
	238	/* Wait and acknowledge irq */
	239	mdelay(1);
	240	rs600_irq_ack(rdev, &tmp);
	241	}
	242
7ed220d7 MD	243	int rs600_irq_process(struct radeon_device *rdev)
	244	{
	245	uint32_t status;
	246	uint32_t r500_disp_int;
	247
	248	status = rs600_irq_ack(rdev, &r500_disp_int);
	249	if (!status && !r500_disp_int) {
	250	return IRQ_NONE;
	251	}
	252	while (status \|\| r500_disp_int) {
	253	/* SW interrupt */
c010f800	254	if (G_000040_SW_INT_EN(status))
7ed220d7	255	radeon_fence_process(rdev);
7ed220d7	256	/* Vertical blank interrupts */
c010f800	257	if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
7ed220d7	258	drm_handle_vblank(rdev->ddev, 0);
c010f800	259	if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int))
7ed220d7	260	drm_handle_vblank(rdev->ddev, 1);
7ed220d7 MD	261	status = rs600_irq_ack(rdev, &r500_disp_int);
	262	}
	263	return IRQ_HANDLED;
	264	}
	265
	266	u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
	267	{
	268	if (crtc == 0)
c010f800	269	return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
7ed220d7	270	else
c010f800	271	return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
7ed220d7 MD	272	}
7ed220d7 MD	273
771fe6b9 JG	274	int rs600_mc_wait_for_idle(struct radeon_device *rdev)
	275	{
	276	unsigned i;
771fe6b9 JG	277
771fe6b9 JG	278	for (i = 0; i < rdev->usec_timeout; i++) {
c010f800	279	if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
771fe6b9	280	return 0;
c010f800	281	udelay(1);
771fe6b9 JG	282	}
	283	return -1;
	284	}
	285
771fe6b9 JG	286	void rs600_gpu_init(struct radeon_device *rdev)
	287	{
	288	/* FIXME: HDP same place on rs600 ? */
	289	r100_hdp_reset(rdev);
771fe6b9 JG	290	/* FIXME: is this correct ? */
771fe6b9 JG	291	r420_pipes_init(rdev);
c010f800 JG	292	/* Wait for mc idle */
	293	if (rs600_mc_wait_for_idle(rdev))
	294	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
771fe6b9 JG	295	}
771fe6b9 JG	296
771fe6b9 JG	297	void rs600_vram_info(struct radeon_device *rdev)
	298	{
	299	/* FIXME: to do or is these values sane ? */
	300	rdev->mc.vram_is_ddr = true;
	301	rdev->mc.vram_width = 128;
	302	}
	303
c93bb85b JG	304	void rs600_bandwidth_update(struct radeon_device *rdev)
	305	{
	306	/* FIXME: implement, should this be like rs690 ? */
	307	}
	308
771fe6b9 JG	309	uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
771fe6b9 JG	310	{
c010f800 JG	311	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) \|
	312	S_000070_MC_IND_CITF_ARB0(1));
	313	return RREG32(R_000074_MC_IND_DATA);
771fe6b9 JG	314	}
	315
	316	void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
	317	{
c010f800 JG	318	WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) \|
	319	S_000070_MC_IND_CITF_ARB0(1) \| S_000070_MC_IND_WR_EN(1));
	320	WREG32(R_000074_MC_IND_DATA, v);
	321	}
	322
	323	void rs600_debugfs(struct radeon_device *rdev)
	324	{
	325	if (r100_debugfs_rbbm_init(rdev))
	326	DRM_ERROR("Failed to register debugfs file for RBBM !\n");
771fe6b9	327	}
3f7dc91a	328
3bc68535	329	void rs600_set_safe_registers(struct radeon_device *rdev)
3f7dc91a DA	330	{
	331	rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
	332	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
3bc68535 JG	333	}
3bc68535 JG	334
c010f800 JG	335	static void rs600_mc_program(struct radeon_device *rdev)
	336	{
	337	struct rv515_mc_save save;
	338
	339	/* Stops all mc clients */
	340	rv515_mc_stop(rdev, &save);
	341
	342	/* Wait for mc idle */
	343	if (rs600_mc_wait_for_idle(rdev))
	344	dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
	345
	346	/* FIXME: What does AGP means for such chipset ? */
	347	WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
	348	WREG32_MC(R_000006_AGP_BASE, 0);
	349	WREG32_MC(R_000007_AGP_BASE_2, 0);
	350	/* Program MC */
	351	WREG32_MC(R_000004_MC_FB_LOCATION,
	352	S_000004_MC_FB_START(rdev->mc.vram_start >> 16) \|
	353	S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
	354	WREG32(R_000134_HDP_FB_LOCATION,
	355	S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
	356
	357	rv515_mc_resume(rdev, &save);
	358	}
	359
	360	static int rs600_startup(struct radeon_device *rdev)
	361	{
	362	int r;
	363
	364	rs600_mc_program(rdev);
	365	/* Resume clock */
	366	rv515_clock_startup(rdev);
	367	/* Initialize GPU configuration (# pipes, ...) */
	368	rs600_gpu_init(rdev);
	369	/* Initialize GART (initialize after TTM so we can allocate
	370	* memory through TTM but finalize after TTM) */
	371	r = rs600_gart_enable(rdev);
	372	if (r)
	373	return r;
	374	/* Enable IRQ */
	375	rdev->irq.sw_int = true;
	376	rs600_irq_set(rdev);
	377	/* 1M ring buffer */
	378	r = r100_cp_init(rdev, 1024 * 1024);
	379	if (r) {
	380	dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
	381	return r;
	382	}
	383	r = r100_wb_init(rdev);
	384	if (r)
	385	dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
	386	r = r100_ib_init(rdev);
	387	if (r) {
	388	dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
	389	return r;
	390	}
	391	return 0;
	392	}
	393
	394	int rs600_resume(struct radeon_device *rdev)
	395	{
	396	/* Make sur GART are not working */
	397	rs600_gart_disable(rdev);
	398	/* Resume clock before doing reset */
399	rv515_clock_startup(rdev);
400	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
401	if (radeon_gpu_reset(rdev)) {
402	dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
403	RREG32(R_000E40_RBBM_STATUS),
404	RREG32(R_0007C0_CP_STAT));
405	}
406	/* post */
407	atom_asic_init(rdev->mode_info.atom_context);
408	/* Resume clock after posting */
409	rv515_clock_startup(rdev);
410	return rs600_startup(rdev);
411	}
412
413	int rs600_suspend(struct radeon_device *rdev)
414	{
415	r100_cp_disable(rdev);
416	r100_wb_disable(rdev);
ac447df4	417	rs600_irq_disable(rdev);
c010f800 JG	418	rs600_gart_disable(rdev);
	419	return 0;
	420	}
	421
	422	void rs600_fini(struct radeon_device *rdev)
	423	{
	424	rs600_suspend(rdev);
	425	r100_cp_fini(rdev);
	426	r100_wb_fini(rdev);
	427	r100_ib_fini(rdev);
	428	radeon_gem_fini(rdev);
	429	rs600_gart_fini(rdev);
	430	radeon_irq_kms_fini(rdev);
	431	radeon_fence_driver_fini(rdev);
	432	radeon_object_fini(rdev);
	433	radeon_atombios_fini(rdev);
	434	kfree(rdev->bios);
	435	rdev->bios = NULL;
	436	}
	437
3bc68535 JG	438	int rs600_init(struct radeon_device *rdev)
3bc68535 JG	439	{
c010f800 JG	440	int r;
c010f800 JG	441
c010f800 JG	442	/* Disable VGA */
	443	rv515_vga_render_disable(rdev);
	444	/* Initialize scratch registers */
	445	radeon_scratch_init(rdev);
	446	/* Initialize surface registers */
	447	radeon_surface_init(rdev);
	448	/* BIOS */
	449	if (!radeon_get_bios(rdev)) {
	450	if (ASIC_IS_AVIVO(rdev))
	451	return -EINVAL;
	452	}
	453	if (rdev->is_atom_bios) {
	454	r = radeon_atombios_init(rdev);
	455	if (r)
	456	return r;
	457	} else {
	458	dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
	459	return -EINVAL;
	460	}
	461	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	462	if (radeon_gpu_reset(rdev)) {
	463	dev_warn(rdev->dev,
	464	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
	465	RREG32(R_000E40_RBBM_STATUS),
	466	RREG32(R_0007C0_CP_STAT));
	467	}
	468	/* check if cards are posted or not */
	469	if (!radeon_card_posted(rdev) && rdev->bios) {
	470	DRM_INFO("GPU not posted. posting now...\n");
	471	atom_asic_init(rdev->mode_info.atom_context);
	472	}
	473	/* Initialize clocks */
	474	radeon_get_clock_info(rdev->ddev);
	475	/* Get vram informations */
	476	rs600_vram_info(rdev);
	477	/* Initialize memory controller (also test AGP) */
	478	r = r420_mc_init(rdev);
	479	if (r)
	480	return r;
	481	rs600_debugfs(rdev);
	482	/* Fence driver */
	483	r = radeon_fence_driver_init(rdev);
	484	if (r)
	485	return r;
	486	r = radeon_irq_kms_init(rdev);
	487	if (r)
	488	return r;
	489	/* Memory manager */
	490	r = radeon_object_init(rdev);
	491	if (r)
	492	return r;
	493	r = rs600_gart_init(rdev);
	494	if (r)
	495	return r;
	496	rs600_set_safe_registers(rdev);
	497	rdev->accel_working = true;
	498	r = rs600_startup(rdev);
	499	if (r) {
	500	/* Somethings want wront with the accel init stop accel */
	501	dev_err(rdev->dev, "Disabling GPU acceleration\n");
	502	rs600_suspend(rdev);
	503	r100_cp_fini(rdev);
	504	r100_wb_fini(rdev);
	505	r100_ib_fini(rdev);
506	rs600_gart_fini(rdev);
507	radeon_irq_kms_fini(rdev);
508	rdev->accel_working = false;
509	}
3f7dc91a DA	510	return 0;
3f7dc91a DA	511	}