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drm/radeon/kms: simplify memory controller setup V2
[net-next-2.6.git] / drivers / gpu / drm / radeon / rs600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
c010f800
JG		 28/* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
771fe6b9 38#include "drmP.h"
771fe6b9 39#include "radeon.h"
c010f800
JG		 40#include "atom.h"
41#include "rs600d.h"
771fe6b9 42
3f7dc91a
DA		 43#include "rs600_reg_safe.h"
44
771fe6b9
JG		 45void rs600_gpu_init(struct radeon_device *rdev);
46int rs600_mc_wait_for_idle(struct radeon_device *rdev);
771fe6b9 47
dcfdd408
AD		 48/* hpd for digital panel detect/disconnect */
49bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
50{
51 u32 tmp;
52 bool connected = false;
53
54 switch (hpd) {
55 case RADEON_HPD_1:
56 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
57 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
58 connected = true;
59 break;
60 case RADEON_HPD_2:
61 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
62 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
63 connected = true;
64 break;
65 default:
66 break;
67 }
68 return connected;
69}
70
71void rs600_hpd_set_polarity(struct radeon_device *rdev,
72 enum radeon_hpd_id hpd)
73{
74 u32 tmp;
75 bool connected = rs600_hpd_sense(rdev, hpd);
76
77 switch (hpd) {
78 case RADEON_HPD_1:
79 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
80 if (connected)
81 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
82 else
83 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
84 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
85 break;
86 case RADEON_HPD_2:
87 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
88 if (connected)
89 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
90 else
91 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
92 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
93 break;
94 default:
95 break;
96 }
97}
98
99void rs600_hpd_init(struct radeon_device *rdev)
100{
101 struct drm_device *dev = rdev->ddev;
102 struct drm_connector *connector;
103
104 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
105 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
106 switch (radeon_connector->hpd.hpd) {
107 case RADEON_HPD_1:
108 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
109 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
110 rdev->irq.hpd[0] = true;
111 break;
112 case RADEON_HPD_2:
113 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
114 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
115 rdev->irq.hpd[1] = true;
116 break;
117 default:
118 break;
119 }
120 }
003e69f9
JG		 121 if (rdev->irq.installed)
122 rs600_irq_set(rdev);
dcfdd408
AD		 123}
124
125void rs600_hpd_fini(struct radeon_device *rdev)
126{
127 struct drm_device *dev = rdev->ddev;
128 struct drm_connector *connector;
129
130 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
131 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
132 switch (radeon_connector->hpd.hpd) {
133 case RADEON_HPD_1:
134 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
135 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
136 rdev->irq.hpd[0] = false;
137 break;
138 case RADEON_HPD_2:
139 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
140 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
141 rdev->irq.hpd[1] = false;
142 break;
143 default:
144 break;
145 }
146 }
147}
148
771fe6b9
JG		 149/*
150 * GART.
151 */
152void rs600_gart_tlb_flush(struct radeon_device *rdev)
153{
154 uint32_t tmp;
155
c010f800
JG		 156 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
157 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
158 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 159
c010f800
JG		 160 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
161 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
162 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 163
c010f800
JG		 164 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
165 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
166 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
167 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
771fe6b9
JG		 168}
169
4aac0473 170int rs600_gart_init(struct radeon_device *rdev)
771fe6b9 171{
771fe6b9
JG		 172 int r;
173
4aac0473
JG		 174 if (rdev->gart.table.vram.robj) {
175 WARN(1, "RS600 GART already initialized.\n");
176 return 0;
177 }
771fe6b9
JG		 178 /* Initialize common gart structure */
179 r = radeon_gart_init(rdev);
180 if (r) {
181 return r;
182 }
183 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 184 return radeon_gart_table_vram_alloc(rdev);
185}
186
187int rs600_gart_enable(struct radeon_device *rdev)
188{
c010f800 189 u32 tmp;
4aac0473
JG		 190 int r, i;
191
192 if (rdev->gart.table.vram.robj == NULL) {
193 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
194 return -EINVAL;
771fe6b9 195 }
4aac0473
JG		 196 r = radeon_gart_table_vram_pin(rdev);
197 if (r)
198 return r;
82568565 199 radeon_gart_restore(rdev);
c010f800
JG		 200 /* Enable bus master */
201 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
202 WREG32(R_00004C_BUS_CNTL, tmp);
771fe6b9 203 /* FIXME: setup default page */
c010f800 204 WREG32_MC(R_000100_MC_PT0_CNTL,
4f15d24a
AD		 205 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
206 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
207
771fe6b9 208 for (i = 0; i < 19; i++) {
c010f800 209 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
4f15d24a
AD		 210 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
211 S_00016C_SYSTEM_ACCESS_MODE_MASK(
212 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
213 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
214 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
215 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
216 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
217 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
771fe6b9 218 }
771fe6b9 219 /* enable first context */
c010f800 220 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
4f15d24a
AD		 221 S_000102_ENABLE_PAGE_TABLE(1) |
222 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
223
771fe6b9 224 /* disable all other contexts */
4f15d24a 225 for (i = 1; i < 8; i++)
c010f800 226 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
771fe6b9
JG		 227
228 /* setup the page table */
c010f800 229 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
4f15d24a
AD		 230 rdev->gart.table_addr);
231 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
232 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
c010f800 233 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
771fe6b9 234
4f15d24a
AD		 235 /* System context maps to VRAM space */
236 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
237 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
238
771fe6b9 239 /* enable page tables */
c010f800
JG		 240 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
241 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
242 tmp = RREG32_MC(R_000009_MC_CNTL1);
243 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
771fe6b9
JG		 244 rs600_gart_tlb_flush(rdev);
245 rdev->gart.ready = true;
246 return 0;
247}
248
249void rs600_gart_disable(struct radeon_device *rdev)
250{
4c788679
JG		 251 u32 tmp;
252 int r;
771fe6b9
JG		 253
254 /* FIXME: disable out of gart access */
c010f800
JG		 255 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
256 tmp = RREG32_MC(R_000009_MC_CNTL1);
257 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
4aac0473 258 if (rdev->gart.table.vram.robj) {
4c788679
JG		 259 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
260 if (r == 0) {
261 radeon_bo_kunmap(rdev->gart.table.vram.robj);
262 radeon_bo_unpin(rdev->gart.table.vram.robj);
263 radeon_bo_unreserve(rdev->gart.table.vram.robj);
264 }
4aac0473
JG		 265 }
266}
267
268void rs600_gart_fini(struct radeon_device *rdev)
269{
270 rs600_gart_disable(rdev);
271 radeon_gart_table_vram_free(rdev);
272 radeon_gart_fini(rdev);
771fe6b9
JG		 273}
274
275#define R600_PTE_VALID (1 << 0)
276#define R600_PTE_SYSTEM (1 << 1)
277#define R600_PTE_SNOOPED (1 << 2)
278#define R600_PTE_READABLE (1 << 5)
279#define R600_PTE_WRITEABLE (1 << 6)
280
281int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
282{
283 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
284
285 if (i < 0 || i > rdev->gart.num_gpu_pages) {
286 return -EINVAL;
287 }
288 addr = addr & 0xFFFFFFFFFFFFF000ULL;
289 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
290 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
291 writeq(addr, ((void __iomem *)ptr) + (i * 8));
292 return 0;
293}
294
7ed220d7
MD		 295int rs600_irq_set(struct radeon_device *rdev)
296{
297 uint32_t tmp = 0;
298 uint32_t mode_int = 0;
dcfdd408
AD		 299 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
300 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
301 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
302 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
7ed220d7 303
003e69f9
JG		 304 if (!rdev->irq.installed) {
305 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
306 WREG32(R_000040_GEN_INT_CNTL, 0);
307 return -EINVAL;
308 }
7ed220d7 309 if (rdev->irq.sw_int) {
c010f800 310 tmp |= S_000040_SW_INT_EN(1);
7ed220d7
MD		 311 }
312 if (rdev->irq.crtc_vblank_int[0]) {
c010f800 313 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
7ed220d7
MD		 314 }
315 if (rdev->irq.crtc_vblank_int[1]) {
c010f800 316 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
7ed220d7 317 }
dcfdd408
AD		 318 if (rdev->irq.hpd[0]) {
319 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
320 }
321 if (rdev->irq.hpd[1]) {
322 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
323 }
c010f800
JG		 324 WREG32(R_000040_GEN_INT_CNTL, tmp);
325 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
dcfdd408
AD		 326 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
327 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
7ed220d7
MD		 328 return 0;
329}
330
331static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
332{
01ceae8e
JG		 333 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
334 uint32_t irq_mask = ~C_000044_SW_INT;
dcfdd408 335 u32 tmp;
c010f800 336
01ceae8e 337 if (G_000044_DISPLAY_INT_STAT(irqs)) {
c010f800
JG		 338 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
339 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
340 WREG32(R_006534_D1MODE_VBLANK_STATUS,
341 S_006534_D1MODE_VBLANK_ACK(1));
7ed220d7 342 }
c010f800
JG		 343 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
344 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
345 S_006D34_D2MODE_VBLANK_ACK(1));
7ed220d7 346 }
dcfdd408
AD		 347 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
348 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
349 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
350 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
351 }
352 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
353 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
354 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
355 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
356 }
7ed220d7
MD		 357 } else {
358 *r500_disp_int = 0;
359 }
360
361 if (irqs) {
01ceae8e 362 WREG32(R_000044_GEN_INT_STATUS, irqs);
7ed220d7
MD		 363 }
364 return irqs & irq_mask;
365}
366
ac447df4
JG		 367void rs600_irq_disable(struct radeon_device *rdev)
368{
369 u32 tmp;
370
371 WREG32(R_000040_GEN_INT_CNTL, 0);
372 WREG32(R_006540_DxMODE_INT_MASK, 0);
373 /* Wait and acknowledge irq */
374 mdelay(1);
375 rs600_irq_ack(rdev, &tmp);
376}
377
7ed220d7
MD		 378int rs600_irq_process(struct radeon_device *rdev)
379{
3e5cb98d 380 uint32_t status, msi_rearm;
7ed220d7 381 uint32_t r500_disp_int;
d4877cf2 382 bool queue_hotplug = false;
7ed220d7
MD		 383
384 status = rs600_irq_ack(rdev, &r500_disp_int);
385 if (!status && !r500_disp_int) {
386 return IRQ_NONE;
387 }
388 while (status || r500_disp_int) {
389 /* SW interrupt */
43b19f16 390 if (G_000044_SW_INT(status))
7ed220d7 391 radeon_fence_process(rdev);
7ed220d7 392 /* Vertical blank interrupts */
c913e23a 393 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
7ed220d7 394 drm_handle_vblank(rdev->ddev, 0);
73a6d3fc 395 wake_up(&rdev->irq.vblank_queue);
c913e23a
RM		 396 }
397 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
7ed220d7 398 drm_handle_vblank(rdev->ddev, 1);
73a6d3fc 399 wake_up(&rdev->irq.vblank_queue);
c913e23a 400 }
dcfdd408 401 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
d4877cf2
AD		 402 queue_hotplug = true;
403 DRM_DEBUG("HPD1\n");
dcfdd408
AD		 404 }
405 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
d4877cf2
AD		 406 queue_hotplug = true;
407 DRM_DEBUG("HPD2\n");
dcfdd408 408 }
7ed220d7
MD		 409 status = rs600_irq_ack(rdev, &r500_disp_int);
410 }
d4877cf2
AD		 411 if (queue_hotplug)
412 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 413 if (rdev->msi_enabled) {
414 switch (rdev->family) {
415 case CHIP_RS600:
416 case CHIP_RS690:
417 case CHIP_RS740:
418 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
419 WREG32(RADEON_BUS_CNTL, msi_rearm);
420 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
421 break;
422 default:
423 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
424 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
425 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
426 break;
427 }
428 }
7ed220d7
MD		 429 return IRQ_HANDLED;
430}
431
432u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
433{
434 if (crtc == 0)
c010f800 435 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
7ed220d7 436 else
c010f800 437 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
7ed220d7
MD		 438}
439
771fe6b9
JG		 440int rs600_mc_wait_for_idle(struct radeon_device *rdev)
441{
442 unsigned i;
771fe6b9
JG		 443
444 for (i = 0; i < rdev->usec_timeout; i++) {
c010f800 445 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
771fe6b9 446 return 0;
c010f800 447 udelay(1);
771fe6b9
JG		 448 }
449 return -1;
450}
451
771fe6b9
JG		 452void rs600_gpu_init(struct radeon_device *rdev)
453{
771fe6b9 454 r100_hdp_reset(rdev);
771fe6b9 455 r420_pipes_init(rdev);
c010f800
JG		 456 /* Wait for mc idle */
457 if (rs600_mc_wait_for_idle(rdev))
458 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
771fe6b9
JG		 459}
460
d594e46a 461void rs600_mc_init(struct radeon_device *rdev)
771fe6b9 462{
d594e46a
JG		 463 u64 base;
464
771fe6b9
JG		 465 rdev->mc.vram_is_ddr = true;
466 rdev->mc.vram_width = 128;
722f2943
AD		 467 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
468 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
722f2943
AD		 469 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
470 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
d594e46a
JG		 471 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
472 base = RREG32_MC(R_000004_MC_FB_LOCATION);
473 base = G_000004_MC_FB_START(base) << 16;
474 radeon_vram_location(rdev, &rdev->mc, base);
475 radeon_gtt_location(rdev, &rdev->mc);
771fe6b9
JG		 476}
477
c93bb85b
JG		 478void rs600_bandwidth_update(struct radeon_device *rdev)
479{
480 /* FIXME: implement, should this be like rs690 ? */
481}
482
771fe6b9
JG		 483uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
484{
c010f800
JG		 485 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
486 S_000070_MC_IND_CITF_ARB0(1));
487 return RREG32(R_000074_MC_IND_DATA);
771fe6b9
JG		 488}
489
490void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
491{
c010f800
JG		 492 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
493 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
494 WREG32(R_000074_MC_IND_DATA, v);
495}
496
497void rs600_debugfs(struct radeon_device *rdev)
498{
499 if (r100_debugfs_rbbm_init(rdev))
500 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
771fe6b9 501}
3f7dc91a 502
3bc68535 503void rs600_set_safe_registers(struct radeon_device *rdev)
3f7dc91a
DA		 504{
505 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
506 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
3bc68535
JG		 507}
508
c010f800
JG		 509static void rs600_mc_program(struct radeon_device *rdev)
510{
511 struct rv515_mc_save save;
512
513 /* Stops all mc clients */
514 rv515_mc_stop(rdev, &save);
515
516 /* Wait for mc idle */
517 if (rs600_mc_wait_for_idle(rdev))
518 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
519
520 /* FIXME: What does AGP means for such chipset ? */
521 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
522 WREG32_MC(R_000006_AGP_BASE, 0);
523 WREG32_MC(R_000007_AGP_BASE_2, 0);
524 /* Program MC */
525 WREG32_MC(R_000004_MC_FB_LOCATION,
526 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
527 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
528 WREG32(R_000134_HDP_FB_LOCATION,
529 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
530
531 rv515_mc_resume(rdev, &save);
532}
533
534static int rs600_startup(struct radeon_device *rdev)
535{
536 int r;
537
538 rs600_mc_program(rdev);
539 /* Resume clock */
540 rv515_clock_startup(rdev);
541 /* Initialize GPU configuration (# pipes, ...) */
542 rs600_gpu_init(rdev);
543 /* Initialize GART (initialize after TTM so we can allocate
544 * memory through TTM but finalize after TTM) */
545 r = rs600_gart_enable(rdev);
546 if (r)
547 return r;
548 /* Enable IRQ */
c010f800 549 rs600_irq_set(rdev);
cafe6609 550 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
c010f800
JG		 551 /* 1M ring buffer */
552 r = r100_cp_init(rdev, 1024 * 1024);
553 if (r) {
554 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
555 return r;
556 }
557 r = r100_wb_init(rdev);
558 if (r)
559 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
560 r = r100_ib_init(rdev);
561 if (r) {
562 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
563 return r;
564 }
565 return 0;
566}
567
568int rs600_resume(struct radeon_device *rdev)
569{
570 /* Make sur GART are not working */
571 rs600_gart_disable(rdev);
572 /* Resume clock before doing reset */
573 rv515_clock_startup(rdev);
574 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
575 if (radeon_gpu_reset(rdev)) {
576 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
577 RREG32(R_000E40_RBBM_STATUS),
578 RREG32(R_0007C0_CP_STAT));
579 }
580 /* post */
581 atom_asic_init(rdev->mode_info.atom_context);
582 /* Resume clock after posting */
583 rv515_clock_startup(rdev);
550e2d92
DA		 584 /* Initialize surface registers */
585 radeon_surface_init(rdev);
c010f800
JG		 586 return rs600_startup(rdev);
587}
588
589int rs600_suspend(struct radeon_device *rdev)
590{
591 r100_cp_disable(rdev);
592 r100_wb_disable(rdev);
ac447df4 593 rs600_irq_disable(rdev);
c010f800
JG		 594 rs600_gart_disable(rdev);
595 return 0;
596}
597
598void rs600_fini(struct radeon_device *rdev)
599{
c010f800
JG		 600 r100_cp_fini(rdev);
601 r100_wb_fini(rdev);
602 r100_ib_fini(rdev);
603 radeon_gem_fini(rdev);
604 rs600_gart_fini(rdev);
605 radeon_irq_kms_fini(rdev);
606 radeon_fence_driver_fini(rdev);
4c788679 607 radeon_bo_fini(rdev);
c010f800
JG		 608 radeon_atombios_fini(rdev);
609 kfree(rdev->bios);
610 rdev->bios = NULL;
611}
612
3bc68535
JG		 613int rs600_init(struct radeon_device *rdev)
614{
c010f800
JG		 615 int r;
616
c010f800
JG		 617 /* Disable VGA */
618 rv515_vga_render_disable(rdev);
619 /* Initialize scratch registers */
620 radeon_scratch_init(rdev);
621 /* Initialize surface registers */
622 radeon_surface_init(rdev);
623 /* BIOS */
624 if (!radeon_get_bios(rdev)) {
625 if (ASIC_IS_AVIVO(rdev))
626 return -EINVAL;
627 }
628 if (rdev->is_atom_bios) {
629 r = radeon_atombios_init(rdev);
630 if (r)
631 return r;
632 } else {
633 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
634 return -EINVAL;
635 }
636 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
637 if (radeon_gpu_reset(rdev)) {
638 dev_warn(rdev->dev,
639 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
640 RREG32(R_000E40_RBBM_STATUS),
641 RREG32(R_0007C0_CP_STAT));
642 }
643 /* check if cards are posted or not */
72542d77
DA		 644 if (radeon_boot_test_post_card(rdev) == false)
645 return -EINVAL;
646
c010f800
JG		 647 /* Initialize clocks */
648 radeon_get_clock_info(rdev->ddev);
7433874e
RM		 649 /* Initialize power management */
650 radeon_pm_init(rdev);
d594e46a
JG		 651 /* initialize memory controller */
652 rs600_mc_init(rdev);
c010f800
JG		 653 rs600_debugfs(rdev);
654 /* Fence driver */
655 r = radeon_fence_driver_init(rdev);
656 if (r)
657 return r;
658 r = radeon_irq_kms_init(rdev);
659 if (r)
660 return r;
661 /* Memory manager */
4c788679 662 r = radeon_bo_init(rdev);
c010f800
JG		 663 if (r)
664 return r;
665 r = rs600_gart_init(rdev);
666 if (r)
667 return r;
668 rs600_set_safe_registers(rdev);
669 rdev->accel_working = true;
670 r = rs600_startup(rdev);
671 if (r) {
672 /* Somethings want wront with the accel init stop accel */
673 dev_err(rdev->dev, "Disabling GPU acceleration\n");
c010f800
JG		 674 r100_cp_fini(rdev);
675 r100_wb_fini(rdev);
676 r100_ib_fini(rdev);
677 rs600_gart_fini(rdev);
678 radeon_irq_kms_fini(rdev);
679 rdev->accel_working = false;
680 }
3f7dc91a
DA		 681 return 0;
682}
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