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drm/radeon/kms/pm: make pm spam debug only
[net-next-2.6.git] / drivers / gpu / drm / radeon / rs600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
c010f800
JG		 28/* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
771fe6b9 38#include "drmP.h"
771fe6b9 39#include "radeon.h"
e6990375 40#include "radeon_asic.h"
c010f800
JG		 41#include "atom.h"
42#include "rs600d.h"
771fe6b9 43
3f7dc91a
DA		 44#include "rs600_reg_safe.h"
45
771fe6b9
JG		 46void rs600_gpu_init(struct radeon_device *rdev);
47int rs600_mc_wait_for_idle(struct radeon_device *rdev);
771fe6b9 48
49e02b73
AD		 49void rs600_pm_misc(struct radeon_device *rdev)
50{
49e02b73
AD		 51 int requested_index = rdev->pm.requested_power_state_index;
52 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
53 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
54 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
536fcd51 55 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
49e02b73
AD		 56
57 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
58 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
59 tmp = RREG32(voltage->gpio.reg);
60 if (voltage->active_high)
61 tmp |= voltage->gpio.mask;
62 else
63 tmp &= ~(voltage->gpio.mask);
64 WREG32(voltage->gpio.reg, tmp);
65 if (voltage->delay)
66 udelay(voltage->delay);
67 } else {
68 tmp = RREG32(voltage->gpio.reg);
69 if (voltage->active_high)
70 tmp &= ~voltage->gpio.mask;
71 else
72 tmp |= voltage->gpio.mask;
73 WREG32(voltage->gpio.reg, tmp);
74 if (voltage->delay)
75 udelay(voltage->delay);
76 }
77 }
78
79 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
80 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
81 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
82 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
83 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
84 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
85 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
86 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
87 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
88 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
89 }
90 } else {
91 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
92 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
93 }
94 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
95
96 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
97 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
98 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
99 if (voltage->delay) {
100 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
101 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
102 } else
103 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
104 } else
105 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
106 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
107
108 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
109 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
110 hdp_dyn_cntl &= ~HDP_FORCEON;
111 else
112 hdp_dyn_cntl |= HDP_FORCEON;
113 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
536fcd51
AD		 114#if 0
115 /* mc_host_dyn seems to cause hangs from time to time */
49e02b73
AD		 116 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
117 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
118 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
119 else
120 mc_host_dyn_cntl |= MC_HOST_FORCEON;
121 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
536fcd51
AD		 122#endif
123 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
124 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
125 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
126 else
127 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
128 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
49e02b73
AD		 129
130 /* set pcie lanes */
131 if ((rdev->flags & RADEON_IS_PCIE) &&
132 !(rdev->flags & RADEON_IS_IGP) &&
133 rdev->asic->set_pcie_lanes &&
134 (ps->pcie_lanes !=
135 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
136 radeon_set_pcie_lanes(rdev,
137 ps->pcie_lanes);
ce8a3eb2 138 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 139 }
49e02b73
AD		 140}
141
142void rs600_pm_prepare(struct radeon_device *rdev)
143{
144 struct drm_device *ddev = rdev->ddev;
145 struct drm_crtc *crtc;
146 struct radeon_crtc *radeon_crtc;
147 u32 tmp;
148
149 /* disable any active CRTCs */
150 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
151 radeon_crtc = to_radeon_crtc(crtc);
152 if (radeon_crtc->enabled) {
153 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
154 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
155 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
156 }
157 }
158}
159
160void rs600_pm_finish(struct radeon_device *rdev)
161{
162 struct drm_device *ddev = rdev->ddev;
163 struct drm_crtc *crtc;
164 struct radeon_crtc *radeon_crtc;
165 u32 tmp;
166
167 /* enable any active CRTCs */
168 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
169 radeon_crtc = to_radeon_crtc(crtc);
170 if (radeon_crtc->enabled) {
171 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
172 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
173 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
174 }
175 }
176}
177
dcfdd408
AD		 178/* hpd for digital panel detect/disconnect */
179bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
180{
181 u32 tmp;
182 bool connected = false;
183
184 switch (hpd) {
185 case RADEON_HPD_1:
186 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
187 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
188 connected = true;
189 break;
190 case RADEON_HPD_2:
191 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
192 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
193 connected = true;
194 break;
195 default:
196 break;
197 }
198 return connected;
199}
200
201void rs600_hpd_set_polarity(struct radeon_device *rdev,
202 enum radeon_hpd_id hpd)
203{
204 u32 tmp;
205 bool connected = rs600_hpd_sense(rdev, hpd);
206
207 switch (hpd) {
208 case RADEON_HPD_1:
209 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
210 if (connected)
211 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
212 else
213 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
214 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
215 break;
216 case RADEON_HPD_2:
217 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
218 if (connected)
219 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
220 else
221 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
222 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
223 break;
224 default:
225 break;
226 }
227}
228
229void rs600_hpd_init(struct radeon_device *rdev)
230{
231 struct drm_device *dev = rdev->ddev;
232 struct drm_connector *connector;
233
234 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
235 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
236 switch (radeon_connector->hpd.hpd) {
237 case RADEON_HPD_1:
238 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
239 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
240 rdev->irq.hpd[0] = true;
241 break;
242 case RADEON_HPD_2:
243 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
244 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
245 rdev->irq.hpd[1] = true;
246 break;
247 default:
248 break;
249 }
250 }
003e69f9
JG		 251 if (rdev->irq.installed)
252 rs600_irq_set(rdev);
dcfdd408
AD		 253}
254
255void rs600_hpd_fini(struct radeon_device *rdev)
256{
257 struct drm_device *dev = rdev->ddev;
258 struct drm_connector *connector;
259
260 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
261 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
262 switch (radeon_connector->hpd.hpd) {
263 case RADEON_HPD_1:
264 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
265 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
266 rdev->irq.hpd[0] = false;
267 break;
268 case RADEON_HPD_2:
269 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
270 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
271 rdev->irq.hpd[1] = false;
272 break;
273 default:
274 break;
275 }
276 }
277}
278
90aca4d2
JG		 279void rs600_bm_disable(struct radeon_device *rdev)
280{
281 u32 tmp;
282
283 /* disable bus mastering */
284 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
285 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
286 mdelay(1);
287}
288
289int rs600_asic_reset(struct radeon_device *rdev)
290{
291 u32 status, tmp;
292
293 struct rv515_mc_save save;
294
295 /* Stops all mc clients */
296 rv515_mc_stop(rdev, &save);
297 status = RREG32(R_000E40_RBBM_STATUS);
298 if (!G_000E40_GUI_ACTIVE(status)) {
299 return 0;
300 }
301 status = RREG32(R_000E40_RBBM_STATUS);
302 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
303 /* stop CP */
304 WREG32(RADEON_CP_CSQ_CNTL, 0);
305 tmp = RREG32(RADEON_CP_RB_CNTL);
306 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
307 WREG32(RADEON_CP_RB_RPTR_WR, 0);
308 WREG32(RADEON_CP_RB_WPTR, 0);
309 WREG32(RADEON_CP_RB_CNTL, tmp);
310 pci_save_state(rdev->pdev);
311 /* disable bus mastering */
312 rs600_bm_disable(rdev);
313 /* reset GA+VAP */
314 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
315 S_0000F0_SOFT_RESET_GA(1));
316 RREG32(R_0000F0_RBBM_SOFT_RESET);
317 mdelay(500);
318 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
319 mdelay(1);
320 status = RREG32(R_000E40_RBBM_STATUS);
321 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
322 /* reset CP */
323 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
324 RREG32(R_0000F0_RBBM_SOFT_RESET);
325 mdelay(500);
326 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
327 mdelay(1);
328 status = RREG32(R_000E40_RBBM_STATUS);
329 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
330 /* reset MC */
331 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
332 RREG32(R_0000F0_RBBM_SOFT_RESET);
333 mdelay(500);
334 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
335 mdelay(1);
336 status = RREG32(R_000E40_RBBM_STATUS);
337 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
338 /* restore PCI & busmastering */
339 pci_restore_state(rdev->pdev);
340 /* Check if GPU is idle */
341 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
342 dev_err(rdev->dev, "failed to reset GPU\n");
343 rdev->gpu_lockup = true;
344 return -1;
345 }
346 rv515_mc_resume(rdev, &save);
347 dev_info(rdev->dev, "GPU reset succeed\n");
348 return 0;
349}
350
771fe6b9
JG		 351/*
352 * GART.
353 */
354void rs600_gart_tlb_flush(struct radeon_device *rdev)
355{
356 uint32_t tmp;
357
c010f800
JG		 358 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
359 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
360 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 361
c010f800 362 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
30f69f3f 363 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
c010f800 364 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
771fe6b9 365
c010f800
JG		 366 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
367 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
368 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
369 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
771fe6b9
JG		 370}
371
4aac0473 372int rs600_gart_init(struct radeon_device *rdev)
771fe6b9 373{
771fe6b9
JG		 374 int r;
375
4aac0473
JG		 376 if (rdev->gart.table.vram.robj) {
377 WARN(1, "RS600 GART already initialized.\n");
378 return 0;
379 }
771fe6b9
JG		 380 /* Initialize common gart structure */
381 r = radeon_gart_init(rdev);
382 if (r) {
383 return r;
384 }
385 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 386 return radeon_gart_table_vram_alloc(rdev);
387}
388
389int rs600_gart_enable(struct radeon_device *rdev)
390{
c010f800 391 u32 tmp;
4aac0473
JG		 392 int r, i;
393
394 if (rdev->gart.table.vram.robj == NULL) {
395 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
396 return -EINVAL;
771fe6b9 397 }
4aac0473
JG		 398 r = radeon_gart_table_vram_pin(rdev);
399 if (r)
400 return r;
82568565 401 radeon_gart_restore(rdev);
c010f800
JG		 402 /* Enable bus master */
403 tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
404 WREG32(R_00004C_BUS_CNTL, tmp);
771fe6b9 405 /* FIXME: setup default page */
c010f800 406 WREG32_MC(R_000100_MC_PT0_CNTL,
4f15d24a
AD		 407 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
408 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
409
771fe6b9 410 for (i = 0; i < 19; i++) {
c010f800 411 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
4f15d24a
AD		 412 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
413 S_00016C_SYSTEM_ACCESS_MODE_MASK(
414 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
415 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
416 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
417 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
418 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
419 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
771fe6b9 420 }
771fe6b9 421 /* enable first context */
c010f800 422 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
4f15d24a
AD		 423 S_000102_ENABLE_PAGE_TABLE(1) |
424 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
425
771fe6b9 426 /* disable all other contexts */
4f15d24a 427 for (i = 1; i < 8; i++)
c010f800 428 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
771fe6b9
JG		 429
430 /* setup the page table */
c010f800 431 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
4f15d24a
AD		 432 rdev->gart.table_addr);
433 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
434 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
c010f800 435 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
771fe6b9 436
4f15d24a
AD		 437 /* System context maps to VRAM space */
438 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
439 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
440
771fe6b9 441 /* enable page tables */
c010f800
JG		 442 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
443 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
444 tmp = RREG32_MC(R_000009_MC_CNTL1);
445 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
771fe6b9
JG		 446 rs600_gart_tlb_flush(rdev);
447 rdev->gart.ready = true;
448 return 0;
449}
450
451void rs600_gart_disable(struct radeon_device *rdev)
452{
4c788679
JG		 453 u32 tmp;
454 int r;
771fe6b9
JG		 455
456 /* FIXME: disable out of gart access */
c010f800
JG		 457 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
458 tmp = RREG32_MC(R_000009_MC_CNTL1);
459 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
4aac0473 460 if (rdev->gart.table.vram.robj) {
4c788679
JG		 461 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
462 if (r == 0) {
463 radeon_bo_kunmap(rdev->gart.table.vram.robj);
464 radeon_bo_unpin(rdev->gart.table.vram.robj);
465 radeon_bo_unreserve(rdev->gart.table.vram.robj);
466 }
4aac0473
JG		 467 }
468}
469
470void rs600_gart_fini(struct radeon_device *rdev)
471{
f9274562 472 radeon_gart_fini(rdev);
4aac0473
JG		 473 rs600_gart_disable(rdev);
474 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 475}
476
477#define R600_PTE_VALID (1 << 0)
478#define R600_PTE_SYSTEM (1 << 1)
479#define R600_PTE_SNOOPED (1 << 2)
480#define R600_PTE_READABLE (1 << 5)
481#define R600_PTE_WRITEABLE (1 << 6)
482
483int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
484{
485 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
486
487 if (i < 0 || i > rdev->gart.num_gpu_pages) {
488 return -EINVAL;
489 }
490 addr = addr & 0xFFFFFFFFFFFFF000ULL;
491 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
492 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
493 writeq(addr, ((void __iomem *)ptr) + (i * 8));
494 return 0;
495}
496
7ed220d7
MD		 497int rs600_irq_set(struct radeon_device *rdev)
498{
499 uint32_t tmp = 0;
500 uint32_t mode_int = 0;
dcfdd408
AD		 501 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
502 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
503 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
504 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
7ed220d7 505
003e69f9
JG		 506 if (!rdev->irq.installed) {
507 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
508 WREG32(R_000040_GEN_INT_CNTL, 0);
509 return -EINVAL;
510 }
7ed220d7 511 if (rdev->irq.sw_int) {
c010f800 512 tmp |= S_000040_SW_INT_EN(1);
7ed220d7 513 }
2031f77c
AD		 514 if (rdev->irq.gui_idle) {
515 tmp |= S_000040_GUI_IDLE(1);
516 }
7ed220d7 517 if (rdev->irq.crtc_vblank_int[0]) {
c010f800 518 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
7ed220d7
MD		 519 }
520 if (rdev->irq.crtc_vblank_int[1]) {
c010f800 521 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
7ed220d7 522 }
dcfdd408
AD		 523 if (rdev->irq.hpd[0]) {
524 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
525 }
526 if (rdev->irq.hpd[1]) {
527 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
528 }
c010f800
JG		 529 WREG32(R_000040_GEN_INT_CNTL, tmp);
530 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
dcfdd408
AD		 531 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
532 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
7ed220d7
MD		 533 return 0;
534}
535
536static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
537{
01ceae8e 538 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
2031f77c 539 uint32_t irq_mask = S_000044_SW_INT(1);
dcfdd408 540 u32 tmp;
c010f800 541
2031f77c
AD		 542 /* the interrupt works, but the status bit is permanently asserted */
543 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
544 if (!rdev->irq.gui_idle_acked)
545 irq_mask |= S_000044_GUI_IDLE_STAT(1);
546 }
547
01ceae8e 548 if (G_000044_DISPLAY_INT_STAT(irqs)) {
c010f800
JG		 549 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
550 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
551 WREG32(R_006534_D1MODE_VBLANK_STATUS,
552 S_006534_D1MODE_VBLANK_ACK(1));
7ed220d7 553 }
c010f800
JG		 554 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
555 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
556 S_006D34_D2MODE_VBLANK_ACK(1));
7ed220d7 557 }
dcfdd408
AD		 558 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
559 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
560 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
561 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
562 }
563 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
564 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
565 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
566 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
567 }
7ed220d7
MD		 568 } else {
569 *r500_disp_int = 0;
570 }
571
572 if (irqs) {
01ceae8e 573 WREG32(R_000044_GEN_INT_STATUS, irqs);
7ed220d7
MD		 574 }
575 return irqs & irq_mask;
576}
577
ac447df4
JG		 578void rs600_irq_disable(struct radeon_device *rdev)
579{
580 u32 tmp;
581
582 WREG32(R_000040_GEN_INT_CNTL, 0);
583 WREG32(R_006540_DxMODE_INT_MASK, 0);
584 /* Wait and acknowledge irq */
585 mdelay(1);
586 rs600_irq_ack(rdev, &tmp);
587}
588
7ed220d7
MD		 589int rs600_irq_process(struct radeon_device *rdev)
590{
3e5cb98d 591 uint32_t status, msi_rearm;
7ed220d7 592 uint32_t r500_disp_int;
d4877cf2 593 bool queue_hotplug = false;
7ed220d7 594
2031f77c
AD		 595 /* reset gui idle ack. the status bit is broken */
596 rdev->irq.gui_idle_acked = false;
597
7ed220d7
MD		 598 status = rs600_irq_ack(rdev, &r500_disp_int);
599 if (!status && !r500_disp_int) {
600 return IRQ_NONE;
601 }
602 while (status || r500_disp_int) {
603 /* SW interrupt */
43b19f16 604 if (G_000044_SW_INT(status))
7ed220d7 605 radeon_fence_process(rdev);
2031f77c
AD		 606 /* GUI idle */
607 if (G_000040_GUI_IDLE(status)) {
608 rdev->irq.gui_idle_acked = true;
609 rdev->pm.gui_idle = true;
610 wake_up(&rdev->irq.idle_queue);
611 }
7ed220d7 612 /* Vertical blank interrupts */
c913e23a 613 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
7ed220d7 614 drm_handle_vblank(rdev->ddev, 0);
839461d3 615 rdev->pm.vblank_sync = true;
73a6d3fc 616 wake_up(&rdev->irq.vblank_queue);
c913e23a
RM		 617 }
618 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
7ed220d7 619 drm_handle_vblank(rdev->ddev, 1);
839461d3 620 rdev->pm.vblank_sync = true;
73a6d3fc 621 wake_up(&rdev->irq.vblank_queue);
c913e23a 622 }
dcfdd408 623 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
d4877cf2
AD		 624 queue_hotplug = true;
625 DRM_DEBUG("HPD1\n");
dcfdd408
AD		 626 }
627 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
d4877cf2
AD		 628 queue_hotplug = true;
629 DRM_DEBUG("HPD2\n");
dcfdd408 630 }
7ed220d7
MD		 631 status = rs600_irq_ack(rdev, &r500_disp_int);
632 }
2031f77c
AD		 633 /* reset gui idle ack. the status bit is broken */
634 rdev->irq.gui_idle_acked = false;
d4877cf2
AD		 635 if (queue_hotplug)
636 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 637 if (rdev->msi_enabled) {
638 switch (rdev->family) {
639 case CHIP_RS600:
640 case CHIP_RS690:
641 case CHIP_RS740:
642 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
643 WREG32(RADEON_BUS_CNTL, msi_rearm);
644 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
645 break;
646 default:
647 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
648 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
649 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
650 break;
651 }
652 }
7ed220d7
MD		 653 return IRQ_HANDLED;
654}
655
656u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
657{
658 if (crtc == 0)
c010f800 659 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
7ed220d7 660 else
c010f800 661 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
7ed220d7
MD		 662}
663
771fe6b9
JG		 664int rs600_mc_wait_for_idle(struct radeon_device *rdev)
665{
666 unsigned i;
771fe6b9
JG		 667
668 for (i = 0; i < rdev->usec_timeout; i++) {
c010f800 669 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
771fe6b9 670 return 0;
c010f800 671 udelay(1);
771fe6b9
JG		 672 }
673 return -1;
674}
675
771fe6b9
JG		 676void rs600_gpu_init(struct radeon_device *rdev)
677{
771fe6b9 678 r420_pipes_init(rdev);
c010f800
JG		 679 /* Wait for mc idle */
680 if (rs600_mc_wait_for_idle(rdev))
681 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
771fe6b9
JG		 682}
683
d594e46a 684void rs600_mc_init(struct radeon_device *rdev)
771fe6b9 685{
d594e46a
JG		 686 u64 base;
687
51e5fcd3
JG		 688 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
689 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
771fe6b9
JG		 690 rdev->mc.vram_is_ddr = true;
691 rdev->mc.vram_width = 128;
722f2943
AD		 692 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
693 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
51e5fcd3 694 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a
JG		 695 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
696 base = RREG32_MC(R_000004_MC_FB_LOCATION);
697 base = G_000004_MC_FB_START(base) << 16;
f47299c5 698 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
d594e46a
JG		 699 radeon_vram_location(rdev, &rdev->mc, base);
700 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 701 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 702}
703
c93bb85b
JG		 704void rs600_bandwidth_update(struct radeon_device *rdev)
705{
f46c0120
AD		 706 struct drm_display_mode *mode0 = NULL;
707 struct drm_display_mode *mode1 = NULL;
708 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
709 /* FIXME: implement full support */
710
711 radeon_update_display_priority(rdev);
712
713 if (rdev->mode_info.crtcs[0]->base.enabled)
714 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
715 if (rdev->mode_info.crtcs[1]->base.enabled)
716 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
717
718 rs690_line_buffer_adjust(rdev, mode0, mode1);
719
720 if (rdev->disp_priority == 2) {
721 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
722 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
723 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
724 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
725 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
726 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
727 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
728 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
729 }
c93bb85b
JG		 730}
731
771fe6b9
JG		 732uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
733{
c010f800
JG		 734 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
735 S_000070_MC_IND_CITF_ARB0(1));
736 return RREG32(R_000074_MC_IND_DATA);
771fe6b9
JG		 737}
738
739void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
740{
c010f800
JG		 741 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
742 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
743 WREG32(R_000074_MC_IND_DATA, v);
744}
745
746void rs600_debugfs(struct radeon_device *rdev)
747{
748 if (r100_debugfs_rbbm_init(rdev))
749 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
771fe6b9 750}
3f7dc91a 751
3bc68535 752void rs600_set_safe_registers(struct radeon_device *rdev)
3f7dc91a
DA		 753{
754 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
755 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
3bc68535
JG		 756}
757
c010f800
JG		 758static void rs600_mc_program(struct radeon_device *rdev)
759{
760 struct rv515_mc_save save;
761
762 /* Stops all mc clients */
763 rv515_mc_stop(rdev, &save);
764
765 /* Wait for mc idle */
766 if (rs600_mc_wait_for_idle(rdev))
767 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
768
769 /* FIXME: What does AGP means for such chipset ? */
770 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
771 WREG32_MC(R_000006_AGP_BASE, 0);
772 WREG32_MC(R_000007_AGP_BASE_2, 0);
773 /* Program MC */
774 WREG32_MC(R_000004_MC_FB_LOCATION,
775 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
776 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
777 WREG32(R_000134_HDP_FB_LOCATION,
778 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
779
780 rv515_mc_resume(rdev, &save);
781}
782
783static int rs600_startup(struct radeon_device *rdev)
784{
785 int r;
786
787 rs600_mc_program(rdev);
788 /* Resume clock */
789 rv515_clock_startup(rdev);
790 /* Initialize GPU configuration (# pipes, ...) */
791 rs600_gpu_init(rdev);
792 /* Initialize GART (initialize after TTM so we can allocate
793 * memory through TTM but finalize after TTM) */
794 r = rs600_gart_enable(rdev);
795 if (r)
796 return r;
797 /* Enable IRQ */
c010f800 798 rs600_irq_set(rdev);
cafe6609 799 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
c010f800
JG		 800 /* 1M ring buffer */
801 r = r100_cp_init(rdev, 1024 * 1024);
802 if (r) {
803 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
804 return r;
805 }
806 r = r100_wb_init(rdev);
807 if (r)
808 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
809 r = r100_ib_init(rdev);
810 if (r) {
811 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
812 return r;
813 }
814 return 0;
815}
816
817int rs600_resume(struct radeon_device *rdev)
818{
819 /* Make sur GART are not working */
820 rs600_gart_disable(rdev);
821 /* Resume clock before doing reset */
822 rv515_clock_startup(rdev);
823 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 824 if (radeon_asic_reset(rdev)) {
c010f800
JG		 825 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
826 RREG32(R_000E40_RBBM_STATUS),
827 RREG32(R_0007C0_CP_STAT));
828 }
829 /* post */
830 atom_asic_init(rdev->mode_info.atom_context);
831 /* Resume clock after posting */
832 rv515_clock_startup(rdev);
550e2d92
DA		 833 /* Initialize surface registers */
834 radeon_surface_init(rdev);
c010f800
JG		 835 return rs600_startup(rdev);
836}
837
838int rs600_suspend(struct radeon_device *rdev)
839{
840 r100_cp_disable(rdev);
841 r100_wb_disable(rdev);
ac447df4 842 rs600_irq_disable(rdev);
c010f800
JG		 843 rs600_gart_disable(rdev);
844 return 0;
845}
846
847void rs600_fini(struct radeon_device *rdev)
848{
c010f800
JG		 849 r100_cp_fini(rdev);
850 r100_wb_fini(rdev);
851 r100_ib_fini(rdev);
852 radeon_gem_fini(rdev);
853 rs600_gart_fini(rdev);
854 radeon_irq_kms_fini(rdev);
855 radeon_fence_driver_fini(rdev);
4c788679 856 radeon_bo_fini(rdev);
c010f800
JG		 857 radeon_atombios_fini(rdev);
858 kfree(rdev->bios);
859 rdev->bios = NULL;
860}
861
3bc68535
JG		 862int rs600_init(struct radeon_device *rdev)
863{
c010f800
JG		 864 int r;
865
c010f800
JG		 866 /* Disable VGA */
867 rv515_vga_render_disable(rdev);
868 /* Initialize scratch registers */
869 radeon_scratch_init(rdev);
870 /* Initialize surface registers */
871 radeon_surface_init(rdev);
872 /* BIOS */
873 if (!radeon_get_bios(rdev)) {
874 if (ASIC_IS_AVIVO(rdev))
875 return -EINVAL;
876 }
877 if (rdev->is_atom_bios) {
878 r = radeon_atombios_init(rdev);
879 if (r)
880 return r;
881 } else {
882 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
883 return -EINVAL;
884 }
885 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 886 if (radeon_asic_reset(rdev)) {
c010f800
JG		 887 dev_warn(rdev->dev,
888 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
889 RREG32(R_000E40_RBBM_STATUS),
890 RREG32(R_0007C0_CP_STAT));
891 }
892 /* check if cards are posted or not */
72542d77
DA		 893 if (radeon_boot_test_post_card(rdev) == false)
894 return -EINVAL;
895
c010f800
JG		 896 /* Initialize clocks */
897 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 898 /* initialize memory controller */
899 rs600_mc_init(rdev);
c010f800
JG		 900 rs600_debugfs(rdev);
901 /* Fence driver */
902 r = radeon_fence_driver_init(rdev);
903 if (r)
904 return r;
905 r = radeon_irq_kms_init(rdev);
906 if (r)
907 return r;
908 /* Memory manager */
4c788679 909 r = radeon_bo_init(rdev);
c010f800
JG		 910 if (r)
911 return r;
912 r = rs600_gart_init(rdev);
913 if (r)
914 return r;
915 rs600_set_safe_registers(rdev);
916 rdev->accel_working = true;
917 r = rs600_startup(rdev);
918 if (r) {
919 /* Somethings want wront with the accel init stop accel */
920 dev_err(rdev->dev, "Disabling GPU acceleration\n");
c010f800
JG		 921 r100_cp_fini(rdev);
922 r100_wb_fini(rdev);
923 r100_ib_fini(rdev);
924 rs600_gart_fini(rdev);
925 radeon_irq_kms_fini(rdev);
926 rdev->accel_working = false;
927 }
3f7dc91a
DA		 928 return 0;
929}
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