]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/radeon/radeon_ttm.c
drm/radeon/kms: actualy set the eviction placements we choose
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_ttm.c
CommitLineData
771fe6b9
JG
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <drm/drmP.h>
37#include <drm/radeon_drm.h>
fa8a1238 38#include <linux/seq_file.h>
771fe6b9
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39#include "radeon_reg.h"
40#include "radeon.h"
41
42#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
43
fa8a1238
DA
44static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
45
771fe6b9
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46static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
47{
48 struct radeon_mman *mman;
49 struct radeon_device *rdev;
50
51 mman = container_of(bdev, struct radeon_mman, bdev);
52 rdev = container_of(mman, struct radeon_device, mman);
53 return rdev;
54}
55
56
57/*
58 * Global memory.
59 */
60static int radeon_ttm_mem_global_init(struct ttm_global_reference *ref)
61{
62 return ttm_mem_global_init(ref->object);
63}
64
65static void radeon_ttm_mem_global_release(struct ttm_global_reference *ref)
66{
67 ttm_mem_global_release(ref->object);
68}
69
70static int radeon_ttm_global_init(struct radeon_device *rdev)
71{
72 struct ttm_global_reference *global_ref;
73 int r;
74
75 rdev->mman.mem_global_referenced = false;
76 global_ref = &rdev->mman.mem_global_ref;
77 global_ref->global_type = TTM_GLOBAL_TTM_MEM;
78 global_ref->size = sizeof(struct ttm_mem_global);
79 global_ref->init = &radeon_ttm_mem_global_init;
80 global_ref->release = &radeon_ttm_mem_global_release;
81 r = ttm_global_item_ref(global_ref);
82 if (r != 0) {
a987fcaa
TH
83 DRM_ERROR("Failed setting up TTM memory accounting "
84 "subsystem.\n");
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85 return r;
86 }
a987fcaa
TH
87
88 rdev->mman.bo_global_ref.mem_glob =
89 rdev->mman.mem_global_ref.object;
90 global_ref = &rdev->mman.bo_global_ref.ref;
91 global_ref->global_type = TTM_GLOBAL_TTM_BO;
7f5f4db2 92 global_ref->size = sizeof(struct ttm_bo_global);
a987fcaa
TH
93 global_ref->init = &ttm_bo_global_init;
94 global_ref->release = &ttm_bo_global_release;
95 r = ttm_global_item_ref(global_ref);
96 if (r != 0) {
97 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
98 ttm_global_item_unref(&rdev->mman.mem_global_ref);
99 return r;
100 }
101
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102 rdev->mman.mem_global_referenced = true;
103 return 0;
104}
105
106static void radeon_ttm_global_fini(struct radeon_device *rdev)
107{
108 if (rdev->mman.mem_global_referenced) {
a987fcaa 109 ttm_global_item_unref(&rdev->mman.bo_global_ref.ref);
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110 ttm_global_item_unref(&rdev->mman.mem_global_ref);
111 rdev->mman.mem_global_referenced = false;
112 }
113}
114
115struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev);
116
117static struct ttm_backend*
118radeon_create_ttm_backend_entry(struct ttm_bo_device *bdev)
119{
120 struct radeon_device *rdev;
121
122 rdev = radeon_get_rdev(bdev);
123#if __OS_HAS_AGP
124 if (rdev->flags & RADEON_IS_AGP) {
125 return ttm_agp_backend_init(bdev, rdev->ddev->agp->bridge);
126 } else
127#endif
128 {
129 return radeon_ttm_backend_create(rdev);
130 }
131}
132
133static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
134{
135 return 0;
136}
137
138static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
139 struct ttm_mem_type_manager *man)
140{
141 struct radeon_device *rdev;
142
143 rdev = radeon_get_rdev(bdev);
144
145 switch (type) {
146 case TTM_PL_SYSTEM:
147 /* System memory */
148 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
149 man->available_caching = TTM_PL_MASK_CACHING;
150 man->default_caching = TTM_PL_FLAG_CACHED;
151 break;
152 case TTM_PL_TT:
4c788679 153 man->gpu_offset = rdev->mc.gtt_location;
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154 man->available_caching = TTM_PL_MASK_CACHING;
155 man->default_caching = TTM_PL_FLAG_CACHED;
55c93278 156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
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157#if __OS_HAS_AGP
158 if (rdev->flags & RADEON_IS_AGP) {
159 if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
160 DRM_ERROR("AGP is not enabled for memory type %u\n",
161 (unsigned)type);
162 return -EINVAL;
163 }
164 man->io_offset = rdev->mc.agp_base;
165 man->io_size = rdev->mc.gtt_size;
166 man->io_addr = NULL;
55c93278
MD
167 if (!rdev->ddev->agp->cant_use_aperture)
168 man->flags = TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
169 TTM_MEMTYPE_FLAG_MAPPABLE;
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170 man->available_caching = TTM_PL_FLAG_UNCACHED |
171 TTM_PL_FLAG_WC;
172 man->default_caching = TTM_PL_FLAG_WC;
173 } else
174#endif
175 {
176 man->io_offset = 0;
177 man->io_size = 0;
178 man->io_addr = NULL;
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179 }
180 break;
181 case TTM_PL_VRAM:
182 /* "On-card" video ram */
4c788679 183 man->gpu_offset = rdev->mc.vram_location;
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184 man->flags = TTM_MEMTYPE_FLAG_FIXED |
185 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
186 TTM_MEMTYPE_FLAG_MAPPABLE;
187 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
188 man->default_caching = TTM_PL_FLAG_WC;
189 man->io_addr = NULL;
190 man->io_offset = rdev->mc.aper_base;
191 man->io_size = rdev->mc.aper_size;
192 break;
193 default:
194 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
195 return -EINVAL;
196 }
197 return 0;
198}
199
312ea8da
JG
200static void radeon_evict_flags(struct ttm_buffer_object *bo,
201 struct ttm_placement *placement)
771fe6b9 202{
312ea8da 203 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
771fe6b9 204 switch (bo->mem.mem_type) {
312ea8da
JG
205 case TTM_PL_VRAM:
206 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
207 break;
208 case TTM_PL_TT:
771fe6b9 209 default:
312ea8da 210 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
771fe6b9 211 }
eaa5fd1a 212 *placement = rbo->placement;
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213}
214
215static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
216{
217 return 0;
218}
219
220static void radeon_move_null(struct ttm_buffer_object *bo,
221 struct ttm_mem_reg *new_mem)
222{
223 struct ttm_mem_reg *old_mem = &bo->mem;
224
225 BUG_ON(old_mem->mm_node != NULL);
226 *old_mem = *new_mem;
227 new_mem->mm_node = NULL;
228}
229
230static int radeon_move_blit(struct ttm_buffer_object *bo,
231 bool evict, int no_wait,
232 struct ttm_mem_reg *new_mem,
233 struct ttm_mem_reg *old_mem)
234{
235 struct radeon_device *rdev;
236 uint64_t old_start, new_start;
237 struct radeon_fence *fence;
238 int r;
239
240 rdev = radeon_get_rdev(bo->bdev);
241 r = radeon_fence_create(rdev, &fence);
242 if (unlikely(r)) {
243 return r;
244 }
245 old_start = old_mem->mm_node->start << PAGE_SHIFT;
246 new_start = new_mem->mm_node->start << PAGE_SHIFT;
247
248 switch (old_mem->mem_type) {
249 case TTM_PL_VRAM:
250 old_start += rdev->mc.vram_location;
251 break;
252 case TTM_PL_TT:
253 old_start += rdev->mc.gtt_location;
254 break;
255 default:
256 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
257 return -EINVAL;
258 }
259 switch (new_mem->mem_type) {
260 case TTM_PL_VRAM:
261 new_start += rdev->mc.vram_location;
262 break;
263 case TTM_PL_TT:
264 new_start += rdev->mc.gtt_location;
265 break;
266 default:
267 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
268 return -EINVAL;
269 }
270 if (!rdev->cp.ready) {
271 DRM_ERROR("Trying to move memory with CP turned off.\n");
272 return -EINVAL;
273 }
274 r = radeon_copy(rdev, old_start, new_start, new_mem->num_pages, fence);
275 /* FIXME: handle copy error */
276 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
277 evict, no_wait, new_mem);
278 radeon_fence_unref(&fence);
279 return r;
280}
281
282static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
283 bool evict, bool interruptible, bool no_wait,
284 struct ttm_mem_reg *new_mem)
285{
286 struct radeon_device *rdev;
287 struct ttm_mem_reg *old_mem = &bo->mem;
288 struct ttm_mem_reg tmp_mem;
312ea8da
JG
289 u32 placements;
290 struct ttm_placement placement;
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291 int r;
292
293 rdev = radeon_get_rdev(bo->bdev);
294 tmp_mem = *new_mem;
295 tmp_mem.mm_node = NULL;
312ea8da
JG
296 placement.fpfn = 0;
297 placement.lpfn = 0;
298 placement.num_placement = 1;
299 placement.placement = &placements;
300 placement.num_busy_placement = 1;
301 placement.busy_placement = &placements;
302 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
303 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
771fe6b9
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304 interruptible, no_wait);
305 if (unlikely(r)) {
306 return r;
307 }
df67bed9
DA
308
309 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
310 if (unlikely(r)) {
311 goto out_cleanup;
312 }
313
771fe6b9
JG
314 r = ttm_tt_bind(bo->ttm, &tmp_mem);
315 if (unlikely(r)) {
316 goto out_cleanup;
317 }
318 r = radeon_move_blit(bo, true, no_wait, &tmp_mem, old_mem);
319 if (unlikely(r)) {
320 goto out_cleanup;
321 }
322 r = ttm_bo_move_ttm(bo, true, no_wait, new_mem);
323out_cleanup:
324 if (tmp_mem.mm_node) {
a987fcaa
TH
325 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
326
327 spin_lock(&glob->lru_lock);
771fe6b9 328 drm_mm_put_block(tmp_mem.mm_node);
a987fcaa 329 spin_unlock(&glob->lru_lock);
771fe6b9
JG
330 return r;
331 }
332 return r;
333}
334
335static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
336 bool evict, bool interruptible, bool no_wait,
337 struct ttm_mem_reg *new_mem)
338{
339 struct radeon_device *rdev;
340 struct ttm_mem_reg *old_mem = &bo->mem;
341 struct ttm_mem_reg tmp_mem;
312ea8da
JG
342 struct ttm_placement placement;
343 u32 placements;
771fe6b9
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344 int r;
345
346 rdev = radeon_get_rdev(bo->bdev);
347 tmp_mem = *new_mem;
348 tmp_mem.mm_node = NULL;
312ea8da
JG
349 placement.fpfn = 0;
350 placement.lpfn = 0;
351 placement.num_placement = 1;
352 placement.placement = &placements;
353 placement.num_busy_placement = 1;
354 placement.busy_placement = &placements;
355 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
356 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait);
771fe6b9
JG
357 if (unlikely(r)) {
358 return r;
359 }
360 r = ttm_bo_move_ttm(bo, true, no_wait, &tmp_mem);
361 if (unlikely(r)) {
362 goto out_cleanup;
363 }
364 r = radeon_move_blit(bo, true, no_wait, new_mem, old_mem);
365 if (unlikely(r)) {
366 goto out_cleanup;
367 }
368out_cleanup:
369 if (tmp_mem.mm_node) {
a987fcaa
TH
370 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
371
372 spin_lock(&glob->lru_lock);
771fe6b9 373 drm_mm_put_block(tmp_mem.mm_node);
a987fcaa 374 spin_unlock(&glob->lru_lock);
771fe6b9
JG
375 return r;
376 }
377 return r;
378}
379
380static int radeon_bo_move(struct ttm_buffer_object *bo,
381 bool evict, bool interruptible, bool no_wait,
382 struct ttm_mem_reg *new_mem)
383{
384 struct radeon_device *rdev;
385 struct ttm_mem_reg *old_mem = &bo->mem;
386 int r;
387
388 rdev = radeon_get_rdev(bo->bdev);
389 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
390 radeon_move_null(bo, new_mem);
391 return 0;
392 }
393 if ((old_mem->mem_type == TTM_PL_TT &&
394 new_mem->mem_type == TTM_PL_SYSTEM) ||
395 (old_mem->mem_type == TTM_PL_SYSTEM &&
396 new_mem->mem_type == TTM_PL_TT)) {
397 /* bind is enought */
398 radeon_move_null(bo, new_mem);
399 return 0;
400 }
3ce0a23d 401 if (!rdev->cp.ready || rdev->asic->copy == NULL) {
771fe6b9 402 /* use memcpy */
1ab2e105 403 goto memcpy;
771fe6b9
JG
404 }
405
406 if (old_mem->mem_type == TTM_PL_VRAM &&
407 new_mem->mem_type == TTM_PL_SYSTEM) {
1ab2e105 408 r = radeon_move_vram_ram(bo, evict, interruptible,
771fe6b9
JG
409 no_wait, new_mem);
410 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
411 new_mem->mem_type == TTM_PL_VRAM) {
1ab2e105 412 r = radeon_move_ram_vram(bo, evict, interruptible,
771fe6b9
JG
413 no_wait, new_mem);
414 } else {
415 r = radeon_move_blit(bo, evict, no_wait, new_mem, old_mem);
771fe6b9 416 }
1ab2e105
MD
417
418 if (r) {
419memcpy:
420 r = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
421 }
422
771fe6b9
JG
423 return r;
424}
425
771fe6b9
JG
426static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
427 bool lazy, bool interruptible)
428{
429 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
430}
431
432static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
433{
434 return 0;
435}
436
437static void radeon_sync_obj_unref(void **sync_obj)
438{
439 radeon_fence_unref((struct radeon_fence **)sync_obj);
440}
441
442static void *radeon_sync_obj_ref(void *sync_obj)
443{
444 return radeon_fence_ref((struct radeon_fence *)sync_obj);
445}
446
447static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
448{
449 return radeon_fence_signaled((struct radeon_fence *)sync_obj);
450}
451
452static struct ttm_bo_driver radeon_bo_driver = {
771fe6b9
JG
453 .create_ttm_backend_entry = &radeon_create_ttm_backend_entry,
454 .invalidate_caches = &radeon_invalidate_caches,
455 .init_mem_type = &radeon_init_mem_type,
456 .evict_flags = &radeon_evict_flags,
457 .move = &radeon_bo_move,
458 .verify_access = &radeon_verify_access,
459 .sync_obj_signaled = &radeon_sync_obj_signaled,
460 .sync_obj_wait = &radeon_sync_obj_wait,
461 .sync_obj_flush = &radeon_sync_obj_flush,
462 .sync_obj_unref = &radeon_sync_obj_unref,
463 .sync_obj_ref = &radeon_sync_obj_ref,
e024e110
DA
464 .move_notify = &radeon_bo_move_notify,
465 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
771fe6b9
JG
466};
467
468int radeon_ttm_init(struct radeon_device *rdev)
469{
470 int r;
471
472 r = radeon_ttm_global_init(rdev);
473 if (r) {
474 return r;
475 }
476 /* No others user of address space so set it to 0 */
477 r = ttm_bo_device_init(&rdev->mman.bdev,
a987fcaa 478 rdev->mman.bo_global_ref.ref.object,
ad49f501
DA
479 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
480 rdev->need_dma32);
771fe6b9
JG
481 if (r) {
482 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
483 return r;
484 }
4c788679 485 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
312ea8da 486 rdev->mc.real_vram_size >> PAGE_SHIFT);
771fe6b9
JG
487 if (r) {
488 DRM_ERROR("Failed initializing VRAM heap.\n");
489 return r;
490 }
4c788679
JG
491 r = radeon_bo_create(rdev, NULL, 256 * 1024, true,
492 RADEON_GEM_DOMAIN_VRAM,
493 &rdev->stollen_vga_memory);
771fe6b9
JG
494 if (r) {
495 return r;
496 }
4c788679
JG
497 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
498 if (r)
499 return r;
500 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
501 radeon_bo_unreserve(rdev->stollen_vga_memory);
771fe6b9 502 if (r) {
4c788679 503 radeon_bo_unref(&rdev->stollen_vga_memory);
771fe6b9
JG
504 return r;
505 }
506 DRM_INFO("radeon: %uM of VRAM memory ready\n",
3ce0a23d 507 (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
4c788679 508 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
312ea8da 509 rdev->mc.gtt_size >> PAGE_SHIFT);
771fe6b9
JG
510 if (r) {
511 DRM_ERROR("Failed initializing GTT heap.\n");
512 return r;
513 }
514 DRM_INFO("radeon: %uM of GTT memory ready.\n",
3ce0a23d 515 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
771fe6b9
JG
516 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
517 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
518 }
fa8a1238
DA
519
520 r = radeon_ttm_debugfs_init(rdev);
521 if (r) {
522 DRM_ERROR("Failed to init debugfs\n");
523 return r;
524 }
771fe6b9
JG
525 return 0;
526}
527
528void radeon_ttm_fini(struct radeon_device *rdev)
529{
4c788679
JG
530 int r;
531
771fe6b9 532 if (rdev->stollen_vga_memory) {
4c788679
JG
533 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
534 if (r == 0) {
535 radeon_bo_unpin(rdev->stollen_vga_memory);
536 radeon_bo_unreserve(rdev->stollen_vga_memory);
537 }
538 radeon_bo_unref(&rdev->stollen_vga_memory);
771fe6b9
JG
539 }
540 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
541 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
542 ttm_bo_device_release(&rdev->mman.bdev);
543 radeon_gart_fini(rdev);
544 radeon_ttm_global_fini(rdev);
545 DRM_INFO("radeon: ttm finalized\n");
546}
547
548static struct vm_operations_struct radeon_ttm_vm_ops;
f0f37e2f 549static const struct vm_operations_struct *ttm_vm_ops = NULL;
771fe6b9
JG
550
551static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
552{
553 struct ttm_buffer_object *bo;
554 int r;
555
556 bo = (struct ttm_buffer_object *)vma->vm_private_data;
557 if (bo == NULL) {
558 return VM_FAULT_NOPAGE;
559 }
560 r = ttm_vm_ops->fault(vma, vmf);
561 return r;
562}
563
564int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
565{
566 struct drm_file *file_priv;
567 struct radeon_device *rdev;
568 int r;
569
570 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
571 return drm_mmap(filp, vma);
572 }
573
574 file_priv = (struct drm_file *)filp->private_data;
575 rdev = file_priv->minor->dev->dev_private;
576 if (rdev == NULL) {
577 return -EINVAL;
578 }
579 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
580 if (unlikely(r != 0)) {
581 return r;
582 }
583 if (unlikely(ttm_vm_ops == NULL)) {
584 ttm_vm_ops = vma->vm_ops;
585 radeon_ttm_vm_ops = *ttm_vm_ops;
586 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
587 }
588 vma->vm_ops = &radeon_ttm_vm_ops;
589 return 0;
590}
591
592
593/*
594 * TTM backend functions.
595 */
596struct radeon_ttm_backend {
597 struct ttm_backend backend;
598 struct radeon_device *rdev;
599 unsigned long num_pages;
600 struct page **pages;
601 struct page *dummy_read_page;
602 bool populated;
603 bool bound;
604 unsigned offset;
605};
606
607static int radeon_ttm_backend_populate(struct ttm_backend *backend,
608 unsigned long num_pages,
609 struct page **pages,
610 struct page *dummy_read_page)
611{
612 struct radeon_ttm_backend *gtt;
613
614 gtt = container_of(backend, struct radeon_ttm_backend, backend);
615 gtt->pages = pages;
616 gtt->num_pages = num_pages;
617 gtt->dummy_read_page = dummy_read_page;
618 gtt->populated = true;
619 return 0;
620}
621
622static void radeon_ttm_backend_clear(struct ttm_backend *backend)
623{
624 struct radeon_ttm_backend *gtt;
625
626 gtt = container_of(backend, struct radeon_ttm_backend, backend);
627 gtt->pages = NULL;
628 gtt->num_pages = 0;
629 gtt->dummy_read_page = NULL;
630 gtt->populated = false;
631 gtt->bound = false;
632}
633
634
635static int radeon_ttm_backend_bind(struct ttm_backend *backend,
636 struct ttm_mem_reg *bo_mem)
637{
638 struct radeon_ttm_backend *gtt;
639 int r;
640
641 gtt = container_of(backend, struct radeon_ttm_backend, backend);
642 gtt->offset = bo_mem->mm_node->start << PAGE_SHIFT;
643 if (!gtt->num_pages) {
644 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", gtt->num_pages, bo_mem, backend);
645 }
646 r = radeon_gart_bind(gtt->rdev, gtt->offset,
647 gtt->num_pages, gtt->pages);
648 if (r) {
649 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
650 gtt->num_pages, gtt->offset);
651 return r;
652 }
653 gtt->bound = true;
654 return 0;
655}
656
657static int radeon_ttm_backend_unbind(struct ttm_backend *backend)
658{
659 struct radeon_ttm_backend *gtt;
660
661 gtt = container_of(backend, struct radeon_ttm_backend, backend);
662 radeon_gart_unbind(gtt->rdev, gtt->offset, gtt->num_pages);
663 gtt->bound = false;
664 return 0;
665}
666
667static void radeon_ttm_backend_destroy(struct ttm_backend *backend)
668{
669 struct radeon_ttm_backend *gtt;
670
671 gtt = container_of(backend, struct radeon_ttm_backend, backend);
672 if (gtt->bound) {
673 radeon_ttm_backend_unbind(backend);
674 }
675 kfree(gtt);
676}
677
678static struct ttm_backend_func radeon_backend_func = {
679 .populate = &radeon_ttm_backend_populate,
680 .clear = &radeon_ttm_backend_clear,
681 .bind = &radeon_ttm_backend_bind,
682 .unbind = &radeon_ttm_backend_unbind,
683 .destroy = &radeon_ttm_backend_destroy,
684};
685
686struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
687{
688 struct radeon_ttm_backend *gtt;
689
690 gtt = kzalloc(sizeof(struct radeon_ttm_backend), GFP_KERNEL);
691 if (gtt == NULL) {
692 return NULL;
693 }
694 gtt->backend.bdev = &rdev->mman.bdev;
695 gtt->backend.flags = 0;
696 gtt->backend.func = &radeon_backend_func;
697 gtt->rdev = rdev;
698 gtt->pages = NULL;
699 gtt->num_pages = 0;
700 gtt->dummy_read_page = NULL;
701 gtt->populated = false;
702 gtt->bound = false;
703 return &gtt->backend;
704}
fa8a1238
DA
705
706#define RADEON_DEBUGFS_MEM_TYPES 2
707
fa8a1238
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708#if defined(CONFIG_DEBUG_FS)
709static int radeon_mm_dump_table(struct seq_file *m, void *data)
710{
711 struct drm_info_node *node = (struct drm_info_node *)m->private;
712 struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
713 struct drm_device *dev = node->minor->dev;
714 struct radeon_device *rdev = dev->dev_private;
715 int ret;
716 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
717
718 spin_lock(&glob->lru_lock);
719 ret = drm_mm_dump_table(m, mm);
720 spin_unlock(&glob->lru_lock);
721 return ret;
722}
723#endif
724
725static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
726{
f4e45d02
MP
727#if defined(CONFIG_DEBUG_FS)
728 static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES];
729 static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES][32];
fa8a1238
DA
730 unsigned i;
731
fa8a1238
DA
732 for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
733 if (i == 0)
734 sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
735 else
736 sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
737 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
738 radeon_mem_types_list[i].show = &radeon_mm_dump_table;
739 radeon_mem_types_list[i].driver_features = 0;
740 if (i == 0)
741 radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_VRAM].manager;
742 else
743 radeon_mem_types_list[i].data = &rdev->mman.bdev.man[TTM_PL_TT].manager;
744
745 }
746 return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES);
747
748#endif
749 return 0;
750}