[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_pm.c

/*
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Rafał Miłecki <zajec5@gmail.com>
 *          Alex Deucher <alexdeucher@gmail.com>
 */
#include "drmP.h"
#include "radeon.h"
#include "avivod.h"

#define RADEON_IDLE_LOOP_MS 100
#define RADEON_RECLOCK_DELAY_MS 200
#define RADEON_WAIT_VBLANK_TIMEOUT 200
#define RADEON_WAIT_IDLE_TIMEOUT 200

static void radeon_pm_idle_work_handler(struct work_struct *work);
static int radeon_debugfs_pm_init(struct radeon_device *rdev);

static void radeon_unmap_vram_bos(struct radeon_device *rdev)
{
	struct radeon_bo *bo, *n;

	if (list_empty(&rdev->gem.objects))
		return;

	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
		if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
			ttm_bo_unmap_virtual(&bo->tbo);
	}

	if (rdev->gart.table.vram.robj)
		ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);

	if (rdev->stollen_vga_memory)
		ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);

	if (rdev->r600_blit.shader_obj)
		ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
}

static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
{
	int i;

	if (!static_switch)
		radeon_get_power_state(rdev, rdev->pm.planned_action);

	mutex_lock(&rdev->ddev->struct_mutex);
	mutex_lock(&rdev->vram_mutex);
	mutex_lock(&rdev->cp.mutex);

	/* wait for GPU idle */
	rdev->pm.gui_idle = false;
	rdev->irq.gui_idle = true;
	radeon_irq_set(rdev);
	wait_event_interruptible_timeout(
		rdev->irq.idle_queue, rdev->pm.gui_idle,
		msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
	rdev->irq.gui_idle = false;
	radeon_irq_set(rdev);

	radeon_unmap_vram_bos(rdev);

	if (!static_switch) {
		for (i = 0; i < rdev->num_crtc; i++) {
			if (rdev->pm.active_crtcs & (1 << i)) {
				rdev->pm.req_vblank |= (1 << i);
				drm_vblank_get(rdev->ddev, i);
			}
		}
	}
	
	radeon_set_power_state(rdev, static_switch);

	if (!static_switch) {
		for (i = 0; i < rdev->num_crtc; i++) {
			if (rdev->pm.req_vblank & (1 << i)) {
				rdev->pm.req_vblank &= ~(1 << i);
				drm_vblank_put(rdev->ddev, i);
			}
		}
	}

	/* update display watermarks based on new power state */
	radeon_update_bandwidth_info(rdev);
	if (rdev->pm.active_crtc_count)
		radeon_bandwidth_update(rdev);

	rdev->pm.planned_action = PM_ACTION_NONE;

	mutex_unlock(&rdev->cp.mutex);
	mutex_unlock(&rdev->vram_mutex);
	mutex_unlock(&rdev->ddev->struct_mutex);
}

static ssize_t radeon_get_power_state_static(struct device *dev,
					     struct device_attribute *attr,
					     char *buf)
{
	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	struct radeon_device *rdev = ddev->dev_private;

	return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
			rdev->pm.current_clock_mode_index);
}

static ssize_t radeon_set_power_state_static(struct device *dev,
					     struct device_attribute *attr,
					     const char *buf,
					     size_t count)
{
	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	struct radeon_device *rdev = ddev->dev_private;
	int ps, cm;

	if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
		DRM_ERROR("Invalid power state!\n");
		return count;
	}

	mutex_lock(&rdev->pm.mutex);
	if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
	    (cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
		if ((rdev->pm.active_crtc_count > 1) &&
		    (rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) {
			DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
		} else {
			/* disable dynpm */
			rdev->pm.state = PM_STATE_DISABLED;
			rdev->pm.planned_action = PM_ACTION_NONE;
			rdev->pm.requested_power_state_index = ps;
			rdev->pm.requested_clock_mode_index = cm;
			radeon_pm_set_clocks(rdev, true);
		}
	} else
		DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
	mutex_unlock(&rdev->pm.mutex);

	return count;
}

static ssize_t radeon_get_dynpm(struct device *dev,
				struct device_attribute *attr,
				char *buf)
{
	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	struct radeon_device *rdev = ddev->dev_private;

	return snprintf(buf, PAGE_SIZE, "%s\n",
			(rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
}

static ssize_t radeon_set_dynpm(struct device *dev,
				struct device_attribute *attr,
				const char *buf,
				size_t count)
{
	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	struct radeon_device *rdev = ddev->dev_private;
	int tmp = simple_strtoul(buf, NULL, 10);

	if (tmp == 0) {
		/* update power mode info */
		radeon_pm_compute_clocks(rdev);
		/* disable dynpm */
		mutex_lock(&rdev->pm.mutex);
		rdev->pm.state = PM_STATE_DISABLED;
		rdev->pm.planned_action = PM_ACTION_NONE;
		mutex_unlock(&rdev->pm.mutex);
		DRM_INFO("radeon: dynamic power management disabled\n");
	} else if (tmp == 1) {
		if (rdev->pm.num_power_states > 1) {
			/* enable dynpm */
			mutex_lock(&rdev->pm.mutex);
			rdev->pm.state = PM_STATE_PAUSED;
			rdev->pm.planned_action = PM_ACTION_DEFAULT;
			radeon_get_power_state(rdev, rdev->pm.planned_action);
			mutex_unlock(&rdev->pm.mutex);
			/* update power mode info */
			radeon_pm_compute_clocks(rdev);
			DRM_INFO("radeon: dynamic power management enabled\n");
		} else
			DRM_ERROR("dynpm not valid on this system\n");
	} else
		DRM_ERROR("Invalid setting: %d\n", tmp);

	return count;
}

static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
static DEVICE_ATTR(dynpm, S_IRUGO | S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);


static const char *pm_state_names[4] = {
	"PM_STATE_DISABLED",
	"PM_STATE_MINIMUM",
	"PM_STATE_PAUSED",
	"PM_STATE_ACTIVE"
};

static const char *pm_state_types[5] = {
	"",
	"Powersave",
	"Battery",
	"Balanced",
	"Performance",
};

static void radeon_print_power_mode_info(struct radeon_device *rdev)
{
	int i, j;
	bool is_default;

	DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
	for (i = 0; i < rdev->pm.num_power_states; i++) {
		if (rdev->pm.default_power_state_index == i)
			is_default = true;
		else
			is_default = false;
		DRM_INFO("State %d %s %s\n", i,
			 pm_state_types[rdev->pm.power_state[i].type],
			 is_default ? "(default)" : "");
		if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
			DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
		if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
			DRM_INFO("\tSingle display only\n");
		DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
		for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
			if (rdev->flags & RADEON_IS_IGP)
				DRM_INFO("\t\t%d engine: %d\n",
					 j,
					 rdev->pm.power_state[i].clock_info[j].sclk * 10);
			else
				DRM_INFO("\t\t%d engine/memory: %d/%d\n",
					 j,
					 rdev->pm.power_state[i].clock_info[j].sclk * 10,
					 rdev->pm.power_state[i].clock_info[j].mclk * 10);
		}
	}
}

void radeon_sync_with_vblank(struct radeon_device *rdev)
{
	if (rdev->pm.active_crtcs) {
		rdev->pm.vblank_sync = false;
		wait_event_timeout(
			rdev->irq.vblank_queue, rdev->pm.vblank_sync,
			msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
	}
}

int radeon_pm_init(struct radeon_device *rdev)
{
	rdev->pm.state = PM_STATE_DISABLED;
	rdev->pm.planned_action = PM_ACTION_NONE;
	rdev->pm.can_upclock = true;
	rdev->pm.can_downclock = true;

	if (rdev->bios) {
		if (rdev->is_atom_bios)
			radeon_atombios_get_power_modes(rdev);
		else
			radeon_combios_get_power_modes(rdev);
		radeon_print_power_mode_info(rdev);
	}

	if (radeon_debugfs_pm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for PM!\n");
	}

	/* where's the best place to put this? */
	device_create_file(rdev->dev, &dev_attr_power_state);
	device_create_file(rdev->dev, &dev_attr_dynpm);

	INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);

	if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
		rdev->pm.state = PM_STATE_PAUSED;
		DRM_INFO("radeon: dynamic power management enabled\n");
	}

	DRM_INFO("radeon: power management initialized\n");

	return 0;
}

void radeon_pm_fini(struct radeon_device *rdev)
{
	if (rdev->pm.state != PM_STATE_DISABLED) {
		/* cancel work */
		cancel_delayed_work_sync(&rdev->pm.idle_work);
		/* reset default clocks */
		rdev->pm.state = PM_STATE_DISABLED;
		rdev->pm.planned_action = PM_ACTION_DEFAULT;
		radeon_pm_set_clocks(rdev, false);
	} else if ((rdev->pm.current_power_state_index !=
		    rdev->pm.default_power_state_index) ||
		   (rdev->pm.current_clock_mode_index != 0)) {
		rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
		rdev->pm.requested_clock_mode_index = 0;
		mutex_lock(&rdev->pm.mutex);
		radeon_pm_set_clocks(rdev, true);
		mutex_unlock(&rdev->pm.mutex);
	}

	device_remove_file(rdev->dev, &dev_attr_power_state);
	device_remove_file(rdev->dev, &dev_attr_dynpm);

	if (rdev->pm.i2c_bus)
		radeon_i2c_destroy(rdev->pm.i2c_bus);
}

void radeon_pm_compute_clocks(struct radeon_device *rdev)
{
	struct drm_device *ddev = rdev->ddev;
	struct drm_crtc *crtc;
	struct radeon_crtc *radeon_crtc;

	if (rdev->pm.state == PM_STATE_DISABLED)
		return;

	mutex_lock(&rdev->pm.mutex);

	rdev->pm.active_crtcs = 0;
	rdev->pm.active_crtc_count = 0;
	list_for_each_entry(crtc,
		&ddev->mode_config.crtc_list, head) {
		radeon_crtc = to_radeon_crtc(crtc);
		if (radeon_crtc->enabled) {
			rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
			rdev->pm.active_crtc_count++;
		}
	}

	if (rdev->pm.active_crtc_count > 1) {
		if (rdev->pm.state == PM_STATE_ACTIVE) {
			cancel_delayed_work(&rdev->pm.idle_work);

			rdev->pm.state = PM_STATE_PAUSED;
			rdev->pm.planned_action = PM_ACTION_UPCLOCK;
			radeon_pm_set_clocks(rdev, false);

			DRM_DEBUG("radeon: dynamic power management deactivated\n");
		}
	} else if (rdev->pm.active_crtc_count == 1) {
		/* TODO: Increase clocks if needed for current mode */

		if (rdev->pm.state == PM_STATE_MINIMUM) {
			rdev->pm.state = PM_STATE_ACTIVE;
			rdev->pm.planned_action = PM_ACTION_UPCLOCK;
			radeon_pm_set_clocks(rdev, false);

			queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
				msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
		} else if (rdev->pm.state == PM_STATE_PAUSED) {
			rdev->pm.state = PM_STATE_ACTIVE;
			queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
				msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
			DRM_DEBUG("radeon: dynamic power management activated\n");
		}
	} else { /* count == 0 */
		if (rdev->pm.state != PM_STATE_MINIMUM) {
			cancel_delayed_work(&rdev->pm.idle_work);

			rdev->pm.state = PM_STATE_MINIMUM;
			rdev->pm.planned_action = PM_ACTION_MINIMUM;
			radeon_pm_set_clocks(rdev, false);
		}
	}

	mutex_unlock(&rdev->pm.mutex);
}

bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
{
	u32 stat_crtc = 0;
	bool in_vbl = true;

	if (ASIC_IS_DCE4(rdev)) {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 2)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 3)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 4)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 5)) {
			stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
	} else if (ASIC_IS_AVIVO(rdev)) {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			stat_crtc = RREG32(D1CRTC_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			stat_crtc = RREG32(D2CRTC_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
	} else {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			stat_crtc = RREG32(RADEON_CRTC_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			stat_crtc = RREG32(RADEON_CRTC2_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
	}
	if (in_vbl == false)
		DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
			 finish ? "exit" : "entry");
	return in_vbl;
}

static void radeon_pm_idle_work_handler(struct work_struct *work)
{
	struct radeon_device *rdev;
	int resched;
	rdev = container_of(work, struct radeon_device,
				pm.idle_work.work);

	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
	mutex_lock(&rdev->pm.mutex);
	if (rdev->pm.state == PM_STATE_ACTIVE) {
		unsigned long irq_flags;
		int not_processed = 0;

		read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
		if (!list_empty(&rdev->fence_drv.emited)) {
			struct list_head *ptr;
			list_for_each(ptr, &rdev->fence_drv.emited) {
				/* count up to 3, that's enought info */
				if (++not_processed >= 3)
					break;
			}
		}
		read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);

		if (not_processed >= 3) { /* should upclock */
			if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
				rdev->pm.planned_action = PM_ACTION_NONE;
			} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
				   rdev->pm.can_upclock) {
				rdev->pm.planned_action =
					PM_ACTION_UPCLOCK;
				rdev->pm.action_timeout = jiffies +
				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
			}
		} else if (not_processed == 0) { /* should downclock */
			if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
				rdev->pm.planned_action = PM_ACTION_NONE;
			} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
				   rdev->pm.can_downclock) {
				rdev->pm.planned_action =
					PM_ACTION_DOWNCLOCK;
				rdev->pm.action_timeout = jiffies +
				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
			}
		}

		if (rdev->pm.planned_action != PM_ACTION_NONE &&
		    jiffies > rdev->pm.action_timeout) {
			radeon_pm_set_clocks(rdev, false);
		}
	}
	mutex_unlock(&rdev->pm.mutex);
	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);

	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
					msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
}

/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)

static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;

	seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
	if (rdev->asic->get_memory_clock)
		seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
	if (rdev->asic->get_pcie_lanes)
		seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));

	return 0;
}

static struct drm_info_list radeon_pm_info_list[] = {
	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
};
#endif

static int radeon_debugfs_pm_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
#else
	return 0;
#endif
}
Commit	Line	Data
7433874e RM	1	/*
	2	* Permission is hereby granted, free of charge, to any person obtaining a
	3	* copy of this software and associated documentation files (the "Software"),
	4	* to deal in the Software without restriction, including without limitation
	5	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	6	* and/or sell copies of the Software, and to permit persons to whom the
	7	* Software is furnished to do so, subject to the following conditions:
	8	*
	9	* The above copyright notice and this permission notice shall be included in
	10	* all copies or substantial portions of the Software.
	11	*
	12	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	13	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	14	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	15	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	16	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	17	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	18	* OTHER DEALINGS IN THE SOFTWARE.
	19	*
	20	* Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e	21	* Alex Deucher <alexdeucher@gmail.com>
7433874e RM	22	*/
	23	#include "drmP.h"
	24	#include "radeon.h"
f735261b	25	#include "avivod.h"
7433874e	26
c913e23a RM	27	#define RADEON_IDLE_LOOP_MS 100
c913e23a RM	28	#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc	29	#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c	30	#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a	31
c913e23a RM	32	static void radeon_pm_idle_work_handler(struct work_struct *work);
	33	static int radeon_debugfs_pm_init(struct radeon_device *rdev);
	34
5876dd24 MG	35	static void radeon_unmap_vram_bos(struct radeon_device *rdev)
	36	{
	37	struct radeon_bo bo, n;
	38
	39	if (list_empty(&rdev->gem.objects))
	40	return;
	41
	42	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
	43	if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
	44	ttm_bo_unmap_virtual(&bo->tbo);
	45	}
	46
	47	if (rdev->gart.table.vram.robj)
	48	ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
	49
	50	if (rdev->stollen_vga_memory)
	51	ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
	52
	53	if (rdev->r600_blit.shader_obj)
	54	ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
	55	}
	56
2aba631c	57	static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
a424816f	58	{
2aba631c MG	59	int i;
2aba631c MG	60
c37d230a MG	61	if (!static_switch)
	62	radeon_get_power_state(rdev, rdev->pm.planned_action);
	63
612e06ce MG	64	mutex_lock(&rdev->ddev->struct_mutex);
612e06ce MG	65	mutex_lock(&rdev->vram_mutex);
a424816f AD	66	mutex_lock(&rdev->cp.mutex);
	67
	68	/* wait for GPU idle */
	69	rdev->pm.gui_idle = false;
	70	rdev->irq.gui_idle = true;
	71	radeon_irq_set(rdev);
	72	wait_event_interruptible_timeout(
	73	rdev->irq.idle_queue, rdev->pm.gui_idle,
	74	msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
	75	rdev->irq.gui_idle = false;
	76	radeon_irq_set(rdev);
	77
5876dd24 MG	78	radeon_unmap_vram_bos(rdev);
5876dd24 MG	79
2aba631c MG	80	if (!static_switch) {
	81	for (i = 0; i < rdev->num_crtc; i++) {
	82	if (rdev->pm.active_crtcs & (1 << i)) {
	83	rdev->pm.req_vblank \|= (1 << i);
	84	drm_vblank_get(rdev->ddev, i);
	85	}
	86	}
	87	}
	88
	89	radeon_set_power_state(rdev, static_switch);
	90
	91	if (!static_switch) {
	92	for (i = 0; i < rdev->num_crtc; i++) {
	93	if (rdev->pm.req_vblank & (1 << i)) {
	94	rdev->pm.req_vblank &= ~(1 << i);
	95	drm_vblank_put(rdev->ddev, i);
	96	}
	97	}
	98	}
5876dd24	99
a424816f AD	100	/* update display watermarks based on new power state */
	101	radeon_update_bandwidth_info(rdev);
	102	if (rdev->pm.active_crtc_count)
	103	radeon_bandwidth_update(rdev);
	104
2aba631c MG	105	rdev->pm.planned_action = PM_ACTION_NONE;
2aba631c MG	106
a424816f	107	mutex_unlock(&rdev->cp.mutex);
612e06ce MG	108	mutex_unlock(&rdev->vram_mutex);
612e06ce MG	109	mutex_unlock(&rdev->ddev->struct_mutex);
a424816f AD	110	}
	111
	112	static ssize_t radeon_get_power_state_static(struct device *dev,
	113	struct device_attribute *attr,
	114	char *buf)
	115	{
	116	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	117	struct radeon_device *rdev = ddev->dev_private;
	118
	119	return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
	120	rdev->pm.current_clock_mode_index);
	121	}
	122
	123	static ssize_t radeon_set_power_state_static(struct device *dev,
	124	struct device_attribute *attr,
	125	const char *buf,
	126	size_t count)
	127	{
	128	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	129	struct radeon_device *rdev = ddev->dev_private;
	130	int ps, cm;
	131
	132	if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
	133	DRM_ERROR("Invalid power state!\n");
	134	return count;
	135	}
	136
	137	mutex_lock(&rdev->pm.mutex);
	138	if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
	139	(cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
	140	if ((rdev->pm.active_crtc_count > 1) &&
	141	(rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) {
	142	DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
	143	} else {
	144	/* disable dynpm */
	145	rdev->pm.state = PM_STATE_DISABLED;
	146	rdev->pm.planned_action = PM_ACTION_NONE;
	147	rdev->pm.requested_power_state_index = ps;
	148	rdev->pm.requested_clock_mode_index = cm;
2aba631c	149	radeon_pm_set_clocks(rdev, true);
a424816f AD	150	}
	151	} else
	152	DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
	153	mutex_unlock(&rdev->pm.mutex);
	154
	155	return count;
	156	}
	157
	158	static ssize_t radeon_get_dynpm(struct device *dev,
	159	struct device_attribute *attr,
	160	char *buf)
	161	{
	162	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	163	struct radeon_device *rdev = ddev->dev_private;
	164
	165	return snprintf(buf, PAGE_SIZE, "%s\n",
	166	(rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
	167	}
	168
	169	static ssize_t radeon_set_dynpm(struct device *dev,
	170	struct device_attribute *attr,
	171	const char *buf,
	172	size_t count)
	173	{
	174	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	175	struct radeon_device *rdev = ddev->dev_private;
	176	int tmp = simple_strtoul(buf, NULL, 10);
	177
	178	if (tmp == 0) {
	179	/* update power mode info */
	180	radeon_pm_compute_clocks(rdev);
	181	/* disable dynpm */
	182	mutex_lock(&rdev->pm.mutex);
	183	rdev->pm.state = PM_STATE_DISABLED;
	184	rdev->pm.planned_action = PM_ACTION_NONE;
	185	mutex_unlock(&rdev->pm.mutex);
	186	DRM_INFO("radeon: dynamic power management disabled\n");
	187	} else if (tmp == 1) {
	188	if (rdev->pm.num_power_states > 1) {
	189	/* enable dynpm */
	190	mutex_lock(&rdev->pm.mutex);
	191	rdev->pm.state = PM_STATE_PAUSED;
	192	rdev->pm.planned_action = PM_ACTION_DEFAULT;
	193	radeon_get_power_state(rdev, rdev->pm.planned_action);
	194	mutex_unlock(&rdev->pm.mutex);
	195	/* update power mode info */
	196	radeon_pm_compute_clocks(rdev);
	197	DRM_INFO("radeon: dynamic power management enabled\n");
	198	} else
	199	DRM_ERROR("dynpm not valid on this system\n");
	200	} else
	201	DRM_ERROR("Invalid setting: %d\n", tmp);
	202
	203	return count;
	204	}
	205
	206	static DEVICE_ATTR(power_state, S_IRUGO \| S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
	207	static DEVICE_ATTR(dynpm, S_IRUGO \| S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);
	208
	209
c913e23a RM	210	static const char *pm_state_names[4] = {
	211	"PM_STATE_DISABLED",
	212	"PM_STATE_MINIMUM",
	213	"PM_STATE_PAUSED",
	214	"PM_STATE_ACTIVE"
	215	};
7433874e	216
0ec0e74f	217	static const char *pm_state_types[5] = {
d91eeb78	218	"",
0ec0e74f AD	219	"Powersave",
	220	"Battery",
	221	"Balanced",
	222	"Performance",
	223	};
	224
56278a8e AD	225	static void radeon_print_power_mode_info(struct radeon_device *rdev)
	226	{
	227	int i, j;
	228	bool is_default;
	229
	230	DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
	231	for (i = 0; i < rdev->pm.num_power_states; i++) {
a48b9b4e	232	if (rdev->pm.default_power_state_index == i)
56278a8e AD	233	is_default = true;
	234	else
	235	is_default = false;
0ec0e74f AD	236	DRM_INFO("State %d %s %s\n", i,
	237	pm_state_types[rdev->pm.power_state[i].type],
	238	is_default ? "(default)" : "");
56278a8e	239	if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
79daedc9	240	DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
a48b9b4e AD	241	if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
a48b9b4e AD	242	DRM_INFO("\tSingle display only\n");
56278a8e AD	243	DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
	244	for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
	245	if (rdev->flags & RADEON_IS_IGP)
	246	DRM_INFO("\t\t%d engine: %d\n",
	247	j,
	248	rdev->pm.power_state[i].clock_info[j].sclk * 10);
	249	else
	250	DRM_INFO("\t\t%d engine/memory: %d/%d\n",
	251	j,
	252	rdev->pm.power_state[i].clock_info[j].sclk * 10,
	253	rdev->pm.power_state[i].clock_info[j].mclk * 10);
	254	}
	255	}
	256	}
	257
bae6b562	258	void radeon_sync_with_vblank(struct radeon_device *rdev)
d0d6cb81 RM	259	{
	260	if (rdev->pm.active_crtcs) {
	261	rdev->pm.vblank_sync = false;
	262	wait_event_timeout(
	263	rdev->irq.vblank_queue, rdev->pm.vblank_sync,
	264	msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
	265	}
	266	}
	267
7433874e RM	268	int radeon_pm_init(struct radeon_device *rdev)
7433874e RM	269	{
c913e23a RM	270	rdev->pm.state = PM_STATE_DISABLED;
c913e23a RM	271	rdev->pm.planned_action = PM_ACTION_NONE;
a48b9b4e AD	272	rdev->pm.can_upclock = true;
a48b9b4e AD	273	rdev->pm.can_downclock = true;
c913e23a	274
56278a8e AD	275	if (rdev->bios) {
	276	if (rdev->is_atom_bios)
	277	radeon_atombios_get_power_modes(rdev);
	278	else
	279	radeon_combios_get_power_modes(rdev);
	280	radeon_print_power_mode_info(rdev);
	281	}
	282
7433874e	283	if (radeon_debugfs_pm_init(rdev)) {
c142c3e5	284	DRM_ERROR("Failed to register debugfs file for PM!\n");
7433874e RM	285	}
7433874e RM	286
a424816f AD	287	/* where's the best place to put this? */
	288	device_create_file(rdev->dev, &dev_attr_power_state);
	289	device_create_file(rdev->dev, &dev_attr_dynpm);
	290
c913e23a RM	291	INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
c913e23a RM	292
90c39059	293	if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
c913e23a RM	294	rdev->pm.state = PM_STATE_PAUSED;
	295	DRM_INFO("radeon: dynamic power management enabled\n");
	296	}
	297
	298	DRM_INFO("radeon: power management initialized\n");
	299
7433874e RM	300	return 0;
	301	}
	302
29fb52ca AD	303	void radeon_pm_fini(struct radeon_device *rdev)
29fb52ca AD	304	{
58e21dff AD	305	if (rdev->pm.state != PM_STATE_DISABLED) {
	306	/* cancel work */
	307	cancel_delayed_work_sync(&rdev->pm.idle_work);
	308	/* reset default clocks */
	309	rdev->pm.state = PM_STATE_DISABLED;
	310	rdev->pm.planned_action = PM_ACTION_DEFAULT;
2aba631c	311	radeon_pm_set_clocks(rdev, false);
a424816f AD	312	} else if ((rdev->pm.current_power_state_index !=
	313	rdev->pm.default_power_state_index) \|\|
	314	(rdev->pm.current_clock_mode_index != 0)) {
	315	rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
	316	rdev->pm.requested_clock_mode_index = 0;
	317	mutex_lock(&rdev->pm.mutex);
2aba631c	318	radeon_pm_set_clocks(rdev, true);
a424816f	319	mutex_unlock(&rdev->pm.mutex);
58e21dff AD	320	}
58e21dff AD	321
a424816f AD	322	device_remove_file(rdev->dev, &dev_attr_power_state);
	323	device_remove_file(rdev->dev, &dev_attr_dynpm);
	324
29fb52ca AD	325	if (rdev->pm.i2c_bus)
	326	radeon_i2c_destroy(rdev->pm.i2c_bus);
	327	}
	328
c913e23a RM	329	void radeon_pm_compute_clocks(struct radeon_device *rdev)
	330	{
	331	struct drm_device *ddev = rdev->ddev;
a48b9b4e	332	struct drm_crtc *crtc;
c913e23a	333	struct radeon_crtc *radeon_crtc;
c913e23a RM	334
	335	if (rdev->pm.state == PM_STATE_DISABLED)
	336	return;
	337
	338	mutex_lock(&rdev->pm.mutex);
	339
	340	rdev->pm.active_crtcs = 0;
a48b9b4e AD	341	rdev->pm.active_crtc_count = 0;
	342	list_for_each_entry(crtc,
	343	&ddev->mode_config.crtc_list, head) {
	344	radeon_crtc = to_radeon_crtc(crtc);
	345	if (radeon_crtc->enabled) {
c913e23a	346	rdev->pm.active_crtcs \|= (1 << radeon_crtc->crtc_id);
a48b9b4e	347	rdev->pm.active_crtc_count++;
c913e23a RM	348	}
	349	}
	350
a48b9b4e	351	if (rdev->pm.active_crtc_count > 1) {
c913e23a	352	if (rdev->pm.state == PM_STATE_ACTIVE) {
c913e23a RM	353	cancel_delayed_work(&rdev->pm.idle_work);
	354
	355	rdev->pm.state = PM_STATE_PAUSED;
	356	rdev->pm.planned_action = PM_ACTION_UPCLOCK;
2aba631c	357	radeon_pm_set_clocks(rdev, false);
c913e23a RM	358
c913e23a RM	359	DRM_DEBUG("radeon: dynamic power management deactivated\n");
c913e23a	360	}
a48b9b4e	361	} else if (rdev->pm.active_crtc_count == 1) {
c913e23a RM	362	/* TODO: Increase clocks if needed for current mode */
	363
	364	if (rdev->pm.state == PM_STATE_MINIMUM) {
	365	rdev->pm.state = PM_STATE_ACTIVE;
	366	rdev->pm.planned_action = PM_ACTION_UPCLOCK;
2aba631c	367	radeon_pm_set_clocks(rdev, false);
c913e23a RM	368
	369	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	370	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
a48b9b4e	371	} else if (rdev->pm.state == PM_STATE_PAUSED) {
c913e23a RM	372	rdev->pm.state = PM_STATE_ACTIVE;
	373	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	374	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
	375	DRM_DEBUG("radeon: dynamic power management activated\n");
	376	}
a48b9b4e	377	} else { /* count == 0 */
c913e23a RM	378	if (rdev->pm.state != PM_STATE_MINIMUM) {
	379	cancel_delayed_work(&rdev->pm.idle_work);
	380
	381	rdev->pm.state = PM_STATE_MINIMUM;
	382	rdev->pm.planned_action = PM_ACTION_MINIMUM;
2aba631c	383	radeon_pm_set_clocks(rdev, false);
c913e23a	384	}
c913e23a	385	}
73a6d3fc RM	386
73a6d3fc RM	387	mutex_unlock(&rdev->pm.mutex);
c913e23a RM	388	}
c913e23a RM	389
bae6b562	390	bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f735261b	391	{
bae6b562	392	u32 stat_crtc = 0;
f735261b DA	393	bool in_vbl = true;
f735261b DA	394
bae6b562 AD	395	if (ASIC_IS_DCE4(rdev)) {
	396	if (rdev->pm.active_crtcs & (1 << 0)) {
	397	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
	398	if (!(stat_crtc & 1))
	399	in_vbl = false;
	400	}
	401	if (rdev->pm.active_crtcs & (1 << 1)) {
	402	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
	403	if (!(stat_crtc & 1))
	404	in_vbl = false;
	405	}
	406	if (rdev->pm.active_crtcs & (1 << 2)) {
	407	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
	408	if (!(stat_crtc & 1))
	409	in_vbl = false;
	410	}
	411	if (rdev->pm.active_crtcs & (1 << 3)) {
	412	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
	413	if (!(stat_crtc & 1))
	414	in_vbl = false;
	415	}
	416	if (rdev->pm.active_crtcs & (1 << 4)) {
	417	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
	418	if (!(stat_crtc & 1))
	419	in_vbl = false;
	420	}
	421	if (rdev->pm.active_crtcs & (1 << 5)) {
	422	stat_crtc = RREG32(EVERGREEN_CRTC_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
	423	if (!(stat_crtc & 1))
	424	in_vbl = false;
	425	}
	426	} else if (ASIC_IS_AVIVO(rdev)) {
	427	if (rdev->pm.active_crtcs & (1 << 0)) {
	428	stat_crtc = RREG32(D1CRTC_STATUS);
	429	if (!(stat_crtc & 1))
	430	in_vbl = false;
	431	}
	432	if (rdev->pm.active_crtcs & (1 << 1)) {
	433	stat_crtc = RREG32(D2CRTC_STATUS);
	434	if (!(stat_crtc & 1))
	435	in_vbl = false;
	436	}
	437	} else {
f735261b	438	if (rdev->pm.active_crtcs & (1 << 0)) {
bae6b562 AD	439	stat_crtc = RREG32(RADEON_CRTC_STATUS);
bae6b562 AD	440	if (!(stat_crtc & 1))
f735261b DA	441	in_vbl = false;
	442	}
	443	if (rdev->pm.active_crtcs & (1 << 1)) {
bae6b562 AD	444	stat_crtc = RREG32(RADEON_CRTC2_STATUS);
bae6b562 AD	445	if (!(stat_crtc & 1))
f735261b DA	446	in_vbl = false;
	447	}
	448	}
	449	if (in_vbl == false)
bae6b562 AD	450	DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 AD	451	finish ? "exit" : "entry");
f735261b DA	452	return in_vbl;
f735261b DA	453	}
c913e23a RM	454
	455	static void radeon_pm_idle_work_handler(struct work_struct *work)
	456	{
	457	struct radeon_device *rdev;
d9932a32	458	int resched;
c913e23a RM	459	rdev = container_of(work, struct radeon_device,
	460	pm.idle_work.work);
	461
d9932a32	462	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a	463	mutex_lock(&rdev->pm.mutex);
73a6d3fc	464	if (rdev->pm.state == PM_STATE_ACTIVE) {
c913e23a RM	465	unsigned long irq_flags;
	466	int not_processed = 0;
	467
	468	read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
	469	if (!list_empty(&rdev->fence_drv.emited)) {
	470	struct list_head *ptr;
	471	list_for_each(ptr, &rdev->fence_drv.emited) {
	472	/* count up to 3, that's enought info */
	473	if (++not_processed >= 3)
	474	break;
	475	}
	476	}
	477	read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
	478
	479	if (not_processed >= 3) { /* should upclock */
	480	if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
	481	rdev->pm.planned_action = PM_ACTION_NONE;
	482	} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
a48b9b4e	483	rdev->pm.can_upclock) {
c913e23a RM	484	rdev->pm.planned_action =
	485	PM_ACTION_UPCLOCK;
	486	rdev->pm.action_timeout = jiffies +
	487	msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
	488	}
	489	} else if (not_processed == 0) { /* should downclock */
	490	if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
	491	rdev->pm.planned_action = PM_ACTION_NONE;
	492	} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
a48b9b4e	493	rdev->pm.can_downclock) {
c913e23a RM	494	rdev->pm.planned_action =
	495	PM_ACTION_DOWNCLOCK;
	496	rdev->pm.action_timeout = jiffies +
	497	msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
	498	}
	499	}
	500
	501	if (rdev->pm.planned_action != PM_ACTION_NONE &&
73a6d3fc	502	jiffies > rdev->pm.action_timeout) {
2aba631c	503	radeon_pm_set_clocks(rdev, false);
c913e23a RM	504	}
	505	}
	506	mutex_unlock(&rdev->pm.mutex);
d9932a32	507	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a RM	508
	509	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	510	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
	511	}
	512
7433874e RM	513	/*
	514	* Debugfs info
	515	*/
	516	#if defined(CONFIG_DEBUG_FS)
	517
	518	static int radeon_debugfs_pm_info(struct seq_file m, void data)
	519	{
	520	struct drm_info_node node = (struct drm_info_node ) m->private;
	521	struct drm_device *dev = node->minor->dev;
	522	struct radeon_device *rdev = dev->dev_private;
	523
c913e23a	524	seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
6234077d RM	525	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
	526	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
	527	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
	528	if (rdev->asic->get_memory_clock)
	529	seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
aa5120d2 RM	530	if (rdev->asic->get_pcie_lanes)
aa5120d2 RM	531	seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e RM	532
	533	return 0;
	534	}
	535
	536	static struct drm_info_list radeon_pm_info_list[] = {
	537	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
	538	};
	539	#endif
	540
c913e23a	541	static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e RM	542	{
	543	#if defined(CONFIG_DEBUG_FS)
	544	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
	545	#else
	546	return 0;
	547	#endif
	548	}