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drm/radeon/kms: add trivial debugging for voltage
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
f735261b 25#include "avivod.h"
ce8f5370
AD		 26#ifdef CONFIG_ACPI
27#include <linux/acpi.h>
28#endif
29#include <linux/power_supply.h>
7433874e 30
c913e23a
RM		 31#define RADEON_IDLE_LOOP_MS 100
32#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 33#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c 34#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a 35
ce8f5370 36static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 37static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 38static bool radeon_pm_in_vbl(struct radeon_device *rdev);
39static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
40static void radeon_pm_update_profile(struct radeon_device *rdev);
41static void radeon_pm_set_clocks(struct radeon_device *rdev);
42
43#define ACPI_AC_CLASS "ac_adapter"
44
45#ifdef CONFIG_ACPI
46static int radeon_acpi_event(struct notifier_block *nb,
47 unsigned long val,
48 void *data)
49{
50 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
51 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
52
53 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
54 if (power_supply_is_system_supplied() > 0)
ce8a3eb2 55 DRM_DEBUG("pm: AC\n");
ce8f5370 56 else
ce8a3eb2 57 DRM_DEBUG("pm: DC\n");
ce8f5370
AD		 58
59 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
60 if (rdev->pm.profile == PM_PROFILE_AUTO) {
61 mutex_lock(&rdev->pm.mutex);
62 radeon_pm_update_profile(rdev);
63 radeon_pm_set_clocks(rdev);
64 mutex_unlock(&rdev->pm.mutex);
65 }
66 }
67 }
68
69 return NOTIFY_OK;
70}
71#endif
72
73static void radeon_pm_update_profile(struct radeon_device *rdev)
74{
75 switch (rdev->pm.profile) {
76 case PM_PROFILE_DEFAULT:
77 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
78 break;
79 case PM_PROFILE_AUTO:
80 if (power_supply_is_system_supplied() > 0) {
81 if (rdev->pm.active_crtc_count > 1)
82 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
83 else
84 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
85 } else {
86 if (rdev->pm.active_crtc_count > 1)
c9e75b21 87 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 88 else
c9e75b21 89 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 90 }
91 break;
92 case PM_PROFILE_LOW:
93 if (rdev->pm.active_crtc_count > 1)
94 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
95 else
96 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
97 break;
c9e75b21
AD		 98 case PM_PROFILE_MID:
99 if (rdev->pm.active_crtc_count > 1)
100 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
101 else
102 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
103 break;
ce8f5370
AD		 104 case PM_PROFILE_HIGH:
105 if (rdev->pm.active_crtc_count > 1)
106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
107 else
108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
109 break;
110 }
111
112 if (rdev->pm.active_crtc_count == 0) {
113 rdev->pm.requested_power_state_index =
114 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
115 rdev->pm.requested_clock_mode_index =
116 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
117 } else {
118 rdev->pm.requested_power_state_index =
119 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
120 rdev->pm.requested_clock_mode_index =
121 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
122 }
123}
c913e23a 124
5876dd24
MG		 125static void radeon_unmap_vram_bos(struct radeon_device *rdev)
126{
127 struct radeon_bo *bo, *n;
128
129 if (list_empty(&rdev->gem.objects))
130 return;
131
132 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
133 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
134 ttm_bo_unmap_virtual(&bo->tbo);
135 }
5876dd24
MG		 136}
137
ce8f5370 138static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 139{
ce8f5370
AD		 140 if (rdev->pm.active_crtcs) {
141 rdev->pm.vblank_sync = false;
142 wait_event_timeout(
143 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
144 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
145 }
146}
147
148static void radeon_set_power_state(struct radeon_device *rdev)
149{
150 u32 sclk, mclk;
92645879 151 bool misc_after = false;
ce8f5370
AD		 152
153 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
154 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
155 return;
156
157 if (radeon_gui_idle(rdev)) {
158 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
159 clock_info[rdev->pm.requested_clock_mode_index].sclk;
160 if (sclk > rdev->clock.default_sclk)
161 sclk = rdev->clock.default_sclk;
162
163 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
164 clock_info[rdev->pm.requested_clock_mode_index].mclk;
165 if (mclk > rdev->clock.default_mclk)
166 mclk = rdev->clock.default_mclk;
167
92645879
AD		 168 /* upvolt before raising clocks, downvolt after lowering clocks */
169 if (sclk < rdev->pm.current_sclk)
170 misc_after = true;
ce8f5370 171
92645879 172 radeon_sync_with_vblank(rdev);
ce8f5370 173
92645879 174 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 175 if (!radeon_pm_in_vbl(rdev))
176 return;
92645879 177 }
ce8f5370 178
92645879 179 radeon_pm_prepare(rdev);
ce8f5370 180
92645879
AD		 181 if (!misc_after)
182 /* voltage, pcie lanes, etc.*/
183 radeon_pm_misc(rdev);
184
185 /* set engine clock */
186 if (sclk != rdev->pm.current_sclk) {
187 radeon_pm_debug_check_in_vbl(rdev, false);
188 radeon_set_engine_clock(rdev, sclk);
189 radeon_pm_debug_check_in_vbl(rdev, true);
190 rdev->pm.current_sclk = sclk;
191 DRM_DEBUG("Setting: e: %d\n", sclk);
192 }
193
194 /* set memory clock */
195 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
196 radeon_pm_debug_check_in_vbl(rdev, false);
197 radeon_set_memory_clock(rdev, mclk);
198 radeon_pm_debug_check_in_vbl(rdev, true);
199 rdev->pm.current_mclk = mclk;
200 DRM_DEBUG("Setting: m: %d\n", mclk);
ce8f5370 201 }
2aba631c 202
92645879
AD		 203 if (misc_after)
204 /* voltage, pcie lanes, etc.*/
205 radeon_pm_misc(rdev);
206
207 radeon_pm_finish(rdev);
208
ce8f5370
AD		 209 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
210 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
211 } else
ce8a3eb2 212 DRM_DEBUG("pm: GUI not idle!!!\n");
ce8f5370
AD		 213}
214
215static void radeon_pm_set_clocks(struct radeon_device *rdev)
216{
217 int i;
c37d230a 218
612e06ce
MG		 219 mutex_lock(&rdev->ddev->struct_mutex);
220 mutex_lock(&rdev->vram_mutex);
a424816f 221 mutex_lock(&rdev->cp.mutex);
4f3218cb
AD		 222
223 /* gui idle int has issues on older chips it seems */
224 if (rdev->family >= CHIP_R600) {
ce8f5370
AD		 225 if (rdev->irq.installed) {
226 /* wait for GPU idle */
227 rdev->pm.gui_idle = false;
228 rdev->irq.gui_idle = true;
229 radeon_irq_set(rdev);
230 wait_event_interruptible_timeout(
231 rdev->irq.idle_queue, rdev->pm.gui_idle,
232 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
233 rdev->irq.gui_idle = false;
234 radeon_irq_set(rdev);
235 }
01434b4b 236 } else {
ce8f5370
AD		 237 if (rdev->cp.ready) {
238 struct radeon_fence *fence;
239 radeon_ring_alloc(rdev, 64);
240 radeon_fence_create(rdev, &fence);
241 radeon_fence_emit(rdev, fence);
242 radeon_ring_commit(rdev);
243 radeon_fence_wait(fence, false);
244 radeon_fence_unref(&fence);
245 }
4f3218cb 246 }
5876dd24
MG		 247 radeon_unmap_vram_bos(rdev);
248
ce8f5370 249 if (rdev->irq.installed) {
2aba631c
MG		 250 for (i = 0; i < rdev->num_crtc; i++) {
251 if (rdev->pm.active_crtcs & (1 << i)) {
252 rdev->pm.req_vblank |= (1 << i);
253 drm_vblank_get(rdev->ddev, i);
254 }
255 }
256 }
539d2418 257
ce8f5370 258 radeon_set_power_state(rdev);
2aba631c 259
ce8f5370 260 if (rdev->irq.installed) {
2aba631c
MG		 261 for (i = 0; i < rdev->num_crtc; i++) {
262 if (rdev->pm.req_vblank & (1 << i)) {
263 rdev->pm.req_vblank &= ~(1 << i);
264 drm_vblank_put(rdev->ddev, i);
265 }
266 }
267 }
5876dd24 268
a424816f
AD		 269 /* update display watermarks based on new power state */
270 radeon_update_bandwidth_info(rdev);
271 if (rdev->pm.active_crtc_count)
272 radeon_bandwidth_update(rdev);
273
ce8f5370 274 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 275
a424816f 276 mutex_unlock(&rdev->cp.mutex);
612e06ce
MG		 277 mutex_unlock(&rdev->vram_mutex);
278 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 279}
280
ce8f5370
AD		 281static ssize_t radeon_get_pm_profile(struct device *dev,
282 struct device_attribute *attr,
283 char *buf)
a424816f
AD		 284{
285 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
286 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 287 int cp = rdev->pm.profile;
a424816f 288
ce8f5370
AD		 289 return snprintf(buf, PAGE_SIZE, "%s\n",
290 (cp == PM_PROFILE_AUTO) ? "auto" :
291 (cp == PM_PROFILE_LOW) ? "low" :
292 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 293}
294
ce8f5370
AD		 295static ssize_t radeon_set_pm_profile(struct device *dev,
296 struct device_attribute *attr,
297 const char *buf,
298 size_t count)
a424816f
AD		 299{
300 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
301 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 302
303 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 304 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
305 if (strncmp("default", buf, strlen("default")) == 0)
306 rdev->pm.profile = PM_PROFILE_DEFAULT;
307 else if (strncmp("auto", buf, strlen("auto")) == 0)
308 rdev->pm.profile = PM_PROFILE_AUTO;
309 else if (strncmp("low", buf, strlen("low")) == 0)
310 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 311 else if (strncmp("mid", buf, strlen("mid")) == 0)
312 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 313 else if (strncmp("high", buf, strlen("high")) == 0)
314 rdev->pm.profile = PM_PROFILE_HIGH;
315 else {
316 DRM_ERROR("invalid power profile!\n");
317 goto fail;
a424816f 318 }
ce8f5370
AD		 319 radeon_pm_update_profile(rdev);
320 radeon_pm_set_clocks(rdev);
321 }
322fail:
a424816f
AD		 323 mutex_unlock(&rdev->pm.mutex);
324
325 return count;
326}
327
ce8f5370
AD		 328static ssize_t radeon_get_pm_method(struct device *dev,
329 struct device_attribute *attr,
330 char *buf)
a424816f
AD		 331{
332 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
333 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 334 int pm = rdev->pm.pm_method;
a424816f
AD		 335
336 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 337 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 338}
339
ce8f5370
AD		 340static ssize_t radeon_set_pm_method(struct device *dev,
341 struct device_attribute *attr,
342 const char *buf,
343 size_t count)
a424816f
AD		 344{
345 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
346 struct radeon_device *rdev = ddev->dev_private;
a424816f 347
ce8f5370
AD		 348
349 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 350 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 351 rdev->pm.pm_method = PM_METHOD_DYNPM;
352 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
353 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 354 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 355 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
356 mutex_lock(&rdev->pm.mutex);
357 rdev->pm.pm_method = PM_METHOD_PROFILE;
358 /* disable dynpm */
359 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
360 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
361 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
362 mutex_unlock(&rdev->pm.mutex);
363 } else {
364 DRM_ERROR("invalid power method!\n");
365 goto fail;
366 }
367 radeon_pm_compute_clocks(rdev);
368fail:
a424816f
AD		 369 return count;
370}
371
ce8f5370
AD		 372static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
373static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 374
ce8f5370 375void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 376{
ce8f5370
AD		 377 mutex_lock(&rdev->pm.mutex);
378 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
ce8f5370 379 mutex_unlock(&rdev->pm.mutex);
56278a8e
AD		 380}
381
ce8f5370 382void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 383{
f8ed8b4c
AD		 384 /* asic init will reset the default power state */
385 mutex_lock(&rdev->pm.mutex);
386 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
387 rdev->pm.current_clock_mode_index = 0;
388 rdev->pm.current_sclk = rdev->clock.default_sclk;
389 rdev->pm.current_mclk = rdev->clock.default_mclk;
4d60173f 390 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
f8ed8b4c 391 mutex_unlock(&rdev->pm.mutex);
ce8f5370 392 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 393}
394
7433874e
RM		 395int radeon_pm_init(struct radeon_device *rdev)
396{
26481fb1 397 int ret;
ce8f5370
AD		 398 /* default to profile method */
399 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 400 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 401 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
402 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
403 rdev->pm.dynpm_can_upclock = true;
404 rdev->pm.dynpm_can_downclock = true;
f8ed8b4c
AD		 405 rdev->pm.current_sclk = rdev->clock.default_sclk;
406 rdev->pm.current_mclk = rdev->clock.default_mclk;
c913e23a 407
56278a8e
AD		 408 if (rdev->bios) {
409 if (rdev->is_atom_bios)
410 radeon_atombios_get_power_modes(rdev);
411 else
412 radeon_combios_get_power_modes(rdev);
ce8f5370 413 radeon_pm_init_profile(rdev);
56278a8e
AD		 414 }
415
ce8f5370 416 if (rdev->pm.num_power_states > 1) {
ce8f5370 417 /* where's the best place to put these? */
26481fb1
DA		 418 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
419 if (ret)
420 DRM_ERROR("failed to create device file for power profile\n");
421 ret = device_create_file(rdev->dev, &dev_attr_power_method);
422 if (ret)
423 DRM_ERROR("failed to create device file for power method\n");
a424816f 424
ce8f5370
AD		 425#ifdef CONFIG_ACPI
426 rdev->acpi_nb.notifier_call = radeon_acpi_event;
427 register_acpi_notifier(&rdev->acpi_nb);
428#endif
429 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
c913e23a 430
ce8f5370
AD		 431 if (radeon_debugfs_pm_init(rdev)) {
432 DRM_ERROR("Failed to register debugfs file for PM!\n");
433 }
c913e23a 434
ce8f5370
AD		 435 DRM_INFO("radeon: power management initialized\n");
436 }
c913e23a 437
7433874e
RM		 438 return 0;
439}
440
29fb52ca
AD		 441void radeon_pm_fini(struct radeon_device *rdev)
442{
ce8f5370 443 if (rdev->pm.num_power_states > 1) {
a424816f 444 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 445 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
446 rdev->pm.profile = PM_PROFILE_DEFAULT;
447 radeon_pm_update_profile(rdev);
448 radeon_pm_set_clocks(rdev);
449 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
450 /* cancel work */
451 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
452 /* reset default clocks */
453 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
454 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
455 radeon_pm_set_clocks(rdev);
456 }
a424816f 457 mutex_unlock(&rdev->pm.mutex);
58e21dff 458
ce8f5370
AD		 459 device_remove_file(rdev->dev, &dev_attr_power_profile);
460 device_remove_file(rdev->dev, &dev_attr_power_method);
461#ifdef CONFIG_ACPI
462 unregister_acpi_notifier(&rdev->acpi_nb);
463#endif
464 }
a424816f 465
29fb52ca
AD		 466 if (rdev->pm.i2c_bus)
467 radeon_i2c_destroy(rdev->pm.i2c_bus);
468}
469
c913e23a
RM		 470void radeon_pm_compute_clocks(struct radeon_device *rdev)
471{
472 struct drm_device *ddev = rdev->ddev;
a48b9b4e 473 struct drm_crtc *crtc;
c913e23a 474 struct radeon_crtc *radeon_crtc;
c913e23a 475
ce8f5370
AD		 476 if (rdev->pm.num_power_states < 2)
477 return;
478
c913e23a
RM		 479 mutex_lock(&rdev->pm.mutex);
480
481 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 482 rdev->pm.active_crtc_count = 0;
483 list_for_each_entry(crtc,
484 &ddev->mode_config.crtc_list, head) {
485 radeon_crtc = to_radeon_crtc(crtc);
486 if (radeon_crtc->enabled) {
c913e23a 487 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 488 rdev->pm.active_crtc_count++;
c913e23a
RM		 489 }
490 }
491
ce8f5370
AD		 492 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
493 radeon_pm_update_profile(rdev);
494 radeon_pm_set_clocks(rdev);
495 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
496 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
497 if (rdev->pm.active_crtc_count > 1) {
498 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
499 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
500
501 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
502 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
503 radeon_pm_get_dynpm_state(rdev);
504 radeon_pm_set_clocks(rdev);
505
506 DRM_DEBUG("radeon: dynamic power management deactivated\n");
507 }
508 } else if (rdev->pm.active_crtc_count == 1) {
509 /* TODO: Increase clocks if needed for current mode */
510
511 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
512 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
513 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
514 radeon_pm_get_dynpm_state(rdev);
515 radeon_pm_set_clocks(rdev);
516
517 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
518 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
519 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
520 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
521 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
522 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
523 DRM_DEBUG("radeon: dynamic power management activated\n");
524 }
525 } else { /* count == 0 */
526 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
527 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
528
529 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
530 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
531 radeon_pm_get_dynpm_state(rdev);
532 radeon_pm_set_clocks(rdev);
533 }
534 }
c913e23a 535 }
c913e23a 536 }
73a6d3fc
RM		 537
538 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 539}
540
ce8f5370 541static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 542{
539d2418 543 u32 stat_crtc = 0, vbl = 0, position = 0;
f735261b
DA		 544 bool in_vbl = true;
545
bae6b562
AD		 546 if (ASIC_IS_DCE4(rdev)) {
547 if (rdev->pm.active_crtcs & (1 << 0)) {
539d2418
AD		 548 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
549 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
550 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
551 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 552 }
553 if (rdev->pm.active_crtcs & (1 << 1)) {
539d2418
AD		 554 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
555 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
556 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
557 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 558 }
559 if (rdev->pm.active_crtcs & (1 << 2)) {
539d2418
AD		 560 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
561 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
562 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
563 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 564 }
565 if (rdev->pm.active_crtcs & (1 << 3)) {
539d2418
AD		 566 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
567 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
568 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
569 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 570 }
571 if (rdev->pm.active_crtcs & (1 << 4)) {
539d2418
AD		 572 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
573 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
574 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
575 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 576 }
577 if (rdev->pm.active_crtcs & (1 << 5)) {
539d2418
AD		 578 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
579 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
580 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
581 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
bae6b562
AD		 582 }
583 } else if (ASIC_IS_AVIVO(rdev)) {
584 if (rdev->pm.active_crtcs & (1 << 0)) {
539d2418
AD		 585 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
586 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
bae6b562
AD		 587 }
588 if (rdev->pm.active_crtcs & (1 << 1)) {
539d2418
AD		 589 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
590 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
bae6b562 591 }
539d2418
AD		 592 if (position < vbl && position > 1)
593 in_vbl = false;
bae6b562 594 } else {
f735261b 595 if (rdev->pm.active_crtcs & (1 << 0)) {
bae6b562
AD		 596 stat_crtc = RREG32(RADEON_CRTC_STATUS);
597 if (!(stat_crtc & 1))
f735261b
DA		 598 in_vbl = false;
599 }
600 if (rdev->pm.active_crtcs & (1 << 1)) {
bae6b562
AD		 601 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
602 if (!(stat_crtc & 1))
f735261b
DA		 603 in_vbl = false;
604 }
605 }
f81f2024 606
539d2418
AD		 607 if (position < vbl && position > 1)
608 in_vbl = false;
609
f81f2024
MG		 610 return in_vbl;
611}
612
ce8f5370 613static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 614{
615 u32 stat_crtc = 0;
616 bool in_vbl = radeon_pm_in_vbl(rdev);
617
f735261b 618 if (in_vbl == false)
ce8a3eb2 619 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 620 finish ? "exit" : "entry");
f735261b
DA		 621 return in_vbl;
622}
c913e23a 623
ce8f5370 624static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 625{
626 struct radeon_device *rdev;
d9932a32 627 int resched;
c913e23a 628 rdev = container_of(work, struct radeon_device,
ce8f5370 629 pm.dynpm_idle_work.work);
c913e23a 630
d9932a32 631 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 632 mutex_lock(&rdev->pm.mutex);
ce8f5370 633 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a
RM		 634 unsigned long irq_flags;
635 int not_processed = 0;
636
637 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
638 if (!list_empty(&rdev->fence_drv.emited)) {
639 struct list_head *ptr;
640 list_for_each(ptr, &rdev->fence_drv.emited) {
641 /* count up to 3, that's enought info */
642 if (++not_processed >= 3)
643 break;
644 }
645 }
646 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
647
648 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 649 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
650 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
651 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
652 rdev->pm.dynpm_can_upclock) {
653 rdev->pm.dynpm_planned_action =
654 DYNPM_ACTION_UPCLOCK;
655 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 656 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
657 }
658 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 659 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
660 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
661 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
662 rdev->pm.dynpm_can_downclock) {
663 rdev->pm.dynpm_planned_action =
664 DYNPM_ACTION_DOWNCLOCK;
665 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 666 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
667 }
668 }
669
d7311171
AD		 670 /* Note, radeon_pm_set_clocks is called with static_switch set
671 * to false since we want to wait for vbl to avoid flicker.
672 */
ce8f5370
AD		 673 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
674 jiffies > rdev->pm.dynpm_action_timeout) {
675 radeon_pm_get_dynpm_state(rdev);
676 radeon_pm_set_clocks(rdev);
c913e23a
RM		 677 }
678 }
679 mutex_unlock(&rdev->pm.mutex);
d9932a32 680 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a 681
ce8f5370 682 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
c913e23a
RM		 683 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
684}
685
7433874e
RM		 686/*
687 * Debugfs info
688 */
689#if defined(CONFIG_DEBUG_FS)
690
691static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
692{
693 struct drm_info_node *node = (struct drm_info_node *) m->private;
694 struct drm_device *dev = node->minor->dev;
695 struct radeon_device *rdev = dev->dev_private;
696
6234077d
RM		 697 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
698 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
699 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
700 if (rdev->asic->get_memory_clock)
701 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 702 if (rdev->pm.current_vddc)
703 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
aa5120d2
RM		 704 if (rdev->asic->get_pcie_lanes)
705 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 706
707 return 0;
708}
709
710static struct drm_info_list radeon_pm_info_list[] = {
711 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
712};
713#endif
714
c913e23a 715static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 716{
717#if defined(CONFIG_DEBUG_FS)
718 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
719#else
720 return 0;
721#endif
722}
Clone of davem's net-next-2.6 tree