[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_pm.c

/*
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Rafał Miłecki <zajec5@gmail.com>
 *          Alex Deucher <alexdeucher@gmail.com>
 */
#include "drmP.h"
#include "radeon.h"
#include "avivod.h"

#define RADEON_IDLE_LOOP_MS 100
#define RADEON_RECLOCK_DELAY_MS 200
#define RADEON_WAIT_VBLANK_TIMEOUT 200
#define RADEON_WAIT_IDLE_TIMEOUT 200

static void radeon_pm_idle_work_handler(struct work_struct *work);
static int radeon_debugfs_pm_init(struct radeon_device *rdev);

static void radeon_unmap_vram_bos(struct radeon_device *rdev)
{
	struct radeon_bo *bo, *n;

	if (list_empty(&rdev->gem.objects))
		return;

	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
		if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
			ttm_bo_unmap_virtual(&bo->tbo);
	}

	if (rdev->gart.table.vram.robj)
		ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);

	if (rdev->stollen_vga_memory)
		ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);

	if (rdev->r600_blit.shader_obj)
		ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
}

static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
{
	int i;

	if (!static_switch)
		radeon_get_power_state(rdev, rdev->pm.planned_action);

	mutex_lock(&rdev->ddev->struct_mutex);
	mutex_lock(&rdev->vram_mutex);
	mutex_lock(&rdev->cp.mutex);

	/* gui idle int has issues on older chips it seems */
	if (rdev->family >= CHIP_R600) {
		/* wait for GPU idle */
		rdev->pm.gui_idle = false;
		rdev->irq.gui_idle = true;
		radeon_irq_set(rdev);
		wait_event_interruptible_timeout(
			rdev->irq.idle_queue, rdev->pm.gui_idle,
			msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
		rdev->irq.gui_idle = false;
		radeon_irq_set(rdev);
	} else {
		struct radeon_fence *fence;
		radeon_ring_alloc(rdev, 64);
		radeon_fence_create(rdev, &fence);
		radeon_fence_emit(rdev, fence);
		radeon_ring_commit(rdev);
		radeon_fence_wait(fence, false);
		radeon_fence_unref(&fence);
	}
	radeon_unmap_vram_bos(rdev);

	if (!static_switch) {
		for (i = 0; i < rdev->num_crtc; i++) {
			if (rdev->pm.active_crtcs & (1 << i)) {
				rdev->pm.req_vblank |= (1 << i);
				drm_vblank_get(rdev->ddev, i);
			}
		}
	}

	radeon_set_power_state(rdev, static_switch);

	if (!static_switch) {
		for (i = 0; i < rdev->num_crtc; i++) {
			if (rdev->pm.req_vblank & (1 << i)) {
				rdev->pm.req_vblank &= ~(1 << i);
				drm_vblank_put(rdev->ddev, i);
			}
		}
	}

	/* update display watermarks based on new power state */
	radeon_update_bandwidth_info(rdev);
	if (rdev->pm.active_crtc_count)
		radeon_bandwidth_update(rdev);

	rdev->pm.planned_action = PM_ACTION_NONE;

	mutex_unlock(&rdev->cp.mutex);
	mutex_unlock(&rdev->vram_mutex);
	mutex_unlock(&rdev->ddev->struct_mutex);
}

static ssize_t radeon_get_power_state_static(struct device *dev,
					     struct device_attribute *attr,
					     char *buf)
{
	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	struct radeon_device *rdev = ddev->dev_private;

	return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
			rdev->pm.current_clock_mode_index);
}

static ssize_t radeon_set_power_state_static(struct device *dev,
					     struct device_attribute *attr,
					     const char *buf,
					     size_t count)
{
	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	struct radeon_device *rdev = ddev->dev_private;
	int ps, cm;

	if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
		DRM_ERROR("Invalid power state!\n");
		return count;
	}

	mutex_lock(&rdev->pm.mutex);
	if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
	    (cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
		if ((rdev->pm.active_crtc_count > 1) &&
		    (rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) {
			DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
		} else {
			/* disable dynpm */
			rdev->pm.state = PM_STATE_DISABLED;
			rdev->pm.planned_action = PM_ACTION_NONE;
			rdev->pm.requested_power_state_index = ps;
			rdev->pm.requested_clock_mode_index = cm;
			radeon_pm_set_clocks(rdev, true);
		}
	} else
		DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
	mutex_unlock(&rdev->pm.mutex);

	return count;
}

static ssize_t radeon_get_dynpm(struct device *dev,
				struct device_attribute *attr,
				char *buf)
{
	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	struct radeon_device *rdev = ddev->dev_private;

	return snprintf(buf, PAGE_SIZE, "%s\n",
			(rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
}

static ssize_t radeon_set_dynpm(struct device *dev,
				struct device_attribute *attr,
				const char *buf,
				size_t count)
{
	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	struct radeon_device *rdev = ddev->dev_private;
	int tmp = simple_strtoul(buf, NULL, 10);

	if (tmp == 0) {
		/* update power mode info */
		radeon_pm_compute_clocks(rdev);
		/* disable dynpm */
		mutex_lock(&rdev->pm.mutex);
		rdev->pm.state = PM_STATE_DISABLED;
		rdev->pm.planned_action = PM_ACTION_NONE;
		mutex_unlock(&rdev->pm.mutex);
		DRM_INFO("radeon: dynamic power management disabled\n");
	} else if (tmp == 1) {
		if (rdev->pm.num_power_states > 1) {
			/* enable dynpm */
			mutex_lock(&rdev->pm.mutex);
			rdev->pm.state = PM_STATE_PAUSED;
			rdev->pm.planned_action = PM_ACTION_DEFAULT;
			radeon_get_power_state(rdev, rdev->pm.planned_action);
			mutex_unlock(&rdev->pm.mutex);
			/* update power mode info */
			radeon_pm_compute_clocks(rdev);
			DRM_INFO("radeon: dynamic power management enabled\n");
		} else
			DRM_ERROR("dynpm not valid on this system\n");
	} else
		DRM_ERROR("Invalid setting: %d\n", tmp);

	return count;
}

static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
static DEVICE_ATTR(dynpm, S_IRUGO | S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);


static const char *pm_state_names[4] = {
	"PM_STATE_DISABLED",
	"PM_STATE_MINIMUM",
	"PM_STATE_PAUSED",
	"PM_STATE_ACTIVE"
};

static const char *pm_state_types[5] = {
	"",
	"Powersave",
	"Battery",
	"Balanced",
	"Performance",
};

static void radeon_print_power_mode_info(struct radeon_device *rdev)
{
	int i, j;
	bool is_default;

	DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
	for (i = 0; i < rdev->pm.num_power_states; i++) {
		if (rdev->pm.default_power_state_index == i)
			is_default = true;
		else
			is_default = false;
		DRM_INFO("State %d %s %s\n", i,
			 pm_state_types[rdev->pm.power_state[i].type],
			 is_default ? "(default)" : "");
		if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
			DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
		if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
			DRM_INFO("\tSingle display only\n");
		DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
		for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
			if (rdev->flags & RADEON_IS_IGP)
				DRM_INFO("\t\t%d engine: %d\n",
					 j,
					 rdev->pm.power_state[i].clock_info[j].sclk * 10);
			else
				DRM_INFO("\t\t%d engine/memory: %d/%d\n",
					 j,
					 rdev->pm.power_state[i].clock_info[j].sclk * 10,
					 rdev->pm.power_state[i].clock_info[j].mclk * 10);
		}
	}
}

void radeon_sync_with_vblank(struct radeon_device *rdev)
{
	if (rdev->pm.active_crtcs) {
		rdev->pm.vblank_sync = false;
		wait_event_timeout(
			rdev->irq.vblank_queue, rdev->pm.vblank_sync,
			msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
	}
}

int radeon_pm_init(struct radeon_device *rdev)
{
	rdev->pm.state = PM_STATE_DISABLED;
	rdev->pm.planned_action = PM_ACTION_NONE;
	rdev->pm.can_upclock = true;
	rdev->pm.can_downclock = true;

	if (rdev->bios) {
		if (rdev->is_atom_bios)
			radeon_atombios_get_power_modes(rdev);
		else
			radeon_combios_get_power_modes(rdev);
		radeon_print_power_mode_info(rdev);
	}

	if (radeon_debugfs_pm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for PM!\n");
	}

	/* where's the best place to put this? */
	device_create_file(rdev->dev, &dev_attr_power_state);
	device_create_file(rdev->dev, &dev_attr_dynpm);

	INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);

	if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
		rdev->pm.state = PM_STATE_PAUSED;
		DRM_INFO("radeon: dynamic power management enabled\n");
	}

	DRM_INFO("radeon: power management initialized\n");

	return 0;
}

void radeon_pm_fini(struct radeon_device *rdev)
{
	if (rdev->pm.state != PM_STATE_DISABLED) {
		/* cancel work */
		cancel_delayed_work_sync(&rdev->pm.idle_work);
		/* reset default clocks */
		rdev->pm.state = PM_STATE_DISABLED;
		rdev->pm.planned_action = PM_ACTION_DEFAULT;
		radeon_pm_set_clocks(rdev, false);
	} else if ((rdev->pm.current_power_state_index !=
		    rdev->pm.default_power_state_index) ||
		   (rdev->pm.current_clock_mode_index != 0)) {
		rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
		rdev->pm.requested_clock_mode_index = 0;
		mutex_lock(&rdev->pm.mutex);
		radeon_pm_set_clocks(rdev, true);
		mutex_unlock(&rdev->pm.mutex);
	}

	device_remove_file(rdev->dev, &dev_attr_power_state);
	device_remove_file(rdev->dev, &dev_attr_dynpm);

	if (rdev->pm.i2c_bus)
		radeon_i2c_destroy(rdev->pm.i2c_bus);
}

void radeon_pm_compute_clocks(struct radeon_device *rdev)
{
	struct drm_device *ddev = rdev->ddev;
	struct drm_crtc *crtc;
	struct radeon_crtc *radeon_crtc;

	if (rdev->pm.state == PM_STATE_DISABLED)
		return;

	mutex_lock(&rdev->pm.mutex);

	rdev->pm.active_crtcs = 0;
	rdev->pm.active_crtc_count = 0;
	list_for_each_entry(crtc,
		&ddev->mode_config.crtc_list, head) {
		radeon_crtc = to_radeon_crtc(crtc);
		if (radeon_crtc->enabled) {
			rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
			rdev->pm.active_crtc_count++;
		}
	}

	if (rdev->pm.active_crtc_count > 1) {
		if (rdev->pm.state == PM_STATE_ACTIVE) {
			cancel_delayed_work(&rdev->pm.idle_work);

			rdev->pm.state = PM_STATE_PAUSED;
			rdev->pm.planned_action = PM_ACTION_UPCLOCK;
			radeon_pm_set_clocks(rdev, false);

			DRM_DEBUG("radeon: dynamic power management deactivated\n");
		}
	} else if (rdev->pm.active_crtc_count == 1) {
		/* TODO: Increase clocks if needed for current mode */

		if (rdev->pm.state == PM_STATE_MINIMUM) {
			rdev->pm.state = PM_STATE_ACTIVE;
			rdev->pm.planned_action = PM_ACTION_UPCLOCK;
			radeon_pm_set_clocks(rdev, false);

			queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
				msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
		} else if (rdev->pm.state == PM_STATE_PAUSED) {
			rdev->pm.state = PM_STATE_ACTIVE;
			queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
				msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
			DRM_DEBUG("radeon: dynamic power management activated\n");
		}
	} else { /* count == 0 */
		if (rdev->pm.state != PM_STATE_MINIMUM) {
			cancel_delayed_work(&rdev->pm.idle_work);

			rdev->pm.state = PM_STATE_MINIMUM;
			rdev->pm.planned_action = PM_ACTION_MINIMUM;
			radeon_pm_set_clocks(rdev, false);
		}
	}

	mutex_unlock(&rdev->pm.mutex);
}

bool radeon_pm_in_vbl(struct radeon_device *rdev)
{
	u32 stat_crtc = 0, vbl = 0, position = 0;
	bool in_vbl = true;

	if (ASIC_IS_DCE4(rdev)) {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
				     EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
					  EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
				     EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
					  EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
		}
		if (rdev->pm.active_crtcs & (1 << 2)) {
			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
				     EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
					  EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
		}
		if (rdev->pm.active_crtcs & (1 << 3)) {
			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
				     EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
					  EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
		}
		if (rdev->pm.active_crtcs & (1 << 4)) {
			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
				     EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
					  EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
		}
		if (rdev->pm.active_crtcs & (1 << 5)) {
			vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
				     EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
			position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
					  EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
		}
	} else if (ASIC_IS_AVIVO(rdev)) {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
			position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
			position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
		}
		if (position < vbl && position > 1)
			in_vbl = false;
	} else {
		if (rdev->pm.active_crtcs & (1 << 0)) {
			stat_crtc = RREG32(RADEON_CRTC_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
		if (rdev->pm.active_crtcs & (1 << 1)) {
			stat_crtc = RREG32(RADEON_CRTC2_STATUS);
			if (!(stat_crtc & 1))
				in_vbl = false;
		}
	}

	if (position < vbl && position > 1)
		in_vbl = false;

	return in_vbl;
}

bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
{
	u32 stat_crtc = 0;
	bool in_vbl = radeon_pm_in_vbl(rdev);

	if (in_vbl == false)
		DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
			 finish ? "exit" : "entry");
	return in_vbl;
}

static void radeon_pm_idle_work_handler(struct work_struct *work)
{
	struct radeon_device *rdev;
	int resched;
	rdev = container_of(work, struct radeon_device,
				pm.idle_work.work);

	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
	mutex_lock(&rdev->pm.mutex);
	if (rdev->pm.state == PM_STATE_ACTIVE) {
		unsigned long irq_flags;
		int not_processed = 0;

		read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
		if (!list_empty(&rdev->fence_drv.emited)) {
			struct list_head *ptr;
			list_for_each(ptr, &rdev->fence_drv.emited) {
				/* count up to 3, that's enought info */
				if (++not_processed >= 3)
					break;
			}
		}
		read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);

		if (not_processed >= 3) { /* should upclock */
			if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
				rdev->pm.planned_action = PM_ACTION_NONE;
			} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
				   rdev->pm.can_upclock) {
				rdev->pm.planned_action =
					PM_ACTION_UPCLOCK;
				rdev->pm.action_timeout = jiffies +
				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
			}
		} else if (not_processed == 0) { /* should downclock */
			if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
				rdev->pm.planned_action = PM_ACTION_NONE;
			} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
				   rdev->pm.can_downclock) {
				rdev->pm.planned_action =
					PM_ACTION_DOWNCLOCK;
				rdev->pm.action_timeout = jiffies +
				msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
			}
		}

		if (rdev->pm.planned_action != PM_ACTION_NONE &&
		    jiffies > rdev->pm.action_timeout) {
			radeon_pm_set_clocks(rdev, false);
		}
	}
	mutex_unlock(&rdev->pm.mutex);
	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);

	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
					msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
}

/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)

static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;

	seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
	if (rdev->asic->get_memory_clock)
		seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
	if (rdev->asic->get_pcie_lanes)
		seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));

	return 0;
}

static struct drm_info_list radeon_pm_info_list[] = {
	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
};
#endif

static int radeon_debugfs_pm_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
#else
	return 0;
#endif
}
Commit	Line	Data
7433874e RM	1	/*
	2	* Permission is hereby granted, free of charge, to any person obtaining a
	3	* copy of this software and associated documentation files (the "Software"),
	4	* to deal in the Software without restriction, including without limitation
	5	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	6	* and/or sell copies of the Software, and to permit persons to whom the
	7	* Software is furnished to do so, subject to the following conditions:
	8	*
	9	* The above copyright notice and this permission notice shall be included in
	10	* all copies or substantial portions of the Software.
	11	*
	12	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	13	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	14	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	15	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	16	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	17	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	18	* OTHER DEALINGS IN THE SOFTWARE.
	19	*
	20	* Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e	21	* Alex Deucher <alexdeucher@gmail.com>
7433874e RM	22	*/
	23	#include "drmP.h"
	24	#include "radeon.h"
f735261b	25	#include "avivod.h"
7433874e	26
c913e23a RM	27	#define RADEON_IDLE_LOOP_MS 100
c913e23a RM	28	#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc	29	#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c	30	#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a	31
c913e23a RM	32	static void radeon_pm_idle_work_handler(struct work_struct *work);
	33	static int radeon_debugfs_pm_init(struct radeon_device *rdev);
	34
5876dd24 MG	35	static void radeon_unmap_vram_bos(struct radeon_device *rdev)
	36	{
	37	struct radeon_bo bo, n;
	38
	39	if (list_empty(&rdev->gem.objects))
	40	return;
	41
	42	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
	43	if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
	44	ttm_bo_unmap_virtual(&bo->tbo);
	45	}
	46
	47	if (rdev->gart.table.vram.robj)
	48	ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
	49
	50	if (rdev->stollen_vga_memory)
	51	ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
	52
	53	if (rdev->r600_blit.shader_obj)
	54	ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
	55	}
	56
2aba631c	57	static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
a424816f	58	{
2aba631c MG	59	int i;
2aba631c MG	60
c37d230a MG	61	if (!static_switch)
	62	radeon_get_power_state(rdev, rdev->pm.planned_action);
	63
612e06ce MG	64	mutex_lock(&rdev->ddev->struct_mutex);
612e06ce MG	65	mutex_lock(&rdev->vram_mutex);
a424816f	66	mutex_lock(&rdev->cp.mutex);
4f3218cb AD	67
	68	/* gui idle int has issues on older chips it seems */
	69	if (rdev->family >= CHIP_R600) {
	70	/* wait for GPU idle */
	71	rdev->pm.gui_idle = false;
	72	rdev->irq.gui_idle = true;
	73	radeon_irq_set(rdev);
	74	wait_event_interruptible_timeout(
	75	rdev->irq.idle_queue, rdev->pm.gui_idle,
	76	msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
	77	rdev->irq.gui_idle = false;
	78	radeon_irq_set(rdev);
01434b4b MG	79	} else {
	80	struct radeon_fence *fence;
	81	radeon_ring_alloc(rdev, 64);
	82	radeon_fence_create(rdev, &fence);
	83	radeon_fence_emit(rdev, fence);
	84	radeon_ring_commit(rdev);
	85	radeon_fence_wait(fence, false);
	86	radeon_fence_unref(&fence);
4f3218cb	87	}
5876dd24 MG	88	radeon_unmap_vram_bos(rdev);
5876dd24 MG	89
2aba631c MG	90	if (!static_switch) {
	91	for (i = 0; i < rdev->num_crtc; i++) {
	92	if (rdev->pm.active_crtcs & (1 << i)) {
	93	rdev->pm.req_vblank \|= (1 << i);
	94	drm_vblank_get(rdev->ddev, i);
	95	}
	96	}
	97	}
539d2418	98
2aba631c MG	99	radeon_set_power_state(rdev, static_switch);
	100
	101	if (!static_switch) {
	102	for (i = 0; i < rdev->num_crtc; i++) {
	103	if (rdev->pm.req_vblank & (1 << i)) {
	104	rdev->pm.req_vblank &= ~(1 << i);
	105	drm_vblank_put(rdev->ddev, i);
	106	}
	107	}
	108	}
5876dd24	109
a424816f AD	110	/* update display watermarks based on new power state */
	111	radeon_update_bandwidth_info(rdev);
	112	if (rdev->pm.active_crtc_count)
	113	radeon_bandwidth_update(rdev);
	114
2aba631c MG	115	rdev->pm.planned_action = PM_ACTION_NONE;
2aba631c MG	116
a424816f	117	mutex_unlock(&rdev->cp.mutex);
612e06ce MG	118	mutex_unlock(&rdev->vram_mutex);
612e06ce MG	119	mutex_unlock(&rdev->ddev->struct_mutex);
a424816f AD	120	}
	121
	122	static ssize_t radeon_get_power_state_static(struct device *dev,
	123	struct device_attribute *attr,
	124	char *buf)
	125	{
	126	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	127	struct radeon_device *rdev = ddev->dev_private;
	128
	129	return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
	130	rdev->pm.current_clock_mode_index);
	131	}
	132
	133	static ssize_t radeon_set_power_state_static(struct device *dev,
	134	struct device_attribute *attr,
	135	const char *buf,
	136	size_t count)
	137	{
	138	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	139	struct radeon_device *rdev = ddev->dev_private;
	140	int ps, cm;
	141
	142	if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
	143	DRM_ERROR("Invalid power state!\n");
	144	return count;
	145	}
	146
	147	mutex_lock(&rdev->pm.mutex);
	148	if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
	149	(cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
	150	if ((rdev->pm.active_crtc_count > 1) &&
	151	(rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) {
	152	DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
	153	} else {
	154	/* disable dynpm */
	155	rdev->pm.state = PM_STATE_DISABLED;
	156	rdev->pm.planned_action = PM_ACTION_NONE;
	157	rdev->pm.requested_power_state_index = ps;
	158	rdev->pm.requested_clock_mode_index = cm;
2aba631c	159	radeon_pm_set_clocks(rdev, true);
a424816f AD	160	}
	161	} else
	162	DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
	163	mutex_unlock(&rdev->pm.mutex);
	164
	165	return count;
	166	}
	167
	168	static ssize_t radeon_get_dynpm(struct device *dev,
	169	struct device_attribute *attr,
	170	char *buf)
	171	{
	172	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	173	struct radeon_device *rdev = ddev->dev_private;
	174
	175	return snprintf(buf, PAGE_SIZE, "%s\n",
	176	(rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
	177	}
	178
	179	static ssize_t radeon_set_dynpm(struct device *dev,
	180	struct device_attribute *attr,
	181	const char *buf,
	182	size_t count)
	183	{
	184	struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
	185	struct radeon_device *rdev = ddev->dev_private;
	186	int tmp = simple_strtoul(buf, NULL, 10);
	187
	188	if (tmp == 0) {
	189	/* update power mode info */
	190	radeon_pm_compute_clocks(rdev);
	191	/* disable dynpm */
	192	mutex_lock(&rdev->pm.mutex);
	193	rdev->pm.state = PM_STATE_DISABLED;
	194	rdev->pm.planned_action = PM_ACTION_NONE;
	195	mutex_unlock(&rdev->pm.mutex);
	196	DRM_INFO("radeon: dynamic power management disabled\n");
	197	} else if (tmp == 1) {
	198	if (rdev->pm.num_power_states > 1) {
	199	/* enable dynpm */
	200	mutex_lock(&rdev->pm.mutex);
	201	rdev->pm.state = PM_STATE_PAUSED;
	202	rdev->pm.planned_action = PM_ACTION_DEFAULT;
	203	radeon_get_power_state(rdev, rdev->pm.planned_action);
	204	mutex_unlock(&rdev->pm.mutex);
	205	/* update power mode info */
	206	radeon_pm_compute_clocks(rdev);
	207	DRM_INFO("radeon: dynamic power management enabled\n");
	208	} else
	209	DRM_ERROR("dynpm not valid on this system\n");
	210	} else
	211	DRM_ERROR("Invalid setting: %d\n", tmp);
	212
	213	return count;
	214	}
	215
	216	static DEVICE_ATTR(power_state, S_IRUGO \| S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
	217	static DEVICE_ATTR(dynpm, S_IRUGO \| S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);
	218
	219
c913e23a RM	220	static const char *pm_state_names[4] = {
	221	"PM_STATE_DISABLED",
	222	"PM_STATE_MINIMUM",
	223	"PM_STATE_PAUSED",
	224	"PM_STATE_ACTIVE"
	225	};
7433874e	226
0ec0e74f	227	static const char *pm_state_types[5] = {
d91eeb78	228	"",
0ec0e74f AD	229	"Powersave",
	230	"Battery",
	231	"Balanced",
	232	"Performance",
	233	};
	234
56278a8e AD	235	static void radeon_print_power_mode_info(struct radeon_device *rdev)
	236	{
	237	int i, j;
	238	bool is_default;
	239
	240	DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
	241	for (i = 0; i < rdev->pm.num_power_states; i++) {
a48b9b4e	242	if (rdev->pm.default_power_state_index == i)
56278a8e AD	243	is_default = true;
	244	else
	245	is_default = false;
0ec0e74f AD	246	DRM_INFO("State %d %s %s\n", i,
	247	pm_state_types[rdev->pm.power_state[i].type],
	248	is_default ? "(default)" : "");
56278a8e	249	if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
79daedc9	250	DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
a48b9b4e AD	251	if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
a48b9b4e AD	252	DRM_INFO("\tSingle display only\n");
56278a8e AD	253	DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
	254	for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
	255	if (rdev->flags & RADEON_IS_IGP)
	256	DRM_INFO("\t\t%d engine: %d\n",
	257	j,
	258	rdev->pm.power_state[i].clock_info[j].sclk * 10);
	259	else
	260	DRM_INFO("\t\t%d engine/memory: %d/%d\n",
	261	j,
	262	rdev->pm.power_state[i].clock_info[j].sclk * 10,
	263	rdev->pm.power_state[i].clock_info[j].mclk * 10);
	264	}
	265	}
	266	}
	267
bae6b562	268	void radeon_sync_with_vblank(struct radeon_device *rdev)
d0d6cb81 RM	269	{
	270	if (rdev->pm.active_crtcs) {
	271	rdev->pm.vblank_sync = false;
	272	wait_event_timeout(
	273	rdev->irq.vblank_queue, rdev->pm.vblank_sync,
	274	msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
	275	}
	276	}
	277
7433874e RM	278	int radeon_pm_init(struct radeon_device *rdev)
7433874e RM	279	{
c913e23a RM	280	rdev->pm.state = PM_STATE_DISABLED;
c913e23a RM	281	rdev->pm.planned_action = PM_ACTION_NONE;
a48b9b4e AD	282	rdev->pm.can_upclock = true;
a48b9b4e AD	283	rdev->pm.can_downclock = true;
c913e23a	284
56278a8e AD	285	if (rdev->bios) {
	286	if (rdev->is_atom_bios)
	287	radeon_atombios_get_power_modes(rdev);
	288	else
	289	radeon_combios_get_power_modes(rdev);
	290	radeon_print_power_mode_info(rdev);
	291	}
	292
7433874e	293	if (radeon_debugfs_pm_init(rdev)) {
c142c3e5	294	DRM_ERROR("Failed to register debugfs file for PM!\n");
7433874e RM	295	}
7433874e RM	296
a424816f AD	297	/* where's the best place to put this? */
	298	device_create_file(rdev->dev, &dev_attr_power_state);
	299	device_create_file(rdev->dev, &dev_attr_dynpm);
	300
c913e23a RM	301	INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
c913e23a RM	302
90c39059	303	if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
c913e23a RM	304	rdev->pm.state = PM_STATE_PAUSED;
	305	DRM_INFO("radeon: dynamic power management enabled\n");
	306	}
	307
	308	DRM_INFO("radeon: power management initialized\n");
	309
7433874e RM	310	return 0;
	311	}
	312
29fb52ca AD	313	void radeon_pm_fini(struct radeon_device *rdev)
29fb52ca AD	314	{
58e21dff AD	315	if (rdev->pm.state != PM_STATE_DISABLED) {
	316	/* cancel work */
	317	cancel_delayed_work_sync(&rdev->pm.idle_work);
	318	/* reset default clocks */
	319	rdev->pm.state = PM_STATE_DISABLED;
	320	rdev->pm.planned_action = PM_ACTION_DEFAULT;
2aba631c	321	radeon_pm_set_clocks(rdev, false);
a424816f AD	322	} else if ((rdev->pm.current_power_state_index !=
	323	rdev->pm.default_power_state_index) \|\|
	324	(rdev->pm.current_clock_mode_index != 0)) {
	325	rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
	326	rdev->pm.requested_clock_mode_index = 0;
	327	mutex_lock(&rdev->pm.mutex);
2aba631c	328	radeon_pm_set_clocks(rdev, true);
a424816f	329	mutex_unlock(&rdev->pm.mutex);
58e21dff AD	330	}
58e21dff AD	331
a424816f AD	332	device_remove_file(rdev->dev, &dev_attr_power_state);
	333	device_remove_file(rdev->dev, &dev_attr_dynpm);
	334
29fb52ca AD	335	if (rdev->pm.i2c_bus)
	336	radeon_i2c_destroy(rdev->pm.i2c_bus);
	337	}
	338
c913e23a RM	339	void radeon_pm_compute_clocks(struct radeon_device *rdev)
	340	{
	341	struct drm_device *ddev = rdev->ddev;
a48b9b4e	342	struct drm_crtc *crtc;
c913e23a	343	struct radeon_crtc *radeon_crtc;
c913e23a RM	344
	345	if (rdev->pm.state == PM_STATE_DISABLED)
	346	return;
	347
	348	mutex_lock(&rdev->pm.mutex);
	349
	350	rdev->pm.active_crtcs = 0;
a48b9b4e AD	351	rdev->pm.active_crtc_count = 0;
	352	list_for_each_entry(crtc,
	353	&ddev->mode_config.crtc_list, head) {
	354	radeon_crtc = to_radeon_crtc(crtc);
	355	if (radeon_crtc->enabled) {
c913e23a	356	rdev->pm.active_crtcs \|= (1 << radeon_crtc->crtc_id);
a48b9b4e	357	rdev->pm.active_crtc_count++;
c913e23a RM	358	}
	359	}
	360
a48b9b4e	361	if (rdev->pm.active_crtc_count > 1) {
c913e23a	362	if (rdev->pm.state == PM_STATE_ACTIVE) {
c913e23a RM	363	cancel_delayed_work(&rdev->pm.idle_work);
	364
	365	rdev->pm.state = PM_STATE_PAUSED;
	366	rdev->pm.planned_action = PM_ACTION_UPCLOCK;
2aba631c	367	radeon_pm_set_clocks(rdev, false);
c913e23a RM	368
c913e23a RM	369	DRM_DEBUG("radeon: dynamic power management deactivated\n");
c913e23a	370	}
a48b9b4e	371	} else if (rdev->pm.active_crtc_count == 1) {
c913e23a RM	372	/* TODO: Increase clocks if needed for current mode */
	373
	374	if (rdev->pm.state == PM_STATE_MINIMUM) {
	375	rdev->pm.state = PM_STATE_ACTIVE;
	376	rdev->pm.planned_action = PM_ACTION_UPCLOCK;
2aba631c	377	radeon_pm_set_clocks(rdev, false);
c913e23a RM	378
	379	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	380	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
a48b9b4e	381	} else if (rdev->pm.state == PM_STATE_PAUSED) {
c913e23a RM	382	rdev->pm.state = PM_STATE_ACTIVE;
	383	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	384	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
	385	DRM_DEBUG("radeon: dynamic power management activated\n");
	386	}
a48b9b4e	387	} else { /* count == 0 */
c913e23a RM	388	if (rdev->pm.state != PM_STATE_MINIMUM) {
	389	cancel_delayed_work(&rdev->pm.idle_work);
	390
	391	rdev->pm.state = PM_STATE_MINIMUM;
	392	rdev->pm.planned_action = PM_ACTION_MINIMUM;
2aba631c	393	radeon_pm_set_clocks(rdev, false);
c913e23a	394	}
c913e23a	395	}
73a6d3fc RM	396
73a6d3fc RM	397	mutex_unlock(&rdev->pm.mutex);
c913e23a RM	398	}
c913e23a RM	399
f81f2024	400	bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b	401	{
539d2418	402	u32 stat_crtc = 0, vbl = 0, position = 0;
f735261b DA	403	bool in_vbl = true;
f735261b DA	404
bae6b562 AD	405	if (ASIC_IS_DCE4(rdev)) {
bae6b562 AD	406	if (rdev->pm.active_crtcs & (1 << 0)) {
539d2418 AD	407	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
	408	EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
	409	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
	410	EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
bae6b562 AD	411	}
bae6b562 AD	412	if (rdev->pm.active_crtcs & (1 << 1)) {
539d2418 AD	413	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
	414	EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
	415	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
	416	EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
bae6b562 AD	417	}
bae6b562 AD	418	if (rdev->pm.active_crtcs & (1 << 2)) {
539d2418 AD	419	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
	420	EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
	421	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
	422	EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
bae6b562 AD	423	}
bae6b562 AD	424	if (rdev->pm.active_crtcs & (1 << 3)) {
539d2418 AD	425	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
	426	EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
	427	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
	428	EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
bae6b562 AD	429	}
bae6b562 AD	430	if (rdev->pm.active_crtcs & (1 << 4)) {
539d2418 AD	431	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
	432	EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
	433	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
	434	EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
bae6b562 AD	435	}
bae6b562 AD	436	if (rdev->pm.active_crtcs & (1 << 5)) {
539d2418 AD	437	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
	438	EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
	439	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
	440	EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
bae6b562 AD	441	}
	442	} else if (ASIC_IS_AVIVO(rdev)) {
	443	if (rdev->pm.active_crtcs & (1 << 0)) {
539d2418 AD	444	vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
539d2418 AD	445	position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
bae6b562 AD	446	}
bae6b562 AD	447	if (rdev->pm.active_crtcs & (1 << 1)) {
539d2418 AD	448	vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
539d2418 AD	449	position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
bae6b562	450	}
539d2418 AD	451	if (position < vbl && position > 1)
539d2418 AD	452	in_vbl = false;
bae6b562	453	} else {
f735261b	454	if (rdev->pm.active_crtcs & (1 << 0)) {
bae6b562 AD	455	stat_crtc = RREG32(RADEON_CRTC_STATUS);
bae6b562 AD	456	if (!(stat_crtc & 1))
f735261b DA	457	in_vbl = false;
	458	}
	459	if (rdev->pm.active_crtcs & (1 << 1)) {
bae6b562 AD	460	stat_crtc = RREG32(RADEON_CRTC2_STATUS);
bae6b562 AD	461	if (!(stat_crtc & 1))
f735261b DA	462	in_vbl = false;
	463	}
	464	}
f81f2024	465
539d2418 AD	466	if (position < vbl && position > 1)
	467	in_vbl = false;
	468
f81f2024 MG	469	return in_vbl;
	470	}
	471
	472	bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
	473	{
	474	u32 stat_crtc = 0;
	475	bool in_vbl = radeon_pm_in_vbl(rdev);
	476
f735261b	477	if (in_vbl == false)
bae6b562 AD	478	DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 AD	479	finish ? "exit" : "entry");
f735261b DA	480	return in_vbl;
f735261b DA	481	}
c913e23a RM	482
	483	static void radeon_pm_idle_work_handler(struct work_struct *work)
	484	{
	485	struct radeon_device *rdev;
d9932a32	486	int resched;
c913e23a RM	487	rdev = container_of(work, struct radeon_device,
	488	pm.idle_work.work);
	489
d9932a32	490	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a	491	mutex_lock(&rdev->pm.mutex);
73a6d3fc	492	if (rdev->pm.state == PM_STATE_ACTIVE) {
c913e23a RM	493	unsigned long irq_flags;
	494	int not_processed = 0;
	495
	496	read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
	497	if (!list_empty(&rdev->fence_drv.emited)) {
	498	struct list_head *ptr;
	499	list_for_each(ptr, &rdev->fence_drv.emited) {
	500	/* count up to 3, that's enought info */
	501	if (++not_processed >= 3)
	502	break;
	503	}
	504	}
	505	read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
	506
	507	if (not_processed >= 3) { /* should upclock */
	508	if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
	509	rdev->pm.planned_action = PM_ACTION_NONE;
	510	} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
a48b9b4e	511	rdev->pm.can_upclock) {
c913e23a RM	512	rdev->pm.planned_action =
	513	PM_ACTION_UPCLOCK;
	514	rdev->pm.action_timeout = jiffies +
	515	msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
	516	}
	517	} else if (not_processed == 0) { /* should downclock */
	518	if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
	519	rdev->pm.planned_action = PM_ACTION_NONE;
	520	} else if (rdev->pm.planned_action == PM_ACTION_NONE &&
a48b9b4e	521	rdev->pm.can_downclock) {
c913e23a RM	522	rdev->pm.planned_action =
	523	PM_ACTION_DOWNCLOCK;
	524	rdev->pm.action_timeout = jiffies +
	525	msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
	526	}
	527	}
	528
	529	if (rdev->pm.planned_action != PM_ACTION_NONE &&
73a6d3fc	530	jiffies > rdev->pm.action_timeout) {
2aba631c	531	radeon_pm_set_clocks(rdev, false);
c913e23a RM	532	}
	533	}
	534	mutex_unlock(&rdev->pm.mutex);
d9932a32	535	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a RM	536
	537	queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
	538	msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
	539	}
	540
7433874e RM	541	/*
	542	* Debugfs info
	543	*/
	544	#if defined(CONFIG_DEBUG_FS)
	545
	546	static int radeon_debugfs_pm_info(struct seq_file m, void data)
	547	{
	548	struct drm_info_node node = (struct drm_info_node ) m->private;
	549	struct drm_device *dev = node->minor->dev;
	550	struct radeon_device *rdev = dev->dev_private;
	551
c913e23a	552	seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
6234077d RM	553	seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
	554	seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
	555	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
	556	if (rdev->asic->get_memory_clock)
	557	seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
aa5120d2 RM	558	if (rdev->asic->get_pcie_lanes)
aa5120d2 RM	559	seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e RM	560
	561	return 0;
	562	}
	563
	564	static struct drm_info_list radeon_pm_info_list[] = {
	565	{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
	566	};
	567	#endif
	568
c913e23a	569	static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e RM	570	{
	571	#if defined(CONFIG_DEBUG_FS)
	572	return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
	573	#else
	574	return 0;
	575	#endif
	576	}