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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <linux/list.h> | |
33 | #include <drm/drmP.h> | |
34 | #include "radeon_drm.h" | |
35 | #include "radeon.h" | |
36 | ||
771fe6b9 JG |
37 | |
38 | int radeon_ttm_init(struct radeon_device *rdev); | |
39 | void radeon_ttm_fini(struct radeon_device *rdev); | |
4c788679 | 40 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
771fe6b9 JG |
41 | |
42 | /* | |
43 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all | |
44 | * function are calling it. | |
45 | */ | |
46 | ||
4c788679 | 47 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
771fe6b9 | 48 | { |
4c788679 | 49 | struct radeon_bo *bo; |
771fe6b9 | 50 | |
4c788679 JG |
51 | bo = container_of(tbo, struct radeon_bo, tbo); |
52 | mutex_lock(&bo->rdev->gem.mutex); | |
53 | list_del_init(&bo->list); | |
54 | mutex_unlock(&bo->rdev->gem.mutex); | |
55 | radeon_bo_clear_surface_reg(bo); | |
56 | kfree(bo); | |
771fe6b9 JG |
57 | } |
58 | ||
4c788679 | 59 | static inline u32 radeon_ttm_flags_from_domain(u32 domain) |
771fe6b9 | 60 | { |
4c788679 | 61 | u32 flags = 0; |
771fe6b9 | 62 | |
771fe6b9 | 63 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
664f8659 | 64 | flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED; |
771fe6b9 JG |
65 | } |
66 | if (domain & RADEON_GEM_DOMAIN_GTT) { | |
985fe845 | 67 | flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; |
771fe6b9 JG |
68 | } |
69 | if (domain & RADEON_GEM_DOMAIN_CPU) { | |
664f8659 | 70 | flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; |
771fe6b9 JG |
71 | } |
72 | if (!flags) { | |
664f8659 | 73 | flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; |
771fe6b9 JG |
74 | } |
75 | return flags; | |
76 | } | |
77 | ||
312ea8da JG |
78 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
79 | { | |
80 | u32 c = 0; | |
81 | ||
82 | rbo->placement.fpfn = 0; | |
83 | rbo->placement.lpfn = 0; | |
84 | rbo->placement.placement = rbo->placements; | |
85 | rbo->placement.busy_placement = rbo->placements; | |
86 | if (domain & RADEON_GEM_DOMAIN_VRAM) | |
87 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | | |
88 | TTM_PL_FLAG_VRAM; | |
89 | if (domain & RADEON_GEM_DOMAIN_GTT) | |
90 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
91 | if (domain & RADEON_GEM_DOMAIN_CPU) | |
92 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
93 | rbo->placement.num_placement = c; | |
94 | rbo->placement.num_busy_placement = c; | |
95 | } | |
96 | ||
4c788679 JG |
97 | int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, |
98 | unsigned long size, bool kernel, u32 domain, | |
99 | struct radeon_bo **bo_ptr) | |
771fe6b9 | 100 | { |
4c788679 | 101 | struct radeon_bo *bo; |
771fe6b9 | 102 | enum ttm_bo_type type; |
4c788679 | 103 | u32 flags; |
771fe6b9 JG |
104 | int r; |
105 | ||
106 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { | |
107 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; | |
108 | } | |
109 | if (kernel) { | |
110 | type = ttm_bo_type_kernel; | |
111 | } else { | |
112 | type = ttm_bo_type_device; | |
113 | } | |
4c788679 JG |
114 | *bo_ptr = NULL; |
115 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); | |
116 | if (bo == NULL) | |
771fe6b9 | 117 | return -ENOMEM; |
4c788679 JG |
118 | bo->rdev = rdev; |
119 | bo->gobj = gobj; | |
120 | bo->surface_reg = -1; | |
121 | INIT_LIST_HEAD(&bo->list); | |
122 | ||
123 | flags = radeon_ttm_flags_from_domain(domain); | |
5cc6fbab | 124 | /* Kernel allocation are uninterruptible */ |
4c788679 | 125 | r = ttm_buffer_object_init(&rdev->mman.bdev, &bo->tbo, size, type, |
5cc6fbab | 126 | flags, 0, 0, !kernel, NULL, size, |
4c788679 | 127 | &radeon_ttm_bo_destroy); |
771fe6b9 | 128 | if (unlikely(r != 0)) { |
5cc6fbab TH |
129 | if (r != -ERESTARTSYS) |
130 | dev_err(rdev->dev, | |
131 | "object_init failed for (%ld, 0x%08X)\n", | |
132 | size, flags); | |
771fe6b9 JG |
133 | return r; |
134 | } | |
4c788679 | 135 | *bo_ptr = bo; |
771fe6b9 | 136 | if (gobj) { |
4c788679 JG |
137 | mutex_lock(&bo->rdev->gem.mutex); |
138 | list_add_tail(&bo->list, &rdev->gem.objects); | |
139 | mutex_unlock(&bo->rdev->gem.mutex); | |
771fe6b9 JG |
140 | } |
141 | return 0; | |
142 | } | |
143 | ||
4c788679 | 144 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
771fe6b9 | 145 | { |
4c788679 | 146 | bool is_iomem; |
771fe6b9 JG |
147 | int r; |
148 | ||
4c788679 | 149 | if (bo->kptr) { |
771fe6b9 | 150 | if (ptr) { |
4c788679 | 151 | *ptr = bo->kptr; |
771fe6b9 | 152 | } |
771fe6b9 JG |
153 | return 0; |
154 | } | |
4c788679 | 155 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
771fe6b9 JG |
156 | if (r) { |
157 | return r; | |
158 | } | |
4c788679 | 159 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
771fe6b9 | 160 | if (ptr) { |
4c788679 | 161 | *ptr = bo->kptr; |
771fe6b9 | 162 | } |
4c788679 | 163 | radeon_bo_check_tiling(bo, 0, 0); |
771fe6b9 JG |
164 | return 0; |
165 | } | |
166 | ||
4c788679 | 167 | void radeon_bo_kunmap(struct radeon_bo *bo) |
771fe6b9 | 168 | { |
4c788679 | 169 | if (bo->kptr == NULL) |
771fe6b9 | 170 | return; |
4c788679 JG |
171 | bo->kptr = NULL; |
172 | radeon_bo_check_tiling(bo, 0, 0); | |
173 | ttm_bo_kunmap(&bo->kmap); | |
771fe6b9 JG |
174 | } |
175 | ||
4c788679 | 176 | void radeon_bo_unref(struct radeon_bo **bo) |
771fe6b9 | 177 | { |
4c788679 | 178 | struct ttm_buffer_object *tbo; |
771fe6b9 | 179 | |
4c788679 | 180 | if ((*bo) == NULL) |
771fe6b9 | 181 | return; |
4c788679 JG |
182 | tbo = &((*bo)->tbo); |
183 | ttm_bo_unref(&tbo); | |
184 | if (tbo == NULL) | |
185 | *bo = NULL; | |
771fe6b9 JG |
186 | } |
187 | ||
4c788679 | 188 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
771fe6b9 | 189 | { |
312ea8da | 190 | int r, i; |
771fe6b9 | 191 | |
312ea8da | 192 | radeon_ttm_placement_from_domain(bo, domain); |
4c788679 JG |
193 | if (bo->pin_count) { |
194 | bo->pin_count++; | |
195 | if (gpu_addr) | |
196 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 JG |
197 | return 0; |
198 | } | |
312ea8da JG |
199 | radeon_ttm_placement_from_domain(bo, domain); |
200 | for (i = 0; i < bo->placement.num_placement; i++) | |
201 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; | |
5cc6fbab | 202 | r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, false, false); |
4c788679 JG |
203 | if (likely(r == 0)) { |
204 | bo->pin_count = 1; | |
205 | if (gpu_addr != NULL) | |
206 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 | 207 | } |
5cc6fbab | 208 | if (unlikely(r != 0)) |
4c788679 | 209 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
771fe6b9 JG |
210 | return r; |
211 | } | |
212 | ||
4c788679 | 213 | int radeon_bo_unpin(struct radeon_bo *bo) |
771fe6b9 | 214 | { |
312ea8da | 215 | int r, i; |
771fe6b9 | 216 | |
4c788679 JG |
217 | if (!bo->pin_count) { |
218 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); | |
219 | return 0; | |
771fe6b9 | 220 | } |
4c788679 JG |
221 | bo->pin_count--; |
222 | if (bo->pin_count) | |
223 | return 0; | |
312ea8da JG |
224 | for (i = 0; i < bo->placement.num_placement; i++) |
225 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; | |
5cc6fbab TH |
226 | r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, false, false); |
227 | if (unlikely(r != 0)) | |
4c788679 | 228 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
5cc6fbab | 229 | return r; |
cefb87ef DA |
230 | } |
231 | ||
4c788679 | 232 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
771fe6b9 JG |
233 | { |
234 | if (rdev->flags & RADEON_IS_IGP) { | |
235 | /* Useless to evict on IGP chips */ | |
236 | return 0; | |
237 | } | |
238 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
239 | } | |
240 | ||
4c788679 | 241 | void radeon_bo_force_delete(struct radeon_device *rdev) |
771fe6b9 | 242 | { |
4c788679 | 243 | struct radeon_bo *bo, *n; |
771fe6b9 JG |
244 | struct drm_gem_object *gobj; |
245 | ||
246 | if (list_empty(&rdev->gem.objects)) { | |
247 | return; | |
248 | } | |
4c788679 JG |
249 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
250 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
771fe6b9 | 251 | mutex_lock(&rdev->ddev->struct_mutex); |
4c788679 JG |
252 | gobj = bo->gobj; |
253 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", | |
254 | gobj, bo, (unsigned long)gobj->size, | |
255 | *((unsigned long *)&gobj->refcount)); | |
256 | mutex_lock(&bo->rdev->gem.mutex); | |
257 | list_del_init(&bo->list); | |
258 | mutex_unlock(&bo->rdev->gem.mutex); | |
259 | radeon_bo_unref(&bo); | |
771fe6b9 JG |
260 | gobj->driver_private = NULL; |
261 | drm_gem_object_unreference(gobj); | |
262 | mutex_unlock(&rdev->ddev->struct_mutex); | |
263 | } | |
264 | } | |
265 | ||
4c788679 | 266 | int radeon_bo_init(struct radeon_device *rdev) |
771fe6b9 | 267 | { |
a4d68279 JG |
268 | /* Add an MTRR for the VRAM */ |
269 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, | |
270 | MTRR_TYPE_WRCOMB, 1); | |
271 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", | |
272 | rdev->mc.mc_vram_size >> 20, | |
273 | (unsigned long long)rdev->mc.aper_size >> 20); | |
274 | DRM_INFO("RAM width %dbits %cDR\n", | |
275 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | |
771fe6b9 JG |
276 | return radeon_ttm_init(rdev); |
277 | } | |
278 | ||
4c788679 | 279 | void radeon_bo_fini(struct radeon_device *rdev) |
771fe6b9 JG |
280 | { |
281 | radeon_ttm_fini(rdev); | |
282 | } | |
283 | ||
4c788679 JG |
284 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
285 | struct list_head *head) | |
771fe6b9 JG |
286 | { |
287 | if (lobj->wdomain) { | |
288 | list_add(&lobj->list, head); | |
289 | } else { | |
290 | list_add_tail(&lobj->list, head); | |
291 | } | |
292 | } | |
293 | ||
4c788679 | 294 | int radeon_bo_list_reserve(struct list_head *head) |
771fe6b9 | 295 | { |
4c788679 | 296 | struct radeon_bo_list *lobj; |
771fe6b9 JG |
297 | int r; |
298 | ||
9d8401fc | 299 | list_for_each_entry(lobj, head, list){ |
4c788679 JG |
300 | r = radeon_bo_reserve(lobj->bo, false); |
301 | if (unlikely(r != 0)) | |
302 | return r; | |
771fe6b9 JG |
303 | } |
304 | return 0; | |
305 | } | |
306 | ||
4c788679 | 307 | void radeon_bo_list_unreserve(struct list_head *head) |
771fe6b9 | 308 | { |
4c788679 | 309 | struct radeon_bo_list *lobj; |
771fe6b9 | 310 | |
9d8401fc | 311 | list_for_each_entry(lobj, head, list) { |
4c788679 JG |
312 | /* only unreserve object we successfully reserved */ |
313 | if (radeon_bo_is_reserved(lobj->bo)) | |
314 | radeon_bo_unreserve(lobj->bo); | |
771fe6b9 JG |
315 | } |
316 | } | |
317 | ||
4c788679 | 318 | int radeon_bo_list_validate(struct list_head *head, void *fence) |
771fe6b9 | 319 | { |
4c788679 JG |
320 | struct radeon_bo_list *lobj; |
321 | struct radeon_bo *bo; | |
771fe6b9 | 322 | struct radeon_fence *old_fence = NULL; |
771fe6b9 JG |
323 | int r; |
324 | ||
4c788679 | 325 | r = radeon_bo_list_reserve(head); |
771fe6b9 | 326 | if (unlikely(r != 0)) { |
771fe6b9 JG |
327 | return r; |
328 | } | |
9d8401fc | 329 | list_for_each_entry(lobj, head, list) { |
4c788679 JG |
330 | bo = lobj->bo; |
331 | if (!bo->pin_count) { | |
664f8659 | 332 | if (lobj->wdomain) { |
312ea8da JG |
333 | radeon_ttm_placement_from_domain(bo, |
334 | lobj->wdomain); | |
664f8659 | 335 | } else { |
312ea8da JG |
336 | radeon_ttm_placement_from_domain(bo, |
337 | lobj->rdomain); | |
664f8659 | 338 | } |
4c788679 | 339 | r = ttm_buffer_object_validate(&bo->tbo, |
312ea8da | 340 | &bo->placement, |
4c788679 | 341 | true, false); |
5cc6fbab | 342 | if (unlikely(r)) |
771fe6b9 | 343 | return r; |
771fe6b9 | 344 | } |
4c788679 JG |
345 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
346 | lobj->tiling_flags = bo->tiling_flags; | |
771fe6b9 | 347 | if (fence) { |
4c788679 JG |
348 | old_fence = (struct radeon_fence *)bo->tbo.sync_obj; |
349 | bo->tbo.sync_obj = radeon_fence_ref(fence); | |
350 | bo->tbo.sync_obj_arg = NULL; | |
771fe6b9 JG |
351 | } |
352 | if (old_fence) { | |
353 | radeon_fence_unref(&old_fence); | |
354 | } | |
355 | } | |
356 | return 0; | |
357 | } | |
358 | ||
4c788679 | 359 | void radeon_bo_list_unvalidate(struct list_head *head, void *fence) |
771fe6b9 | 360 | { |
4c788679 JG |
361 | struct radeon_bo_list *lobj; |
362 | struct radeon_fence *old_fence; | |
771fe6b9 | 363 | |
4c788679 JG |
364 | if (fence) |
365 | list_for_each_entry(lobj, head, list) { | |
366 | old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj); | |
367 | if (old_fence == fence) { | |
368 | lobj->bo->tbo.sync_obj = NULL; | |
369 | radeon_fence_unref(&old_fence); | |
370 | } | |
771fe6b9 | 371 | } |
4c788679 | 372 | radeon_bo_list_unreserve(head); |
771fe6b9 JG |
373 | } |
374 | ||
4c788679 | 375 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
771fe6b9 JG |
376 | struct vm_area_struct *vma) |
377 | { | |
4c788679 | 378 | return ttm_fbdev_mmap(vma, &bo->tbo); |
771fe6b9 JG |
379 | } |
380 | ||
4c788679 | 381 | static int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
771fe6b9 | 382 | { |
4c788679 | 383 | struct radeon_device *rdev = bo->rdev; |
e024e110 | 384 | struct radeon_surface_reg *reg; |
4c788679 | 385 | struct radeon_bo *old_object; |
e024e110 DA |
386 | int steal; |
387 | int i; | |
388 | ||
4c788679 JG |
389 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
390 | ||
391 | if (!bo->tiling_flags) | |
e024e110 DA |
392 | return 0; |
393 | ||
4c788679 JG |
394 | if (bo->surface_reg >= 0) { |
395 | reg = &rdev->surface_regs[bo->surface_reg]; | |
396 | i = bo->surface_reg; | |
e024e110 DA |
397 | goto out; |
398 | } | |
399 | ||
400 | steal = -1; | |
401 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { | |
402 | ||
403 | reg = &rdev->surface_regs[i]; | |
4c788679 | 404 | if (!reg->bo) |
e024e110 DA |
405 | break; |
406 | ||
4c788679 | 407 | old_object = reg->bo; |
e024e110 DA |
408 | if (old_object->pin_count == 0) |
409 | steal = i; | |
410 | } | |
411 | ||
412 | /* if we are all out */ | |
413 | if (i == RADEON_GEM_MAX_SURFACES) { | |
414 | if (steal == -1) | |
415 | return -ENOMEM; | |
416 | /* find someone with a surface reg and nuke their BO */ | |
417 | reg = &rdev->surface_regs[steal]; | |
4c788679 | 418 | old_object = reg->bo; |
e024e110 DA |
419 | /* blow away the mapping */ |
420 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); | |
4c788679 | 421 | ttm_bo_unmap_virtual(&old_object->tbo); |
e024e110 DA |
422 | old_object->surface_reg = -1; |
423 | i = steal; | |
424 | } | |
425 | ||
4c788679 JG |
426 | bo->surface_reg = i; |
427 | reg->bo = bo; | |
e024e110 DA |
428 | |
429 | out: | |
4c788679 JG |
430 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
431 | bo->tbo.mem.mm_node->start << PAGE_SHIFT, | |
432 | bo->tbo.num_pages << PAGE_SHIFT); | |
e024e110 DA |
433 | return 0; |
434 | } | |
435 | ||
4c788679 | 436 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
e024e110 | 437 | { |
4c788679 | 438 | struct radeon_device *rdev = bo->rdev; |
e024e110 DA |
439 | struct radeon_surface_reg *reg; |
440 | ||
4c788679 | 441 | if (bo->surface_reg == -1) |
e024e110 DA |
442 | return; |
443 | ||
4c788679 JG |
444 | reg = &rdev->surface_regs[bo->surface_reg]; |
445 | radeon_clear_surface_reg(rdev, bo->surface_reg); | |
e024e110 | 446 | |
4c788679 JG |
447 | reg->bo = NULL; |
448 | bo->surface_reg = -1; | |
e024e110 DA |
449 | } |
450 | ||
4c788679 JG |
451 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
452 | uint32_t tiling_flags, uint32_t pitch) | |
e024e110 | 453 | { |
4c788679 JG |
454 | int r; |
455 | ||
456 | r = radeon_bo_reserve(bo, false); | |
457 | if (unlikely(r != 0)) | |
458 | return r; | |
459 | bo->tiling_flags = tiling_flags; | |
460 | bo->pitch = pitch; | |
461 | radeon_bo_unreserve(bo); | |
462 | return 0; | |
e024e110 DA |
463 | } |
464 | ||
4c788679 JG |
465 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
466 | uint32_t *tiling_flags, | |
467 | uint32_t *pitch) | |
e024e110 | 468 | { |
4c788679 | 469 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
e024e110 | 470 | if (tiling_flags) |
4c788679 | 471 | *tiling_flags = bo->tiling_flags; |
e024e110 | 472 | if (pitch) |
4c788679 | 473 | *pitch = bo->pitch; |
e024e110 DA |
474 | } |
475 | ||
4c788679 JG |
476 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
477 | bool force_drop) | |
e024e110 | 478 | { |
4c788679 JG |
479 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
480 | ||
481 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) | |
e024e110 DA |
482 | return 0; |
483 | ||
484 | if (force_drop) { | |
4c788679 | 485 | radeon_bo_clear_surface_reg(bo); |
e024e110 DA |
486 | return 0; |
487 | } | |
488 | ||
4c788679 | 489 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
e024e110 DA |
490 | if (!has_moved) |
491 | return 0; | |
492 | ||
4c788679 JG |
493 | if (bo->surface_reg >= 0) |
494 | radeon_bo_clear_surface_reg(bo); | |
e024e110 DA |
495 | return 0; |
496 | } | |
497 | ||
4c788679 | 498 | if ((bo->surface_reg >= 0) && !has_moved) |
e024e110 DA |
499 | return 0; |
500 | ||
4c788679 | 501 | return radeon_bo_get_surface_reg(bo); |
e024e110 DA |
502 | } |
503 | ||
504 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | |
4c788679 | 505 | struct ttm_mem_reg *mem) |
e024e110 | 506 | { |
4c788679 JG |
507 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
508 | radeon_bo_check_tiling(rbo, 0, 1); | |
e024e110 DA |
509 | } |
510 | ||
511 | void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) | |
512 | { | |
4c788679 JG |
513 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
514 | radeon_bo_check_tiling(rbo, 0, 0); | |
e024e110 | 515 | } |