]>
Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <linux/list.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
771fe6b9 JG |
34 | #include <drm/drmP.h> |
35 | #include "radeon_drm.h" | |
36 | #include "radeon.h" | |
37 | ||
771fe6b9 JG |
38 | |
39 | int radeon_ttm_init(struct radeon_device *rdev); | |
40 | void radeon_ttm_fini(struct radeon_device *rdev); | |
4c788679 | 41 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
771fe6b9 JG |
42 | |
43 | /* | |
44 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all | |
45 | * function are calling it. | |
46 | */ | |
47 | ||
4c788679 | 48 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
771fe6b9 | 49 | { |
4c788679 | 50 | struct radeon_bo *bo; |
771fe6b9 | 51 | |
4c788679 JG |
52 | bo = container_of(tbo, struct radeon_bo, tbo); |
53 | mutex_lock(&bo->rdev->gem.mutex); | |
54 | list_del_init(&bo->list); | |
55 | mutex_unlock(&bo->rdev->gem.mutex); | |
56 | radeon_bo_clear_surface_reg(bo); | |
57 | kfree(bo); | |
771fe6b9 JG |
58 | } |
59 | ||
d03d8589 JG |
60 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
61 | { | |
62 | if (bo->destroy == &radeon_ttm_bo_destroy) | |
63 | return true; | |
64 | return false; | |
65 | } | |
66 | ||
312ea8da JG |
67 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
68 | { | |
69 | u32 c = 0; | |
70 | ||
71 | rbo->placement.fpfn = 0; | |
72 | rbo->placement.lpfn = 0; | |
73 | rbo->placement.placement = rbo->placements; | |
74 | rbo->placement.busy_placement = rbo->placements; | |
75 | if (domain & RADEON_GEM_DOMAIN_VRAM) | |
76 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | | |
77 | TTM_PL_FLAG_VRAM; | |
78 | if (domain & RADEON_GEM_DOMAIN_GTT) | |
79 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
80 | if (domain & RADEON_GEM_DOMAIN_CPU) | |
81 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
9fb03e63 JG |
82 | if (!c) |
83 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
312ea8da JG |
84 | rbo->placement.num_placement = c; |
85 | rbo->placement.num_busy_placement = c; | |
86 | } | |
87 | ||
4c788679 JG |
88 | int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, |
89 | unsigned long size, bool kernel, u32 domain, | |
90 | struct radeon_bo **bo_ptr) | |
771fe6b9 | 91 | { |
4c788679 | 92 | struct radeon_bo *bo; |
771fe6b9 | 93 | enum ttm_bo_type type; |
771fe6b9 JG |
94 | int r; |
95 | ||
96 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { | |
97 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; | |
98 | } | |
99 | if (kernel) { | |
100 | type = ttm_bo_type_kernel; | |
101 | } else { | |
102 | type = ttm_bo_type_device; | |
103 | } | |
4c788679 JG |
104 | *bo_ptr = NULL; |
105 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); | |
106 | if (bo == NULL) | |
771fe6b9 | 107 | return -ENOMEM; |
4c788679 JG |
108 | bo->rdev = rdev; |
109 | bo->gobj = gobj; | |
110 | bo->surface_reg = -1; | |
111 | INIT_LIST_HEAD(&bo->list); | |
112 | ||
1fb107fc | 113 | radeon_ttm_placement_from_domain(bo, domain); |
5cc6fbab | 114 | /* Kernel allocation are uninterruptible */ |
1fb107fc JG |
115 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
116 | &bo->placement, 0, 0, !kernel, NULL, size, | |
117 | &radeon_ttm_bo_destroy); | |
771fe6b9 | 118 | if (unlikely(r != 0)) { |
5cc6fbab TH |
119 | if (r != -ERESTARTSYS) |
120 | dev_err(rdev->dev, | |
1fb107fc JG |
121 | "object_init failed for (%lu, 0x%08X)\n", |
122 | size, domain); | |
771fe6b9 JG |
123 | return r; |
124 | } | |
4c788679 | 125 | *bo_ptr = bo; |
771fe6b9 | 126 | if (gobj) { |
4c788679 JG |
127 | mutex_lock(&bo->rdev->gem.mutex); |
128 | list_add_tail(&bo->list, &rdev->gem.objects); | |
129 | mutex_unlock(&bo->rdev->gem.mutex); | |
771fe6b9 JG |
130 | } |
131 | return 0; | |
132 | } | |
133 | ||
4c788679 | 134 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
771fe6b9 | 135 | { |
4c788679 | 136 | bool is_iomem; |
771fe6b9 JG |
137 | int r; |
138 | ||
4c788679 | 139 | if (bo->kptr) { |
771fe6b9 | 140 | if (ptr) { |
4c788679 | 141 | *ptr = bo->kptr; |
771fe6b9 | 142 | } |
771fe6b9 JG |
143 | return 0; |
144 | } | |
4c788679 | 145 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
771fe6b9 JG |
146 | if (r) { |
147 | return r; | |
148 | } | |
4c788679 | 149 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
771fe6b9 | 150 | if (ptr) { |
4c788679 | 151 | *ptr = bo->kptr; |
771fe6b9 | 152 | } |
4c788679 | 153 | radeon_bo_check_tiling(bo, 0, 0); |
771fe6b9 JG |
154 | return 0; |
155 | } | |
156 | ||
4c788679 | 157 | void radeon_bo_kunmap(struct radeon_bo *bo) |
771fe6b9 | 158 | { |
4c788679 | 159 | if (bo->kptr == NULL) |
771fe6b9 | 160 | return; |
4c788679 JG |
161 | bo->kptr = NULL; |
162 | radeon_bo_check_tiling(bo, 0, 0); | |
163 | ttm_bo_kunmap(&bo->kmap); | |
771fe6b9 JG |
164 | } |
165 | ||
4c788679 | 166 | void radeon_bo_unref(struct radeon_bo **bo) |
771fe6b9 | 167 | { |
4c788679 | 168 | struct ttm_buffer_object *tbo; |
771fe6b9 | 169 | |
4c788679 | 170 | if ((*bo) == NULL) |
771fe6b9 | 171 | return; |
4c788679 JG |
172 | tbo = &((*bo)->tbo); |
173 | ttm_bo_unref(&tbo); | |
174 | if (tbo == NULL) | |
175 | *bo = NULL; | |
771fe6b9 JG |
176 | } |
177 | ||
4c788679 | 178 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
771fe6b9 | 179 | { |
312ea8da | 180 | int r, i; |
771fe6b9 | 181 | |
4c788679 JG |
182 | if (bo->pin_count) { |
183 | bo->pin_count++; | |
184 | if (gpu_addr) | |
185 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 JG |
186 | return 0; |
187 | } | |
312ea8da | 188 | radeon_ttm_placement_from_domain(bo, domain); |
3ca82da3 MD |
189 | if (domain == RADEON_GEM_DOMAIN_VRAM) { |
190 | /* force to pin into visible video ram */ | |
191 | bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
192 | } | |
312ea8da JG |
193 | for (i = 0; i < bo->placement.num_placement; i++) |
194 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; | |
9d87fa21 | 195 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); |
4c788679 JG |
196 | if (likely(r == 0)) { |
197 | bo->pin_count = 1; | |
198 | if (gpu_addr != NULL) | |
199 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 | 200 | } |
5cc6fbab | 201 | if (unlikely(r != 0)) |
4c788679 | 202 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
771fe6b9 JG |
203 | return r; |
204 | } | |
205 | ||
4c788679 | 206 | int radeon_bo_unpin(struct radeon_bo *bo) |
771fe6b9 | 207 | { |
312ea8da | 208 | int r, i; |
771fe6b9 | 209 | |
4c788679 JG |
210 | if (!bo->pin_count) { |
211 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); | |
212 | return 0; | |
771fe6b9 | 213 | } |
4c788679 JG |
214 | bo->pin_count--; |
215 | if (bo->pin_count) | |
216 | return 0; | |
312ea8da JG |
217 | for (i = 0; i < bo->placement.num_placement; i++) |
218 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; | |
9d87fa21 | 219 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false); |
5cc6fbab | 220 | if (unlikely(r != 0)) |
4c788679 | 221 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
5cc6fbab | 222 | return r; |
cefb87ef DA |
223 | } |
224 | ||
4c788679 | 225 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
771fe6b9 | 226 | { |
d796d844 DA |
227 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
228 | if (0 && (rdev->flags & RADEON_IS_IGP)) { | |
06b6476d AD |
229 | if (rdev->mc.igp_sideport_enabled == false) |
230 | /* Useless to evict on IGP chips */ | |
231 | return 0; | |
771fe6b9 JG |
232 | } |
233 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
234 | } | |
235 | ||
4c788679 | 236 | void radeon_bo_force_delete(struct radeon_device *rdev) |
771fe6b9 | 237 | { |
4c788679 | 238 | struct radeon_bo *bo, *n; |
771fe6b9 JG |
239 | struct drm_gem_object *gobj; |
240 | ||
241 | if (list_empty(&rdev->gem.objects)) { | |
242 | return; | |
243 | } | |
4c788679 JG |
244 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
245 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
771fe6b9 | 246 | mutex_lock(&rdev->ddev->struct_mutex); |
4c788679 JG |
247 | gobj = bo->gobj; |
248 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", | |
249 | gobj, bo, (unsigned long)gobj->size, | |
250 | *((unsigned long *)&gobj->refcount)); | |
251 | mutex_lock(&bo->rdev->gem.mutex); | |
252 | list_del_init(&bo->list); | |
253 | mutex_unlock(&bo->rdev->gem.mutex); | |
254 | radeon_bo_unref(&bo); | |
771fe6b9 JG |
255 | gobj->driver_private = NULL; |
256 | drm_gem_object_unreference(gobj); | |
257 | mutex_unlock(&rdev->ddev->struct_mutex); | |
258 | } | |
259 | } | |
260 | ||
4c788679 | 261 | int radeon_bo_init(struct radeon_device *rdev) |
771fe6b9 | 262 | { |
a4d68279 JG |
263 | /* Add an MTRR for the VRAM */ |
264 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, | |
265 | MTRR_TYPE_WRCOMB, 1); | |
266 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", | |
267 | rdev->mc.mc_vram_size >> 20, | |
268 | (unsigned long long)rdev->mc.aper_size >> 20); | |
269 | DRM_INFO("RAM width %dbits %cDR\n", | |
270 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | |
771fe6b9 JG |
271 | return radeon_ttm_init(rdev); |
272 | } | |
273 | ||
4c788679 | 274 | void radeon_bo_fini(struct radeon_device *rdev) |
771fe6b9 JG |
275 | { |
276 | radeon_ttm_fini(rdev); | |
277 | } | |
278 | ||
4c788679 JG |
279 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
280 | struct list_head *head) | |
771fe6b9 JG |
281 | { |
282 | if (lobj->wdomain) { | |
283 | list_add(&lobj->list, head); | |
284 | } else { | |
285 | list_add_tail(&lobj->list, head); | |
286 | } | |
287 | } | |
288 | ||
4c788679 | 289 | int radeon_bo_list_reserve(struct list_head *head) |
771fe6b9 | 290 | { |
4c788679 | 291 | struct radeon_bo_list *lobj; |
771fe6b9 JG |
292 | int r; |
293 | ||
9d8401fc | 294 | list_for_each_entry(lobj, head, list){ |
4c788679 JG |
295 | r = radeon_bo_reserve(lobj->bo, false); |
296 | if (unlikely(r != 0)) | |
297 | return r; | |
771fe6b9 JG |
298 | } |
299 | return 0; | |
300 | } | |
301 | ||
4c788679 | 302 | void radeon_bo_list_unreserve(struct list_head *head) |
771fe6b9 | 303 | { |
4c788679 | 304 | struct radeon_bo_list *lobj; |
771fe6b9 | 305 | |
9d8401fc | 306 | list_for_each_entry(lobj, head, list) { |
4c788679 JG |
307 | /* only unreserve object we successfully reserved */ |
308 | if (radeon_bo_is_reserved(lobj->bo)) | |
309 | radeon_bo_unreserve(lobj->bo); | |
771fe6b9 JG |
310 | } |
311 | } | |
312 | ||
6cb8e1f7 | 313 | int radeon_bo_list_validate(struct list_head *head) |
771fe6b9 | 314 | { |
4c788679 JG |
315 | struct radeon_bo_list *lobj; |
316 | struct radeon_bo *bo; | |
771fe6b9 JG |
317 | int r; |
318 | ||
4c788679 | 319 | r = radeon_bo_list_reserve(head); |
771fe6b9 | 320 | if (unlikely(r != 0)) { |
771fe6b9 JG |
321 | return r; |
322 | } | |
9d8401fc | 323 | list_for_each_entry(lobj, head, list) { |
4c788679 JG |
324 | bo = lobj->bo; |
325 | if (!bo->pin_count) { | |
664f8659 | 326 | if (lobj->wdomain) { |
312ea8da JG |
327 | radeon_ttm_placement_from_domain(bo, |
328 | lobj->wdomain); | |
664f8659 | 329 | } else { |
312ea8da JG |
330 | radeon_ttm_placement_from_domain(bo, |
331 | lobj->rdomain); | |
664f8659 | 332 | } |
1fb107fc | 333 | r = ttm_bo_validate(&bo->tbo, &bo->placement, |
9d87fa21 | 334 | true, false, false); |
5cc6fbab | 335 | if (unlikely(r)) |
771fe6b9 | 336 | return r; |
771fe6b9 | 337 | } |
4c788679 JG |
338 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
339 | lobj->tiling_flags = bo->tiling_flags; | |
771fe6b9 JG |
340 | } |
341 | return 0; | |
342 | } | |
343 | ||
6cb8e1f7 | 344 | void radeon_bo_list_fence(struct list_head *head, void *fence) |
771fe6b9 | 345 | { |
4c788679 | 346 | struct radeon_bo_list *lobj; |
6cb8e1f7 JG |
347 | struct radeon_bo *bo; |
348 | struct radeon_fence *old_fence = NULL; | |
349 | ||
350 | list_for_each_entry(lobj, head, list) { | |
351 | bo = lobj->bo; | |
352 | spin_lock(&bo->tbo.lock); | |
353 | old_fence = (struct radeon_fence *)bo->tbo.sync_obj; | |
354 | bo->tbo.sync_obj = radeon_fence_ref(fence); | |
355 | bo->tbo.sync_obj_arg = NULL; | |
356 | spin_unlock(&bo->tbo.lock); | |
357 | if (old_fence) { | |
358 | radeon_fence_unref(&old_fence); | |
771fe6b9 | 359 | } |
6cb8e1f7 | 360 | } |
771fe6b9 JG |
361 | } |
362 | ||
4c788679 | 363 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
771fe6b9 JG |
364 | struct vm_area_struct *vma) |
365 | { | |
4c788679 | 366 | return ttm_fbdev_mmap(vma, &bo->tbo); |
771fe6b9 JG |
367 | } |
368 | ||
550e2d92 | 369 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
771fe6b9 | 370 | { |
4c788679 | 371 | struct radeon_device *rdev = bo->rdev; |
e024e110 | 372 | struct radeon_surface_reg *reg; |
4c788679 | 373 | struct radeon_bo *old_object; |
e024e110 DA |
374 | int steal; |
375 | int i; | |
376 | ||
4c788679 JG |
377 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
378 | ||
379 | if (!bo->tiling_flags) | |
e024e110 DA |
380 | return 0; |
381 | ||
4c788679 JG |
382 | if (bo->surface_reg >= 0) { |
383 | reg = &rdev->surface_regs[bo->surface_reg]; | |
384 | i = bo->surface_reg; | |
e024e110 DA |
385 | goto out; |
386 | } | |
387 | ||
388 | steal = -1; | |
389 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { | |
390 | ||
391 | reg = &rdev->surface_regs[i]; | |
4c788679 | 392 | if (!reg->bo) |
e024e110 DA |
393 | break; |
394 | ||
4c788679 | 395 | old_object = reg->bo; |
e024e110 DA |
396 | if (old_object->pin_count == 0) |
397 | steal = i; | |
398 | } | |
399 | ||
400 | /* if we are all out */ | |
401 | if (i == RADEON_GEM_MAX_SURFACES) { | |
402 | if (steal == -1) | |
403 | return -ENOMEM; | |
404 | /* find someone with a surface reg and nuke their BO */ | |
405 | reg = &rdev->surface_regs[steal]; | |
4c788679 | 406 | old_object = reg->bo; |
e024e110 DA |
407 | /* blow away the mapping */ |
408 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); | |
4c788679 | 409 | ttm_bo_unmap_virtual(&old_object->tbo); |
e024e110 DA |
410 | old_object->surface_reg = -1; |
411 | i = steal; | |
412 | } | |
413 | ||
4c788679 JG |
414 | bo->surface_reg = i; |
415 | reg->bo = bo; | |
e024e110 DA |
416 | |
417 | out: | |
4c788679 JG |
418 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
419 | bo->tbo.mem.mm_node->start << PAGE_SHIFT, | |
420 | bo->tbo.num_pages << PAGE_SHIFT); | |
e024e110 DA |
421 | return 0; |
422 | } | |
423 | ||
4c788679 | 424 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
e024e110 | 425 | { |
4c788679 | 426 | struct radeon_device *rdev = bo->rdev; |
e024e110 DA |
427 | struct radeon_surface_reg *reg; |
428 | ||
4c788679 | 429 | if (bo->surface_reg == -1) |
e024e110 DA |
430 | return; |
431 | ||
4c788679 JG |
432 | reg = &rdev->surface_regs[bo->surface_reg]; |
433 | radeon_clear_surface_reg(rdev, bo->surface_reg); | |
e024e110 | 434 | |
4c788679 JG |
435 | reg->bo = NULL; |
436 | bo->surface_reg = -1; | |
e024e110 DA |
437 | } |
438 | ||
4c788679 JG |
439 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
440 | uint32_t tiling_flags, uint32_t pitch) | |
e024e110 | 441 | { |
4c788679 JG |
442 | int r; |
443 | ||
444 | r = radeon_bo_reserve(bo, false); | |
445 | if (unlikely(r != 0)) | |
446 | return r; | |
447 | bo->tiling_flags = tiling_flags; | |
448 | bo->pitch = pitch; | |
449 | radeon_bo_unreserve(bo); | |
450 | return 0; | |
e024e110 DA |
451 | } |
452 | ||
4c788679 JG |
453 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
454 | uint32_t *tiling_flags, | |
455 | uint32_t *pitch) | |
e024e110 | 456 | { |
4c788679 | 457 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
e024e110 | 458 | if (tiling_flags) |
4c788679 | 459 | *tiling_flags = bo->tiling_flags; |
e024e110 | 460 | if (pitch) |
4c788679 | 461 | *pitch = bo->pitch; |
e024e110 DA |
462 | } |
463 | ||
4c788679 JG |
464 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
465 | bool force_drop) | |
e024e110 | 466 | { |
4c788679 JG |
467 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
468 | ||
469 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) | |
e024e110 DA |
470 | return 0; |
471 | ||
472 | if (force_drop) { | |
4c788679 | 473 | radeon_bo_clear_surface_reg(bo); |
e024e110 DA |
474 | return 0; |
475 | } | |
476 | ||
4c788679 | 477 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
e024e110 DA |
478 | if (!has_moved) |
479 | return 0; | |
480 | ||
4c788679 JG |
481 | if (bo->surface_reg >= 0) |
482 | radeon_bo_clear_surface_reg(bo); | |
e024e110 DA |
483 | return 0; |
484 | } | |
485 | ||
4c788679 | 486 | if ((bo->surface_reg >= 0) && !has_moved) |
e024e110 DA |
487 | return 0; |
488 | ||
4c788679 | 489 | return radeon_bo_get_surface_reg(bo); |
e024e110 DA |
490 | } |
491 | ||
492 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | |
d03d8589 | 493 | struct ttm_mem_reg *mem) |
e024e110 | 494 | { |
d03d8589 JG |
495 | struct radeon_bo *rbo; |
496 | if (!radeon_ttm_bo_is_radeon_bo(bo)) | |
497 | return; | |
498 | rbo = container_of(bo, struct radeon_bo, tbo); | |
4c788679 | 499 | radeon_bo_check_tiling(rbo, 0, 1); |
e024e110 DA |
500 | } |
501 | ||
0a2d50e3 | 502 | int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
e024e110 | 503 | { |
0a2d50e3 | 504 | struct radeon_device *rdev; |
d03d8589 | 505 | struct radeon_bo *rbo; |
0a2d50e3 JG |
506 | unsigned long offset, size; |
507 | int r; | |
508 | ||
d03d8589 | 509 | if (!radeon_ttm_bo_is_radeon_bo(bo)) |
0a2d50e3 | 510 | return 0; |
d03d8589 | 511 | rbo = container_of(bo, struct radeon_bo, tbo); |
4c788679 | 512 | radeon_bo_check_tiling(rbo, 0, 0); |
0a2d50e3 JG |
513 | rdev = rbo->rdev; |
514 | if (bo->mem.mem_type == TTM_PL_VRAM) { | |
515 | size = bo->mem.num_pages << PAGE_SHIFT; | |
516 | offset = bo->mem.mm_node->start << PAGE_SHIFT; | |
517 | if ((offset + size) > rdev->mc.visible_vram_size) { | |
518 | /* hurrah the memory is not visible ! */ | |
519 | radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); | |
520 | rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
521 | r = ttm_bo_validate(bo, &rbo->placement, false, true, false); | |
522 | if (unlikely(r != 0)) | |
523 | return r; | |
524 | offset = bo->mem.mm_node->start << PAGE_SHIFT; | |
525 | /* this should not happen */ | |
526 | if ((offset + size) > rdev->mc.visible_vram_size) | |
527 | return -EINVAL; | |
528 | } | |
529 | } | |
530 | return 0; | |
e024e110 | 531 | } |