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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_legacy_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9 30#include "radeon.h"
4ce001ab 31#include "atom.h"
771fe6b9 32
6b02af1c
AD		 33static void radeon_overscan_setup(struct drm_crtc *crtc,
34 struct drm_display_mode *mode)
35{
36 struct drm_device *dev = crtc->dev;
37 struct radeon_device *rdev = dev->dev_private;
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39
40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
43}
44
c93bb85b 45static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
310a82c8 46 struct drm_display_mode *mode)
c93bb85b
JG		 47{
48 struct drm_device *dev = crtc->dev;
49 struct radeon_device *rdev = dev->dev_private;
50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
51 int xres = mode->hdisplay;
52 int yres = mode->vdisplay;
53 bool hscale = true, vscale = true;
54 int hsync_wid;
55 int vsync_wid;
56 int hsync_start;
57 int blank_width;
58 u32 scale, inc, crtc_more_cntl;
59 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
60 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
61 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
de2103e4 62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
c93bb85b
JG		 63
64 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
65 (RADEON_VERT_STRETCH_RESERVED |
66 RADEON_VERT_AUTO_RATIO_INC);
67 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
68 (RADEON_HORZ_FP_LOOP_STRETCH |
69 RADEON_HORZ_AUTO_RATIO_INC);
70
71 crtc_more_cntl = 0;
72 if ((rdev->family == CHIP_RS100) ||
73 (rdev->family == CHIP_RS200)) {
74 /* This is to workaround the asic bug for RMX, some versions
75 of BIOS dosen't have this register initialized correctly. */
76 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
77 }
78
79
80 fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
81 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
82
83 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
84 if (!hsync_wid)
85 hsync_wid = 1;
86 hsync_start = mode->crtc_hsync_start - 8;
87
88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
89 | ((hsync_wid & 0x3f) << 16)
90 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
91 ? RADEON_CRTC_H_SYNC_POL
92 : 0));
93
94 fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
95 | ((mode->crtc_vdisplay - 1) << 16));
96
97 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
98 if (!vsync_wid)
99 vsync_wid = 1;
100
101 fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
102 | ((vsync_wid & 0x1f) << 16)
103 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
104 ? RADEON_CRTC_V_SYNC_POL
105 : 0));
106
107 fp_horz_vert_active = 0;
108
de2103e4
AD		 109 if (native_mode->hdisplay == 0 ||
110 native_mode->vdisplay == 0) {
c93bb85b
JG		 111 hscale = false;
112 vscale = false;
113 } else {
de2103e4
AD		 114 if (xres > native_mode->hdisplay)
115 xres = native_mode->hdisplay;
116 if (yres > native_mode->vdisplay)
117 yres = native_mode->vdisplay;
c93bb85b 118
de2103e4 119 if (xres == native_mode->hdisplay)
c93bb85b 120 hscale = false;
de2103e4 121 if (yres == native_mode->vdisplay)
c93bb85b
JG		 122 vscale = false;
123 }
124
125 switch (radeon_crtc->rmx_type) {
126 case RMX_FULL:
127 case RMX_ASPECT:
128 if (!hscale)
129 fp_horz_stretch |= ((xres/8-1) << 16);
130 else {
131 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
132 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
de2103e4 133 / native_mode->hdisplay + 1;
c93bb85b
JG		 134 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
135 RADEON_HORZ_STRETCH_BLEND |
136 RADEON_HORZ_STRETCH_ENABLE |
de2103e4 137 ((native_mode->hdisplay/8-1) << 16));
c93bb85b
JG		 138 }
139
140 if (!vscale)
141 fp_vert_stretch |= ((yres-1) << 12);
142 else {
143 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
144 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
de2103e4 145 / native_mode->vdisplay + 1;
c93bb85b
JG		 146 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
147 RADEON_VERT_STRETCH_ENABLE |
148 RADEON_VERT_STRETCH_BLEND |
de2103e4 149 ((native_mode->vdisplay-1) << 12));
c93bb85b
JG		 150 }
151 break;
152 case RMX_CENTER:
153 fp_horz_stretch |= ((xres/8-1) << 16);
154 fp_vert_stretch |= ((yres-1) << 12);
155
156 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
157 RADEON_CRTC_AUTO_VERT_CENTER_EN);
158
159 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
160 if (blank_width > 110)
161 blank_width = 110;
162
163 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
164 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
165
166 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
167 if (!hsync_wid)
168 hsync_wid = 1;
169
170 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
171 | ((hsync_wid & 0x3f) << 16)
172 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
173 ? RADEON_CRTC_H_SYNC_POL
174 : 0));
175
176 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
177 | ((mode->crtc_vdisplay - 1) << 16));
178
179 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
180 if (!vsync_wid)
181 vsync_wid = 1;
182
183 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
184 | ((vsync_wid & 0x1f) << 16)
185 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
186 ? RADEON_CRTC_V_SYNC_POL
187 : 0)));
188
de2103e4
AD		 189 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
190 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
c93bb85b
JG		 191 break;
192 case RMX_OFF:
193 default:
194 fp_horz_stretch |= ((xres/8-1) << 16);
195 fp_vert_stretch |= ((yres-1) << 12);
196 break;
197 }
198
199 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);
200 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);
201 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);
202 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);
203 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);
204 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);
205 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
206 WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
207}
208
771fe6b9
JG		 209void radeon_restore_common_regs(struct drm_device *dev)
210{
211 /* don't need this yet */
212}
213
214static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
215{
216 struct radeon_device *rdev = dev->dev_private;
217 int i = 0;
218
219 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
220 the cause yet, but this workaround will mask the problem for now.
221 Other chips usually will pass at the very first test, so the
222 workaround shouldn't have any effect on them. */
223 for (i = 0;
224 (i < 10000 &&
225 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
226 i++);
227}
228
229static void radeon_pll_write_update(struct drm_device *dev)
230{
231 struct radeon_device *rdev = dev->dev_private;
232
233 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
234
235 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
236 RADEON_PPLL_ATOMIC_UPDATE_W,
237 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
238}
239
240static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
241{
242 struct radeon_device *rdev = dev->dev_private;
243 int i = 0;
244
245
246 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
247 the cause yet, but this workaround will mask the problem for now.
248 Other chips usually will pass at the very first test, so the
249 workaround shouldn't have any effect on them. */
250 for (i = 0;
251 (i < 10000 &&
252 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
253 i++);
254}
255
256static void radeon_pll2_write_update(struct drm_device *dev)
257{
258 struct radeon_device *rdev = dev->dev_private;
259
260 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
261
262 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
263 RADEON_P2PLL_ATOMIC_UPDATE_W,
264 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
265}
266
267static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
268 uint16_t fb_div)
269{
270 unsigned int vcoFreq;
271
272 if (!ref_div)
273 return 1;
274
0537398b 275 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
771fe6b9
JG		 276
277 /*
278 * This is horribly crude: the VCO frequency range is divided into
279 * 3 parts, each part having a fixed PLL gain value.
280 */
281 if (vcoFreq >= 30000)
282 /*
283 * [300..max] MHz : 7
284 */
285 return 7;
286 else if (vcoFreq >= 18000)
287 /*
288 * [180..300) MHz : 4
289 */
290 return 4;
291 else
292 /*
293 * [0..180) MHz : 1
294 */
295 return 1;
296}
297
298void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
299{
300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301 struct drm_device *dev = crtc->dev;
302 struct radeon_device *rdev = dev->dev_private;
303 uint32_t mask;
304
305 if (radeon_crtc->crtc_id)
8de21525 306 mask = (RADEON_CRTC2_DISP_DIS |
771fe6b9
JG		 307 RADEON_CRTC2_VSYNC_DIS |
308 RADEON_CRTC2_HSYNC_DIS |
309 RADEON_CRTC2_DISP_REQ_EN_B);
310 else
311 mask = (RADEON_CRTC_DISPLAY_DIS |
312 RADEON_CRTC_VSYNC_DIS |
313 RADEON_CRTC_HSYNC_DIS);
314
315 switch (mode) {
316 case DRM_MODE_DPMS_ON:
d7311171
AD		 317 radeon_crtc->enabled = true;
318 /* adjust pm to dpms changes BEFORE enabling crtcs */
319 radeon_pm_compute_clocks(rdev);
771fe6b9 320 if (radeon_crtc->crtc_id)
8de21525 321 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
771fe6b9
JG		 322 else {
323 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
324 RADEON_CRTC_DISP_REQ_EN_B));
325 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
326 }
7ed220d7
MD		 327 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
328 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 329 break;
330 case DRM_MODE_DPMS_STANDBY:
331 case DRM_MODE_DPMS_SUSPEND:
332 case DRM_MODE_DPMS_OFF:
7ed220d7 333 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
771fe6b9 334 if (radeon_crtc->crtc_id)
8de21525 335 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
771fe6b9
JG		 336 else {
337 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
338 RADEON_CRTC_DISP_REQ_EN_B));
339 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
340 }
a48b9b4e 341 radeon_crtc->enabled = false;
d7311171
AD		 342 /* adjust pm to dpms changes AFTER disabling crtcs */
343 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 344 break;
345 }
771fe6b9
JG		 346}
347
771fe6b9
JG		 348int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
349 struct drm_framebuffer *old_fb)
350{
351 struct drm_device *dev = crtc->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
354 struct radeon_framebuffer *radeon_fb;
355 struct drm_gem_object *obj;
4c788679 356 struct radeon_bo *rbo;
771fe6b9
JG		 357 uint64_t base;
358 uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
359 uint32_t crtc_pitch, pitch_pixels;
e024e110 360 uint32_t tiling_flags;
41456df2
DA		 361 int format;
362 uint32_t gen_cntl_reg, gen_cntl_val;
4c788679 363 int r;
771fe6b9 364
d9fdaafb 365 DRM_DEBUG_KMS("\n");
2de3b484
JG		 366 /* no fb bound */
367 if (!crtc->fb) {
d9fdaafb 368 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 369 return 0;
370 }
771fe6b9
JG		 371
372 radeon_fb = to_radeon_framebuffer(crtc->fb);
373
41456df2
DA		 374 switch (crtc->fb->bits_per_pixel) {
375 case 8:
376 format = 2;
377 break;
378 case 15: /* 555 */
379 format = 3;
380 break;
381 case 16: /* 565 */
382 format = 4;
383 break;
384 case 24: /* RGB */
385 format = 5;
386 break;
387 case 32: /* xRGB */
388 format = 6;
389 break;
390 default:
391 return false;
392 }
393
4c788679 394 /* Pin framebuffer & get tilling informations */
771fe6b9 395 obj = radeon_fb->obj;
4c788679
JG		 396 rbo = obj->driver_private;
397 r = radeon_bo_reserve(rbo, false);
398 if (unlikely(r != 0))
399 return r;
400 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
401 if (unlikely(r != 0)) {
402 radeon_bo_unreserve(rbo);
771fe6b9
JG		 403 return -EINVAL;
404 }
4c788679
JG		 405 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
406 radeon_bo_unreserve(rbo);
407 if (tiling_flags & RADEON_TILING_MICRO)
408 DRM_ERROR("trying to scanout microtiled buffer\n");
409
4162338a
DA		 410 /* if scanout was in GTT this really wouldn't work */
411 /* crtc offset is from display base addr not FB location */
d594e46a 412 radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
4162338a
DA		 413
414 base -= radeon_crtc->legacy_display_base_addr;
415
771fe6b9
JG		 416 crtc_offset_cntl = 0;
417
418 pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
419 crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) +
420 ((crtc->fb->bits_per_pixel * 8) - 1)) /
421 (crtc->fb->bits_per_pixel * 8));
422 crtc_pitch |= crtc_pitch << 16;
423
e024e110
DA		 424
425 if (tiling_flags & RADEON_TILING_MACRO) {
771fe6b9
JG		 426 if (ASIC_IS_R300(rdev))
427 crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
428 R300_CRTC_MICRO_TILE_BUFFER_DIS |
429 R300_CRTC_MACRO_TILE_EN);
430 else
431 crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
432 } else {
433 if (ASIC_IS_R300(rdev))
434 crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
435 R300_CRTC_MICRO_TILE_BUFFER_DIS |
436 R300_CRTC_MACRO_TILE_EN);
437 else
438 crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
439 }
440
e024e110 441 if (tiling_flags & RADEON_TILING_MACRO) {
771fe6b9
JG		 442 if (ASIC_IS_R300(rdev)) {
443 crtc_tile_x0_y0 = x | (y << 16);
444 base &= ~0x7ff;
445 } else {
446 int byteshift = crtc->fb->bits_per_pixel >> 4;
e024e110 447 int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
771fe6b9
JG		 448 base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
449 crtc_offset_cntl |= (y % 16);
450 }
451 } else {
452 int offset = y * pitch_pixels + x;
453 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 454 case 8:
455 offset *= 1;
456 break;
771fe6b9
JG		 457 case 15:
458 case 16:
459 offset *= 2;
460 break;
461 case 24:
462 offset *= 3;
463 break;
464 case 32:
465 offset *= 4;
466 break;
467 default:
468 return false;
469 }
470 base += offset;
471 }
472
473 base &= ~7;
474
41456df2
DA		 475 if (radeon_crtc->crtc_id == 1)
476 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
477 else
478 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
479
480 gen_cntl_val = RREG32(gen_cntl_reg);
481 gen_cntl_val &= ~(0xf << 8);
482 gen_cntl_val |= (format << 8);
483 WREG32(gen_cntl_reg, gen_cntl_val);
484
771fe6b9
JG		 485 crtc_offset = (u32)base;
486
4162338a 487 WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
771fe6b9
JG		 488
489 if (ASIC_IS_R300(rdev)) {
490 if (radeon_crtc->crtc_id)
491 WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
492 else
493 WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
494 }
495 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
496 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
497 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
498
499 if (old_fb && old_fb != crtc->fb) {
500 radeon_fb = to_radeon_framebuffer(old_fb);
4c788679
JG		 501 rbo = radeon_fb->obj->driver_private;
502 r = radeon_bo_reserve(rbo, false);
503 if (unlikely(r != 0))
504 return r;
505 radeon_bo_unpin(rbo);
506 radeon_bo_unreserve(rbo);
771fe6b9 507 }
f30f37de
MD		 508
509 /* Bytes per pixel may have changed */
510 radeon_bandwidth_update(rdev);
511
771fe6b9
JG		 512 return 0;
513}
514
515static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
516{
517 struct drm_device *dev = crtc->dev;
518 struct radeon_device *rdev = dev->dev_private;
519 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
4ce001ab 520 struct drm_encoder *encoder;
771fe6b9
JG		 521 int format;
522 int hsync_start;
523 int hsync_wid;
524 int vsync_wid;
525 uint32_t crtc_h_total_disp;
526 uint32_t crtc_h_sync_strt_wid;
527 uint32_t crtc_v_total_disp;
528 uint32_t crtc_v_sync_strt_wid;
4ce001ab 529 bool is_tv = false;
771fe6b9 530
d9fdaafb 531 DRM_DEBUG_KMS("\n");
4ce001ab
DA		 532 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
533 if (encoder->crtc == crtc) {
534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
535 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
536 is_tv = true;
537 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
538 break;
539 }
540 }
541 }
771fe6b9
JG		 542
543 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 544 case 8:
545 format = 2;
546 break;
771fe6b9
JG		 547 case 15: /* 555 */
548 format = 3;
549 break;
550 case 16: /* 565 */
551 format = 4;
552 break;
553 case 24: /* RGB */
554 format = 5;
555 break;
556 case 32: /* xRGB */
557 format = 6;
558 break;
559 default:
560 return false;
561 }
562
563 crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
564 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
565
566 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
567 if (!hsync_wid)
568 hsync_wid = 1;
569 hsync_start = mode->crtc_hsync_start - 8;
570
571 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
572 | ((hsync_wid & 0x3f) << 16)
573 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
574 ? RADEON_CRTC_H_SYNC_POL
575 : 0));
576
577 /* This works for double scan mode. */
578 crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
579 | ((mode->crtc_vdisplay - 1) << 16));
580
581 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
582 if (!vsync_wid)
583 vsync_wid = 1;
584
585 crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
586 | ((vsync_wid & 0x1f) << 16)
587 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
588 ? RADEON_CRTC_V_SYNC_POL
589 : 0));
590
771fe6b9
JG		 591 if (radeon_crtc->crtc_id) {
592 uint32_t crtc2_gen_cntl;
593 uint32_t disp2_merge_cntl;
594
ee2215f0
JG		 595 /* if TV DAC is enabled for another crtc and keep it enabled */
596 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
771fe6b9
JG		 597 crtc2_gen_cntl |= ((format << 8)
598 | RADEON_CRTC2_VSYNC_DIS
599 | RADEON_CRTC2_HSYNC_DIS
600 | RADEON_CRTC2_DISP_DIS
601 | RADEON_CRTC2_DISP_REQ_EN_B
602 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
603 ? RADEON_CRTC2_DBL_SCAN_EN
604 : 0)
605 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
606 ? RADEON_CRTC2_CSYNC_EN
607 : 0)
608 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
609 ? RADEON_CRTC2_INTERLACE_EN
610 : 0));
611
d805f50a
AD		 612 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
613 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
614 crtc2_gen_cntl |= RADEON_CRTC2_EN;
615
771fe6b9
JG		 616 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
617 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
618
619 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
620 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1b4d7d75
AD		 621
622 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
623 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
771fe6b9
JG		 624 } else {
625 uint32_t crtc_gen_cntl;
626 uint32_t crtc_ext_cntl;
627 uint32_t disp_merge_cntl;
628
ee2215f0
JG		 629 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
630 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
771fe6b9
JG		 631 | (format << 8)
632 | RADEON_CRTC_DISP_REQ_EN_B
633 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
634 ? RADEON_CRTC_DBL_SCAN_EN
635 : 0)
636 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
637 ? RADEON_CRTC_CSYNC_EN
638 : 0)
639 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
640 ? RADEON_CRTC_INTERLACE_EN
641 : 0));
642
d805f50a
AD		 643 /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
644 if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
645 crtc_gen_cntl |= RADEON_CRTC_EN;
646
771fe6b9
JG		 647 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
648 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
649 RADEON_CRTC_VSYNC_DIS |
650 RADEON_CRTC_HSYNC_DIS |
651 RADEON_CRTC_DISPLAY_DIS);
652
653 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
654 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
655
656 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
657 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
658 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
659 }
660
4ce001ab
DA		 661 if (is_tv)
662 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
663 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
664 &crtc_v_sync_strt_wid);
665
771fe6b9
JG		 666 WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
667 WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
668 WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
669 WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
670
671 return true;
672}
673
674static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
675{
676 struct drm_device *dev = crtc->dev;
677 struct radeon_device *rdev = dev->dev_private;
678 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
679 struct drm_encoder *encoder;
680 uint32_t feedback_div = 0;
681 uint32_t frac_fb_div = 0;
682 uint32_t reference_div = 0;
683 uint32_t post_divider = 0;
684 uint32_t freq = 0;
685 uint8_t pll_gain;
771fe6b9
JG		 686 bool use_bios_divs = false;
687 /* PLL registers */
688 uint32_t pll_ref_div = 0;
689 uint32_t pll_fb_post_div = 0;
690 uint32_t htotal_cntl = 0;
4ce001ab 691 bool is_tv = false;
771fe6b9
JG		 692 struct radeon_pll *pll;
693
694 struct {
695 int divider;
696 int bitvalue;
697 } *post_div, post_divs[] = {
698 /* From RAGE 128 VR/RAGE 128 GL Register
699 * Reference Manual (Technical Reference
700 * Manual P/N RRG-G04100-C Rev. 0.04), page
701 * 3-17 (PLL_DIV_[3:0]).
702 */
703 { 1, 0 }, /* VCLK_SRC */
704 { 2, 1 }, /* VCLK_SRC/2 */
705 { 4, 2 }, /* VCLK_SRC/4 */
706 { 8, 3 }, /* VCLK_SRC/8 */
707 { 3, 4 }, /* VCLK_SRC/3 */
708 { 16, 5 }, /* VCLK_SRC/16 */
709 { 6, 6 }, /* VCLK_SRC/6 */
710 { 12, 7 }, /* VCLK_SRC/12 */
711 { 0, 0 }
712 };
713
714 if (radeon_crtc->crtc_id)
715 pll = &rdev->clock.p2pll;
716 else
717 pll = &rdev->clock.p1pll;
718
fc10332b 719 pll->flags = RADEON_PLL_LEGACY;
383be5d1
AD		 720 if (radeon_new_pll == 1)
721 pll->algo = PLL_ALGO_NEW;
722 else
723 pll->algo = PLL_ALGO_LEGACY;
fc10332b 724
771fe6b9 725 if (mode->clock > 200000) /* range limits??? */
fc10332b 726 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 727 else
fc10332b 728 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9
JG		 729
730 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
731 if (encoder->crtc == crtc) {
4ce001ab
DA		 732 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
733
734 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
735 is_tv = true;
736 break;
737 }
738
771fe6b9 739 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 740 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
771fe6b9 741 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
4c4f5413
AD		 742 if (!rdev->is_atom_bios) {
743 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
744 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
745 if (lvds) {
746 if (lvds->use_bios_dividers) {
747 pll_ref_div = lvds->panel_ref_divider;
748 pll_fb_post_div = (lvds->panel_fb_divider |
749 (lvds->panel_post_divider << 16));
750 htotal_cntl = 0;
751 use_bios_divs = true;
752 }
771fe6b9
JG		 753 }
754 }
fc10332b 755 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9
JG		 756 }
757 }
758 }
759
d9fdaafb 760 DRM_DEBUG_KMS("\n");
771fe6b9
JG		 761
762 if (!use_bios_divs) {
763 radeon_compute_pll(pll, mode->clock,
764 &freq, &feedback_div, &frac_fb_div,
fc10332b 765 &reference_div, &post_divider);
771fe6b9
JG		 766
767 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
768 if (post_div->divider == post_divider)
769 break;
770 }
771
772 if (!post_div->divider)
773 post_div = &post_divs[0];
774
d9fdaafb 775 DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
771fe6b9
JG		 776 (unsigned)freq,
777 feedback_div,
778 reference_div,
779 post_divider);
780
781 pll_ref_div = reference_div;
782#if defined(__powerpc__) && (0) /* TODO */
783 /* apparently programming this otherwise causes a hang??? */
784 if (info->MacModel == RADEON_MAC_IBOOK)
785 pll_fb_post_div = 0x000600ad;
786 else
787#endif
788 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16));
789
790 htotal_cntl = mode->htotal & 0x7;
791
792 }
793
794 pll_gain = radeon_compute_pll_gain(pll->reference_freq,
795 pll_ref_div & 0x3ff,
796 pll_fb_post_div & 0x7ff);
797
798 if (radeon_crtc->crtc_id) {
799 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
800 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
801 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
802
4ce001ab
DA		 803 if (is_tv) {
804 radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
805 &pll_ref_div, &pll_fb_post_div,
806 &pixclks_cntl);
807 }
808
771fe6b9
JG		 809 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
810 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
811 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
812
813 WREG32_PLL_P(RADEON_P2PLL_CNTL,
814 RADEON_P2PLL_RESET
815 | RADEON_P2PLL_ATOMIC_UPDATE_EN
816 | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
817 ~(RADEON_P2PLL_RESET
818 | RADEON_P2PLL_ATOMIC_UPDATE_EN
819 | RADEON_P2PLL_PVG_MASK));
820
821 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
822 pll_ref_div,
823 ~RADEON_P2PLL_REF_DIV_MASK);
824
825 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
826 pll_fb_post_div,
827 ~RADEON_P2PLL_FB0_DIV_MASK);
828
829 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
830 pll_fb_post_div,
831 ~RADEON_P2PLL_POST0_DIV_MASK);
832
833 radeon_pll2_write_update(dev);
834 radeon_pll2_wait_for_read_update_complete(dev);
835
836 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
837
838 WREG32_PLL_P(RADEON_P2PLL_CNTL,
839 0,
840 ~(RADEON_P2PLL_RESET
841 | RADEON_P2PLL_SLEEP
842 | RADEON_P2PLL_ATOMIC_UPDATE_EN));
843
d9fdaafb 844 DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
771fe6b9
JG		 845 (unsigned)pll_ref_div,
846 (unsigned)pll_fb_post_div,
847 (unsigned)htotal_cntl,
848 RREG32_PLL(RADEON_P2PLL_CNTL));
d9fdaafb 849 DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
771fe6b9
JG		 850 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
851 (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
852 (unsigned)((pll_fb_post_div &
853 RADEON_P2PLL_POST0_DIV_MASK) >> 16));
854
855 mdelay(50); /* Let the clock to lock */
856
857 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
858 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
859 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
860
861 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
862 } else {
4ce001ab
DA		 863 uint32_t pixclks_cntl;
864
865
866 if (is_tv) {
867 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
868 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
869 &pll_fb_post_div, &pixclks_cntl);
870 }
871
771fe6b9
JG		 872 if (rdev->flags & RADEON_IS_MOBILITY) {
873 /* A temporal workaround for the occational blanking on certain laptop panels.
874 This appears to related to the PLL divider registers (fail to lock?).
875 It occurs even when all dividers are the same with their old settings.
876 In this case we really don't need to fiddle with PLL registers.
877 By doing this we can avoid the blanking problem with some panels.
878 */
879 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
880 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
881 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
882 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
883 RADEON_PLL_DIV_SEL,
884 ~(RADEON_PLL_DIV_SEL));
885 r100_pll_errata_after_index(rdev);
886 return;
887 }
888 }
889
890 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
891 RADEON_VCLK_SRC_SEL_CPUCLK,
892 ~(RADEON_VCLK_SRC_SEL_MASK));
893 WREG32_PLL_P(RADEON_PPLL_CNTL,
894 RADEON_PPLL_RESET
895 | RADEON_PPLL_ATOMIC_UPDATE_EN
896 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
897 | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
898 ~(RADEON_PPLL_RESET
899 | RADEON_PPLL_ATOMIC_UPDATE_EN
900 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
901 | RADEON_PPLL_PVG_MASK));
902
903 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
904 RADEON_PLL_DIV_SEL,
905 ~(RADEON_PLL_DIV_SEL));
906 r100_pll_errata_after_index(rdev);
907
908 if (ASIC_IS_R300(rdev) ||
909 (rdev->family == CHIP_RS300) ||
910 (rdev->family == CHIP_RS400) ||
911 (rdev->family == CHIP_RS480)) {
912 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
913 /* When restoring console mode, use saved PPLL_REF_DIV
914 * setting.
915 */
916 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
917 pll_ref_div,
918 0);
919 } else {
920 /* R300 uses ref_div_acc field as real ref divider */
921 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
922 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
923 ~R300_PPLL_REF_DIV_ACC_MASK);
924 }
925 } else
926 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
927 pll_ref_div,
928 ~RADEON_PPLL_REF_DIV_MASK);
929
930 WREG32_PLL_P(RADEON_PPLL_DIV_3,
931 pll_fb_post_div,
932 ~RADEON_PPLL_FB3_DIV_MASK);
933
934 WREG32_PLL_P(RADEON_PPLL_DIV_3,
935 pll_fb_post_div,
936 ~RADEON_PPLL_POST3_DIV_MASK);
937
938 radeon_pll_write_update(dev);
939 radeon_pll_wait_for_read_update_complete(dev);
940
941 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
942
943 WREG32_PLL_P(RADEON_PPLL_CNTL,
944 0,
945 ~(RADEON_PPLL_RESET
946 | RADEON_PPLL_SLEEP
947 | RADEON_PPLL_ATOMIC_UPDATE_EN
948 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
949
d9fdaafb 950 DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
771fe6b9
JG		 951 pll_ref_div,
952 pll_fb_post_div,
953 (unsigned)htotal_cntl,
954 RREG32_PLL(RADEON_PPLL_CNTL));
d9fdaafb 955 DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
771fe6b9
JG		 956 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
957 pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
958 (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
959
960 mdelay(50); /* Let the clock to lock */
961
962 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
963 RADEON_VCLK_SRC_SEL_PPLLCLK,
964 ~(RADEON_VCLK_SRC_SEL_MASK));
965
4ce001ab
DA		 966 if (is_tv)
967 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
771fe6b9
JG		 968 }
969}
970
971static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
972 struct drm_display_mode *mode,
973 struct drm_display_mode *adjusted_mode)
974{
03214bd5
AD		 975 struct drm_device *dev = crtc->dev;
976 struct radeon_device *rdev = dev->dev_private;
977
978 /* adjust pm to upcoming mode change */
979 radeon_pm_compute_clocks(rdev);
980
c93bb85b
JG		 981 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
982 return false;
771fe6b9
JG		 983 return true;
984}
985
986static int radeon_crtc_mode_set(struct drm_crtc *crtc,
987 struct drm_display_mode *mode,
988 struct drm_display_mode *adjusted_mode,
989 int x, int y, struct drm_framebuffer *old_fb)
990{
c93bb85b 991 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 992
993 /* TODO TV */
771fe6b9
JG		 994 radeon_crtc_set_base(crtc, x, y, old_fb);
995 radeon_set_crtc_timing(crtc, adjusted_mode);
996 radeon_set_pll(crtc, adjusted_mode);
6b02af1c 997 radeon_overscan_setup(crtc, adjusted_mode);
c93bb85b 998 if (radeon_crtc->crtc_id == 0) {
310a82c8 999 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
c93bb85b
JG		 1000 } else {
1001 if (radeon_crtc->rmx_type != RMX_OFF) {
1002 /* FIXME: only first crtc has rmx what should we
1003 * do ?
1004 */
1005 DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1006 }
1007 }
771fe6b9
JG		 1008 return 0;
1009}
1010
1011static void radeon_crtc_prepare(struct drm_crtc *crtc)
1012{
ec51efa9
PO		 1013 struct drm_device *dev = crtc->dev;
1014 struct drm_crtc *crtci;
1015
1016 /*
1017 * The hardware wedges sometimes if you reconfigure one CRTC
1018 * whilst another is running (see fdo bug #24611).
1019 */
1020 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1021 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1022}
1023
1024static void radeon_crtc_commit(struct drm_crtc *crtc)
1025{
ec51efa9
PO		 1026 struct drm_device *dev = crtc->dev;
1027 struct drm_crtc *crtci;
1028
1029 /*
1030 * Reenable the CRTCs that should be running.
1031 */
1032 list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1033 if (crtci->enabled)
1034 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1035 }
771fe6b9
JG		 1036}
1037
1038static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1039 .dpms = radeon_crtc_dpms,
1040 .mode_fixup = radeon_crtc_mode_fixup,
1041 .mode_set = radeon_crtc_mode_set,
1042 .mode_set_base = radeon_crtc_set_base,
1043 .prepare = radeon_crtc_prepare,
1044 .commit = radeon_crtc_commit,
068143d3 1045 .load_lut = radeon_crtc_load_lut,
771fe6b9
JG		 1046};
1047
1048
1049void radeon_legacy_init_crtc(struct drm_device *dev,
1050 struct radeon_crtc *radeon_crtc)
1051{
1052 if (radeon_crtc->crtc_id == 1)
1053 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1054 drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1055}
Clone of davem's net-next-2.6 tree