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771fe6b9 JG |
1 | /* |
2 | * Copyright © 2007 David Airlie | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * David Airlie | |
25 | */ | |
771fe6b9 | 26 | #include <linux/module.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
771fe6b9 | 28 | #include <linux/fb.h> |
771fe6b9 JG |
29 | |
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "radeon_drm.h" | |
35 | #include "radeon.h" | |
36 | ||
785b93ef DA |
37 | #include "drm_fb_helper.h" |
38 | ||
6a9ee8af DA |
39 | #include <linux/vga_switcheroo.h> |
40 | ||
38651674 DA |
41 | /* object hierarchy - |
42 | this contains a helper + a radeon fb | |
43 | the helper contains a pointer to radeon framebuffer baseclass. | |
44 | */ | |
8be48d92 | 45 | struct radeon_fbdev { |
785b93ef | 46 | struct drm_fb_helper helper; |
38651674 DA |
47 | struct radeon_framebuffer rfb; |
48 | struct list_head fbdev_list; | |
49 | struct radeon_device *rdev; | |
771fe6b9 JG |
50 | }; |
51 | ||
771fe6b9 JG |
52 | static struct fb_ops radeonfb_ops = { |
53 | .owner = THIS_MODULE, | |
c88f9f0c | 54 | .fb_check_var = drm_fb_helper_check_var, |
785b93ef | 55 | .fb_set_par = drm_fb_helper_set_par, |
771fe6b9 JG |
56 | .fb_fillrect = cfb_fillrect, |
57 | .fb_copyarea = cfb_copyarea, | |
58 | .fb_imageblit = cfb_imageblit, | |
785b93ef DA |
59 | .fb_pan_display = drm_fb_helper_pan_display, |
60 | .fb_blank = drm_fb_helper_blank, | |
068143d3 | 61 | .fb_setcmap = drm_fb_helper_setcmap, |
771fe6b9 JG |
62 | }; |
63 | ||
771fe6b9 | 64 | |
e024e110 | 65 | static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) |
771fe6b9 JG |
66 | { |
67 | int aligned = width; | |
e024e110 | 68 | int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; |
771fe6b9 JG |
69 | int pitch_mask = 0; |
70 | ||
71 | switch (bpp / 8) { | |
72 | case 1: | |
73 | pitch_mask = align_large ? 255 : 127; | |
74 | break; | |
75 | case 2: | |
76 | pitch_mask = align_large ? 127 : 31; | |
77 | break; | |
78 | case 3: | |
79 | case 4: | |
80 | pitch_mask = align_large ? 63 : 15; | |
81 | break; | |
82 | } | |
83 | ||
84 | aligned += pitch_mask; | |
85 | aligned &= ~pitch_mask; | |
86 | return aligned; | |
87 | } | |
88 | ||
8be48d92 | 89 | static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj) |
771fe6b9 | 90 | { |
8be48d92 DA |
91 | struct radeon_bo *rbo = gobj->driver_private; |
92 | int ret; | |
93 | ||
94 | ret = radeon_bo_reserve(rbo, false); | |
95 | if (likely(ret == 0)) { | |
96 | radeon_bo_kunmap(rbo); | |
29d08b3e | 97 | radeon_bo_unpin(rbo); |
8be48d92 DA |
98 | radeon_bo_unreserve(rbo); |
99 | } | |
29d08b3e | 100 | drm_gem_object_handle_unreference(gobj); |
8be48d92 DA |
101 | drm_gem_object_unreference_unlocked(gobj); |
102 | } | |
785b93ef | 103 | |
8be48d92 DA |
104 | static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, |
105 | struct drm_mode_fb_cmd *mode_cmd, | |
106 | struct drm_gem_object **gobj_p) | |
771fe6b9 | 107 | { |
8be48d92 | 108 | struct radeon_device *rdev = rfbdev->rdev; |
771fe6b9 | 109 | struct drm_gem_object *gobj = NULL; |
4c788679 | 110 | struct radeon_bo *rbo = NULL; |
e024e110 | 111 | bool fb_tiled = false; /* useful for testing */ |
c88f9f0c | 112 | u32 tiling_flags = 0; |
8be48d92 DA |
113 | int ret; |
114 | int aligned_size, size; | |
771fe6b9 | 115 | |
771fe6b9 | 116 | /* need to align pitch with crtc limits */ |
8be48d92 | 117 | mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8); |
771fe6b9 | 118 | |
8be48d92 | 119 | size = mode_cmd->pitch * mode_cmd->height; |
771fe6b9 | 120 | aligned_size = ALIGN(size, PAGE_SIZE); |
771fe6b9 | 121 | ret = radeon_gem_object_create(rdev, aligned_size, 0, |
8be48d92 | 122 | RADEON_GEM_DOMAIN_VRAM, |
4dfe947e | 123 | false, true, |
8be48d92 | 124 | &gobj); |
771fe6b9 | 125 | if (ret) { |
8be48d92 DA |
126 | printk(KERN_ERR "failed to allocate framebuffer (%d)\n", |
127 | aligned_size); | |
128 | return -ENOMEM; | |
771fe6b9 | 129 | } |
4c788679 | 130 | rbo = gobj->driver_private; |
771fe6b9 | 131 | |
e024e110 | 132 | if (fb_tiled) |
c88f9f0c MD |
133 | tiling_flags = RADEON_TILING_MACRO; |
134 | ||
135 | #ifdef __BIG_ENDIAN | |
8be48d92 | 136 | switch (mode_cmd->bpp) { |
c88f9f0c MD |
137 | case 32: |
138 | tiling_flags |= RADEON_TILING_SWAP_32BIT; | |
139 | break; | |
140 | case 16: | |
141 | tiling_flags |= RADEON_TILING_SWAP_16BIT; | |
142 | default: | |
143 | break; | |
144 | } | |
145 | #endif | |
146 | ||
4c788679 JG |
147 | if (tiling_flags) { |
148 | ret = radeon_bo_set_tiling_flags(rbo, | |
8be48d92 DA |
149 | tiling_flags | RADEON_TILING_SURFACE, |
150 | mode_cmd->pitch); | |
4c788679 JG |
151 | if (ret) |
152 | dev_err(rdev->dev, "FB failed to set tiling flags\n"); | |
153 | } | |
8be48d92 | 154 | |
38651674 | 155 | |
4c788679 JG |
156 | ret = radeon_bo_reserve(rbo, false); |
157 | if (unlikely(ret != 0)) | |
158 | goto out_unref; | |
8be48d92 | 159 | ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL); |
4c788679 JG |
160 | if (ret) { |
161 | radeon_bo_unreserve(rbo); | |
162 | goto out_unref; | |
163 | } | |
164 | if (fb_tiled) | |
165 | radeon_bo_check_tiling(rbo, 0, 0); | |
8be48d92 | 166 | ret = radeon_bo_kmap(rbo, NULL); |
4c788679 | 167 | radeon_bo_unreserve(rbo); |
f92e93eb | 168 | if (ret) { |
f92e93eb JG |
169 | goto out_unref; |
170 | } | |
771fe6b9 | 171 | |
8be48d92 DA |
172 | *gobj_p = gobj; |
173 | return 0; | |
174 | out_unref: | |
175 | radeonfb_destroy_pinned_object(gobj); | |
176 | *gobj_p = NULL; | |
177 | return ret; | |
178 | } | |
179 | ||
180 | static int radeonfb_create(struct radeon_fbdev *rfbdev, | |
181 | struct drm_fb_helper_surface_size *sizes) | |
182 | { | |
183 | struct radeon_device *rdev = rfbdev->rdev; | |
184 | struct fb_info *info; | |
185 | struct drm_framebuffer *fb = NULL; | |
186 | struct drm_mode_fb_cmd mode_cmd; | |
187 | struct drm_gem_object *gobj = NULL; | |
188 | struct radeon_bo *rbo = NULL; | |
189 | struct device *device = &rdev->pdev->dev; | |
190 | int ret; | |
191 | unsigned long tmp; | |
192 | ||
193 | mode_cmd.width = sizes->surface_width; | |
194 | mode_cmd.height = sizes->surface_height; | |
195 | ||
196 | /* avivo can't scanout real 24bpp */ | |
197 | if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev)) | |
198 | sizes->surface_bpp = 32; | |
199 | ||
200 | mode_cmd.bpp = sizes->surface_bpp; | |
201 | mode_cmd.depth = sizes->surface_depth; | |
771fe6b9 | 202 | |
8be48d92 DA |
203 | ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj); |
204 | rbo = gobj->driver_private; | |
771fe6b9 | 205 | |
8be48d92 DA |
206 | /* okay we have an object now allocate the framebuffer */ |
207 | info = framebuffer_alloc(0, device); | |
771fe6b9 JG |
208 | if (info == NULL) { |
209 | ret = -ENOMEM; | |
210 | goto out_unref; | |
211 | } | |
785b93ef | 212 | |
8be48d92 | 213 | info->par = rfbdev; |
771fe6b9 | 214 | |
8be48d92 DA |
215 | radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); |
216 | ||
38651674 DA |
217 | fb = &rfbdev->rfb.base; |
218 | ||
219 | /* setup helper */ | |
220 | rfbdev->helper.fb = fb; | |
221 | rfbdev->helper.fbdev = info; | |
38651674 | 222 | |
8be48d92 | 223 | memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo)); |
bf8e828b | 224 | |
771fe6b9 | 225 | strcpy(info->fix.id, "radeondrmfb"); |
785b93ef | 226 | |
068143d3 | 227 | drm_fb_helper_fill_fix(info, fb->pitch, fb->depth); |
785b93ef | 228 | |
8fd4bd22 | 229 | info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT; |
771fe6b9 | 230 | info->fbops = &radeonfb_ops; |
785b93ef | 231 | |
8be48d92 | 232 | tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; |
f92e93eb | 233 | info->fix.smem_start = rdev->mc.aper_base + tmp; |
8be48d92 DA |
234 | info->fix.smem_len = radeon_bo_size(rbo); |
235 | info->screen_base = rbo->kptr; | |
236 | info->screen_size = radeon_bo_size(rbo); | |
785b93ef | 237 | |
38651674 | 238 | drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height); |
ed8f0d9e DA |
239 | |
240 | /* setup aperture base/size for vesafb takeover */ | |
1471ca9a MS |
241 | info->apertures = alloc_apertures(1); |
242 | if (!info->apertures) { | |
243 | ret = -ENOMEM; | |
244 | goto out_unref; | |
245 | } | |
246 | info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base; | |
247 | info->apertures->ranges[0].size = rdev->mc.real_vram_size; | |
ed8f0d9e | 248 | |
696d4df1 MD |
249 | info->fix.mmio_start = 0; |
250 | info->fix.mmio_len = 0; | |
771fe6b9 JG |
251 | info->pixmap.size = 64*1024; |
252 | info->pixmap.buf_align = 8; | |
253 | info->pixmap.access_align = 32; | |
254 | info->pixmap.flags = FB_PIXMAP_SYSTEM; | |
255 | info->pixmap.scan_align = 1; | |
4abe3520 | 256 | |
771fe6b9 JG |
257 | if (info->screen_base == NULL) { |
258 | ret = -ENOSPC; | |
259 | goto out_unref; | |
260 | } | |
4abe3520 DA |
261 | |
262 | ret = fb_alloc_cmap(&info->cmap, 256, 0); | |
263 | if (ret) { | |
264 | ret = -ENOMEM; | |
265 | goto out_unref; | |
266 | } | |
267 | ||
771fe6b9 JG |
268 | DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); |
269 | DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base); | |
8be48d92 | 270 | DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); |
771fe6b9 JG |
271 | DRM_INFO("fb depth is %d\n", fb->depth); |
272 | DRM_INFO(" pitch is %d\n", fb->pitch); | |
273 | ||
6a9ee8af | 274 | vga_switcheroo_client_fb_set(rdev->ddev->pdev, info); |
771fe6b9 JG |
275 | return 0; |
276 | ||
277 | out_unref: | |
4c788679 | 278 | if (rbo) { |
8be48d92 | 279 | |
771fe6b9 | 280 | } |
f92e93eb | 281 | if (fb && ret) { |
771fe6b9 JG |
282 | drm_gem_object_unreference(gobj); |
283 | drm_framebuffer_cleanup(fb); | |
284 | kfree(fb); | |
285 | } | |
771fe6b9 JG |
286 | return ret; |
287 | } | |
288 | ||
8be48d92 DA |
289 | static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper, |
290 | struct drm_fb_helper_surface_size *sizes) | |
38651674 | 291 | { |
8be48d92 | 292 | struct radeon_fbdev *rfbdev = (struct radeon_fbdev *)helper; |
38651674 DA |
293 | int new_fb = 0; |
294 | int ret; | |
295 | ||
8be48d92 DA |
296 | if (!helper->fb) { |
297 | ret = radeonfb_create(rfbdev, sizes); | |
38651674 DA |
298 | if (ret) |
299 | return ret; | |
38651674 | 300 | new_fb = 1; |
38651674 | 301 | } |
38651674 DA |
302 | return new_fb; |
303 | } | |
304 | ||
d50ba256 DA |
305 | static char *mode_option; |
306 | int radeon_parse_options(char *options) | |
307 | { | |
308 | char *this_opt; | |
309 | ||
310 | if (!options || !*options) | |
311 | return 0; | |
312 | ||
313 | while ((this_opt = strsep(&options, ",")) != NULL) { | |
314 | if (!*this_opt) | |
315 | continue; | |
316 | mode_option = this_opt; | |
317 | } | |
318 | return 0; | |
319 | } | |
320 | ||
eb1f8e4f | 321 | void radeon_fb_output_poll_changed(struct radeon_device *rdev) |
771fe6b9 | 322 | { |
eb1f8e4f | 323 | drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper); |
771fe6b9 | 324 | } |
771fe6b9 | 325 | |
8be48d92 | 326 | static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev) |
771fe6b9 JG |
327 | { |
328 | struct fb_info *info; | |
38651674 | 329 | struct radeon_framebuffer *rfb = &rfbdev->rfb; |
771fe6b9 | 330 | |
8be48d92 DA |
331 | if (rfbdev->helper.fbdev) { |
332 | info = rfbdev->helper.fbdev; | |
4abe3520 | 333 | |
8be48d92 | 334 | unregister_framebuffer(info); |
4abe3520 DA |
335 | if (info->cmap.len) |
336 | fb_dealloc_cmap(&info->cmap); | |
8be48d92 | 337 | framebuffer_release(info); |
771fe6b9 | 338 | } |
771fe6b9 | 339 | |
8be48d92 | 340 | if (rfb->obj) { |
29d08b3e DA |
341 | radeonfb_destroy_pinned_object(rfb->obj); |
342 | rfb->obj = NULL; | |
771fe6b9 | 343 | } |
4abe3520 | 344 | drm_fb_helper_fini(&rfbdev->helper); |
38651674 | 345 | drm_framebuffer_cleanup(&rfb->base); |
771fe6b9 | 346 | |
771fe6b9 JG |
347 | return 0; |
348 | } | |
785b93ef | 349 | |
4abe3520 DA |
350 | static struct drm_fb_helper_funcs radeon_fb_helper_funcs = { |
351 | .gamma_set = radeon_crtc_fb_gamma_set, | |
352 | .gamma_get = radeon_crtc_fb_gamma_get, | |
353 | .fb_probe = radeon_fb_find_or_create_single, | |
4abe3520 | 354 | }; |
38651674 DA |
355 | |
356 | int radeon_fbdev_init(struct radeon_device *rdev) | |
357 | { | |
8be48d92 | 358 | struct radeon_fbdev *rfbdev; |
4abe3520 | 359 | int bpp_sel = 32; |
5a79395b | 360 | int ret; |
4abe3520 DA |
361 | |
362 | /* select 8 bpp console on RN50 or 16MB cards */ | |
363 | if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024)) | |
364 | bpp_sel = 8; | |
8be48d92 DA |
365 | |
366 | rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL); | |
367 | if (!rfbdev) | |
368 | return -ENOMEM; | |
369 | ||
370 | rfbdev->rdev = rdev; | |
371 | rdev->mode_info.rfbdev = rfbdev; | |
4abe3520 | 372 | rfbdev->helper.funcs = &radeon_fb_helper_funcs; |
8be48d92 | 373 | |
5a79395b CW |
374 | ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper, |
375 | rdev->num_crtc, | |
376 | RADEONFB_CONN_LIMIT); | |
377 | if (ret) { | |
378 | kfree(rfbdev); | |
379 | return ret; | |
380 | } | |
381 | ||
0b4c0f3f | 382 | drm_fb_helper_single_add_all_connectors(&rfbdev->helper); |
4abe3520 | 383 | drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); |
771fe6b9 | 384 | return 0; |
38651674 DA |
385 | } |
386 | ||
387 | void radeon_fbdev_fini(struct radeon_device *rdev) | |
388 | { | |
8be48d92 DA |
389 | if (!rdev->mode_info.rfbdev) |
390 | return; | |
391 | ||
38651674 | 392 | radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev); |
8be48d92 | 393 | kfree(rdev->mode_info.rfbdev); |
38651674 DA |
394 | rdev->mode_info.rfbdev = NULL; |
395 | } | |
396 | ||
397 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state) | |
398 | { | |
399 | fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state); | |
400 | } | |
401 | ||
402 | int radeon_fbdev_total_size(struct radeon_device *rdev) | |
403 | { | |
404 | struct radeon_bo *robj; | |
405 | int size = 0; | |
406 | ||
407 | robj = rdev->mode_info.rfbdev->rfb.obj->driver_private; | |
408 | size += radeon_bo_size(robj); | |
409 | return size; | |
410 | } | |
411 | ||
412 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj) | |
413 | { | |
414 | if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private) | |
415 | return true; | |
416 | return false; | |
771fe6b9 | 417 | } |