[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/fb.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon.h"

#include "drm_fb_helper.h"

#include <linux/vga_switcheroo.h>

/* object hierarchy -
   this contains a helper + a radeon fb
   the helper contains a pointer to radeon framebuffer baseclass.
*/
struct radeon_fbdev {
	struct drm_fb_helper helper;
	struct radeon_framebuffer rfb;
	struct list_head fbdev_list;
	struct radeon_device *rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_fillrect = cfb_fillrect,
	.fb_copyarea = cfb_copyarea,
	.fb_imageblit = cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
};


static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct radeon_bo *rbo = gobj->driver_private;
	int ret;

	ret = radeon_bo_reserve(rbo, false);
	if (likely(ret == 0)) {
		radeon_bo_kunmap(rbo);
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
	}
	drm_gem_object_unreference_unlocked(gobj);
}

static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
					 struct drm_mode_fb_cmd *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;
	int ret;
	int aligned_size, size;

	/* need to align pitch with crtc limits */
	mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);

	size = mode_cmd->pitch * mode_cmd->height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = radeon_gem_object_create(rdev, aligned_size, 0,
				       RADEON_GEM_DOMAIN_VRAM,
				       false, true,
				       &gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
		       aligned_size);
		return -ENOMEM;
	}
	rbo = gobj->driver_private;

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (mode_cmd->bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags) {
		ret = radeon_bo_set_tiling_flags(rbo,
						 tiling_flags | RADEON_TILING_SURFACE,
						 mode_cmd->pitch);
		if (ret)
			dev_err(rdev->dev, "FB failed to set tiling flags\n");
	}


	ret = radeon_bo_reserve(rbo, false);
	if (unlikely(ret != 0))
		goto out_unref;
	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
	if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;
	}
	if (fb_tiled)
		radeon_bo_check_tiling(rbo, 0, 0);
	ret = radeon_bo_kmap(rbo, NULL);
	radeon_bo_unreserve(rbo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	radeonfb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int radeonfb_create(struct radeon_fbdev *rfbdev,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	struct device *device = &rdev->pdev->dev;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	/* avivo can't scanout real 24bpp */
	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		sizes->surface_bpp = 32;

	mode_cmd.bpp = sizes->surface_bpp;
	mode_cmd.depth = sizes->surface_depth;

	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	rbo = gobj->driver_private;

	/* okay we have an object now allocate the framebuffer */
	info = framebuffer_alloc(0, device);
	if (info == NULL) {
		ret = -ENOMEM;
		goto out_unref;
	}

	info->par = rfbdev;

	radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;
	rfbdev->helper.fbdev = info;

	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);

	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
	info->fbops = &radeonfb_ops;

	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = radeon_bo_size(rbo);
	info->screen_base = rbo->kptr;
	info->screen_size = radeon_bo_size(rbo);

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->apertures = alloc_apertures(1);
	if (!info->apertures) {
		ret = -ENOMEM;
		goto out_unref;
	}
	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
	info->apertures->ranges[0].size = rdev->mc.real_vram_size;

	info->fix.mmio_start = 0;
	info->fix.mmio_len = 0;
	info->pixmap.size = 64*1024;
	info->pixmap.buf_align = 8;
	info->pixmap.access_align = 32;
	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	info->pixmap.scan_align = 1;

	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_unref;
	}

	ret = fb_alloc_cmap(&info->cmap, 256, 0);
	if (ret) {
		ret = -ENOMEM;
		goto out_unref;
	}

	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitch);

	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	return 0;

out_unref:
	if (rbo) {

	}
	if (fb && ret) {
		drm_gem_object_unreference(gobj);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper,
					   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_fbdev *rfbdev = (struct radeon_fbdev *)helper;
	int new_fb = 0;
	int ret;

	if (!helper->fb) {
		ret = radeonfb_create(rfbdev, sizes);
		if (ret)
			return ret;
		new_fb = 1;
	}
	return new_fb;
}

static char *mode_option;
int radeon_parse_options(char *options)
{
	char *this_opt;

	if (!options || !*options)
		return 0;

	while ((this_opt = strsep(&options, ",")) != NULL) {
		if (!*this_opt)
			continue;
		mode_option = this_opt;
	}
	return 0;
}

void radeon_fb_output_poll_changed(struct radeon_device *rdev)
{
	drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
}

static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev)
{
	struct fb_info *info;
	struct radeon_framebuffer *rfb = &rfbdev->rfb;

	if (rfbdev->helper.fbdev) {
		info = rfbdev->helper.fbdev;

		unregister_framebuffer(info);
		if (info->cmap.len)
			fb_dealloc_cmap(&info->cmap);
		framebuffer_release(info);
	}

	if (rfb->obj) {
		radeonfb_destroy_pinned_object(rfb->obj);
		rfb->obj = NULL;
	}
	drm_fb_helper_fini(&rfbdev->helper);
	drm_framebuffer_cleanup(&rfb->base);

	return 0;
}

static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
	.fb_probe = radeon_fb_find_or_create_single,
};

int radeon_fbdev_init(struct radeon_device *rdev)
{
	struct radeon_fbdev *rfbdev;
	int bpp_sel = 32;
	int ret;

	/* select 8 bpp console on RN50 or 16MB cards */
	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->rdev = rdev;
	rdev->mode_info.rfbdev = rfbdev;
	rfbdev->helper.funcs = &radeon_fb_helper_funcs;

	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
				 rdev->num_crtc,
				 RADEONFB_CONN_LIMIT);
	if (ret) {
		kfree(rfbdev);
		return ret;
	}

	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	return 0;
}

void radeon_fbdev_fini(struct radeon_device *rdev)
{
	if (!rdev->mode_info.rfbdev)
		return;

	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
	kfree(rdev->mode_info.rfbdev);
	rdev->mode_info.rfbdev = NULL;
}

void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
{
	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
}

int radeon_fbdev_total_size(struct radeon_device *rdev)
{
	struct radeon_bo *robj;
	int size = 0;

	robj = rdev->mode_info.rfbdev->rfb.obj->driver_private;
	size += radeon_bo_size(robj);
	return size;
}

bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
{
	if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private)
		return true;
	return false;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
771fe6b9	26	#include <linux/module.h>
5a0e3ad6	27	#include <linux/slab.h>
771fe6b9	28	#include <linux/fb.h>
771fe6b9 JG	29
	30	#include "drmP.h"
	31	#include "drm.h"
	32	#include "drm_crtc.h"
	33	#include "drm_crtc_helper.h"
	34	#include "radeon_drm.h"
	35	#include "radeon.h"
	36
785b93ef DA	37	#include "drm_fb_helper.h"
785b93ef DA	38
6a9ee8af DA	39	#include <linux/vga_switcheroo.h>
6a9ee8af DA	40
38651674 DA	41	/* object hierarchy -
	42	this contains a helper + a radeon fb
	43	the helper contains a pointer to radeon framebuffer baseclass.
	44	*/
8be48d92	45	struct radeon_fbdev {
785b93ef	46	struct drm_fb_helper helper;
38651674 DA	47	struct radeon_framebuffer rfb;
	48	struct list_head fbdev_list;
	49	struct radeon_device *rdev;
771fe6b9 JG	50	};
771fe6b9 JG	51
771fe6b9 JG	52	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	53	.owner = THIS_MODULE,
c88f9f0c	54	.fb_check_var = drm_fb_helper_check_var,
785b93ef	55	.fb_set_par = drm_fb_helper_set_par,
771fe6b9 JG	56	.fb_fillrect = cfb_fillrect,
	57	.fb_copyarea = cfb_copyarea,
	58	.fb_imageblit = cfb_imageblit,
785b93ef DA	59	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	60	.fb_blank = drm_fb_helper_blank,
068143d3	61	.fb_setcmap = drm_fb_helper_setcmap,
771fe6b9 JG	62	};
771fe6b9 JG	63
771fe6b9	64
e024e110	65	static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	66	{
771fe6b9 JG	67	int aligned = width;
e024e110	68	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	69	int pitch_mask = 0;
	70
	71	switch (bpp / 8) {
	72	case 1:
	73	pitch_mask = align_large ? 255 : 127;
	74	break;
	75	case 2:
	76	pitch_mask = align_large ? 127 : 31;
	77	break;
	78	case 3:
	79	case 4:
	80	pitch_mask = align_large ? 63 : 15;
	81	break;
	82	}
	83
	84	aligned += pitch_mask;
	85	aligned &= ~pitch_mask;
	86	return aligned;
	87	}
	88
8be48d92	89	static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
771fe6b9	90	{
8be48d92 DA	91	struct radeon_bo *rbo = gobj->driver_private;
	92	int ret;
	93
	94	ret = radeon_bo_reserve(rbo, false);
	95	if (likely(ret == 0)) {
	96	radeon_bo_kunmap(rbo);
29d08b3e	97	radeon_bo_unpin(rbo);
8be48d92 DA	98	radeon_bo_unreserve(rbo);
	99	}
	100	drm_gem_object_unreference_unlocked(gobj);
	101	}
785b93ef	102
8be48d92 DA	103	static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
	104	struct drm_mode_fb_cmd *mode_cmd,
	105	struct drm_gem_object **gobj_p)
771fe6b9	106	{
8be48d92	107	struct radeon_device *rdev = rfbdev->rdev;
771fe6b9	108	struct drm_gem_object *gobj = NULL;
4c788679	109	struct radeon_bo *rbo = NULL;
e024e110	110	bool fb_tiled = false; /* useful for testing */
c88f9f0c	111	u32 tiling_flags = 0;
8be48d92 DA	112	int ret;
8be48d92 DA	113	int aligned_size, size;
771fe6b9	114
771fe6b9	115	/* need to align pitch with crtc limits */
8be48d92	116	mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);
771fe6b9	117
8be48d92	118	size = mode_cmd->pitch * mode_cmd->height;
771fe6b9	119	aligned_size = ALIGN(size, PAGE_SIZE);
771fe6b9	120	ret = radeon_gem_object_create(rdev, aligned_size, 0,
8be48d92	121	RADEON_GEM_DOMAIN_VRAM,
4dfe947e	122	false, true,
8be48d92	123	&gobj);
771fe6b9	124	if (ret) {
8be48d92 DA	125	printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
	126	aligned_size);
	127	return -ENOMEM;
771fe6b9	128	}
4c788679	129	rbo = gobj->driver_private;
771fe6b9	130
e024e110	131	if (fb_tiled)
c88f9f0c MD	132	tiling_flags = RADEON_TILING_MACRO;
	133
	134	#ifdef __BIG_ENDIAN
8be48d92	135	switch (mode_cmd->bpp) {
c88f9f0c MD	136	case 32:
	137	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	138	break;
	139	case 16:
	140	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	141	default:
	142	break;
	143	}
	144	#endif
	145
4c788679 JG	146	if (tiling_flags) {
4c788679 JG	147	ret = radeon_bo_set_tiling_flags(rbo,
8be48d92 DA	148	tiling_flags \| RADEON_TILING_SURFACE,
8be48d92 DA	149	mode_cmd->pitch);
4c788679 JG	150	if (ret)
	151	dev_err(rdev->dev, "FB failed to set tiling flags\n");
	152	}
8be48d92	153
38651674	154
4c788679 JG	155	ret = radeon_bo_reserve(rbo, false);
	156	if (unlikely(ret != 0))
	157	goto out_unref;
8be48d92	158	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
4c788679 JG	159	if (ret) {
	160	radeon_bo_unreserve(rbo);
	161	goto out_unref;
	162	}
	163	if (fb_tiled)
	164	radeon_bo_check_tiling(rbo, 0, 0);
8be48d92	165	ret = radeon_bo_kmap(rbo, NULL);
4c788679	166	radeon_bo_unreserve(rbo);
f92e93eb	167	if (ret) {
f92e93eb JG	168	goto out_unref;
f92e93eb JG	169	}
771fe6b9	170
8be48d92 DA	171	*gobj_p = gobj;
	172	return 0;
	173	out_unref:
	174	radeonfb_destroy_pinned_object(gobj);
	175	*gobj_p = NULL;
	176	return ret;
	177	}
	178
	179	static int radeonfb_create(struct radeon_fbdev *rfbdev,
	180	struct drm_fb_helper_surface_size *sizes)
	181	{
	182	struct radeon_device *rdev = rfbdev->rdev;
	183	struct fb_info *info;
	184	struct drm_framebuffer *fb = NULL;
	185	struct drm_mode_fb_cmd mode_cmd;
	186	struct drm_gem_object *gobj = NULL;
	187	struct radeon_bo *rbo = NULL;
	188	struct device *device = &rdev->pdev->dev;
	189	int ret;
	190	unsigned long tmp;
	191
	192	mode_cmd.width = sizes->surface_width;
	193	mode_cmd.height = sizes->surface_height;
	194
	195	/* avivo can't scanout real 24bpp */
	196	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
	197	sizes->surface_bpp = 32;
	198
	199	mode_cmd.bpp = sizes->surface_bpp;
	200	mode_cmd.depth = sizes->surface_depth;
771fe6b9	201
8be48d92 DA	202	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
8be48d92 DA	203	rbo = gobj->driver_private;
771fe6b9	204
8be48d92 DA	205	/* okay we have an object now allocate the framebuffer */
8be48d92 DA	206	info = framebuffer_alloc(0, device);
771fe6b9 JG	207	if (info == NULL) {
	208	ret = -ENOMEM;
	209	goto out_unref;
	210	}
785b93ef	211
8be48d92	212	info->par = rfbdev;
771fe6b9	213
8be48d92 DA	214	radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
8be48d92 DA	215
38651674 DA	216	fb = &rfbdev->rfb.base;
	217
	218	/* setup helper */
	219	rfbdev->helper.fb = fb;
	220	rfbdev->helper.fbdev = info;
38651674	221
8be48d92	222	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
bf8e828b	223
771fe6b9	224	strcpy(info->fix.id, "radeondrmfb");
785b93ef	225
068143d3	226	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
785b93ef	227
8fd4bd22	228	info->flags = FBINFO_DEFAULT \| FBINFO_CAN_FORCE_OUTPUT;
771fe6b9	229	info->fbops = &radeonfb_ops;
785b93ef	230
8be48d92	231	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
f92e93eb	232	info->fix.smem_start = rdev->mc.aper_base + tmp;
8be48d92 DA	233	info->fix.smem_len = radeon_bo_size(rbo);
	234	info->screen_base = rbo->kptr;
	235	info->screen_size = radeon_bo_size(rbo);
785b93ef	236
38651674	237	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
ed8f0d9e DA	238
ed8f0d9e DA	239	/* setup aperture base/size for vesafb takeover */
1471ca9a MS	240	info->apertures = alloc_apertures(1);
	241	if (!info->apertures) {
	242	ret = -ENOMEM;
	243	goto out_unref;
	244	}
	245	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
	246	info->apertures->ranges[0].size = rdev->mc.real_vram_size;
ed8f0d9e	247
696d4df1 MD	248	info->fix.mmio_start = 0;
696d4df1 MD	249	info->fix.mmio_len = 0;
771fe6b9 JG	250	info->pixmap.size = 64*1024;
	251	info->pixmap.buf_align = 8;
	252	info->pixmap.access_align = 32;
	253	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	254	info->pixmap.scan_align = 1;
4abe3520	255
771fe6b9 JG	256	if (info->screen_base == NULL) {
	257	ret = -ENOSPC;
	258	goto out_unref;
	259	}
4abe3520 DA	260
	261	ret = fb_alloc_cmap(&info->cmap, 256, 0);
	262	if (ret) {
	263	ret = -ENOMEM;
	264	goto out_unref;
	265	}
	266
771fe6b9 JG	267	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
771fe6b9 JG	268	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
8be48d92	269	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
771fe6b9 JG	270	DRM_INFO("fb depth is %d\n", fb->depth);
	271	DRM_INFO(" pitch is %d\n", fb->pitch);
	272
6a9ee8af	273	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
771fe6b9 JG	274	return 0;
	275
	276	out_unref:
4c788679	277	if (rbo) {
8be48d92	278
771fe6b9	279	}
f92e93eb	280	if (fb && ret) {
771fe6b9 JG	281	drm_gem_object_unreference(gobj);
	282	drm_framebuffer_cleanup(fb);
	283	kfree(fb);
	284	}
771fe6b9 JG	285	return ret;
	286	}
	287
8be48d92 DA	288	static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper,
8be48d92 DA	289	struct drm_fb_helper_surface_size *sizes)
38651674	290	{
8be48d92	291	struct radeon_fbdev rfbdev = (struct radeon_fbdev )helper;
38651674 DA	292	int new_fb = 0;
	293	int ret;
	294
8be48d92 DA	295	if (!helper->fb) {
8be48d92 DA	296	ret = radeonfb_create(rfbdev, sizes);
38651674 DA	297	if (ret)
38651674 DA	298	return ret;
38651674	299	new_fb = 1;
38651674	300	}
38651674 DA	301	return new_fb;
	302	}
	303
d50ba256 DA	304	static char *mode_option;
	305	int radeon_parse_options(char *options)
	306	{
	307	char *this_opt;
	308
	309	if (!options \|\| !*options)
	310	return 0;
	311
	312	while ((this_opt = strsep(&options, ",")) != NULL) {
	313	if (!*this_opt)
	314	continue;
	315	mode_option = this_opt;
	316	}
	317	return 0;
	318	}
	319
eb1f8e4f	320	void radeon_fb_output_poll_changed(struct radeon_device *rdev)
771fe6b9	321	{
eb1f8e4f	322	drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
771fe6b9	323	}
771fe6b9	324
8be48d92	325	static int radeon_fbdev_destroy(struct drm_device dev, struct radeon_fbdev rfbdev)
771fe6b9 JG	326	{
771fe6b9 JG	327	struct fb_info *info;
38651674	328	struct radeon_framebuffer *rfb = &rfbdev->rfb;
771fe6b9	329
8be48d92 DA	330	if (rfbdev->helper.fbdev) {
8be48d92 DA	331	info = rfbdev->helper.fbdev;
4abe3520	332
8be48d92	333	unregister_framebuffer(info);
4abe3520 DA	334	if (info->cmap.len)
4abe3520 DA	335	fb_dealloc_cmap(&info->cmap);
8be48d92	336	framebuffer_release(info);
771fe6b9	337	}
771fe6b9	338
8be48d92	339	if (rfb->obj) {
29d08b3e DA	340	radeonfb_destroy_pinned_object(rfb->obj);
29d08b3e DA	341	rfb->obj = NULL;
771fe6b9	342	}
4abe3520	343	drm_fb_helper_fini(&rfbdev->helper);
38651674	344	drm_framebuffer_cleanup(&rfb->base);
771fe6b9	345
771fe6b9 JG	346	return 0;
771fe6b9 JG	347	}
785b93ef	348
4abe3520 DA	349	static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	350	.gamma_set = radeon_crtc_fb_gamma_set,
	351	.gamma_get = radeon_crtc_fb_gamma_get,
	352	.fb_probe = radeon_fb_find_or_create_single,
4abe3520	353	};
38651674 DA	354
	355	int radeon_fbdev_init(struct radeon_device *rdev)
	356	{
8be48d92	357	struct radeon_fbdev *rfbdev;
4abe3520	358	int bpp_sel = 32;
5a79395b	359	int ret;
4abe3520 DA	360
	361	/* select 8 bpp console on RN50 or 16MB cards */
	362	if (ASIC_IS_RN50(rdev) \|\| rdev->mc.real_vram_size <= (3210241024))
	363	bpp_sel = 8;
8be48d92 DA	364
	365	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	366	if (!rfbdev)
	367	return -ENOMEM;
	368
	369	rfbdev->rdev = rdev;
	370	rdev->mode_info.rfbdev = rfbdev;
4abe3520	371	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
8be48d92	372
5a79395b CW	373	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
	374	rdev->num_crtc,
	375	RADEONFB_CONN_LIMIT);
	376	if (ret) {
	377	kfree(rfbdev);
	378	return ret;
	379	}
	380
0b4c0f3f	381	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
4abe3520	382	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
771fe6b9	383	return 0;
38651674 DA	384	}
	385
	386	void radeon_fbdev_fini(struct radeon_device *rdev)
	387	{
8be48d92 DA	388	if (!rdev->mode_info.rfbdev)
	389	return;
	390
38651674	391	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
8be48d92	392	kfree(rdev->mode_info.rfbdev);
38651674 DA	393	rdev->mode_info.rfbdev = NULL;
	394	}
	395
	396	void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
	397	{
	398	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
	399	}
	400
	401	int radeon_fbdev_total_size(struct radeon_device *rdev)
	402	{
	403	struct radeon_bo *robj;
	404	int size = 0;
	405
	406	robj = rdev->mode_info.rfbdev->rfb.obj->driver_private;
	407	size += radeon_bo_size(robj);
	408	return size;
	409	}
	410
	411	bool radeon_fbdev_robj_is_fb(struct radeon_device rdev, struct radeon_bo robj)
	412	{
	413	if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private)
	414	return true;
	415	return false;
771fe6b9	416	}