[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
#include <linux/module.h>
#include <linux/fb.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon.h"

#include "drm_fb_helper.h"

#include <linux/vga_switcheroo.h>

/* object hierarchy -
   this contains a helper + a radeon fb
   the helper contains a pointer to radeon framebuffer baseclass.
*/
struct radeon_fbdev {
	struct drm_fb_helper helper;
	struct radeon_framebuffer rfb;
	struct list_head fbdev_list;
	struct radeon_device *rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_setcolreg = drm_fb_helper_setcolreg,
	.fb_fillrect = cfb_fillrect,
	.fb_copyarea = cfb_copyarea,
	.fb_imageblit = cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
};


static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
};

static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct radeon_bo *rbo = gobj->driver_private;
	int ret;

	ret = radeon_bo_reserve(rbo, false);
	if (likely(ret == 0)) {
		radeon_bo_kunmap(rbo);
		radeon_bo_unreserve(rbo);
	}
	drm_gem_object_unreference_unlocked(gobj);
}

static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
					 struct drm_mode_fb_cmd *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;
	int ret;
	int aligned_size, size;

	/* need to align pitch with crtc limits */
	mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);

	size = mode_cmd->pitch * mode_cmd->height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = radeon_gem_object_create(rdev, aligned_size, 0,
				       RADEON_GEM_DOMAIN_VRAM,
				       false, ttm_bo_type_kernel,
				       &gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
		       aligned_size);
		return -ENOMEM;
	}
	rbo = gobj->driver_private;

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (mode_cmd->bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags) {
		ret = radeon_bo_set_tiling_flags(rbo,
						 tiling_flags | RADEON_TILING_SURFACE,
						 mode_cmd->pitch);
		if (ret)
			dev_err(rdev->dev, "FB failed to set tiling flags\n");
	}


	ret = radeon_bo_reserve(rbo, false);
	if (unlikely(ret != 0))
		goto out_unref;
	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
	if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;
	}
	if (fb_tiled)
		radeon_bo_check_tiling(rbo, 0, 0);
	ret = radeon_bo_kmap(rbo, NULL);
	radeon_bo_unreserve(rbo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	radeonfb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int radeonfb_create(struct radeon_fbdev *rfbdev,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	struct device *device = &rdev->pdev->dev;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	/* avivo can't scanout real 24bpp */
	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		sizes->surface_bpp = 32;

	mode_cmd.bpp = sizes->surface_bpp;
	mode_cmd.depth = sizes->surface_depth;

	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	rbo = gobj->driver_private;

	/* okay we have an object now allocate the framebuffer */
	info = framebuffer_alloc(0, device);
	if (info == NULL) {
		ret = -ENOMEM;
		goto out_unref;
	}

	info->par = rfbdev;

	radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;
	rfbdev->helper.fbdev = info;
	rfbdev->helper.funcs = &radeon_fb_helper_funcs;

	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);

	info->flags = FBINFO_DEFAULT;
	info->fbops = &radeonfb_ops;

	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = radeon_bo_size(rbo);
	info->screen_base = rbo->kptr;
	info->screen_size = radeon_bo_size(rbo);

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->aperture_base = rdev->ddev->mode_config.fb_base;
	info->aperture_size = rdev->mc.real_vram_size;

	info->fix.mmio_start = 0;
	info->fix.mmio_len = 0;
	info->pixmap.size = 64*1024;
	info->pixmap.buf_align = 8;
	info->pixmap.access_align = 32;
	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	info->pixmap.scan_align = 1;
	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_unref;
	}
	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitch);

	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	return 0;

out_unref:
	if (rbo) {

	}
	if (fb && ret) {
		drm_gem_object_unreference(gobj);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper,
					   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_fbdev *rfbdev = (struct radeon_fbdev *)helper;
	int new_fb = 0;
	int ret;

	if (!helper->fb) {
		ret = radeonfb_create(rfbdev, sizes);
		if (ret)
			return ret;
		new_fb = 1;
	}
	return new_fb;
}

static char *mode_option;
int radeon_parse_options(char *options)
{
	char *this_opt;

	if (!options || !*options)
		return 0;

	while ((this_opt = strsep(&options, ",")) != NULL) {
		if (!*this_opt)
			continue;
		mode_option = this_opt;
	}
	return 0;
}

static int radeonfb_probe(struct radeon_fbdev *rfbdev)
{
	struct radeon_device *rdev = rfbdev->rdev;
	int bpp_sel = 32;

	/* select 8 bpp console on RN50 or 16MB cards */
	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	return drm_fb_helper_single_fb_probe(&rfbdev->helper, bpp_sel);
}

void radeonfb_hotplug(struct drm_device *dev, bool polled)
{
	struct radeon_device *rdev = dev->dev_private;
	int max_width, max_height;

	max_width = rdev->mode_info.rfbdev->rfb.base.width;
	max_height = rdev->mode_info.rfbdev->rfb.base.height;
	drm_helper_fb_hotplug_event(&rdev->mode_info.rfbdev->helper, max_width, max_height, polled);

	radeonfb_probe(rdev->mode_info.rfbdev);
}

static void radeon_fb_poll_changed(struct drm_fb_helper *fb_helper)
{
	radeonfb_hotplug(fb_helper->dev, true);
}

static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev)
{
	struct fb_info *info;
	struct radeon_framebuffer *rfb = &rfbdev->rfb;
	struct radeon_bo *rbo;
	int r;

	if (rfbdev->helper.fbdev) {
		info = rfbdev->helper.fbdev;
		unregister_framebuffer(info);
		framebuffer_release(info);
	}

	if (rfb->obj) {
		rbo = rfb->obj->driver_private;
		r = radeon_bo_reserve(rbo, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(rbo);
			radeon_bo_unpin(rbo);
			radeon_bo_unreserve(rbo);
		}
		drm_gem_object_unreference_unlocked(rfb->obj);
	}
	drm_fb_helper_free(&rfbdev->helper);
	drm_framebuffer_cleanup(&rfb->base);

	return 0;
}
MODULE_LICENSE("GPL");

int radeon_fbdev_init(struct radeon_device *rdev)
{
	struct radeon_fbdev *rfbdev;

	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->rdev = rdev;
	rdev->mode_info.rfbdev = rfbdev;

	drm_fb_helper_init_crtc_count(rdev->ddev, &rfbdev->helper,
				      rdev->num_crtc,
				      RADEONFB_CONN_LIMIT);
	rfbdev->helper.fb_probe = radeon_fb_find_or_create_single;

	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);

	rfbdev->helper.fb_poll_changed = radeon_fb_poll_changed;
	drm_fb_helper_poll_init(&rfbdev->helper);

	drm_fb_helper_initial_config(&rfbdev->helper);
	radeonfb_probe(rfbdev);

	return 0;

}

void radeon_fbdev_fini(struct radeon_device *rdev)
{
	if (!rdev->mode_info.rfbdev)
		return;

	drm_fb_helper_poll_fini(&rdev->mode_info.rfbdev->helper);
	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
	kfree(rdev->mode_info.rfbdev);
	rdev->mode_info.rfbdev = NULL;
}

void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
{
	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
}

int radeon_fbdev_total_size(struct radeon_device *rdev)
{
	struct radeon_bo *robj;
	int size = 0;

	robj = rdev->mode_info.rfbdev->rfb.obj->driver_private;
	size += radeon_bo_size(robj);
	return size;
}

bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
{
	if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private)
		return true;
	return false;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
771fe6b9	26	#include <linux/module.h>
771fe6b9	27	#include <linux/fb.h>
771fe6b9 JG	28
	29	#include "drmP.h"
	30	#include "drm.h"
	31	#include "drm_crtc.h"
	32	#include "drm_crtc_helper.h"
	33	#include "radeon_drm.h"
	34	#include "radeon.h"
	35
785b93ef DA	36	#include "drm_fb_helper.h"
785b93ef DA	37
6a9ee8af DA	38	#include <linux/vga_switcheroo.h>
6a9ee8af DA	39
38651674 DA	40	/* object hierarchy -
	41	this contains a helper + a radeon fb
	42	the helper contains a pointer to radeon framebuffer baseclass.
	43	*/
8be48d92	44	struct radeon_fbdev {
785b93ef	45	struct drm_fb_helper helper;
38651674 DA	46	struct radeon_framebuffer rfb;
	47	struct list_head fbdev_list;
	48	struct radeon_device *rdev;
771fe6b9 JG	49	};
771fe6b9 JG	50
771fe6b9 JG	51	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	52	.owner = THIS_MODULE,
c88f9f0c	53	.fb_check_var = drm_fb_helper_check_var,
785b93ef DA	54	.fb_set_par = drm_fb_helper_set_par,
785b93ef DA	55	.fb_setcolreg = drm_fb_helper_setcolreg,
771fe6b9 JG	56	.fb_fillrect = cfb_fillrect,
	57	.fb_copyarea = cfb_copyarea,
	58	.fb_imageblit = cfb_imageblit,
785b93ef DA	59	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	60	.fb_blank = drm_fb_helper_blank,
068143d3	61	.fb_setcmap = drm_fb_helper_setcmap,
771fe6b9 JG	62	};
771fe6b9 JG	63
771fe6b9	64
e024e110	65	static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	66	{
771fe6b9 JG	67	int aligned = width;
e024e110	68	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	69	int pitch_mask = 0;
	70
	71	switch (bpp / 8) {
	72	case 1:
	73	pitch_mask = align_large ? 255 : 127;
	74	break;
	75	case 2:
	76	pitch_mask = align_large ? 127 : 31;
	77	break;
	78	case 3:
	79	case 4:
	80	pitch_mask = align_large ? 63 : 15;
	81	break;
	82	}
	83
	84	aligned += pitch_mask;
	85	aligned &= ~pitch_mask;
	86	return aligned;
	87	}
	88
785b93ef DA	89	static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
785b93ef DA	90	.gamma_set = radeon_crtc_fb_gamma_set,
b8c00ac5	91	.gamma_get = radeon_crtc_fb_gamma_get,
785b93ef DA	92	};
785b93ef DA	93
8be48d92	94	static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
771fe6b9	95	{
8be48d92 DA	96	struct radeon_bo *rbo = gobj->driver_private;
	97	int ret;
	98
	99	ret = radeon_bo_reserve(rbo, false);
	100	if (likely(ret == 0)) {
	101	radeon_bo_kunmap(rbo);
	102	radeon_bo_unreserve(rbo);
	103	}
	104	drm_gem_object_unreference_unlocked(gobj);
	105	}
	106
	107	static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
	108	struct drm_mode_fb_cmd *mode_cmd,
	109	struct drm_gem_object **gobj_p)
	110	{
	111	struct radeon_device *rdev = rfbdev->rdev;
771fe6b9	112	struct drm_gem_object *gobj = NULL;
4c788679	113	struct radeon_bo *rbo = NULL;
e024e110	114	bool fb_tiled = false; /* useful for testing */
c88f9f0c	115	u32 tiling_flags = 0;
8be48d92 DA	116	int ret;
8be48d92 DA	117	int aligned_size, size;
771fe6b9	118
771fe6b9	119	/* need to align pitch with crtc limits */
8be48d92	120	mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);
771fe6b9	121
8be48d92	122	size = mode_cmd->pitch * mode_cmd->height;
771fe6b9	123	aligned_size = ALIGN(size, PAGE_SIZE);
771fe6b9	124	ret = radeon_gem_object_create(rdev, aligned_size, 0,
8be48d92 DA	125	RADEON_GEM_DOMAIN_VRAM,
	126	false, ttm_bo_type_kernel,
	127	&gobj);
771fe6b9	128	if (ret) {
8be48d92 DA	129	printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
	130	aligned_size);
	131	return -ENOMEM;
771fe6b9	132	}
4c788679	133	rbo = gobj->driver_private;
771fe6b9	134
e024e110	135	if (fb_tiled)
c88f9f0c MD	136	tiling_flags = RADEON_TILING_MACRO;
	137
	138	#ifdef __BIG_ENDIAN
8be48d92	139	switch (mode_cmd->bpp) {
c88f9f0c MD	140	case 32:
	141	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	142	break;
	143	case 16:
	144	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	145	default:
	146	break;
	147	}
	148	#endif
	149
4c788679 JG	150	if (tiling_flags) {
4c788679 JG	151	ret = radeon_bo_set_tiling_flags(rbo,
8be48d92 DA	152	tiling_flags \| RADEON_TILING_SURFACE,
8be48d92 DA	153	mode_cmd->pitch);
4c788679 JG	154	if (ret)
	155	dev_err(rdev->dev, "FB failed to set tiling flags\n");
	156	}
8be48d92	157
38651674	158
4c788679 JG	159	ret = radeon_bo_reserve(rbo, false);
	160	if (unlikely(ret != 0))
	161	goto out_unref;
8be48d92	162	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
4c788679 JG	163	if (ret) {
	164	radeon_bo_unreserve(rbo);
	165	goto out_unref;
	166	}
	167	if (fb_tiled)
	168	radeon_bo_check_tiling(rbo, 0, 0);
8be48d92	169	ret = radeon_bo_kmap(rbo, NULL);
4c788679	170	radeon_bo_unreserve(rbo);
f92e93eb	171	if (ret) {
f92e93eb JG	172	goto out_unref;
f92e93eb JG	173	}
771fe6b9	174
8be48d92 DA	175	*gobj_p = gobj;
	176	return 0;
	177	out_unref:
	178	radeonfb_destroy_pinned_object(gobj);
	179	*gobj_p = NULL;
	180	return ret;
	181	}
	182
	183	static int radeonfb_create(struct radeon_fbdev *rfbdev,
	184	struct drm_fb_helper_surface_size *sizes)
	185	{
	186	struct radeon_device *rdev = rfbdev->rdev;
	187	struct fb_info *info;
	188	struct drm_framebuffer *fb = NULL;
	189	struct drm_mode_fb_cmd mode_cmd;
	190	struct drm_gem_object *gobj = NULL;
	191	struct radeon_bo *rbo = NULL;
	192	struct device *device = &rdev->pdev->dev;
	193	int ret;
	194	unsigned long tmp;
	195
	196	mode_cmd.width = sizes->surface_width;
	197	mode_cmd.height = sizes->surface_height;
	198
	199	/* avivo can't scanout real 24bpp */
	200	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
	201	sizes->surface_bpp = 32;
	202
	203	mode_cmd.bpp = sizes->surface_bpp;
	204	mode_cmd.depth = sizes->surface_depth;
	205
	206	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	207	rbo = gobj->driver_private;
	208
	209	/* okay we have an object now allocate the framebuffer */
	210	info = framebuffer_alloc(0, device);
771fe6b9 JG	211	if (info == NULL) {
	212	ret = -ENOMEM;
	213	goto out_unref;
	214	}
785b93ef	215
8be48d92 DA	216	info->par = rfbdev;
	217
	218	radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
	219
38651674 DA	220	fb = &rfbdev->rfb.base;
	221
	222	/* setup helper */
	223	rfbdev->helper.fb = fb;
	224	rfbdev->helper.fbdev = info;
785b93ef	225	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
38651674	226
8be48d92	227	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
bf8e828b	228
771fe6b9	229	strcpy(info->fix.id, "radeondrmfb");
785b93ef	230
068143d3	231	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
785b93ef	232
771fe6b9 JG	233	info->flags = FBINFO_DEFAULT;
771fe6b9 JG	234	info->fbops = &radeonfb_ops;
785b93ef	235
8be48d92	236	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
f92e93eb	237	info->fix.smem_start = rdev->mc.aper_base + tmp;
8be48d92 DA	238	info->fix.smem_len = radeon_bo_size(rbo);
	239	info->screen_base = rbo->kptr;
	240	info->screen_size = radeon_bo_size(rbo);
785b93ef	241
38651674	242	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
ed8f0d9e DA	243
	244	/* setup aperture base/size for vesafb takeover */
	245	info->aperture_base = rdev->ddev->mode_config.fb_base;
	246	info->aperture_size = rdev->mc.real_vram_size;
	247
696d4df1 MD	248	info->fix.mmio_start = 0;
696d4df1 MD	249	info->fix.mmio_len = 0;
771fe6b9 JG	250	info->pixmap.size = 64*1024;
	251	info->pixmap.buf_align = 8;
	252	info->pixmap.access_align = 32;
	253	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	254	info->pixmap.scan_align = 1;
	255	if (info->screen_base == NULL) {
	256	ret = -ENOSPC;
	257	goto out_unref;
	258	}
	259	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
	260	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
8be48d92	261	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
771fe6b9 JG	262	DRM_INFO("fb depth is %d\n", fb->depth);
	263	DRM_INFO(" pitch is %d\n", fb->pitch);
	264
6a9ee8af	265	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
771fe6b9 JG	266	return 0;
	267
	268	out_unref:
4c788679	269	if (rbo) {
8be48d92	270
771fe6b9	271	}
f92e93eb	272	if (fb && ret) {
771fe6b9 JG	273	drm_gem_object_unreference(gobj);
	274	drm_framebuffer_cleanup(fb);
	275	kfree(fb);
	276	}
771fe6b9 JG	277	return ret;
	278	}
	279
8be48d92 DA	280	static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper,
8be48d92 DA	281	struct drm_fb_helper_surface_size *sizes)
38651674	282	{
8be48d92	283	struct radeon_fbdev rfbdev = (struct radeon_fbdev )helper;
38651674 DA	284	int new_fb = 0;
	285	int ret;
	286
8be48d92 DA	287	if (!helper->fb) {
8be48d92 DA	288	ret = radeonfb_create(rfbdev, sizes);
38651674 DA	289	if (ret)
38651674 DA	290	return ret;
38651674	291	new_fb = 1;
38651674	292	}
38651674 DA	293	return new_fb;
	294	}
	295
d50ba256 DA	296	static char *mode_option;
	297	int radeon_parse_options(char *options)
	298	{
	299	char *this_opt;
	300
	301	if (!options \|\| !*options)
	302	return 0;
	303
	304	while ((this_opt = strsep(&options, ",")) != NULL) {
	305	if (!*this_opt)
	306	continue;
	307	mode_option = this_opt;
	308	}
	309	return 0;
	310	}
	311
8be48d92	312	static int radeonfb_probe(struct radeon_fbdev *rfbdev)
771fe6b9	313	{
8be48d92	314	struct radeon_device *rdev = rfbdev->rdev;
47381156 DA	315	int bpp_sel = 32;
	316
	317	/* select 8 bpp console on RN50 or 16MB cards */
	318	if (ASIC_IS_RN50(rdev) \|\| rdev->mc.real_vram_size <= (3210241024))
	319	bpp_sel = 8;
	320
8be48d92	321	return drm_fb_helper_single_fb_probe(&rfbdev->helper, bpp_sel);
38651674 DA	322	}
38651674 DA	323
5c4426a7	324	void radeonfb_hotplug(struct drm_device *dev, bool polled)
38651674	325	{
8be48d92 DA	326	struct radeon_device *rdev = dev->dev_private;
	327	int max_width, max_height;
	328
	329	max_width = rdev->mode_info.rfbdev->rfb.base.width;
	330	max_height = rdev->mode_info.rfbdev->rfb.base.height;
5c4426a7	331	drm_helper_fb_hotplug_event(&rdev->mode_info.rfbdev->helper, max_width, max_height, polled);
38651674	332
8be48d92	333	radeonfb_probe(rdev->mode_info.rfbdev);
771fe6b9	334	}
771fe6b9	335
5c4426a7 DA	336	static void radeon_fb_poll_changed(struct drm_fb_helper *fb_helper)
	337	{
	338	radeonfb_hotplug(fb_helper->dev, true);
	339	}
	340
8be48d92	341	static int radeon_fbdev_destroy(struct drm_device dev, struct radeon_fbdev rfbdev)
771fe6b9 JG	342	{
771fe6b9 JG	343	struct fb_info *info;
38651674	344	struct radeon_framebuffer *rfb = &rfbdev->rfb;
4c788679 JG	345	struct radeon_bo *rbo;
4c788679 JG	346	int r;
771fe6b9	347
8be48d92 DA	348	if (rfbdev->helper.fbdev) {
	349	info = rfbdev->helper.fbdev;
	350	unregister_framebuffer(info);
	351	framebuffer_release(info);
771fe6b9 JG	352	}
771fe6b9 JG	353
8be48d92 DA	354	if (rfb->obj) {
	355	rbo = rfb->obj->driver_private;
	356	r = radeon_bo_reserve(rbo, false);
	357	if (likely(r == 0)) {
	358	radeon_bo_kunmap(rbo);
	359	radeon_bo_unpin(rbo);
	360	radeon_bo_unreserve(rbo);
	361	}
	362	drm_gem_object_unreference_unlocked(rfb->obj);
	363	}
38651674 DA	364	drm_fb_helper_free(&rfbdev->helper);
38651674 DA	365	drm_framebuffer_cleanup(&rfb->base);
785b93ef	366
771fe6b9 JG	367	return 0;
771fe6b9 JG	368	}
771fe6b9	369	MODULE_LICENSE("GPL");
38651674 DA	370
	371	int radeon_fbdev_init(struct radeon_device *rdev)
	372	{
8be48d92 DA	373	struct radeon_fbdev *rfbdev;
	374
	375	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	376	if (!rfbdev)
	377	return -ENOMEM;
	378
	379	rfbdev->rdev = rdev;
	380	rdev->mode_info.rfbdev = rfbdev;
	381
	382	drm_fb_helper_init_crtc_count(rdev->ddev, &rfbdev->helper,
	383	rdev->num_crtc,
	384	RADEONFB_CONN_LIMIT);
	385	rfbdev->helper.fb_probe = radeon_fb_find_or_create_single;
0b4c0f3f DA	386
	387	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	388
5c4426a7 DA	389	rfbdev->helper.fb_poll_changed = radeon_fb_poll_changed;
	390	drm_fb_helper_poll_init(&rfbdev->helper);
	391
8be48d92 DA	392	drm_fb_helper_initial_config(&rfbdev->helper);
8be48d92 DA	393	radeonfb_probe(rfbdev);
5c4426a7	394
38651674	395	return 0;
8be48d92	396
38651674 DA	397	}
	398
	399	void radeon_fbdev_fini(struct radeon_device *rdev)
	400	{
8be48d92 DA	401	if (!rdev->mode_info.rfbdev)
	402	return;
	403
5c4426a7	404	drm_fb_helper_poll_fini(&rdev->mode_info.rfbdev->helper);
38651674	405	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
8be48d92	406	kfree(rdev->mode_info.rfbdev);
38651674 DA	407	rdev->mode_info.rfbdev = NULL;
	408	}
	409
	410	void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
	411	{
	412	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
	413	}
	414
	415	int radeon_fbdev_total_size(struct radeon_device *rdev)
	416	{
	417	struct radeon_bo *robj;
	418	int size = 0;
	419
	420	robj = rdev->mode_info.rfbdev->rfb.obj->driver_private;
	421	size += radeon_bo_size(robj);
	422	return size;
	423	}
	424
	425	bool radeon_fbdev_robj_is_fb(struct radeon_device rdev, struct radeon_bo robj)
	426	{
	427	if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private)
	428	return true;
	429	return false;
	430	}
	431