[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
    /*
     *  Modularization
     */

#include <linux/module.h>
#include <linux/fb.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon.h"

#include "drm_fb_helper.h"

#include <linux/vga_switcheroo.h>

/* object hierarchy -
   this contains a helper + a radeon fb
   the helper contains a pointer to radeon framebuffer baseclass.
*/
struct radeon_kernel_fbdev {
	struct drm_fb_helper helper;
	struct radeon_framebuffer rfb;
	struct list_head fbdev_list;
	struct radeon_device *rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_setcolreg = drm_fb_helper_setcolreg,
	.fb_fillrect = cfb_fillrect,
	.fb_copyarea = cfb_copyarea,
	.fb_imageblit = cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
};


static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
};

static int radeonfb_create(struct drm_device *dev,
			   struct drm_fb_helper_surface_size *sizes,
			   struct radeon_kernel_fbdev **rfbdev_p)
{
	struct radeon_device *rdev = dev->dev_private;
	struct fb_info *info;
	struct radeon_kernel_fbdev *rfbdev;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	struct device *device = &rdev->pdev->dev;
	int size, aligned_size, ret;
	u64 fb_gpuaddr;
	void *fbptr = NULL;
	unsigned long tmp;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	/* avivo can't scanout real 24bpp */
	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		sizes->surface_bpp = 32;

	mode_cmd.bpp = sizes->surface_bpp;
	/* need to align pitch with crtc limits */
	mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
	mode_cmd.depth = sizes->surface_depth;

	size = mode_cmd.pitch * mode_cmd.height;
	aligned_size = ALIGN(size, PAGE_SIZE);

	ret = radeon_gem_object_create(rdev, aligned_size, 0,
			RADEON_GEM_DOMAIN_VRAM,
			false, ttm_bo_type_kernel,
			&gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
		       sizes->surface_width, sizes->surface_height);
		ret = -ENOMEM;
		goto out;
	}
	rbo = gobj->driver_private;

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (mode_cmd.bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags) {
		ret = radeon_bo_set_tiling_flags(rbo,
					tiling_flags | RADEON_TILING_SURFACE,
					mode_cmd.pitch);
		if (ret)
			dev_err(rdev->dev, "FB failed to set tiling flags\n");
	}
	mutex_lock(&rdev->ddev->struct_mutex);

	ret = radeon_bo_reserve(rbo, false);
	if (unlikely(ret != 0))
		goto out_unref;
	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
	if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;
	}
	if (fb_tiled)
		radeon_bo_check_tiling(rbo, 0, 0);
	ret = radeon_bo_kmap(rbo, &fbptr);
	radeon_bo_unreserve(rbo);
	if (ret) {
		goto out_unref;
	}

	info = framebuffer_alloc(sizeof(struct radeon_kernel_fbdev), device);
	if (info == NULL) {
		ret = -ENOMEM;
		goto out_unref;
	}

	rfbdev = info->par;
	rfbdev->rdev = rdev;
	radeon_framebuffer_init(dev, &rfbdev->rfb, &mode_cmd, gobj);
	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;
	rfbdev->helper.fbdev = info;
	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
	rfbdev->helper.dev = dev;

	*rfbdev_p = rfbdev;

	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, rdev->num_crtc,
					    RADEONFB_CONN_LIMIT);
	if (ret)
		goto out_unref;

	memset_io(fbptr, 0x0, aligned_size);

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);

	info->flags = FBINFO_DEFAULT;
	info->fbops = &radeonfb_ops;

	tmp = fb_gpuaddr - rdev->mc.vram_start;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = size;
	info->screen_base = fbptr;
	info->screen_size = size;

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->aperture_base = rdev->ddev->mode_config.fb_base;
	info->aperture_size = rdev->mc.real_vram_size;

	info->fix.mmio_start = 0;
	info->fix.mmio_len = 0;
	info->pixmap.size = 64*1024;
	info->pixmap.buf_align = 8;
	info->pixmap.access_align = 32;
	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	info->pixmap.scan_align = 1;
	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_unref;
	}
	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)size);
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitch);


	mutex_unlock(&rdev->ddev->struct_mutex);
	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	return 0;

out_unref:
	if (rbo) {
		ret = radeon_bo_reserve(rbo, false);
		if (likely(ret == 0)) {
			radeon_bo_kunmap(rbo);
			radeon_bo_unreserve(rbo);
		}
	}
	if (fb && ret) {
		drm_gem_object_unreference(gobj);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	drm_gem_object_unreference(gobj);
	mutex_unlock(&rdev->ddev->struct_mutex);
out:
	return ret;
}

static int radeon_fb_find_or_create_single(struct drm_device *dev,
					   struct drm_fb_helper_surface_size *sizes,
					   struct drm_fb_helper **fb_ptr)
{
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_kernel_fbdev *rfbdev = NULL;
	int new_fb = 0;
	int ret;

	if (!rdev->mode_info.rfbdev) {
		ret = radeonfb_create(dev, sizes,
				      &rfbdev);
		if (ret)
			return ret;
		rdev->mode_info.rfbdev = rfbdev;
		new_fb = 1;
	} else {
		rfbdev = rdev->mode_info.rfbdev;
		if (rfbdev->rfb.base.width < sizes->surface_width ||
		    rfbdev->rfb.base.height < sizes->surface_height) {
			DRM_ERROR("Framebuffer not large enough to scale console onto.\n");
			return -EINVAL;
		}
	}

	*fb_ptr = &rfbdev->helper;
	return new_fb;
}

static char *mode_option;
int radeon_parse_options(char *options)
{
	char *this_opt;

	if (!options || !*options)
		return 0;

	while ((this_opt = strsep(&options, ",")) != NULL) {
		if (!*this_opt)
			continue;
		mode_option = this_opt;
	}
	return 0;
}

static int radeonfb_probe(struct drm_device *dev)
{
	struct radeon_device *rdev = dev->dev_private;
	int bpp_sel = 32;

	/* select 8 bpp console on RN50 or 16MB cards */
	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	return drm_fb_helper_single_fb_probe(dev, bpp_sel, &radeon_fb_find_or_create_single);
}

void radeonfb_hotplug(struct drm_device *dev)
{
	drm_helper_fb_hotplug_event(dev);

	radeonfb_probe(dev);
}

static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_kernel_fbdev *rfbdev)
{
	struct fb_info *info;
	struct radeon_framebuffer *rfb = &rfbdev->rfb;
	struct radeon_bo *rbo;
	int r;

	rbo = rfb->obj->driver_private;
	info = rfbdev->helper.fbdev;
	unregister_framebuffer(info);
	r = radeon_bo_reserve(rbo, false);
	if (likely(r == 0)) {
		radeon_bo_kunmap(rbo);
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
	}

	drm_fb_helper_free(&rfbdev->helper);
	drm_framebuffer_cleanup(&rfb->base);
	if (rfb->obj)
		drm_gem_object_unreference_unlocked(rfb->obj);

	framebuffer_release(info);

	return 0;
}
MODULE_LICENSE("GPL");

int radeon_fbdev_init(struct radeon_device *rdev)
{
	drm_helper_initial_config(rdev->ddev);
	radeonfb_probe(rdev->ddev);
	return 0;
}

void radeon_fbdev_fini(struct radeon_device *rdev)
{
	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
	rdev->mode_info.rfbdev = NULL;
}

void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
{
	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
}

int radeon_fbdev_total_size(struct radeon_device *rdev)
{
	struct radeon_bo *robj;
	int size = 0;

	robj = rdev->mode_info.rfbdev->rfb.obj->driver_private;
	size += radeon_bo_size(robj);
	return size;
}

bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
{
	if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private)
		return true;
	return false;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
	26	/*
	27	* Modularization
	28	*/
	29
	30	#include <linux/module.h>
771fe6b9	31	#include <linux/fb.h>
771fe6b9 JG	32
	33	#include "drmP.h"
	34	#include "drm.h"
	35	#include "drm_crtc.h"
	36	#include "drm_crtc_helper.h"
	37	#include "radeon_drm.h"
	38	#include "radeon.h"
	39
785b93ef DA	40	#include "drm_fb_helper.h"
785b93ef DA	41
6a9ee8af DA	42	#include <linux/vga_switcheroo.h>
6a9ee8af DA	43
38651674 DA	44	/* object hierarchy -
	45	this contains a helper + a radeon fb
	46	the helper contains a pointer to radeon framebuffer baseclass.
	47	*/
	48	struct radeon_kernel_fbdev {
785b93ef	49	struct drm_fb_helper helper;
38651674 DA	50	struct radeon_framebuffer rfb;
	51	struct list_head fbdev_list;
	52	struct radeon_device *rdev;
771fe6b9 JG	53	};
771fe6b9 JG	54
771fe6b9 JG	55	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	56	.owner = THIS_MODULE,
c88f9f0c	57	.fb_check_var = drm_fb_helper_check_var,
785b93ef DA	58	.fb_set_par = drm_fb_helper_set_par,
785b93ef DA	59	.fb_setcolreg = drm_fb_helper_setcolreg,
771fe6b9 JG	60	.fb_fillrect = cfb_fillrect,
	61	.fb_copyarea = cfb_copyarea,
	62	.fb_imageblit = cfb_imageblit,
785b93ef DA	63	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	64	.fb_blank = drm_fb_helper_blank,
068143d3	65	.fb_setcmap = drm_fb_helper_setcmap,
771fe6b9 JG	66	};
771fe6b9 JG	67
771fe6b9	68
e024e110	69	static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	70	{
771fe6b9 JG	71	int aligned = width;
e024e110	72	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	73	int pitch_mask = 0;
	74
	75	switch (bpp / 8) {
	76	case 1:
	77	pitch_mask = align_large ? 255 : 127;
	78	break;
	79	case 2:
	80	pitch_mask = align_large ? 127 : 31;
	81	break;
	82	case 3:
	83	case 4:
	84	pitch_mask = align_large ? 63 : 15;
	85	break;
	86	}
	87
	88	aligned += pitch_mask;
	89	aligned &= ~pitch_mask;
	90	return aligned;
	91	}
	92
785b93ef DA	93	static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
785b93ef DA	94	.gamma_set = radeon_crtc_fb_gamma_set,
b8c00ac5	95	.gamma_get = radeon_crtc_fb_gamma_get,
785b93ef DA	96	};
785b93ef DA	97
38651674 DA	98	static int radeonfb_create(struct drm_device *dev,
	99	struct drm_fb_helper_surface_size *sizes,
	100	struct radeon_kernel_fbdev **rfbdev_p)
771fe6b9	101	{
785b93ef	102	struct radeon_device *rdev = dev->dev_private;
771fe6b9	103	struct fb_info *info;
38651674	104	struct radeon_kernel_fbdev *rfbdev;
f92e93eb	105	struct drm_framebuffer *fb = NULL;
771fe6b9 JG	106	struct drm_mode_fb_cmd mode_cmd;
771fe6b9 JG	107	struct drm_gem_object *gobj = NULL;
4c788679	108	struct radeon_bo *rbo = NULL;
771fe6b9 JG	109	struct device *device = &rdev->pdev->dev;
771fe6b9 JG	110	int size, aligned_size, ret;
f92e93eb	111	u64 fb_gpuaddr;
771fe6b9	112	void *fbptr = NULL;
f92e93eb	113	unsigned long tmp;
e024e110	114	bool fb_tiled = false; /* useful for testing */
c88f9f0c	115	u32 tiling_flags = 0;
771fe6b9	116
38651674 DA	117	mode_cmd.width = sizes->surface_width;
38651674 DA	118	mode_cmd.height = sizes->surface_height;
b8c00ac5 DA	119
b8c00ac5 DA	120	/* avivo can't scanout real 24bpp */
38651674 DA	121	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
38651674 DA	122	sizes->surface_bpp = 32;
b8c00ac5	123
38651674	124	mode_cmd.bpp = sizes->surface_bpp;
771fe6b9	125	/* need to align pitch with crtc limits */
e024e110	126	mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
38651674	127	mode_cmd.depth = sizes->surface_depth;
771fe6b9 JG	128
	129	size = mode_cmd.pitch * mode_cmd.height;
	130	aligned_size = ALIGN(size, PAGE_SIZE);
	131
	132	ret = radeon_gem_object_create(rdev, aligned_size, 0,
f92e93eb JG	133	RADEON_GEM_DOMAIN_VRAM,
f92e93eb JG	134	false, ttm_bo_type_kernel,
4c788679	135	&gobj);
771fe6b9	136	if (ret) {
f92e93eb	137	printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
38651674	138	sizes->surface_width, sizes->surface_height);
771fe6b9 JG	139	ret = -ENOMEM;
	140	goto out;
	141	}
4c788679	142	rbo = gobj->driver_private;
771fe6b9	143
e024e110	144	if (fb_tiled)
c88f9f0c MD	145	tiling_flags = RADEON_TILING_MACRO;
	146
	147	#ifdef __BIG_ENDIAN
	148	switch (mode_cmd.bpp) {
	149	case 32:
	150	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	151	break;
	152	case 16:
	153	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	154	default:
	155	break;
	156	}
	157	#endif
	158
4c788679 JG	159	if (tiling_flags) {
	160	ret = radeon_bo_set_tiling_flags(rbo,
	161	tiling_flags \| RADEON_TILING_SURFACE,
	162	mode_cmd.pitch);
	163	if (ret)
	164	dev_err(rdev->dev, "FB failed to set tiling flags\n");
	165	}
771fe6b9	166	mutex_lock(&rdev->ddev->struct_mutex);
38651674	167
4c788679 JG	168	ret = radeon_bo_reserve(rbo, false);
	169	if (unlikely(ret != 0))
	170	goto out_unref;
	171	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
	172	if (ret) {
	173	radeon_bo_unreserve(rbo);
	174	goto out_unref;
	175	}
	176	if (fb_tiled)
	177	radeon_bo_check_tiling(rbo, 0, 0);
	178	ret = radeon_bo_kmap(rbo, &fbptr);
	179	radeon_bo_unreserve(rbo);
f92e93eb	180	if (ret) {
f92e93eb JG	181	goto out_unref;
f92e93eb JG	182	}
771fe6b9	183
38651674	184	info = framebuffer_alloc(sizeof(struct radeon_kernel_fbdev), device);
771fe6b9 JG	185	if (info == NULL) {
	186	ret = -ENOMEM;
	187	goto out_unref;
	188	}
785b93ef	189
771fe6b9	190	rfbdev = info->par;
38651674 DA	191	rfbdev->rdev = rdev;
	192	radeon_framebuffer_init(dev, &rfbdev->rfb, &mode_cmd, gobj);
	193	fb = &rfbdev->rfb.base;
	194
	195	/* setup helper */
	196	rfbdev->helper.fb = fb;
	197	rfbdev->helper.fbdev = info;
785b93ef DA	198	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
785b93ef DA	199	rfbdev->helper.dev = dev;
38651674 DA	200
	201	*rfbdev_p = rfbdev;
	202
18917b60	203	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, rdev->num_crtc,
785b93ef DA	204	RADEONFB_CONN_LIMIT);
	205	if (ret)
	206	goto out_unref;
771fe6b9	207
6719fc66	208	memset_io(fbptr, 0x0, aligned_size);
bf8e828b	209
771fe6b9	210	strcpy(info->fix.id, "radeondrmfb");
785b93ef	211
068143d3	212	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
785b93ef	213
771fe6b9 JG	214	info->flags = FBINFO_DEFAULT;
771fe6b9 JG	215	info->fbops = &radeonfb_ops;
785b93ef	216
d594e46a	217	tmp = fb_gpuaddr - rdev->mc.vram_start;
f92e93eb	218	info->fix.smem_start = rdev->mc.aper_base + tmp;
771fe6b9 JG	219	info->fix.smem_len = size;
	220	info->screen_base = fbptr;
	221	info->screen_size = size;
785b93ef	222
38651674	223	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
ed8f0d9e DA	224
	225	/* setup aperture base/size for vesafb takeover */
	226	info->aperture_base = rdev->ddev->mode_config.fb_base;
	227	info->aperture_size = rdev->mc.real_vram_size;
	228
696d4df1 MD	229	info->fix.mmio_start = 0;
696d4df1 MD	230	info->fix.mmio_len = 0;
771fe6b9 JG	231	info->pixmap.size = 64*1024;
	232	info->pixmap.buf_align = 8;
	233	info->pixmap.access_align = 32;
	234	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	235	info->pixmap.scan_align = 1;
	236	if (info->screen_base == NULL) {
	237	ret = -ENOSPC;
	238	goto out_unref;
	239	}
	240	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
	241	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
	242	DRM_INFO("size %lu\n", (unsigned long)size);
	243	DRM_INFO("fb depth is %d\n", fb->depth);
	244	DRM_INFO(" pitch is %d\n", fb->pitch);
	245
771fe6b9 JG	246
771fe6b9 JG	247	mutex_unlock(&rdev->ddev->struct_mutex);
6a9ee8af	248	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
771fe6b9 JG	249	return 0;
	250
	251	out_unref:
4c788679 JG	252	if (rbo) {
	253	ret = radeon_bo_reserve(rbo, false);
	254	if (likely(ret == 0)) {
	255	radeon_bo_kunmap(rbo);
	256	radeon_bo_unreserve(rbo);
	257	}
771fe6b9	258	}
f92e93eb	259	if (fb && ret) {
771fe6b9 JG	260	drm_gem_object_unreference(gobj);
	261	drm_framebuffer_cleanup(fb);
	262	kfree(fb);
	263	}
	264	drm_gem_object_unreference(gobj);
	265	mutex_unlock(&rdev->ddev->struct_mutex);
	266	out:
	267	return ret;
	268	}
	269
38651674 DA	270	static int radeon_fb_find_or_create_single(struct drm_device *dev,
	271	struct drm_fb_helper_surface_size *sizes,
	272	struct drm_fb_helper **fb_ptr)
	273	{
	274	struct radeon_device *rdev = dev->dev_private;
	275	struct radeon_kernel_fbdev *rfbdev = NULL;
	276	int new_fb = 0;
	277	int ret;
	278
	279	if (!rdev->mode_info.rfbdev) {
	280	ret = radeonfb_create(dev, sizes,
	281	&rfbdev);
	282	if (ret)
	283	return ret;
	284	rdev->mode_info.rfbdev = rfbdev;
	285	new_fb = 1;
	286	} else {
	287	rfbdev = rdev->mode_info.rfbdev;
	288	if (rfbdev->rfb.base.width < sizes->surface_width \|\|
	289	rfbdev->rfb.base.height < sizes->surface_height) {
	290	DRM_ERROR("Framebuffer not large enough to scale console onto.\n");
	291	return -EINVAL;
	292	}
	293	}
	294
	295	*fb_ptr = &rfbdev->helper;
	296	return new_fb;
	297	}
	298
d50ba256 DA	299	static char *mode_option;
	300	int radeon_parse_options(char *options)
	301	{
	302	char *this_opt;
	303
	304	if (!options \|\| !*options)
	305	return 0;
	306
	307	while ((this_opt = strsep(&options, ",")) != NULL) {
	308	if (!*this_opt)
	309	continue;
	310	mode_option = this_opt;
	311	}
	312	return 0;
	313	}
	314
38651674	315	static int radeonfb_probe(struct drm_device *dev)
771fe6b9	316	{
47381156 DA	317	struct radeon_device *rdev = dev->dev_private;
	318	int bpp_sel = 32;
	319
	320	/* select 8 bpp console on RN50 or 16MB cards */
	321	if (ASIC_IS_RN50(rdev) \|\| rdev->mc.real_vram_size <= (3210241024))
	322	bpp_sel = 8;
	323
38651674 DA	324	return drm_fb_helper_single_fb_probe(dev, bpp_sel, &radeon_fb_find_or_create_single);
	325	}
	326
	327	void radeonfb_hotplug(struct drm_device *dev)
	328	{
	329	drm_helper_fb_hotplug_event(dev);
	330
	331	radeonfb_probe(dev);
771fe6b9	332	}
771fe6b9	333
38651674	334	static int radeon_fbdev_destroy(struct drm_device dev, struct radeon_kernel_fbdev rfbdev)
771fe6b9 JG	335	{
771fe6b9 JG	336	struct fb_info *info;
38651674	337	struct radeon_framebuffer *rfb = &rfbdev->rfb;
4c788679 JG	338	struct radeon_bo *rbo;
4c788679 JG	339	int r;
771fe6b9	340
38651674 DA	341	rbo = rfb->obj->driver_private;
	342	info = rfbdev->helper.fbdev;
	343	unregister_framebuffer(info);
	344	r = radeon_bo_reserve(rbo, false);
	345	if (likely(r == 0)) {
	346	radeon_bo_kunmap(rbo);
	347	radeon_bo_unpin(rbo);
	348	radeon_bo_unreserve(rbo);
771fe6b9 JG	349	}
771fe6b9 JG	350
38651674 DA	351	drm_fb_helper_free(&rfbdev->helper);
	352	drm_framebuffer_cleanup(&rfb->base);
	353	if (rfb->obj)
	354	drm_gem_object_unreference_unlocked(rfb->obj);
	355
	356	framebuffer_release(info);
785b93ef	357
771fe6b9 JG	358	return 0;
771fe6b9 JG	359	}
771fe6b9	360	MODULE_LICENSE("GPL");
38651674 DA	361
	362	int radeon_fbdev_init(struct radeon_device *rdev)
	363	{
	364	drm_helper_initial_config(rdev->ddev);
	365	radeonfb_probe(rdev->ddev);
	366	return 0;
	367	}
	368
	369	void radeon_fbdev_fini(struct radeon_device *rdev)
	370	{
	371	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
	372	rdev->mode_info.rfbdev = NULL;
	373	}
	374
	375	void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
	376	{
	377	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
	378	}
	379
	380	int radeon_fbdev_total_size(struct radeon_device *rdev)
	381	{
	382	struct radeon_bo *robj;
	383	int size = 0;
	384
	385	robj = rdev->mode_info.rfbdev->rfb.obj->driver_private;
	386	size += radeon_bo_size(robj);
	387	return size;
	388	}
	389
	390	bool radeon_fbdev_robj_is_fb(struct radeon_device rdev, struct radeon_bo robj)
	391	{
	392	if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private)
	393	return true;
	394	return false;
	395	}
	396