[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/fb.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon.h"

#include "drm_fb_helper.h"

#include <linux/vga_switcheroo.h>

/* object hierarchy -
   this contains a helper + a radeon fb
   the helper contains a pointer to radeon framebuffer baseclass.
*/
struct radeon_fbdev {
	struct drm_fb_helper helper;
	struct radeon_framebuffer rfb;
	struct list_head fbdev_list;
	struct radeon_device *rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_fillrect = cfb_fillrect,
	.fb_copyarea = cfb_copyarea,
	.fb_imageblit = cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
};


static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct radeon_bo *rbo = gobj->driver_private;
	int ret;

	ret = radeon_bo_reserve(rbo, false);
	if (likely(ret == 0)) {
		radeon_bo_kunmap(rbo);
		radeon_bo_unreserve(rbo);
	}
	drm_gem_object_unreference_unlocked(gobj);
}

static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
					 struct drm_mode_fb_cmd *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;
	int ret;
	int aligned_size, size;

	/* need to align pitch with crtc limits */
	mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);

	size = mode_cmd->pitch * mode_cmd->height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = radeon_gem_object_create(rdev, aligned_size, 0,
				       RADEON_GEM_DOMAIN_VRAM,
				       false, true,
				       &gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
		       aligned_size);
		return -ENOMEM;
	}
	rbo = gobj->driver_private;

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (mode_cmd->bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags) {
		ret = radeon_bo_set_tiling_flags(rbo,
						 tiling_flags | RADEON_TILING_SURFACE,
						 mode_cmd->pitch);
		if (ret)
			dev_err(rdev->dev, "FB failed to set tiling flags\n");
	}


	ret = radeon_bo_reserve(rbo, false);
	if (unlikely(ret != 0))
		goto out_unref;
	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
	if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;
	}
	if (fb_tiled)
		radeon_bo_check_tiling(rbo, 0, 0);
	ret = radeon_bo_kmap(rbo, NULL);
	radeon_bo_unreserve(rbo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	radeonfb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int radeonfb_create(struct radeon_fbdev *rfbdev,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	struct device *device = &rdev->pdev->dev;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	/* avivo can't scanout real 24bpp */
	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		sizes->surface_bpp = 32;

	mode_cmd.bpp = sizes->surface_bpp;
	mode_cmd.depth = sizes->surface_depth;

	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	rbo = gobj->driver_private;

	/* okay we have an object now allocate the framebuffer */
	info = framebuffer_alloc(0, device);
	if (info == NULL) {
		ret = -ENOMEM;
		goto out_unref;
	}

	info->par = rfbdev;

	radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;
	rfbdev->helper.fbdev = info;

	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);

	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
	info->fbops = &radeonfb_ops;

	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = radeon_bo_size(rbo);
	info->screen_base = rbo->kptr;
	info->screen_size = radeon_bo_size(rbo);

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->apertures = alloc_apertures(1);
	if (!info->apertures) {
		ret = -ENOMEM;
		goto out_unref;
	}
	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
	info->apertures->ranges[0].size = rdev->mc.real_vram_size;

	info->fix.mmio_start = 0;
	info->fix.mmio_len = 0;
	info->pixmap.size = 64*1024;
	info->pixmap.buf_align = 8;
	info->pixmap.access_align = 32;
	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	info->pixmap.scan_align = 1;

	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_unref;
	}

	ret = fb_alloc_cmap(&info->cmap, 256, 0);
	if (ret) {
		ret = -ENOMEM;
		goto out_unref;
	}

	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitch);

	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	return 0;

out_unref:
	if (rbo) {

	}
	if (fb && ret) {
		drm_gem_object_unreference(gobj);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper,
					   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_fbdev *rfbdev = (struct radeon_fbdev *)helper;
	int new_fb = 0;
	int ret;

	if (!helper->fb) {
		ret = radeonfb_create(rfbdev, sizes);
		if (ret)
			return ret;
		new_fb = 1;
	}
	return new_fb;
}

static char *mode_option;
int radeon_parse_options(char *options)
{
	char *this_opt;

	if (!options || !*options)
		return 0;

	while ((this_opt = strsep(&options, ",")) != NULL) {
		if (!*this_opt)
			continue;
		mode_option = this_opt;
	}
	return 0;
}

void radeon_fb_output_poll_changed(struct radeon_device *rdev)
{
	drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
}

static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev)
{
	struct fb_info *info;
	struct radeon_framebuffer *rfb = &rfbdev->rfb;
	struct radeon_bo *rbo;
	int r;

	if (rfbdev->helper.fbdev) {
		info = rfbdev->helper.fbdev;

		unregister_framebuffer(info);
		if (info->cmap.len)
			fb_dealloc_cmap(&info->cmap);
		framebuffer_release(info);
	}

	if (rfb->obj) {
		rbo = rfb->obj->driver_private;
		r = radeon_bo_reserve(rbo, false);
		if (likely(r == 0)) {
			radeon_bo_kunmap(rbo);
			radeon_bo_unpin(rbo);
			radeon_bo_unreserve(rbo);
		}
		drm_gem_object_unreference_unlocked(rfb->obj);
	}
	drm_fb_helper_fini(&rfbdev->helper);
	drm_framebuffer_cleanup(&rfb->base);

	return 0;
}

static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
	.fb_probe = radeon_fb_find_or_create_single,
};

int radeon_fbdev_init(struct radeon_device *rdev)
{
	struct radeon_fbdev *rfbdev;
	int bpp_sel = 32;
	int ret;

	/* select 8 bpp console on RN50 or 16MB cards */
	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->rdev = rdev;
	rdev->mode_info.rfbdev = rfbdev;
	rfbdev->helper.funcs = &radeon_fb_helper_funcs;

	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
				 rdev->num_crtc,
				 RADEONFB_CONN_LIMIT);
	if (ret) {
		kfree(rfbdev);
		return ret;
	}

	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	return 0;
}

void radeon_fbdev_fini(struct radeon_device *rdev)
{
	if (!rdev->mode_info.rfbdev)
		return;

	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
	kfree(rdev->mode_info.rfbdev);
	rdev->mode_info.rfbdev = NULL;
}

void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
{
	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
}

int radeon_fbdev_total_size(struct radeon_device *rdev)
{
	struct radeon_bo *robj;
	int size = 0;

	robj = rdev->mode_info.rfbdev->rfb.obj->driver_private;
	size += radeon_bo_size(robj);
	return size;
}

bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
{
	if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private)
		return true;
	return false;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
771fe6b9	26	#include <linux/module.h>
5a0e3ad6	27	#include <linux/slab.h>
771fe6b9	28	#include <linux/fb.h>
771fe6b9 JG	29
	30	#include "drmP.h"
	31	#include "drm.h"
	32	#include "drm_crtc.h"
	33	#include "drm_crtc_helper.h"
	34	#include "radeon_drm.h"
	35	#include "radeon.h"
	36
785b93ef DA	37	#include "drm_fb_helper.h"
785b93ef DA	38
6a9ee8af DA	39	#include <linux/vga_switcheroo.h>
6a9ee8af DA	40
38651674 DA	41	/* object hierarchy -
	42	this contains a helper + a radeon fb
	43	the helper contains a pointer to radeon framebuffer baseclass.
	44	*/
8be48d92	45	struct radeon_fbdev {
785b93ef	46	struct drm_fb_helper helper;
38651674 DA	47	struct radeon_framebuffer rfb;
	48	struct list_head fbdev_list;
	49	struct radeon_device *rdev;
771fe6b9 JG	50	};
771fe6b9 JG	51
771fe6b9 JG	52	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	53	.owner = THIS_MODULE,
c88f9f0c	54	.fb_check_var = drm_fb_helper_check_var,
785b93ef	55	.fb_set_par = drm_fb_helper_set_par,
771fe6b9 JG	56	.fb_fillrect = cfb_fillrect,
	57	.fb_copyarea = cfb_copyarea,
	58	.fb_imageblit = cfb_imageblit,
785b93ef DA	59	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	60	.fb_blank = drm_fb_helper_blank,
068143d3	61	.fb_setcmap = drm_fb_helper_setcmap,
771fe6b9 JG	62	};
771fe6b9 JG	63
771fe6b9	64
e024e110	65	static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	66	{
771fe6b9 JG	67	int aligned = width;
e024e110	68	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	69	int pitch_mask = 0;
	70
	71	switch (bpp / 8) {
	72	case 1:
	73	pitch_mask = align_large ? 255 : 127;
	74	break;
	75	case 2:
	76	pitch_mask = align_large ? 127 : 31;
	77	break;
	78	case 3:
	79	case 4:
	80	pitch_mask = align_large ? 63 : 15;
	81	break;
	82	}
	83
	84	aligned += pitch_mask;
	85	aligned &= ~pitch_mask;
	86	return aligned;
	87	}
	88
8be48d92	89	static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
771fe6b9	90	{
8be48d92 DA	91	struct radeon_bo *rbo = gobj->driver_private;
	92	int ret;
	93
	94	ret = radeon_bo_reserve(rbo, false);
	95	if (likely(ret == 0)) {
	96	radeon_bo_kunmap(rbo);
	97	radeon_bo_unreserve(rbo);
	98	}
	99	drm_gem_object_unreference_unlocked(gobj);
	100	}
785b93ef	101
8be48d92 DA	102	static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
	103	struct drm_mode_fb_cmd *mode_cmd,
	104	struct drm_gem_object **gobj_p)
771fe6b9	105	{
8be48d92	106	struct radeon_device *rdev = rfbdev->rdev;
771fe6b9	107	struct drm_gem_object *gobj = NULL;
4c788679	108	struct radeon_bo *rbo = NULL;
e024e110	109	bool fb_tiled = false; /* useful for testing */
c88f9f0c	110	u32 tiling_flags = 0;
8be48d92 DA	111	int ret;
8be48d92 DA	112	int aligned_size, size;
771fe6b9	113
771fe6b9	114	/* need to align pitch with crtc limits */
8be48d92	115	mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);
771fe6b9	116
8be48d92	117	size = mode_cmd->pitch * mode_cmd->height;
771fe6b9	118	aligned_size = ALIGN(size, PAGE_SIZE);
771fe6b9	119	ret = radeon_gem_object_create(rdev, aligned_size, 0,
8be48d92	120	RADEON_GEM_DOMAIN_VRAM,
4dfe947e	121	false, true,
8be48d92	122	&gobj);
771fe6b9	123	if (ret) {
8be48d92 DA	124	printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
	125	aligned_size);
	126	return -ENOMEM;
771fe6b9	127	}
4c788679	128	rbo = gobj->driver_private;
771fe6b9	129
e024e110	130	if (fb_tiled)
c88f9f0c MD	131	tiling_flags = RADEON_TILING_MACRO;
	132
	133	#ifdef __BIG_ENDIAN
8be48d92	134	switch (mode_cmd->bpp) {
c88f9f0c MD	135	case 32:
	136	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	137	break;
	138	case 16:
	139	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	140	default:
	141	break;
	142	}
	143	#endif
	144
4c788679 JG	145	if (tiling_flags) {
4c788679 JG	146	ret = radeon_bo_set_tiling_flags(rbo,
8be48d92 DA	147	tiling_flags \| RADEON_TILING_SURFACE,
8be48d92 DA	148	mode_cmd->pitch);
4c788679 JG	149	if (ret)
	150	dev_err(rdev->dev, "FB failed to set tiling flags\n");
	151	}
8be48d92	152
38651674	153
4c788679 JG	154	ret = radeon_bo_reserve(rbo, false);
	155	if (unlikely(ret != 0))
	156	goto out_unref;
8be48d92	157	ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
4c788679 JG	158	if (ret) {
	159	radeon_bo_unreserve(rbo);
	160	goto out_unref;
	161	}
	162	if (fb_tiled)
	163	radeon_bo_check_tiling(rbo, 0, 0);
8be48d92	164	ret = radeon_bo_kmap(rbo, NULL);
4c788679	165	radeon_bo_unreserve(rbo);
f92e93eb	166	if (ret) {
f92e93eb JG	167	goto out_unref;
f92e93eb JG	168	}
771fe6b9	169
8be48d92 DA	170	*gobj_p = gobj;
	171	return 0;
	172	out_unref:
	173	radeonfb_destroy_pinned_object(gobj);
	174	*gobj_p = NULL;
	175	return ret;
	176	}
	177
	178	static int radeonfb_create(struct radeon_fbdev *rfbdev,
	179	struct drm_fb_helper_surface_size *sizes)
	180	{
	181	struct radeon_device *rdev = rfbdev->rdev;
	182	struct fb_info *info;
	183	struct drm_framebuffer *fb = NULL;
	184	struct drm_mode_fb_cmd mode_cmd;
	185	struct drm_gem_object *gobj = NULL;
	186	struct radeon_bo *rbo = NULL;
	187	struct device *device = &rdev->pdev->dev;
	188	int ret;
	189	unsigned long tmp;
	190
	191	mode_cmd.width = sizes->surface_width;
	192	mode_cmd.height = sizes->surface_height;
	193
	194	/* avivo can't scanout real 24bpp */
	195	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
	196	sizes->surface_bpp = 32;
	197
	198	mode_cmd.bpp = sizes->surface_bpp;
	199	mode_cmd.depth = sizes->surface_depth;
771fe6b9	200
8be48d92 DA	201	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
8be48d92 DA	202	rbo = gobj->driver_private;
771fe6b9	203
8be48d92 DA	204	/* okay we have an object now allocate the framebuffer */
8be48d92 DA	205	info = framebuffer_alloc(0, device);
771fe6b9 JG	206	if (info == NULL) {
	207	ret = -ENOMEM;
	208	goto out_unref;
	209	}
785b93ef	210
8be48d92	211	info->par = rfbdev;
771fe6b9	212
8be48d92 DA	213	radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
8be48d92 DA	214
38651674 DA	215	fb = &rfbdev->rfb.base;
	216
	217	/* setup helper */
	218	rfbdev->helper.fb = fb;
	219	rfbdev->helper.fbdev = info;
38651674	220
8be48d92	221	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
bf8e828b	222
771fe6b9	223	strcpy(info->fix.id, "radeondrmfb");
785b93ef	224
068143d3	225	drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
785b93ef	226
8fd4bd22	227	info->flags = FBINFO_DEFAULT \| FBINFO_CAN_FORCE_OUTPUT;
771fe6b9	228	info->fbops = &radeonfb_ops;
785b93ef	229
8be48d92	230	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
f92e93eb	231	info->fix.smem_start = rdev->mc.aper_base + tmp;
8be48d92 DA	232	info->fix.smem_len = radeon_bo_size(rbo);
	233	info->screen_base = rbo->kptr;
	234	info->screen_size = radeon_bo_size(rbo);
785b93ef	235
38651674	236	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
ed8f0d9e DA	237
ed8f0d9e DA	238	/* setup aperture base/size for vesafb takeover */
1471ca9a MS	239	info->apertures = alloc_apertures(1);
	240	if (!info->apertures) {
	241	ret = -ENOMEM;
	242	goto out_unref;
	243	}
	244	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
	245	info->apertures->ranges[0].size = rdev->mc.real_vram_size;
ed8f0d9e	246
696d4df1 MD	247	info->fix.mmio_start = 0;
696d4df1 MD	248	info->fix.mmio_len = 0;
771fe6b9 JG	249	info->pixmap.size = 64*1024;
	250	info->pixmap.buf_align = 8;
	251	info->pixmap.access_align = 32;
	252	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	253	info->pixmap.scan_align = 1;
4abe3520	254
771fe6b9 JG	255	if (info->screen_base == NULL) {
	256	ret = -ENOSPC;
	257	goto out_unref;
	258	}
4abe3520 DA	259
	260	ret = fb_alloc_cmap(&info->cmap, 256, 0);
	261	if (ret) {
	262	ret = -ENOMEM;
	263	goto out_unref;
	264	}
	265
771fe6b9 JG	266	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
771fe6b9 JG	267	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
8be48d92	268	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
771fe6b9 JG	269	DRM_INFO("fb depth is %d\n", fb->depth);
	270	DRM_INFO(" pitch is %d\n", fb->pitch);
	271
6a9ee8af	272	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
771fe6b9 JG	273	return 0;
	274
	275	out_unref:
4c788679	276	if (rbo) {
8be48d92	277
771fe6b9	278	}
f92e93eb	279	if (fb && ret) {
771fe6b9 JG	280	drm_gem_object_unreference(gobj);
	281	drm_framebuffer_cleanup(fb);
	282	kfree(fb);
	283	}
771fe6b9 JG	284	return ret;
	285	}
	286
8be48d92 DA	287	static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper,
8be48d92 DA	288	struct drm_fb_helper_surface_size *sizes)
38651674	289	{
8be48d92	290	struct radeon_fbdev rfbdev = (struct radeon_fbdev )helper;
38651674 DA	291	int new_fb = 0;
	292	int ret;
	293
8be48d92 DA	294	if (!helper->fb) {
8be48d92 DA	295	ret = radeonfb_create(rfbdev, sizes);
38651674 DA	296	if (ret)
38651674 DA	297	return ret;
38651674	298	new_fb = 1;
38651674	299	}
38651674 DA	300	return new_fb;
	301	}
	302
d50ba256 DA	303	static char *mode_option;
	304	int radeon_parse_options(char *options)
	305	{
	306	char *this_opt;
	307
	308	if (!options \|\| !*options)
	309	return 0;
	310
	311	while ((this_opt = strsep(&options, ",")) != NULL) {
	312	if (!*this_opt)
	313	continue;
	314	mode_option = this_opt;
	315	}
	316	return 0;
	317	}
	318
eb1f8e4f	319	void radeon_fb_output_poll_changed(struct radeon_device *rdev)
771fe6b9	320	{
eb1f8e4f	321	drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
771fe6b9	322	}
771fe6b9	323
8be48d92	324	static int radeon_fbdev_destroy(struct drm_device dev, struct radeon_fbdev rfbdev)
771fe6b9 JG	325	{
771fe6b9 JG	326	struct fb_info *info;
38651674	327	struct radeon_framebuffer *rfb = &rfbdev->rfb;
4c788679 JG	328	struct radeon_bo *rbo;
4c788679 JG	329	int r;
771fe6b9	330
8be48d92 DA	331	if (rfbdev->helper.fbdev) {
8be48d92 DA	332	info = rfbdev->helper.fbdev;
4abe3520	333
8be48d92	334	unregister_framebuffer(info);
4abe3520 DA	335	if (info->cmap.len)
4abe3520 DA	336	fb_dealloc_cmap(&info->cmap);
8be48d92	337	framebuffer_release(info);
771fe6b9	338	}
771fe6b9	339
8be48d92	340	if (rfb->obj) {
4c788679	341	rbo = rfb->obj->driver_private;
4c788679 JG	342	r = radeon_bo_reserve(rbo, false);
	343	if (likely(r == 0)) {
	344	radeon_bo_kunmap(rbo);
	345	radeon_bo_unpin(rbo);
	346	radeon_bo_unreserve(rbo);
	347	}
8be48d92	348	drm_gem_object_unreference_unlocked(rfb->obj);
771fe6b9	349	}
4abe3520	350	drm_fb_helper_fini(&rfbdev->helper);
38651674	351	drm_framebuffer_cleanup(&rfb->base);
771fe6b9	352
771fe6b9 JG	353	return 0;
771fe6b9 JG	354	}
785b93ef	355
4abe3520 DA	356	static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	357	.gamma_set = radeon_crtc_fb_gamma_set,
	358	.gamma_get = radeon_crtc_fb_gamma_get,
	359	.fb_probe = radeon_fb_find_or_create_single,
4abe3520	360	};
38651674 DA	361
	362	int radeon_fbdev_init(struct radeon_device *rdev)
	363	{
8be48d92	364	struct radeon_fbdev *rfbdev;
4abe3520	365	int bpp_sel = 32;
5a79395b	366	int ret;
4abe3520 DA	367
	368	/* select 8 bpp console on RN50 or 16MB cards */
	369	if (ASIC_IS_RN50(rdev) \|\| rdev->mc.real_vram_size <= (3210241024))
	370	bpp_sel = 8;
8be48d92 DA	371
	372	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	373	if (!rfbdev)
	374	return -ENOMEM;
	375
	376	rfbdev->rdev = rdev;
	377	rdev->mode_info.rfbdev = rfbdev;
4abe3520	378	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
8be48d92	379
5a79395b CW	380	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
	381	rdev->num_crtc,
	382	RADEONFB_CONN_LIMIT);
	383	if (ret) {
	384	kfree(rfbdev);
	385	return ret;
	386	}
	387
0b4c0f3f	388	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
4abe3520	389	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
771fe6b9	390	return 0;
38651674 DA	391	}
	392
	393	void radeon_fbdev_fini(struct radeon_device *rdev)
	394	{
8be48d92 DA	395	if (!rdev->mode_info.rfbdev)
	396	return;
	397
38651674	398	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
8be48d92	399	kfree(rdev->mode_info.rfbdev);
38651674 DA	400	rdev->mode_info.rfbdev = NULL;
	401	}
	402
	403	void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
	404	{
	405	fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
	406	}
	407
	408	int radeon_fbdev_total_size(struct radeon_device *rdev)
	409	{
	410	struct radeon_bo *robj;
	411	int size = 0;
	412
	413	robj = rdev->mode_info.rfbdev->rfb.obj->driver_private;
	414	size += radeon_bo_size(robj);
	415	return size;
	416	}
	417
	418	bool radeon_fbdev_robj_is_fb(struct radeon_device rdev, struct radeon_bo robj)
	419	{
	420	if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private)
	421	return true;
	422	return false;
771fe6b9	423	}