]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/radeon/radeon_drv.h
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/kms: r600/r700 command stream checker
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_drv.h
CommitLineData
1da177e4
LT		 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
70967ab9
BH		 34#include <linux/firmware.h>
35#include <linux/platform_device.h>
36
c2142715
DA		 37#include "radeon_family.h"
38
1da177e4
LT		 39/* General customization:
40 */
41
42#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
43
44#define DRIVER_NAME "radeon"
45#define DRIVER_DESC "ATI Radeon"
c0beb2a7 46#define DRIVER_DATE "20080528"
1da177e4
LT		 47
48/* Interface history:
49 *
50 * 1.1 - ??
51 * 1.2 - Add vertex2 ioctl (keith)
52 * - Add stencil capability to clear ioctl (gareth, keith)
53 * - Increase MAX_TEXTURE_LEVELS (brian)
54 * 1.3 - Add cmdbuf ioctl (keith)
55 * - Add support for new radeon packets (keith)
56 * - Add getparam ioctl (keith)
57 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
58 * 1.4 - Add scratch registers to get_param ioctl.
59 * 1.5 - Add r200 packets to cmdbuf ioctl
60 * - Add r200 function to init ioctl
61 * - Add 'scalar2' instruction to cmdbuf
62 * 1.6 - Add static GART memory manager
63 * Add irq handler (won't be turned on unless X server knows to)
64 * Add irq ioctls and irq_active getparam.
65 * Add wait command for cmdbuf ioctl
66 * Add GART offset query for getparam
67 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
68 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
69 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
70 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
71 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
72 * Add 'GET' queries for starting additional clients on different VT's.
73 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
74 * Add texture rectangle support for r100.
75 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
b5e89ed5 76 * clients use to tell the DRM where they think the framebuffer is
1da177e4
LT		 77 * located in the card's address space
78 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
79 * and GL_EXT_blend_[func|equation]_separate on r200
80 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
d985c108 81 * (No 3D support yet - just microcode loading).
1da177e4
LT		 82 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
83 * - Add hyperz support, add hyperz flags to clear ioctl.
84 * 1.14- Add support for color tiling
85 * - Add R100/R200 surface allocation/free support
86 * 1.15- Add support for texture micro tiling
87 * - Add support for r100 cube maps
88 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
89 * texture filtering on r200
414ed537 90 * 1.17- Add initial support for R300 (3D).
9d17601c
DA		 91 * 1.18- Add support for GL_ATI_fragment_shader, new packets
92 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
93 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
94 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
ea98a92f 95 * 1.19- Add support for gart table in FB memory and PCIE r300
d985c108
DA		 96 * 1.20- Add support for r300 texrect
97 * 1.21- Add support for card type getparam
4e5e2e25 98 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
d5ea702f 99 * 1.23- Add new radeon memory map work from benh
ee4621f0 100 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
d6fece05
DA		 101 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
102 * new packet type)
f2b04cd2
DA		 103 * 1.26- Add support for variable size PCI(E) gart aperture
104 * 1.27- Add support for IGP GART
ddbee333 105 * 1.28- Add support for VBL on CRTC2
c0beb2a7 106 * 1.29- R500 3D cmd buffer support
e8a13441 107 * 1.30- Add support for occlusion queries
f779b3e5 108 * 1.31- Add support for num Z pipes from GET_PARAM
1da177e4
LT		 109 */
110#define DRIVER_MAJOR 1
f779b3e5 111#define DRIVER_MINOR 31
1da177e4
LT		 112#define DRIVER_PATCHLEVEL 0
113
1da177e4
LT		 114enum radeon_cp_microcode_version {
115 UCODE_R100,
116 UCODE_R200,
117 UCODE_R300,
118};
119
1da177e4 120typedef struct drm_radeon_freelist {
b5e89ed5 121 unsigned int age;
056219e2 122 struct drm_buf *buf;
b5e89ed5
DA		 123 struct drm_radeon_freelist *next;
124 struct drm_radeon_freelist *prev;
1da177e4
LT		 125} drm_radeon_freelist_t;
126
127typedef struct drm_radeon_ring_buffer {
128 u32 *start;
129 u32 *end;
130 int size;
131 int size_l2qw;
132
576cc458
RS		 133 int rptr_update; /* Double Words */
134 int rptr_update_l2qw; /* log2 Quad Words */
135
136 int fetch_size; /* Double Words */
137 int fetch_size_l2ow; /* log2 Oct Words */
138
1da177e4
LT		 139 u32 tail;
140 u32 tail_mask;
141 int space;
142
143 int high_mark;
144} drm_radeon_ring_buffer_t;
145
146typedef struct drm_radeon_depth_clear_t {
147 u32 rb3d_cntl;
148 u32 rb3d_zstencilcntl;
149 u32 se_cntl;
150} drm_radeon_depth_clear_t;
151
152struct drm_radeon_driver_file_fields {
153 int64_t radeon_fb_delta;
154};
155
156struct mem_block {
157 struct mem_block *next;
158 struct mem_block *prev;
159 int start;
160 int size;
6c340eac 161 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT		 162};
163
164struct radeon_surface {
165 int refcount;
166 u32 lower;
167 u32 upper;
168 u32 flags;
169};
170
171struct radeon_virt_surface {
172 int surface_index;
173 u32 lower;
174 u32 upper;
175 u32 flags;
6c340eac 176 struct drm_file *file_priv;
6abf6bb0 177#define PCIGART_FILE_PRIV ((void *) -1L)
1da177e4
LT		 178};
179
b2665030
DM		 180#define RADEON_FLUSH_EMITED (1 << 0)
181#define RADEON_PURGE_EMITED (1 << 1)
54f961a6 182
7c1c2871
DA		 183struct drm_radeon_master_private {
184 drm_local_map_t *sarea;
185 drm_radeon_sarea_t *sarea_priv;
186};
187
1da177e4
LT		 188typedef struct drm_radeon_private {
189 drm_radeon_ring_buffer_t ring;
1da177e4
LT		 190
191 u32 fb_location;
d5ea702f
DA		 192 u32 fb_size;
193 int new_memmap;
1da177e4
LT		 194
195 int gart_size;
196 u32 gart_vm_start;
197 unsigned long gart_buffers_offset;
198
199 int cp_mode;
200 int cp_running;
201
b5e89ed5
DA		 202 drm_radeon_freelist_t *head;
203 drm_radeon_freelist_t *tail;
1da177e4 204 int last_buf;
1da177e4
LT		 205 int writeback_works;
206
207 int usec_timeout;
208
209 int microcode_version;
210
1da177e4
LT		 211 struct {
212 u32 boxes;
213 int freelist_timeouts;
214 int freelist_loops;
215 int requested_bufs;
216 int last_frame_reads;
217 int last_clear_reads;
218 int clears;
219 int texture_uploads;
220 } stats;
221
222 int do_boxes;
223 int page_flipping;
1da177e4
LT		 224
225 u32 color_fmt;
226 unsigned int front_offset;
227 unsigned int front_pitch;
228 unsigned int back_offset;
229 unsigned int back_pitch;
230
231 u32 depth_fmt;
232 unsigned int depth_offset;
233 unsigned int depth_pitch;
234
235 u32 front_pitch_offset;
236 u32 back_pitch_offset;
237 u32 depth_pitch_offset;
238
239 drm_radeon_depth_clear_t depth_clear;
b5e89ed5 240
1da177e4
LT		 241 unsigned long ring_offset;
242 unsigned long ring_rptr_offset;
243 unsigned long buffers_offset;
244 unsigned long gart_textures_offset;
245
246 drm_local_map_t *sarea;
1da177e4
LT		 247 drm_local_map_t *cp_ring;
248 drm_local_map_t *ring_rptr;
249 drm_local_map_t *gart_textures;
250
251 struct mem_block *gart_heap;
252 struct mem_block *fb_heap;
253
254 /* SW interrupt */
b5e89ed5
DA		 255 wait_queue_head_t swi_queue;
256 atomic_t swi_emitted;
ddbee333
DA		 257 int vblank_crtc;
258 uint32_t irq_enable_reg;
c0beb2a7 259 uint32_t r500_disp_irq_reg;
1da177e4
LT		 260
261 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
b5e89ed5 262 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
1da177e4 263
b5e89ed5 264 unsigned long pcigart_offset;
f2b04cd2 265 unsigned int pcigart_offset_set;
55910517 266 struct drm_ati_pcigart_info gart_info;
ea98a92f 267
ee4621f0
DA		 268 u32 scratch_ages[5];
269
1da177e4
LT		 270 /* starting from here on, data is preserved accross an open */
271 uint32_t flags; /* see radeon_chip_flags */
d883f7f1 272 resource_size_t fb_aper_offset;
5b92c404
AD		 273
274 int num_gb_pipes;
f779b3e5 275 int num_z_pipes;
54f961a6 276 int track_flush;
78538bf1 277 drm_local_map_t *mmio;
befb73c2
AD		 278
279 /* r6xx/r7xx pipe/shader config */
280 int r600_max_pipes;
281 int r600_max_tile_pipes;
282 int r600_max_simds;
283 int r600_max_backends;
284 int r600_max_gprs;
285 int r600_max_threads;
286 int r600_max_stack_entries;
287 int r600_max_hw_contexts;
288 int r600_max_gs_threads;
289 int r600_sx_max_export_size;
290 int r600_sx_max_export_pos_size;
291 int r600_sx_max_export_smx_size;
292 int r600_sq_num_cf_insts;
293 int r700_sx_num_of_sets;
294 int r700_sc_prim_fifo_size;
295 int r700_sc_hiz_tile_fifo_size;
296 int r700_sc_earlyz_tile_fifo_fize;
961fb597
JG		 297 int r600_group_size;
298 int r600_npipes;
299 int r600_nbanks;
befb73c2 300
3ce0a23d
JG		 301 struct mutex cs_mutex;
302 u32 cs_id_scnt;
303 u32 cs_id_wcnt;
304 /* r6xx/r7xx drm blit vertex buffer */
305 struct drm_buf *blit_vb;
306
70967ab9
BH		 307 /* firmware */
308 const struct firmware *me_fw, *pfp_fw;
1da177e4
LT		 309} drm_radeon_private_t;
310
311typedef struct drm_radeon_buf_priv {
312 u32 age;
313} drm_radeon_buf_priv_t;
314
b3a83639
DA		 315typedef struct drm_radeon_kcmd_buffer {
316 int bufsz;
317 char *buf;
318 int nbox;
c60ce623 319 struct drm_clip_rect __user *boxes;
b3a83639
DA		 320} drm_radeon_kcmd_buffer_t;
321
689b9d74 322extern int radeon_no_wb;
c153f45f 323extern struct drm_ioctl_desc radeon_ioctls[];
b3a83639
DA		 324extern int radeon_max_ioctl;
325
b07fa022
DM		 326extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
327extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
328
329#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
330#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
331
1d6bb8e5
MD		 332/* Check whether the given hardware address is inside the framebuffer or the
333 * GART area.
334 */
335static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
336 u64 off)
337{
338 u32 fb_start = dev_priv->fb_location;
339 u32 fb_end = fb_start + dev_priv->fb_size - 1;
340 u32 gart_start = dev_priv->gart_vm_start;
341 u32 gart_end = gart_start + dev_priv->gart_size - 1;
342
343 return ((off >= fb_start && off <= fb_end) ||
344 (off >= gart_start && off <= gart_end));
345}
346
3ce0a23d
JG		 347/* radeon_state.c */
348extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf);
349
1da177e4 350 /* radeon_cp.c */
c153f45f
EA		 351extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
352extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
353extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
354extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
355extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
356extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
357extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
358extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
359extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
3d5e2c13 360extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
c05ce083
AD		 361extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
362extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
befb73c2 363extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
1da177e4 364
84b1fd10 365extern void radeon_freelist_reset(struct drm_device * dev);
056219e2 366extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
1da177e4 367
b5e89ed5 368extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
1da177e4 369
b5e89ed5 370extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
1da177e4
LT		 371
372extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
836cf046 373extern int radeon_presetup(struct drm_device *dev);
1da177e4
LT		 374extern int radeon_driver_postcleanup(struct drm_device *dev);
375
c153f45f
EA		 376extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
377extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
378extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
b5e89ed5 379extern void radeon_mem_takedown(struct mem_block **heap);
6c340eac
EA		 380extern void radeon_mem_release(struct drm_file *file_priv,
381 struct mem_block *heap);
1da177e4 382
c05ce083
AD		 383extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
384extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
385extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
386
1da177e4 387 /* radeon_irq.c */
0a3e67a4 388extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
c153f45f
EA		 389extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
390extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
b5e89ed5 391
84b1fd10 392extern void radeon_do_release(struct drm_device * dev);
0a3e67a4
JB		 393extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
394extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
395extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
b5e89ed5 396extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10 397extern void radeon_driver_irq_preinstall(struct drm_device * dev);
0a3e67a4 398extern int radeon_driver_irq_postinstall(struct drm_device *dev);
84b1fd10 399extern void radeon_driver_irq_uninstall(struct drm_device * dev);
7ecabc53 400extern void radeon_enable_interrupt(struct drm_device *dev);
84b1fd10
DA		 401extern int radeon_vblank_crtc_get(struct drm_device *dev);
402extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
1da177e4 403
22eae947
DA		 404extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
405extern int radeon_driver_unload(struct drm_device *dev);
406extern int radeon_driver_firstopen(struct drm_device *dev);
0a3e67a4
JB		 407extern void radeon_driver_preclose(struct drm_device *dev,
408 struct drm_file *file_priv);
409extern void radeon_driver_postclose(struct drm_device *dev,
410 struct drm_file *file_priv);
84b1fd10 411extern void radeon_driver_lastclose(struct drm_device * dev);
0a3e67a4
JB		 412extern int radeon_driver_open(struct drm_device *dev,
413 struct drm_file *file_priv);
9a186645
DA		 414extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
415 unsigned long arg);
70ba2a37
DA		 416extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
417 unsigned long arg);
9a186645 418
7c1c2871
DA		 419extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
420extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
421extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master);
414ed537 422/* r300_cmdbuf.c */
3d5e2c13 423extern void r300_init_reg_flags(struct drm_device *dev);
414ed537 424
0a3e67a4 425extern int r300_do_cp_cmdbuf(struct drm_device *dev,
6c340eac 426 struct drm_file *file_priv,
0a3e67a4 427 drm_radeon_kcmd_buffer_t *cmdbuf);
414ed537 428
c05ce083
AD		 429/* r600_cp.c */
430extern int r600_do_engine_reset(struct drm_device *dev);
431extern int r600_do_cleanup_cp(struct drm_device *dev);
432extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
433 struct drm_file *file_priv);
434extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
435extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
436extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
437extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
438extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
439extern int r600_cp_dispatch_indirect(struct drm_device *dev,
440 struct drm_buf *buf, int start, int end);
c1556f71
AD		 441extern int r600_page_table_init(struct drm_device *dev);
442extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
3ce0a23d
JG		 443extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
444extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv);
445extern int r600_cp_dispatch_texture(struct drm_device *dev,
446 struct drm_file *file_priv,
447 drm_radeon_texture_t *tex,
448 drm_radeon_tex_image_t *image);
449/* r600_blit.c */
450extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv);
451extern void r600_done_blit_copy(struct drm_device *dev);
452extern void r600_blit_copy(struct drm_device *dev,
453 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
454 int size_bytes);
455extern void r600_blit_swap(struct drm_device *dev,
456 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
457 int sx, int sy, int dx, int dy,
458 int w, int h, int src_pitch, int dst_pitch, int cpp);
c05ce083 459
1da177e4
LT		 460/* Flags for stats.boxes
461 */
462#define RADEON_BOX_DMA_IDLE 0x1
463#define RADEON_BOX_RING_FULL 0x2
464#define RADEON_BOX_FLIP 0x4
465#define RADEON_BOX_WAIT_IDLE 0x8
466#define RADEON_BOX_TEXTURE_LOAD 0x10
467
1da177e4
LT		 468/* Register definitions, register access macros and drmAddMap constants
469 * for Radeon kernel driver.
470 */
befb73c2
AD		 471#define RADEON_MM_INDEX 0x0000
472#define RADEON_MM_DATA 0x0004
1da177e4
LT		 473
474#define RADEON_AGP_COMMAND 0x0f60
d985c108
DA		 475#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
476# define RADEON_AGP_ENABLE (1<<8)
1da177e4
LT		 477#define RADEON_AUX_SCISSOR_CNTL 0x26f0
478# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
479# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
480# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
481# define RADEON_SCISSOR_0_ENABLE (1 << 28)
482# define RADEON_SCISSOR_1_ENABLE (1 << 29)
483# define RADEON_SCISSOR_2_ENABLE (1 << 30)
484
edc6f389
AD		 485/*
486 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
487 * don't have an explicit bus mastering disable bit. It's handled
488 * by the PCI D-states. PMI_BM_DIS disables D-state bus master
489 * handling, not bus mastering itself.
490 */
1da177e4 491#define RADEON_BUS_CNTL 0x0030
4e270e9b 492/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
1da177e4 493# define RADEON_BUS_MASTER_DIS (1 << 6)
4e270e9b
AD		 494/* rs600/rs690/rs740 */
495# define RS600_BUS_MASTER_DIS (1 << 14)
496# define RS600_MSI_REARM (1 << 20)
497/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
edc6f389
AD		 498
499#define RADEON_BUS_CNTL1 0x0034
500# define RADEON_PMI_BM_DIS (1 << 2)
501# define RADEON_PMI_INT_DIS (1 << 3)
502
503#define RV370_BUS_CNTL 0x004c
504# define RV370_PMI_BM_DIS (1 << 5)
505# define RV370_PMI_INT_DIS (1 << 6)
506
507#define RADEON_MSI_REARM_EN 0x0160
508/* rv370/rv380, rv410, r423/r430/r480, r5xx */
509# define RV370_MSI_REARM_EN (1 << 0)
1da177e4
LT		 510
511#define RADEON_CLOCK_CNTL_DATA 0x000c
512# define RADEON_PLL_WR_EN (1 << 7)
513#define RADEON_CLOCK_CNTL_INDEX 0x0008
514#define RADEON_CONFIG_APER_SIZE 0x0108
d985c108 515#define RADEON_CONFIG_MEMSIZE 0x00f8
1da177e4
LT		 516#define RADEON_CRTC_OFFSET 0x0224
517#define RADEON_CRTC_OFFSET_CNTL 0x0228
518# define RADEON_CRTC_TILE_EN (1 << 15)
519# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
520#define RADEON_CRTC2_OFFSET 0x0324
521#define RADEON_CRTC2_OFFSET_CNTL 0x0328
522
ea98a92f
DA		 523#define RADEON_PCIE_INDEX 0x0030
524#define RADEON_PCIE_DATA 0x0034
525#define RADEON_PCIE_TX_GART_CNTL 0x10
bc5f4523 526# define RADEON_PCIE_TX_GART_EN (1 << 0)
2735977b
AD		 527# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
528# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
529# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
530# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
531# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
532# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
533# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
ea98a92f
DA		 534#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
535#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
bc5f4523 536#define RADEON_PCIE_TX_GART_BASE 0x13
ea98a92f
DA		 537#define RADEON_PCIE_TX_GART_START_LO 0x14
538#define RADEON_PCIE_TX_GART_START_HI 0x15
539#define RADEON_PCIE_TX_GART_END_LO 0x16
540#define RADEON_PCIE_TX_GART_END_HI 0x17
541
45e51905
AD		 542#define RS480_NB_MC_INDEX 0x168
543# define RS480_NB_MC_IND_WR_EN (1 << 8)
544#define RS480_NB_MC_DATA 0x16c
f2b04cd2 545
60f92683
MC		 546#define RS690_MC_INDEX 0x78
547# define RS690_MC_INDEX_MASK 0x1ff
548# define RS690_MC_INDEX_WR_EN (1 << 9)
549# define RS690_MC_INDEX_WR_ACK 0x7f
550#define RS690_MC_DATA 0x7c
551
2735977b 552/* MC indirect registers */
45e51905
AD		 553#define RS480_MC_MISC_CNTL 0x18
554# define RS480_DISABLE_GTW (1 << 1)
2735977b 555/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
45e51905 556# define RS480_GART_INDEX_REG_EN (1 << 12)
2735977b 557# define RS690_BLOCK_GFX_D3_EN (1 << 14)
45e51905
AD		 558#define RS480_K8_FB_LOCATION 0x1e
559#define RS480_GART_FEATURE_ID 0x2b
560# define RS480_HANG_EN (1 << 11)
561# define RS480_TLB_ENABLE (1 << 18)
562# define RS480_P2P_ENABLE (1 << 19)
563# define RS480_GTW_LAC_EN (1 << 25)
564# define RS480_2LEVEL_GART (0 << 30)
565# define RS480_1LEVEL_GART (1 << 30)
566# define RS480_PDC_EN (1 << 31)
567#define RS480_GART_BASE 0x2c
568#define RS480_GART_CACHE_CNTRL 0x2e
569# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
570#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
571# define RS480_GART_EN (1 << 0)
572# define RS480_VA_SIZE_32MB (0 << 1)
573# define RS480_VA_SIZE_64MB (1 << 1)
574# define RS480_VA_SIZE_128MB (2 << 1)
575# define RS480_VA_SIZE_256MB (3 << 1)
576# define RS480_VA_SIZE_512MB (4 << 1)
577# define RS480_VA_SIZE_1GB (5 << 1)
578# define RS480_VA_SIZE_2GB (6 << 1)
579#define RS480_AGP_MODE_CNTL 0x39
580# define RS480_POST_GART_Q_SIZE (1 << 18)
581# define RS480_NONGART_SNOOP (1 << 19)
582# define RS480_AGP_RD_BUF_SIZE (1 << 20)
583# define RS480_REQ_TYPE_SNOOP_SHIFT 22
584# define RS480_REQ_TYPE_SNOOP_MASK 0x3
585# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
586#define RS480_MC_MISC_UMA_CNTL 0x5f
587#define RS480_MC_MCLK_CNTL 0x7a
588#define RS480_MC_UMA_DUALCH_CNTL 0x86
2735977b 589
60f92683
MC		 590#define RS690_MC_FB_LOCATION 0x100
591#define RS690_MC_AGP_LOCATION 0x101
592#define RS690_MC_AGP_BASE 0x102
3722bfc6 593#define RS690_MC_AGP_BASE_2 0x103
60f92683 594
c1556f71
AD		 595#define RS600_MC_INDEX 0x70
596# define RS600_MC_ADDR_MASK 0xffff
597# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
598# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
599# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
600# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
601# define RS600_MC_IND_AIC_RBS (1 << 20)
602# define RS600_MC_IND_CITF_ARB0 (1 << 21)
603# define RS600_MC_IND_CITF_ARB1 (1 << 22)
604# define RS600_MC_IND_WR_EN (1 << 23)
605#define RS600_MC_DATA 0x74
606
607#define RS600_MC_STATUS 0x0
608# define RS600_MC_IDLE (1 << 1)
609#define RS600_MC_FB_LOCATION 0x4
610#define RS600_MC_AGP_LOCATION 0x5
611#define RS600_AGP_BASE 0x6
612#define RS600_AGP_BASE_2 0x7
613#define RS600_MC_CNTL1 0x9
614# define RS600_ENABLE_PAGE_TABLES (1 << 26)
615#define RS600_MC_PT0_CNTL 0x100
616# define RS600_ENABLE_PT (1 << 0)
617# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)
618# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)
619# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28)
620# define RS600_INVALIDATE_L2_CACHE (1 << 29)
621#define RS600_MC_PT0_CONTEXT0_CNTL 0x102
622# define RS600_ENABLE_PAGE_TABLE (1 << 0)
623# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)
624#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
625#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114
626#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
627#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c
628#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c
629#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c
630#define RS600_MC_PT0_CLIENT0_CNTL 0x16c
631# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)
632# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1)
633# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8)
634# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)
635# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8)
636# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8)
637# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8)
638# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)
639# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10)
640# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)
641# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)
642# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
643# define RS600_INVALIDATE_L1_TLB (1 << 20)
644
3d5e2c13 645#define R520_MC_IND_INDEX 0x70
2735977b 646#define R520_MC_IND_WR_EN (1 << 24)
3d5e2c13
DA		 647#define R520_MC_IND_DATA 0x74
648
649#define RV515_MC_FB_LOCATION 0x01
650#define RV515_MC_AGP_LOCATION 0x02
70b13d51
DA		 651#define RV515_MC_AGP_BASE 0x03
652#define RV515_MC_AGP_BASE_2 0x04
3d5e2c13
DA		 653
654#define R520_MC_FB_LOCATION 0x04
655#define R520_MC_AGP_LOCATION 0x05
70b13d51
DA		 656#define R520_MC_AGP_BASE 0x06
657#define R520_MC_AGP_BASE_2 0x07
3d5e2c13 658
414ed537
DA		 659#define RADEON_MPP_TB_CONFIG 0x01c0
660#define RADEON_MEM_CNTL 0x0140
661#define RADEON_MEM_SDRAM_MODE_REG 0x0158
45e51905
AD		 662#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
663#define RS480_AGP_BASE_2 0x0164
414ed537
DA		 664#define RADEON_AGP_BASE 0x0170
665
5b92c404
AD		 666/* pipe config regs */
667#define R400_GB_PIPE_SELECT 0x402c
f779b3e5 668#define RV530_GB_PIPE_SELECT2 0x4124
5b92c404 669#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
5b92c404
AD		 670#define R300_GB_TILE_CONFIG 0x4018
671# define R300_ENABLE_TILING (1 << 0)
672# define R300_PIPE_COUNT_RV350 (0 << 1)
673# define R300_PIPE_COUNT_R300 (3 << 1)
674# define R300_PIPE_COUNT_R420_3P (6 << 1)
675# define R300_PIPE_COUNT_R420 (7 << 1)
676# define R300_TILE_SIZE_8 (0 << 4)
677# define R300_TILE_SIZE_16 (1 << 4)
678# define R300_TILE_SIZE_32 (2 << 4)
679# define R300_SUBPIXEL_1_12 (0 << 16)
680# define R300_SUBPIXEL_1_16 (1 << 16)
681#define R300_DST_PIPE_CONFIG 0x170c
682# define R300_PIPE_AUTO_CONFIG (1 << 31)
683#define R300_RB2D_DSTCACHE_MODE 0x3428
684# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
685# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
686
1da177e4
LT		 687#define RADEON_RB3D_COLOROFFSET 0x1c40
688#define RADEON_RB3D_COLORPITCH 0x1c48
689
3e14a286
MD		 690#define RADEON_SRC_X_Y 0x1590
691
1da177e4
LT		 692#define RADEON_DP_GUI_MASTER_CNTL 0x146c
693# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
694# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
695# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
696# define RADEON_GMC_BRUSH_NONE (15 << 4)
697# define RADEON_GMC_DST_16BPP (4 << 8)
698# define RADEON_GMC_DST_24BPP (5 << 8)
699# define RADEON_GMC_DST_32BPP (6 << 8)
700# define RADEON_GMC_DST_DATATYPE_SHIFT 8
701# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
702# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
703# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
704# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
705# define RADEON_GMC_WR_MSK_DIS (1 << 30)
706# define RADEON_ROP3_S 0x00cc0000
707# define RADEON_ROP3_P 0x00f00000
708#define RADEON_DP_WRITE_MASK 0x16cc
3e14a286 709#define RADEON_SRC_PITCH_OFFSET 0x1428
1da177e4
LT		 710#define RADEON_DST_PITCH_OFFSET 0x142c
711#define RADEON_DST_PITCH_OFFSET_C 0x1c80
712# define RADEON_DST_TILE_LINEAR (0 << 30)
713# define RADEON_DST_TILE_MACRO (1 << 30)
714# define RADEON_DST_TILE_MICRO (2 << 30)
715# define RADEON_DST_TILE_BOTH (3 << 30)
716
717#define RADEON_SCRATCH_REG0 0x15e0
718#define RADEON_SCRATCH_REG1 0x15e4
719#define RADEON_SCRATCH_REG2 0x15e8
720#define RADEON_SCRATCH_REG3 0x15ec
721#define RADEON_SCRATCH_REG4 0x15f0
722#define RADEON_SCRATCH_REG5 0x15f4
723#define RADEON_SCRATCH_UMSK 0x0770
724#define RADEON_SCRATCH_ADDR 0x0774
725
726#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
727
b07fa022
DM		 728extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
729
730#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
1da177e4 731
befb73c2
AD		 732#define R600_SCRATCH_REG0 0x8500
733#define R600_SCRATCH_REG1 0x8504
734#define R600_SCRATCH_REG2 0x8508
735#define R600_SCRATCH_REG3 0x850c
736#define R600_SCRATCH_REG4 0x8510
737#define R600_SCRATCH_REG5 0x8514
738#define R600_SCRATCH_REG6 0x8518
739#define R600_SCRATCH_REG7 0x851c
740#define R600_SCRATCH_UMSK 0x8540
741#define R600_SCRATCH_ADDR 0x8544
742
743#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
744
1da177e4
LT		 745#define RADEON_GEN_INT_CNTL 0x0040
746# define RADEON_CRTC_VBLANK_MASK (1 << 0)
ddbee333 747# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
1da177e4
LT		 748# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
749# define RADEON_SW_INT_ENABLE (1 << 25)
750
751#define RADEON_GEN_INT_STATUS 0x0044
752# define RADEON_CRTC_VBLANK_STAT (1 << 0)
bc5f4523 753# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
ddbee333 754# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
bc5f4523 755# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
1da177e4
LT		 756# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
757# define RADEON_SW_INT_TEST (1 << 25)
bc5f4523 758# define RADEON_SW_INT_TEST_ACK (1 << 25)
1da177e4 759# define RADEON_SW_INT_FIRE (1 << 26)
0a3e67a4 760# define R500_DISPLAY_INT_STATUS (1 << 0)
1da177e4
LT		 761
762#define RADEON_HOST_PATH_CNTL 0x0130
763# define RADEON_HDP_SOFT_RESET (1 << 26)
764# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
765# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
766
767#define RADEON_ISYNC_CNTL 0x1724
768# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
769# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
770# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
771# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
772# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
773# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
774
775#define RADEON_RBBM_GUICNTL 0x172c
776# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
777# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
778# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
779# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
780
781#define RADEON_MC_AGP_LOCATION 0x014c
782#define RADEON_MC_FB_LOCATION 0x0148
783#define RADEON_MCLK_CNTL 0x0012
784# define RADEON_FORCEON_MCLKA (1 << 16)
785# define RADEON_FORCEON_MCLKB (1 << 17)
786# define RADEON_FORCEON_YCLKA (1 << 18)
787# define RADEON_FORCEON_YCLKB (1 << 19)
788# define RADEON_FORCEON_MC (1 << 20)
789# define RADEON_FORCEON_AIC (1 << 21)
790
791#define RADEON_PP_BORDER_COLOR_0 0x1d40
792#define RADEON_PP_BORDER_COLOR_1 0x1d44
793#define RADEON_PP_BORDER_COLOR_2 0x1d48
794#define RADEON_PP_CNTL 0x1c38
795# define RADEON_SCISSOR_ENABLE (1 << 1)
796#define RADEON_PP_LUM_MATRIX 0x1d00
797#define RADEON_PP_MISC 0x1c14
798#define RADEON_PP_ROT_MATRIX_0 0x1d58
799#define RADEON_PP_TXFILTER_0 0x1c54
800#define RADEON_PP_TXOFFSET_0 0x1c5c
801#define RADEON_PP_TXFILTER_1 0x1c6c
802#define RADEON_PP_TXFILTER_2 0x1c84
803
5e35eff1
AD		 804#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
805#define R300_DSTCACHE_CTLSTAT 0x1714
806# define R300_RB2D_DC_FLUSH (3 << 0)
807# define R300_RB2D_DC_FREE (3 << 2)
808# define R300_RB2D_DC_FLUSH_ALL 0xf
809# define R300_RB2D_DC_BUSY (1 << 31)
1da177e4
LT		 810#define RADEON_RB3D_CNTL 0x1c3c
811# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
812# define RADEON_PLANE_MASK_ENABLE (1 << 1)
813# define RADEON_DITHER_ENABLE (1 << 2)
814# define RADEON_ROUND_ENABLE (1 << 3)
815# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
816# define RADEON_DITHER_INIT (1 << 5)
817# define RADEON_ROP_ENABLE (1 << 6)
818# define RADEON_STENCIL_ENABLE (1 << 7)
819# define RADEON_Z_ENABLE (1 << 8)
820# define RADEON_ZBLOCK16 (1 << 15)
821#define RADEON_RB3D_DEPTHOFFSET 0x1c24
822#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
823#define RADEON_RB3D_DEPTHPITCH 0x1c28
824#define RADEON_RB3D_PLANEMASK 0x1d84
825#define RADEON_RB3D_STENCILREFMASK 0x1d7c
826#define RADEON_RB3D_ZCACHE_MODE 0x3250
827#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
828# define RADEON_RB3D_ZC_FLUSH (1 << 0)
829# define RADEON_RB3D_ZC_FREE (1 << 2)
830# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
831# define RADEON_RB3D_ZC_BUSY (1 << 31)
259434ac
AD		 832#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
833# define R300_ZC_FLUSH (1 << 0)
834# define R300_ZC_FREE (1 << 1)
259434ac 835# define R300_ZC_BUSY (1 << 31)
b9b603dd
MD		 836#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
837# define RADEON_RB3D_DC_FLUSH (3 << 0)
838# define RADEON_RB3D_DC_FREE (3 << 2)
839# define RADEON_RB3D_DC_FLUSH_ALL 0xf
840# define RADEON_RB3D_DC_BUSY (1 << 31)
259434ac 841#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
54f961a6
JG		 842# define R300_RB3D_DC_FLUSH (2 << 0)
843# define R300_RB3D_DC_FREE (2 << 2)
259434ac 844# define R300_RB3D_DC_FINISH (1 << 4)
1da177e4
LT		 845#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
846# define RADEON_Z_TEST_MASK (7 << 4)
847# define RADEON_Z_TEST_ALWAYS (7 << 4)
848# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
849# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
850# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
851# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
852# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
853# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
854# define RADEON_FORCE_Z_DIRTY (1 << 29)
855# define RADEON_Z_WRITE_ENABLE (1 << 30)
856# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
857#define RADEON_RBBM_SOFT_RESET 0x00f0
858# define RADEON_SOFT_RESET_CP (1 << 0)
859# define RADEON_SOFT_RESET_HI (1 << 1)
860# define RADEON_SOFT_RESET_SE (1 << 2)
861# define RADEON_SOFT_RESET_RE (1 << 3)
862# define RADEON_SOFT_RESET_PP (1 << 4)
863# define RADEON_SOFT_RESET_E2 (1 << 5)
864# define RADEON_SOFT_RESET_RB (1 << 6)
865# define RADEON_SOFT_RESET_HDP (1 << 7)
576cc458
RS		 866/*
867 * 6:0 Available slots in the FIFO
868 * 8 Host Interface active
869 * 9 CP request active
870 * 10 FIFO request active
871 * 11 Host Interface retry active
872 * 12 CP retry active
873 * 13 FIFO retry active
874 * 14 FIFO pipeline busy
875 * 15 Event engine busy
876 * 16 CP command stream busy
877 * 17 2D engine busy
878 * 18 2D portion of render backend busy
879 * 20 3D setup engine busy
880 * 26 GA engine busy
881 * 27 CBA 2D engine busy
882 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
883 * command stream queue not empty or Ring Buffer not empty
884 */
1da177e4 885#define RADEON_RBBM_STATUS 0x0e40
576cc458
RS		 886/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
887/* #define RADEON_RBBM_STATUS 0x1740 */
888/* bits 6:0 are dword slots available in the cmd fifo */
1da177e4 889# define RADEON_RBBM_FIFOCNT_MASK 0x007f
576cc458
RS		 890# define RADEON_HIRQ_ON_RBB (1 << 8)
891# define RADEON_CPRQ_ON_RBB (1 << 9)
892# define RADEON_CFRQ_ON_RBB (1 << 10)
893# define RADEON_HIRQ_IN_RTBUF (1 << 11)
894# define RADEON_CPRQ_IN_RTBUF (1 << 12)
895# define RADEON_CFRQ_IN_RTBUF (1 << 13)
896# define RADEON_PIPE_BUSY (1 << 14)
897# define RADEON_ENG_EV_BUSY (1 << 15)
898# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
899# define RADEON_E2_BUSY (1 << 17)
900# define RADEON_RB2D_BUSY (1 << 18)
901# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
902# define RADEON_VAP_BUSY (1 << 20)
903# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
904# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
905# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
906# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
907# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
908# define RADEON_GA_BUSY (1 << 26)
909# define RADEON_CBA2D_BUSY (1 << 27)
910# define RADEON_RBBM_ACTIVE (1 << 31)
1da177e4
LT		 911#define RADEON_RE_LINE_PATTERN 0x1cd0
912#define RADEON_RE_MISC 0x26c4
913#define RADEON_RE_TOP_LEFT 0x26c0
914#define RADEON_RE_WIDTH_HEIGHT 0x1c44
915#define RADEON_RE_STIPPLE_ADDR 0x1cc8
916#define RADEON_RE_STIPPLE_DATA 0x1ccc
917
918#define RADEON_SCISSOR_TL_0 0x1cd8
919#define RADEON_SCISSOR_BR_0 0x1cdc
920#define RADEON_SCISSOR_TL_1 0x1ce0
921#define RADEON_SCISSOR_BR_1 0x1ce4
922#define RADEON_SCISSOR_TL_2 0x1ce8
923#define RADEON_SCISSOR_BR_2 0x1cec
924#define RADEON_SE_COORD_FMT 0x1c50
925#define RADEON_SE_CNTL 0x1c4c
926# define RADEON_FFACE_CULL_CW (0 << 0)
927# define RADEON_BFACE_SOLID (3 << 1)
928# define RADEON_FFACE_SOLID (3 << 3)
929# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
930# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
931# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
932# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
933# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
934# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
935# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
936# define RADEON_FOG_SHADE_FLAT (1 << 14)
937# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
938# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
939# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
940# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
941# define RADEON_ROUND_MODE_TRUNC (0 << 28)
942# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
943#define RADEON_SE_CNTL_STATUS 0x2140
944#define RADEON_SE_LINE_WIDTH 0x1db8
945#define RADEON_SE_VPORT_XSCALE 0x1d98
946#define RADEON_SE_ZBIAS_FACTOR 0x1db0
947#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
948#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
949#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
950# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
951# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
952#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
953#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
954# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
955#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
956#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
957#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
958#define RADEON_SURFACE_CNTL 0x0b00
959# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
960# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
961# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
962# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
963# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
964# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
965# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
966# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
967# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
968#define RADEON_SURFACE0_INFO 0x0b0c
969# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
970# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
971# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
972# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
973# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
974# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
975#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
976#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
977# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
978#define RADEON_SURFACE1_INFO 0x0b1c
979#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
980#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
981#define RADEON_SURFACE2_INFO 0x0b2c
982#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
983#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
984#define RADEON_SURFACE3_INFO 0x0b3c
985#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
986#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
987#define RADEON_SURFACE4_INFO 0x0b4c
988#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
989#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
990#define RADEON_SURFACE5_INFO 0x0b5c
991#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
992#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
993#define RADEON_SURFACE6_INFO 0x0b6c
994#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
995#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
996#define RADEON_SURFACE7_INFO 0x0b7c
997#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
998#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
999#define RADEON_SW_SEMAPHORE 0x013c
1000
1001#define RADEON_WAIT_UNTIL 0x1720
1002# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
d985c108
DA		 1003# define RADEON_WAIT_2D_IDLE (1 << 14)
1004# define RADEON_WAIT_3D_IDLE (1 << 15)
1da177e4
LT		 1005# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1006# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1007# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1008
1009#define RADEON_RB3D_ZMASKOFFSET 0x3234
1010#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
1011# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
1012# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
1013
1da177e4
LT		 1014/* CP registers */
1015#define RADEON_CP_ME_RAM_ADDR 0x07d4
1016#define RADEON_CP_ME_RAM_RADDR 0x07d8
1017#define RADEON_CP_ME_RAM_DATAH 0x07dc
1018#define RADEON_CP_ME_RAM_DATAL 0x07e0
1019
1020#define RADEON_CP_RB_BASE 0x0700
1021#define RADEON_CP_RB_CNTL 0x0704
1022# define RADEON_BUF_SWAP_32BIT (2 << 16)
ae1b1a48 1023# define RADEON_RB_NO_UPDATE (1 << 27)
befb73c2 1024# define RADEON_RB_RPTR_WR_ENA (1 << 31)
1da177e4
LT		 1025#define RADEON_CP_RB_RPTR_ADDR 0x070c
1026#define RADEON_CP_RB_RPTR 0x0710
1027#define RADEON_CP_RB_WPTR 0x0714
1028
1029#define RADEON_CP_RB_WPTR_DELAY 0x0718
1030# define RADEON_PRE_WRITE_TIMER_SHIFT 0
1031# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
1032
1033#define RADEON_CP_IB_BASE 0x0738
1034
1035#define RADEON_CP_CSQ_CNTL 0x0740
1036# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
1037# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
1038# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
1039# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
1040# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
1041# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
1042# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
1043
aadd4e17
AD		 1044#define R300_CP_RESYNC_ADDR 0x0778
1045#define R300_CP_RESYNC_DATA 0x077c
1046
1da177e4
LT		 1047#define RADEON_AIC_CNTL 0x01d0
1048# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
4e270e9b 1049# define RS400_MSI_REARM (1 << 3)
1da177e4
LT		 1050#define RADEON_AIC_STAT 0x01d4
1051#define RADEON_AIC_PT_BASE 0x01d8
1052#define RADEON_AIC_LO_ADDR 0x01dc
1053#define RADEON_AIC_HI_ADDR 0x01e0
1054#define RADEON_AIC_TLB_ADDR 0x01e4
1055#define RADEON_AIC_TLB_DATA 0x01e8
1056
1057/* CP command packets */
1058#define RADEON_CP_PACKET0 0x00000000
1059# define RADEON_ONE_REG_WR (1 << 15)
1060#define RADEON_CP_PACKET1 0x40000000
1061#define RADEON_CP_PACKET2 0x80000000
1062#define RADEON_CP_PACKET3 0xC0000000
414ed537
DA		 1063# define RADEON_CP_NOP 0x00001000
1064# define RADEON_CP_NEXT_CHAR 0x00001900
1065# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
1066# define RADEON_CP_SET_SCISSORS 0x00001E00
b5e89ed5 1067 /* GEN_INDX_PRIM is unsupported starting with R300 */
1da177e4
LT		 1068# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1069# define RADEON_WAIT_FOR_IDLE 0x00002600
1070# define RADEON_3D_DRAW_VBUF 0x00002800
1071# define RADEON_3D_DRAW_IMMD 0x00002900
1072# define RADEON_3D_DRAW_INDX 0x00002A00
414ed537 1073# define RADEON_CP_LOAD_PALETTE 0x00002C00
1da177e4
LT		 1074# define RADEON_3D_LOAD_VBPNTR 0x00002F00
1075# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1076# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1077# define RADEON_3D_CLEAR_ZMASK 0x00003200
414ed537
DA		 1078# define RADEON_CP_INDX_BUFFER 0x00003300
1079# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1080# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1081# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1da177e4 1082# define RADEON_3D_CLEAR_HIZ 0x00003700
414ed537 1083# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1da177e4
LT		 1084# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1085# define RADEON_CNTL_PAINT_MULTI 0x00009A00
1086# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1087# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1088
3ce0a23d
JG		 1089# define R600_IT_INDIRECT_BUFFER_END 0x00001700
1090# define R600_IT_SET_PREDICATION 0x00002000
1091# define R600_IT_REG_RMW 0x00002100
1092# define R600_IT_COND_EXEC 0x00002200
1093# define R600_IT_PRED_EXEC 0x00002300
1094# define R600_IT_START_3D_CMDBUF 0x00002400
1095# define R600_IT_DRAW_INDEX_2 0x00002700
1096# define R600_IT_CONTEXT_CONTROL 0x00002800
1097# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900
1098# define R600_IT_INDEX_TYPE 0x00002A00
1099# define R600_IT_DRAW_INDEX 0x00002B00
1100# define R600_IT_DRAW_INDEX_AUTO 0x00002D00
1101# define R600_IT_DRAW_INDEX_IMMD 0x00002E00
1102# define R600_IT_NUM_INSTANCES 0x00002F00
1103# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400
1104# define R600_IT_INDIRECT_BUFFER_MP 0x00003800
1105# define R600_IT_MEM_SEMAPHORE 0x00003900
1106# define R600_IT_MPEG_INDEX 0x00003A00
1107# define R600_IT_WAIT_REG_MEM 0x00003C00
1108# define R600_IT_MEM_WRITE 0x00003D00
1109# define R600_IT_INDIRECT_BUFFER 0x00003200
3ce0a23d
JG		 1110# define R600_IT_SURFACE_SYNC 0x00004300
1111# define R600_CB0_DEST_BASE_ENA (1 << 6)
1112# define R600_TC_ACTION_ENA (1 << 23)
1113# define R600_VC_ACTION_ENA (1 << 24)
1114# define R600_CB_ACTION_ENA (1 << 25)
1115# define R600_DB_ACTION_ENA (1 << 26)
1116# define R600_SH_ACTION_ENA (1 << 27)
1117# define R600_SMX_ACTION_ENA (1 << 28)
1118# define R600_IT_ME_INITIALIZE 0x00004400
befb73c2 1119# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
3ce0a23d
JG		 1120# define R600_IT_COND_WRITE 0x00004500
1121# define R600_IT_EVENT_WRITE 0x00004600
1122# define R600_IT_EVENT_WRITE_EOP 0x00004700
1123# define R600_IT_ONE_REG_WRITE 0x00005700
1124# define R600_IT_SET_CONFIG_REG 0x00006800
1125# define R600_SET_CONFIG_REG_OFFSET 0x00008000
1126# define R600_SET_CONFIG_REG_END 0x0000ac00
1127# define R600_IT_SET_CONTEXT_REG 0x00006900
1128# define R600_SET_CONTEXT_REG_OFFSET 0x00028000
1129# define R600_SET_CONTEXT_REG_END 0x00029000
1130# define R600_IT_SET_ALU_CONST 0x00006A00
1131# define R600_SET_ALU_CONST_OFFSET 0x00030000
1132# define R600_SET_ALU_CONST_END 0x00032000
1133# define R600_IT_SET_BOOL_CONST 0x00006B00
1134# define R600_SET_BOOL_CONST_OFFSET 0x0003e380
1135# define R600_SET_BOOL_CONST_END 0x00040000
1136# define R600_IT_SET_LOOP_CONST 0x00006C00
1137# define R600_SET_LOOP_CONST_OFFSET 0x0003e200
1138# define R600_SET_LOOP_CONST_END 0x0003e380
1139# define R600_IT_SET_RESOURCE 0x00006D00
1140# define R600_SET_RESOURCE_OFFSET 0x00038000
1141# define R600_SET_RESOURCE_END 0x0003c000
1142# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0
1143# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1
1144# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2
1145# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3
1146# define R600_IT_SET_SAMPLER 0x00006E00
1147# define R600_SET_SAMPLER_OFFSET 0x0003c000
1148# define R600_SET_SAMPLER_END 0x0003cff0
1149# define R600_IT_SET_CTL_CONST 0x00006F00
1150# define R600_SET_CTL_CONST_OFFSET 0x0003cff0
1151# define R600_SET_CTL_CONST_END 0x0003e200
1152# define R600_IT_SURFACE_BASE_UPDATE 0x00007300
befb73c2 1153
1da177e4
LT		 1154#define RADEON_CP_PACKET_MASK 0xC0000000
1155#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1156#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1157#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1158#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1159
1160#define RADEON_VTX_Z_PRESENT (1 << 31)
1161#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1162
1163#define RADEON_PRIM_TYPE_NONE (0 << 0)
1164#define RADEON_PRIM_TYPE_POINT (1 << 0)
1165#define RADEON_PRIM_TYPE_LINE (2 << 0)
1166#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1167#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1168#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1169#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1170#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1171#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1172#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1173#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1174#define RADEON_PRIM_TYPE_MASK 0xf
1175#define RADEON_PRIM_WALK_IND (1 << 4)
1176#define RADEON_PRIM_WALK_LIST (2 << 4)
1177#define RADEON_PRIM_WALK_RING (3 << 4)
1178#define RADEON_COLOR_ORDER_BGRA (0 << 6)
1179#define RADEON_COLOR_ORDER_RGBA (1 << 6)
1180#define RADEON_MAOS_ENABLE (1 << 7)
1181#define RADEON_VTX_FMT_R128_MODE (0 << 8)
1182#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1183#define RADEON_NUM_VERTICES_SHIFT 16
1184
1185#define RADEON_COLOR_FORMAT_CI8 2
1186#define RADEON_COLOR_FORMAT_ARGB1555 3
1187#define RADEON_COLOR_FORMAT_RGB565 4
1188#define RADEON_COLOR_FORMAT_ARGB8888 6
1189#define RADEON_COLOR_FORMAT_RGB332 7
1190#define RADEON_COLOR_FORMAT_RGB8 9
1191#define RADEON_COLOR_FORMAT_ARGB4444 15
1192
1193#define RADEON_TXFORMAT_I8 0
1194#define RADEON_TXFORMAT_AI88 1
1195#define RADEON_TXFORMAT_RGB332 2
1196#define RADEON_TXFORMAT_ARGB1555 3
1197#define RADEON_TXFORMAT_RGB565 4
1198#define RADEON_TXFORMAT_ARGB4444 5
1199#define RADEON_TXFORMAT_ARGB8888 6
1200#define RADEON_TXFORMAT_RGBA8888 7
1201#define RADEON_TXFORMAT_Y8 8
1202#define RADEON_TXFORMAT_VYUY422 10
1203#define RADEON_TXFORMAT_YVYU422 11
1204#define RADEON_TXFORMAT_DXT1 12
1205#define RADEON_TXFORMAT_DXT23 14
1206#define RADEON_TXFORMAT_DXT45 15
1207
1208#define R200_PP_TXCBLEND_0 0x2f00
1209#define R200_PP_TXCBLEND_1 0x2f10
1210#define R200_PP_TXCBLEND_2 0x2f20
1211#define R200_PP_TXCBLEND_3 0x2f30
1212#define R200_PP_TXCBLEND_4 0x2f40
1213#define R200_PP_TXCBLEND_5 0x2f50
1214#define R200_PP_TXCBLEND_6 0x2f60
1215#define R200_PP_TXCBLEND_7 0x2f70
b5e89ed5 1216#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1da177e4
LT		 1217#define R200_PP_TFACTOR_0 0x2ee0
1218#define R200_SE_VTX_FMT_0 0x2088
1219#define R200_SE_VAP_CNTL 0x2080
1220#define R200_SE_TCL_MATRIX_SEL_0 0x2230
b5e89ed5
DA		 1221#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1222#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1223#define R200_PP_TXFILTER_5 0x2ca0
1224#define R200_PP_TXFILTER_4 0x2c80
1225#define R200_PP_TXFILTER_3 0x2c60
1226#define R200_PP_TXFILTER_2 0x2c40
1227#define R200_PP_TXFILTER_1 0x2c20
1228#define R200_PP_TXFILTER_0 0x2c00
1da177e4
LT		 1229#define R200_PP_TXOFFSET_5 0x2d78
1230#define R200_PP_TXOFFSET_4 0x2d60
1231#define R200_PP_TXOFFSET_3 0x2d48
1232#define R200_PP_TXOFFSET_2 0x2d30
1233#define R200_PP_TXOFFSET_1 0x2d18
1234#define R200_PP_TXOFFSET_0 0x2d00
1235
1236#define R200_PP_CUBIC_FACES_0 0x2c18
1237#define R200_PP_CUBIC_FACES_1 0x2c38
1238#define R200_PP_CUBIC_FACES_2 0x2c58
1239#define R200_PP_CUBIC_FACES_3 0x2c78
1240#define R200_PP_CUBIC_FACES_4 0x2c98
1241#define R200_PP_CUBIC_FACES_5 0x2cb8
1242#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1243#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1244#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1245#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1246#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1247#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1248#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1249#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1250#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1251#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1252#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1253#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1254#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1255#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1256#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1257#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1258#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1259#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1260#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1261#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1262#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1263#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1264#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1265#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1266#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1267#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1268#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1269#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1270#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1271#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1272
1273#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1274#define R200_SE_VTE_CNTL 0x20b0
1275#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1276#define R200_PP_TAM_DEBUG3 0x2d9c
1277#define R200_PP_CNTL_X 0x2cc4
1278#define R200_SE_VAP_CNTL_STATUS 0x2140
1279#define R200_RE_SCISSOR_TL_0 0x1cd8
1280#define R200_RE_SCISSOR_TL_1 0x1ce0
1281#define R200_RE_SCISSOR_TL_2 0x1ce8
b5e89ed5 1282#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1da177e4
LT		 1283#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1284#define R200_SE_VTX_STATE_CNTL 0x2180
1285#define R200_RE_POINTSIZE 0x2648
1286#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1287
b5e89ed5 1288#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1da177e4
LT		 1289#define RADEON_PP_TEX_SIZE_1 0x1d0c
1290#define RADEON_PP_TEX_SIZE_2 0x1d14
1291
1292#define RADEON_PP_CUBIC_FACES_0 0x1d24
1293#define RADEON_PP_CUBIC_FACES_1 0x1d28
1294#define RADEON_PP_CUBIC_FACES_2 0x1d2c
1295#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1296#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1297#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1298
f2a2279f
DA		 1299#define RADEON_SE_TCL_STATE_FLUSH 0x2284
1300
1da177e4
LT		 1301#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1302#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1303#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1304#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1305#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1306#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1307#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1308#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1309#define R200_3D_DRAW_IMMD_2 0xC0003500
1310#define R200_SE_VTX_FMT_1 0x208c
b5e89ed5 1311#define R200_RE_CNTL 0x1c50
1da177e4
LT		 1312
1313#define R200_RB3D_BLENDCOLOR 0x3218
1314
1315#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1316
1317#define R200_PP_TRI_PERF 0x2cf8
1318
9d17601c 1319#define R200_PP_AFS_0 0x2f80
b5e89ed5 1320#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
9d17601c 1321
d6fece05
DA		 1322#define R200_VAP_PVS_CNTL_1 0x22D0
1323
0a3e67a4
JB		 1324#define RADEON_CRTC_CRNT_FRAME 0x0214
1325#define RADEON_CRTC2_CRNT_FRAME 0x0314
1326
c0beb2a7
DA		 1327#define R500_D1CRTC_STATUS 0x609c
1328#define R500_D2CRTC_STATUS 0x689c
1329#define R500_CRTC_V_BLANK (1<<0)
1330
1331#define R500_D1CRTC_FRAME_COUNT 0x60a4
1332#define R500_D2CRTC_FRAME_COUNT 0x68a4
1333
1334#define R500_D1MODE_V_COUNTER 0x6530
1335#define R500_D2MODE_V_COUNTER 0x6d30
1336
1337#define R500_D1MODE_VBLANK_STATUS 0x6534
1338#define R500_D2MODE_VBLANK_STATUS 0x6d34
1339#define R500_VBLANK_OCCURED (1<<0)
1340#define R500_VBLANK_ACK (1<<4)
1341#define R500_VBLANK_STAT (1<<12)
1342#define R500_VBLANK_INT (1<<16)
1343
1344#define R500_DxMODE_INT_MASK 0x6540
1345#define R500_D1MODE_INT_MASK (1<<0)
1346#define R500_D2MODE_INT_MASK (1<<8)
1347
1348#define R500_DISP_INTERRUPT_STATUS 0x7edc
1349#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1350#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1351
befb73c2
AD		 1352/* R6xx/R7xx registers */
1353#define R600_MC_VM_FB_LOCATION 0x2180
1354#define R600_MC_VM_AGP_TOP 0x2184
1355#define R600_MC_VM_AGP_BOT 0x2188
1356#define R600_MC_VM_AGP_BASE 0x218c
1357#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
1358#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
1359#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
1360
1361#define R700_MC_VM_FB_LOCATION 0x2024
1362#define R700_MC_VM_AGP_TOP 0x2028
1363#define R700_MC_VM_AGP_BOT 0x202c
1364#define R700_MC_VM_AGP_BASE 0x2030
1365#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
1366#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
1367#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
1368
1369#define R600_MCD_RD_A_CNTL 0x219c
1370#define R600_MCD_RD_B_CNTL 0x21a0
1371
1372#define R600_MCD_WR_A_CNTL 0x21a4
1373#define R600_MCD_WR_B_CNTL 0x21a8
1374
1375#define R600_MCD_RD_SYS_CNTL 0x2200
1376#define R600_MCD_WR_SYS_CNTL 0x2214
1377
1378#define R600_MCD_RD_GFX_CNTL 0x21fc
1379#define R600_MCD_RD_HDP_CNTL 0x2204
1380#define R600_MCD_RD_PDMA_CNTL 0x2208
1381#define R600_MCD_RD_SEM_CNTL 0x220c
1382#define R600_MCD_WR_GFX_CNTL 0x2210
1383#define R600_MCD_WR_HDP_CNTL 0x2218
1384#define R600_MCD_WR_PDMA_CNTL 0x221c
1385#define R600_MCD_WR_SEM_CNTL 0x2220
1386
1387# define R600_MCD_L1_TLB (1 << 0)
1388# define R600_MCD_L1_FRAG_PROC (1 << 1)
1389# define R600_MCD_L1_STRICT_ORDERING (1 << 2)
1390
1391# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
1392# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
1393# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
1394# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
1395# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
1396
1397# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
1398# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
1399
1400# define R600_MCD_SEMAPHORE_MODE (1 << 10)
1401# define R600_MCD_WAIT_L2_QUERY (1 << 11)
1402# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
1403# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
1404
1405#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
1406#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
1407#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
1408
1409#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
1410#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
1411#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
1412#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
1413
1414# define R700_ENABLE_L1_TLB (1 << 0)
1415# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
1416# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
1417# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
1418# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
1419# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
1420
1421#define R700_MC_ARB_RAMCFG 0x2760
1422# define R700_NOOFBANK_SHIFT 0
1423# define R700_NOOFBANK_MASK 0x3
1424# define R700_NOOFRANK_SHIFT 2
1425# define R700_NOOFRANK_MASK 0x1
1426# define R700_NOOFROWS_SHIFT 3
1427# define R700_NOOFROWS_MASK 0x7
1428# define R700_NOOFCOLS_SHIFT 6
1429# define R700_NOOFCOLS_MASK 0x3
1430# define R700_CHANSIZE_SHIFT 8
1431# define R700_CHANSIZE_MASK 0x1
1432# define R700_BURSTLENGTH_SHIFT 9
1433# define R700_BURSTLENGTH_MASK 0x1
1434#define R600_RAMCFG 0x2408
1435# define R600_NOOFBANK_SHIFT 0
1436# define R600_NOOFBANK_MASK 0x1
1437# define R600_NOOFRANK_SHIFT 1
1438# define R600_NOOFRANK_MASK 0x1
1439# define R600_NOOFROWS_SHIFT 2
1440# define R600_NOOFROWS_MASK 0x7
1441# define R600_NOOFCOLS_SHIFT 5
1442# define R600_NOOFCOLS_MASK 0x3
1443# define R600_CHANSIZE_SHIFT 7
1444# define R600_CHANSIZE_MASK 0x1
1445# define R600_BURSTLENGTH_SHIFT 8
1446# define R600_BURSTLENGTH_MASK 0x1
1447
1448#define R600_VM_L2_CNTL 0x1400
1449# define R600_VM_L2_CACHE_EN (1 << 0)
1450# define R600_VM_L2_FRAG_PROC (1 << 1)
1451# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
1452# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
1453# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
1454
1455#define R600_VM_L2_CNTL2 0x1404
1456# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
1457# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
1458#define R600_VM_L2_CNTL3 0x1408
1459# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
1460# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
1461# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
1462# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
1463# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
1464
1465#define R600_VM_L2_STATUS 0x140c
1466
1467#define R600_VM_CONTEXT0_CNTL 0x1410
1468# define R600_VM_ENABLE_CONTEXT (1 << 0)
1469# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
1470
1471#define R600_VM_CONTEXT0_CNTL2 0x1430
1472#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1473#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
1474#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
1475#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
1476#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
1477#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
1478
1479#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
1480#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
1481#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
1482
1483#define R600_HDP_HOST_PATH_CNTL 0x2c00
1484
1485#define R600_GRBM_CNTL 0x8000
1486# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
1487
1488#define R600_GRBM_STATUS 0x8010
1489# define R600_CMDFIFO_AVAIL_MASK 0x1f
1490# define R700_CMDFIFO_AVAIL_MASK 0xf
1491# define R600_GUI_ACTIVE (1 << 31)
1492#define R600_GRBM_STATUS2 0x8014
1493#define R600_GRBM_SOFT_RESET 0x8020
1494# define R600_SOFT_RESET_CP (1 << 0)
1495#define R600_WAIT_UNTIL 0x8040
1496
1497#define R600_CP_SEM_WAIT_TIMER 0x85bc
1498#define R600_CP_ME_CNTL 0x86d8
1499# define R600_CP_ME_HALT (1 << 28)
1500#define R600_CP_QUEUE_THRESHOLDS 0x8760
1501# define R600_ROQ_IB1_START(x) ((x) << 0)
1502# define R600_ROQ_IB2_START(x) ((x) << 8)
1503#define R600_CP_MEQ_THRESHOLDS 0x8764
1504# define R700_STQ_SPLIT(x) ((x) << 0)
1505# define R600_MEQ_END(x) ((x) << 16)
1506# define R600_ROQ_END(x) ((x) << 24)
1507#define R600_CP_PERFMON_CNTL 0x87fc
1508#define R600_CP_RB_BASE 0xc100
1509#define R600_CP_RB_CNTL 0xc104
1510# define R600_RB_BUFSZ(x) ((x) << 0)
1511# define R600_RB_BLKSZ(x) ((x) << 8)
1512# define R600_RB_NO_UPDATE (1 << 27)
1513# define R600_RB_RPTR_WR_ENA (1 << 31)
1514#define R600_CP_RB_RPTR_WR 0xc108
1515#define R600_CP_RB_RPTR_ADDR 0xc10c
1516#define R600_CP_RB_RPTR_ADDR_HI 0xc110
1517#define R600_CP_RB_WPTR 0xc114
1518#define R600_CP_RB_WPTR_ADDR 0xc118
1519#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
1520#define R600_CP_RB_RPTR 0x8700
1521#define R600_CP_RB_WPTR_DELAY 0x8704
1522#define R600_CP_PFP_UCODE_ADDR 0xc150
1523#define R600_CP_PFP_UCODE_DATA 0xc154
1524#define R600_CP_ME_RAM_RADDR 0xc158
1525#define R600_CP_ME_RAM_WADDR 0xc15c
1526#define R600_CP_ME_RAM_DATA 0xc160
1527#define R600_CP_DEBUG 0xc1fc
1528
1529#define R600_PA_CL_ENHANCE 0x8a14
1530# define R600_CLIP_VTX_REORDER_ENA (1 << 0)
1531# define R600_NUM_CLIP_SEQ(x) ((x) << 1)
1532#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
1533#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
1534#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
1535# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1536# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1537#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
1538#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
1539#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
1540#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
1541# define R600_S0_X(x) ((x) << 0)
1542# define R600_S0_Y(x) ((x) << 4)
1543# define R600_S1_X(x) ((x) << 8)
1544# define R600_S1_Y(x) ((x) << 12)
1545# define R600_S2_X(x) ((x) << 16)
1546# define R600_S2_Y(x) ((x) << 20)
1547# define R600_S3_X(x) ((x) << 24)
1548# define R600_S3_Y(x) ((x) << 28)
1549# define R600_S4_X(x) ((x) << 0)
1550# define R600_S4_Y(x) ((x) << 4)
1551# define R600_S5_X(x) ((x) << 8)
1552# define R600_S5_Y(x) ((x) << 12)
1553# define R600_S6_X(x) ((x) << 16)
1554# define R600_S6_Y(x) ((x) << 20)
1555# define R600_S7_X(x) ((x) << 24)
1556# define R600_S7_Y(x) ((x) << 28)
1557#define R600_PA_SC_FIFO_SIZE 0x8bd0
1558# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1559# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
1560# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
1561#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
1562# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1563# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
1564# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
1565#define R600_PA_SC_ENHANCE 0x8bf0
1566# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1567# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
1568#define R600_PA_SC_CLIPRECT_RULE 0x2820c
1569#define R700_PA_SC_EDGERULE 0x28230
1570#define R600_PA_SC_LINE_STIPPLE 0x28a0c
1571#define R600_PA_SC_MODE_CNTL 0x28a4c
1572#define R600_PA_SC_AA_CONFIG 0x28c04
1573
1574#define R600_SX_EXPORT_BUFFER_SIZES 0x900c
1575# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
1576# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
1577# define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
1578#define R600_SX_DEBUG_1 0x9054
1579# define R600_SMX_EVENT_RELEASE (1 << 0)
1580# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1581#define R700_SX_DEBUG_1 0x9058
1582# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1583#define R600_SX_MISC 0x28350
1584
1585#define R600_DB_DEBUG 0x9830
1586# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
1587#define R600_DB_WATERMARKS 0x9838
1588# define R600_DEPTH_FREE(x) ((x) << 0)
1589# define R600_DEPTH_FLUSH(x) ((x) << 5)
1590# define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
1591# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
1592#define R700_DB_DEBUG3 0x98b0
1593# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
1594#define RV700_DB_DEBUG4 0x9b8c
1595# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
1596
1597#define R600_VGT_CACHE_INVALIDATION 0x88c4
1598# define R600_CACHE_INVALIDATION(x) ((x) << 0)
1599# define R600_VC_ONLY 0
1600# define R600_TC_ONLY 1
1601# define R600_VC_AND_TC 2
1602# define R700_AUTO_INVLD_EN(x) ((x) << 6)
1603# define R700_NO_AUTO 0
1604# define R700_ES_AUTO 1
1605# define R700_GS_AUTO 2
1606# define R700_ES_AND_GS_AUTO 3
1607#define R600_VGT_GS_PER_ES 0x88c8
1608#define R600_VGT_ES_PER_GS 0x88cc
1609#define R600_VGT_GS_PER_VS 0x88e8
1610#define R600_VGT_GS_VERTEX_REUSE 0x88d4
1611#define R600_VGT_NUM_INSTANCES 0x8974
1612#define R600_VGT_STRMOUT_EN 0x28ab0
1613#define R600_VGT_EVENT_INITIATOR 0x28a90
1614# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
1615#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
1616# define R600_VTX_REUSE_DEPTH_MASK 0xff
1617#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
1618# define R600_DEALLOC_DIST_MASK 0x7f
1619
1620#define R600_CB_COLOR0_BASE 0x28040
1621#define R600_CB_COLOR1_BASE 0x28044
1622#define R600_CB_COLOR2_BASE 0x28048
1623#define R600_CB_COLOR3_BASE 0x2804c
1624#define R600_CB_COLOR4_BASE 0x28050
1625#define R600_CB_COLOR5_BASE 0x28054
1626#define R600_CB_COLOR6_BASE 0x28058
1627#define R600_CB_COLOR7_BASE 0x2805c
1628#define R600_CB_COLOR7_FRAG 0x280fc
1629
3ce0a23d
JG		 1630#define R600_CB_COLOR0_SIZE 0x28060
1631#define R600_CB_COLOR0_VIEW 0x28080
1632#define R600_CB_COLOR0_INFO 0x280a0
1633#define R600_CB_COLOR0_TILE 0x280c0
1634#define R600_CB_COLOR0_FRAG 0x280e0
1635#define R600_CB_COLOR0_MASK 0x28100
1636
1637#define AVIVO_D1MODE_VLINE_START_END 0x6538
1638#define AVIVO_D2MODE_VLINE_START_END 0x6d38
1639#define R600_CP_COHER_BASE 0x85f8
1640#define R600_DB_DEPTH_BASE 0x2800c
1641#define R600_SQ_PGM_START_FS 0x28894
1642#define R600_SQ_PGM_START_ES 0x28880
1643#define R600_SQ_PGM_START_VS 0x28858
1644#define R600_SQ_PGM_RESOURCES_VS 0x28868
1645#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0
1646#define R600_SQ_PGM_START_GS 0x2886c
1647#define R600_SQ_PGM_START_PS 0x28840
1648#define R600_SQ_PGM_RESOURCES_PS 0x28850
1649#define R600_SQ_PGM_EXPORTS_PS 0x28854
1650#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc
1651#define R600_VGT_DMA_BASE 0x287e8
1652#define R600_VGT_DMA_BASE_HI 0x287e4
1653#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10
1654#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14
1655#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18
1656#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c
1657#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44
1658#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48
1659#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c
1660#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50
1661#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8
1662#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8
1663#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8
1664#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08
1665#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc
1666#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec
1667#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc
1668#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c
1669
1670#define R600_VGT_PRIMITIVE_TYPE 0x8958
1671
1672#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030
1673#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240
1674#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204
1675
befb73c2
AD		 1676#define R600_TC_CNTL 0x9608
1677# define R600_TC_L2_SIZE(x) ((x) << 5)
1678# define R600_L2_DISABLE_LATE_HIT (1 << 9)
1679
1680#define R600_ARB_POP 0x2418
1681# define R600_ENABLE_TC128 (1 << 30)
1682#define R600_ARB_GDEC_RD_CNTL 0x246c
1683
1684#define R600_TA_CNTL_AUX 0x9508
1685# define R600_DISABLE_CUBE_WRAP (1 << 0)
1686# define R600_DISABLE_CUBE_ANISO (1 << 1)
1687# define R700_GETLOD_SELECT(x) ((x) << 2)
1688# define R600_SYNC_GRADIENT (1 << 24)
1689# define R600_SYNC_WALKER (1 << 25)
1690# define R600_SYNC_ALIGNER (1 << 26)
1691# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
1692# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
1693
1694#define R700_TCP_CNTL 0x9610
1695
1696#define R600_SMX_DC_CTL0 0xa020
1697# define R700_USE_HASH_FUNCTION (1 << 0)
1698# define R700_CACHE_DEPTH(x) ((x) << 1)
1699# define R700_FLUSH_ALL_ON_EVENT (1 << 10)
1700# define R700_STALL_ON_EVENT (1 << 11)
1701#define R700_SMX_EVENT_CTL 0xa02c
1702# define R700_ES_FLUSH_CTL(x) ((x) << 0)
1703# define R700_GS_FLUSH_CTL(x) ((x) << 3)
1704# define R700_ACK_FLUSH_CTL(x) ((x) << 6)
1705# define R700_SYNC_FLUSH_CTL (1 << 8)
1706
1707#define R600_SQ_CONFIG 0x8c00
1708# define R600_VC_ENABLE (1 << 0)
1709# define R600_EXPORT_SRC_C (1 << 1)
1710# define R600_DX9_CONSTS (1 << 2)
1711# define R600_ALU_INST_PREFER_VECTOR (1 << 3)
1712# define R600_DX10_CLAMP (1 << 4)
1713# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
1714# define R600_PS_PRIO(x) ((x) << 24)
1715# define R600_VS_PRIO(x) ((x) << 26)
1716# define R600_GS_PRIO(x) ((x) << 28)
1717# define R600_ES_PRIO(x) ((x) << 30)
1718#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
1719# define R600_NUM_PS_GPRS(x) ((x) << 0)
1720# define R600_NUM_VS_GPRS(x) ((x) << 16)
1721# define R700_DYN_GPR_ENABLE (1 << 27)
1722# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1723#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
1724# define R600_NUM_GS_GPRS(x) ((x) << 0)
1725# define R600_NUM_ES_GPRS(x) ((x) << 16)
1726#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
1727# define R600_NUM_PS_THREADS(x) ((x) << 0)
1728# define R600_NUM_VS_THREADS(x) ((x) << 8)
1729# define R600_NUM_GS_THREADS(x) ((x) << 16)
1730# define R600_NUM_ES_THREADS(x) ((x) << 24)
1731#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
1732# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1733# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1734#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
1735# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1736# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1737#define R600_SQ_MS_FIFO_SIZES 0x8cf0
1738# define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
1739# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
1740# define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
1741# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1742#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
1743# define R700_SIMDA_RING0(x) ((x) << 0)
1744# define R700_SIMDA_RING1(x) ((x) << 8)
1745# define R700_SIMDB_RING0(x) ((x) << 16)
1746# define R700_SIMDB_RING1(x) ((x) << 24)
1747#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
1748#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
1749#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
1750#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
1751#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
1752#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
1753#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
1754
1755#define R600_SPI_PS_IN_CONTROL_0 0x286cc
1756# define R600_NUM_INTERP(x) ((x) << 0)
1757# define R600_POSITION_ENA (1 << 8)
1758# define R600_POSITION_CENTROID (1 << 9)
1759# define R600_POSITION_ADDR(x) ((x) << 10)
1760# define R600_PARAM_GEN(x) ((x) << 15)
1761# define R600_PARAM_GEN_ADDR(x) ((x) << 19)
1762# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
1763# define R600_PERSP_GRADIENT_ENA (1 << 28)
1764# define R600_LINEAR_GRADIENT_ENA (1 << 29)
1765# define R600_POSITION_SAMPLE (1 << 30)
1766# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
1767#define R600_SPI_PS_IN_CONTROL_1 0x286d0
1768# define R600_GEN_INDEX_PIX (1 << 0)
1769# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
1770# define R600_FRONT_FACE_ENA (1 << 8)
1771# define R600_FRONT_FACE_CHAN(x) ((x) << 9)
1772# define R600_FRONT_FACE_ALL_BITS (1 << 11)
1773# define R600_FRONT_FACE_ADDR(x) ((x) << 12)
1774# define R600_FOG_ADDR(x) ((x) << 17)
1775# define R600_FIXED_PT_POSITION_ENA (1 << 24)
1776# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
1777# define R700_POSITION_ULC (1 << 30)
1778#define R600_SPI_INPUT_Z 0x286d8
1779
1780#define R600_SPI_CONFIG_CNTL 0x9100
1781# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
1782# define R600_DISABLE_INTERP_1 (1 << 5)
1783#define R600_SPI_CONFIG_CNTL_1 0x913c
1784# define R600_VTX_DONE_DELAY(x) ((x) << 0)
1785# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
1786
1787#define R600_GB_TILING_CONFIG 0x98f0
1788# define R600_PIPE_TILING(x) ((x) << 1)
1789# define R600_BANK_TILING(x) ((x) << 4)
1790# define R600_GROUP_SIZE(x) ((x) << 6)
1791# define R600_ROW_TILING(x) ((x) << 8)
1792# define R600_BANK_SWAPS(x) ((x) << 11)
1793# define R600_SAMPLE_SPLIT(x) ((x) << 14)
1794# define R600_BACKEND_MAP(x) ((x) << 16)
1795#define R600_DCP_TILING_CONFIG 0x6ca0
1796#define R600_HDP_TILING_CONFIG 0x2f3c
1797
1798#define R600_CC_RB_BACKEND_DISABLE 0x98f4
1799#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
1800# define R600_BACKEND_DISABLE(x) ((x) << 16)
1801
1802#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
1803#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
1804# define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
1805# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
1806# define R600_INACTIVE_SIMDS(x) ((x) << 16)
1807# define R600_INACTIVE_SIMDS_MASK (0xff << 16)
1808
1809#define R700_CGTS_SYS_TCC_DISABLE 0x3f90
1810#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
1811#define R700_CGTS_TCC_DISABLE 0x9148
1812#define R700_CGTS_USER_TCC_DISABLE 0x914c
1813
1da177e4
LT		 1814/* Constants */
1815#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1816
1817#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1818#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1819#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1820#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1821#define RADEON_LAST_DISPATCH 1
1822
befb73c2
AD		 1823#define R600_LAST_FRAME_REG R600_SCRATCH_REG0
1824#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
1825#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
1826#define R600_LAST_SWI_REG R600_SCRATCH_REG3
1827
1da177e4
LT		 1828#define RADEON_MAX_VB_AGE 0x7fffffff
1829#define RADEON_MAX_VB_VERTS (0xffff)
1830
1831#define RADEON_RING_HIGH_MARK 128
1832
ea98a92f
DA		 1833#define RADEON_PCIGART_TABLE_SIZE (32*1024)
1834
1da177e4 1835#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
befb73c2
AD		 1836#define RADEON_WRITE(reg, val) \
1837do { \
1838 if (reg < 0x10000) { \
1839 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1840 } else { \
1841 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1842 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1843 } \
1844} while (0)
1da177e4
LT		 1845#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1846#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1847
2735977b 1848#define RADEON_WRITE_PLL(addr, val) \
1da177e4 1849do { \
2735977b 1850 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1da177e4 1851 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
2735977b 1852 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1da177e4
LT		 1853} while (0)
1854
2735977b 1855#define RADEON_WRITE_PCIE(addr, val) \
ea98a92f 1856do { \
2735977b 1857 RADEON_WRITE8(RADEON_PCIE_INDEX, \
ea98a92f 1858 ((addr) & 0xff)); \
2735977b 1859 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
ea98a92f
DA		 1860} while (0)
1861
45e51905
AD		 1862#define R500_WRITE_MCIND(addr, val) \
1863do { \
1864 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1865 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1866 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1867} while (0)
1868
1869#define RS480_WRITE_MCIND(addr, val) \
1870do { \
1871 RADEON_WRITE(RS480_NB_MC_INDEX, \
1872 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1873 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1874 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1875} while (0)
3d5e2c13 1876
2735977b 1877#define RS690_WRITE_MCIND(addr, val) \
60f92683
MC		 1878do { \
1879 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1880 RADEON_WRITE(RS690_MC_DATA, val); \
1881 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1882} while (0)
1883
c1556f71
AD		 1884#define RS600_WRITE_MCIND(addr, val) \
1885do { \
1886 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \
1887 RADEON_WRITE(RS600_MC_DATA, val); \
1888} while (0)
1889
45e51905
AD		 1890#define IGP_WRITE_MCIND(addr, val) \
1891do { \
f0738e92
AD		 1892 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1893 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
45e51905 1894 RS690_WRITE_MCIND(addr, val); \
c1556f71
AD		 1895 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \
1896 RS600_WRITE_MCIND(addr, val); \
45e51905
AD		 1897 else \
1898 RS480_WRITE_MCIND(addr, val); \
1899} while (0)
1900
1da177e4
LT		 1901#define CP_PACKET0( reg, n ) \
1902 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1903#define CP_PACKET0_TABLE( reg, n ) \
1904 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1905#define CP_PACKET1( reg0, reg1 ) \
1906 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1907#define CP_PACKET2() \
1908 (RADEON_CP_PACKET2)
1909#define CP_PACKET3( pkt, n ) \
1910 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1911
1da177e4
LT		 1912/* ================================================================
1913 * Engine control helper macros
1914 */
1915
1916#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1917 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1918 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1919 RADEON_WAIT_HOST_IDLECLEAN) ); \
1920} while (0)
1921
1922#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1923 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1924 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1925 RADEON_WAIT_HOST_IDLECLEAN) ); \
1926} while (0)
1927
1928#define RADEON_WAIT_UNTIL_IDLE() do { \
1929 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1930 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1931 RADEON_WAIT_3D_IDLECLEAN | \
1932 RADEON_WAIT_HOST_IDLECLEAN) ); \
1933} while (0)
1934
1935#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1936 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1937 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1938} while (0)
1939
1940#define RADEON_FLUSH_CACHE() do { \
259434ac
AD		 1941 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1942 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1943 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1944 } else { \
1945 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
54f961a6 1946 OUT_RING(R300_RB3D_DC_FLUSH); \
259434ac 1947 } \
1da177e4
LT		 1948} while (0)
1949
1950#define RADEON_PURGE_CACHE() do { \
259434ac
AD		 1951 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1952 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
54f961a6 1953 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
259434ac
AD		 1954 } else { \
1955 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
54f961a6 1956 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
259434ac 1957 } \
1da177e4
LT		 1958} while (0)
1959
1960#define RADEON_FLUSH_ZCACHE() do { \
259434ac
AD		 1961 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1962 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1963 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1964 } else { \
1965 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1966 OUT_RING(R300_ZC_FLUSH); \
1967 } \
1da177e4
LT		 1968} while (0)
1969
1970#define RADEON_PURGE_ZCACHE() do { \
259434ac
AD		 1971 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1972 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
54f961a6 1973 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
259434ac 1974 } else { \
54f961a6
JG		 1975 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1976 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
259434ac 1977 } \
1da177e4
LT		 1978} while (0)
1979
1da177e4
LT		 1980/* ================================================================
1981 * Misc helper macros
1982 */
1983
b5e89ed5 1984/* Perfbox functionality only.
1da177e4
LT		 1985 */
1986#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1987do { \
1988 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1989 u32 head = GET_RING_HEAD( dev_priv ); \
1990 if (head == dev_priv->ring.tail) \
1991 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1992 } \
1993} while (0)
1994
1995#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
7c1c2871
DA		 1996do { \
1997 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
1998 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
1da177e4 1999 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
c05ce083
AD		 2000 int __ret; \
2001 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
2002 __ret = r600_do_cp_idle(dev_priv); \
2003 else \
2004 __ret = radeon_do_cp_idle(dev_priv); \
1da177e4
LT		 2005 if ( __ret ) return __ret; \
2006 sarea_priv->last_dispatch = 0; \
2007 radeon_freelist_reset( dev ); \
2008 } \
2009} while (0)
2010
2011#define RADEON_DISPATCH_AGE( age ) do { \
2012 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
2013 OUT_RING( age ); \
2014} while (0)
2015
2016#define RADEON_FRAME_AGE( age ) do { \
2017 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
2018 OUT_RING( age ); \
2019} while (0)
2020
2021#define RADEON_CLEAR_AGE( age ) do { \
2022 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
2023 OUT_RING( age ); \
2024} while (0)
2025
befb73c2
AD		 2026#define R600_DISPATCH_AGE(age) do { \
2027 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2028 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2029 OUT_RING(age); \
2030} while (0)
2031
2032#define R600_FRAME_AGE(age) do { \
2033 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2034 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2035 OUT_RING(age); \
2036} while (0)
2037
2038#define R600_CLEAR_AGE(age) do { \
2039 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2040 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2041 OUT_RING(age); \
2042} while (0)
2043
1da177e4
LT		 2044/* ================================================================
2045 * Ring control
2046 */
2047
2048#define RADEON_VERBOSE 0
2049
4247ca94 2050#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
1da177e4 2051
9863871b
DA		 2052#define RADEON_RING_ALIGN 16
2053
1da177e4
LT		 2054#define BEGIN_RING( n ) do { \
2055 if ( RADEON_VERBOSE ) { \
3e684eae 2056 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1da177e4 2057 } \
9863871b
DA		 2058 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \
2059 _align_nr += n; \
4247ca94 2060 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
1da177e4 2061 COMMIT_RING(); \
4247ca94 2062 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
1da177e4
LT		 2063 } \
2064 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
2065 ring = dev_priv->ring.start; \
2066 write = dev_priv->ring.tail; \
2067 mask = dev_priv->ring.tail_mask; \
2068} while (0)
2069
2070#define ADVANCE_RING() do { \
2071 if ( RADEON_VERBOSE ) { \
2072 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
2073 write, dev_priv->ring.tail ); \
2074 } \
2075 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
bc5f4523 2076 DRM_ERROR( \
1da177e4
LT		 2077 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
2078 ((dev_priv->ring.tail + _nr) & mask), \
4247ca94 2079 write, __LINE__); \
1da177e4
LT		 2080 } else \
2081 dev_priv->ring.tail = write; \
2082} while (0)
2083
4247ca94
DA		 2084extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
2085
1da177e4 2086#define COMMIT_RING() do { \
4247ca94
DA		 2087 radeon_commit_ring(dev_priv); \
2088 } while(0)
1da177e4
LT		 2089
2090#define OUT_RING( x ) do { \
2091 if ( RADEON_VERBOSE ) { \
2092 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
2093 (unsigned int)(x), write ); \
2094 } \
2095 ring[write++] = (x); \
2096 write &= mask; \
2097} while (0)
2098
2099#define OUT_RING_REG( reg, val ) do { \
2100 OUT_RING( CP_PACKET0( reg, 0 ) ); \
2101 OUT_RING( val ); \
2102} while (0)
2103
1da177e4
LT		 2104#define OUT_RING_TABLE( tab, sz ) do { \
2105 int _size = (sz); \
2106 int *_tab = (int *)(tab); \
2107 \
2108 if (write + _size > mask) { \
2109 int _i = (mask+1) - write; \
2110 _size -= _i; \
2111 while (_i > 0 ) { \
2112 *(int *)(ring + write) = *_tab++; \
2113 write++; \
2114 _i--; \
2115 } \
2116 write = 0; \
2117 _tab += _i; \
2118 } \
1da177e4
LT		 2119 while (_size > 0) { \
2120 *(ring + write) = *_tab++; \
2121 write++; \
2122 _size--; \
2123 } \
2124 write &= mask; \
2125} while (0)
2126
b5e89ed5 2127#endif /* __RADEON_DRV_H__ */
Clone of davem's net-next-2.6 tree