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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_display.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include <asm/div64.h>
32
33#include "drm_crtc_helper.h"
34#include "drm_edid.h"
35
36static int radeon_ddc_dump(struct drm_connector *connector);
37
38static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39{
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
d9fdaafb 45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
771fe6b9
JG		 46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69}
70
bcc1c2a1
AD		 71static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
72{
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77
d9fdaafb 78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
bcc1c2a1
AD		 79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
84
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88
677d0768
AD		 89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
bcc1c2a1 91
677d0768 92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
bcc1c2a1 93 for (i = 0; i < 256; i++) {
677d0768 94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
bcc1c2a1
AD		 95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
98 }
99}
100
771fe6b9
JG		 101static void legacy_crtc_load_lut(struct drm_crtc *crtc)
102{
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
106 int i;
107 uint32_t dac2_cntl;
108
109 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
110 if (radeon_crtc->crtc_id == 0)
111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
112 else
113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
114 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
115
116 WREG8(RADEON_PALETTE_INDEX, 0);
117 for (i = 0; i < 256; i++) {
118 WREG32(RADEON_PALETTE_30_DATA,
119 (radeon_crtc->lut_r[i] << 20) |
120 (radeon_crtc->lut_g[i] << 10) |
121 (radeon_crtc->lut_b[i] << 0));
122 }
123}
124
125void radeon_crtc_load_lut(struct drm_crtc *crtc)
126{
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
129
130 if (!crtc->enabled)
131 return;
132
bcc1c2a1
AD		 133 if (ASIC_IS_DCE4(rdev))
134 evergreen_crtc_load_lut(crtc);
135 else if (ASIC_IS_AVIVO(rdev))
771fe6b9
JG		 136 avivo_crtc_load_lut(crtc);
137 else
138 legacy_crtc_load_lut(crtc);
139}
140
b8c00ac5 141/** Sets the color ramps on behalf of fbcon */
771fe6b9
JG		 142void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
143 u16 blue, int regno)
144{
145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
146
771fe6b9
JG		 147 radeon_crtc->lut_r[regno] = red >> 6;
148 radeon_crtc->lut_g[regno] = green >> 6;
149 radeon_crtc->lut_b[regno] = blue >> 6;
150}
151
b8c00ac5
DA		 152/** Gets the color ramps on behalf of fbcon */
153void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
154 u16 *blue, int regno)
155{
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
157
158 *red = radeon_crtc->lut_r[regno] << 6;
159 *green = radeon_crtc->lut_g[regno] << 6;
160 *blue = radeon_crtc->lut_b[regno] << 6;
161}
162
771fe6b9 163static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 164 u16 *blue, uint32_t start, uint32_t size)
771fe6b9
JG		 165{
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
7203425a 167 int end = (start + size > 256) ? 256 : start + size, i;
771fe6b9 168
b8c00ac5 169 /* userspace palettes are always correct as is */
7203425a 170 for (i = start; i < end; i++) {
b8c00ac5
DA		 171 radeon_crtc->lut_r[i] = red[i] >> 6;
172 radeon_crtc->lut_g[i] = green[i] >> 6;
173 radeon_crtc->lut_b[i] = blue[i] >> 6;
771fe6b9 174 }
771fe6b9
JG		 175 radeon_crtc_load_lut(crtc);
176}
177
178static void radeon_crtc_destroy(struct drm_crtc *crtc)
179{
180 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
181
771fe6b9
JG		 182 drm_crtc_cleanup(crtc);
183 kfree(radeon_crtc);
184}
185
186static const struct drm_crtc_funcs radeon_crtc_funcs = {
187 .cursor_set = radeon_crtc_cursor_set,
188 .cursor_move = radeon_crtc_cursor_move,
189 .gamma_set = radeon_crtc_gamma_set,
190 .set_config = drm_crtc_helper_set_config,
191 .destroy = radeon_crtc_destroy,
192};
193
194static void radeon_crtc_init(struct drm_device *dev, int index)
195{
196 struct radeon_device *rdev = dev->dev_private;
197 struct radeon_crtc *radeon_crtc;
198 int i;
199
200 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
201 if (radeon_crtc == NULL)
202 return;
203
204 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
205
206 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
207 radeon_crtc->crtc_id = index;
c93bb85b 208 rdev->mode_info.crtcs[index] = radeon_crtc;
771fe6b9 209
785b93ef 210#if 0
771fe6b9
JG		 211 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
212 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
213 radeon_crtc->mode_set.num_connectors = 0;
785b93ef 214#endif
771fe6b9
JG		 215
216 for (i = 0; i < 256; i++) {
217 radeon_crtc->lut_r[i] = i << 2;
218 radeon_crtc->lut_g[i] = i << 2;
219 radeon_crtc->lut_b[i] = i << 2;
220 }
221
222 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
223 radeon_atombios_init_crtc(dev, radeon_crtc);
224 else
225 radeon_legacy_init_crtc(dev, radeon_crtc);
226}
227
228static const char *encoder_names[34] = {
229 "NONE",
230 "INTERNAL_LVDS",
231 "INTERNAL_TMDS1",
232 "INTERNAL_TMDS2",
233 "INTERNAL_DAC1",
234 "INTERNAL_DAC2",
235 "INTERNAL_SDVOA",
236 "INTERNAL_SDVOB",
237 "SI170B",
238 "CH7303",
239 "CH7301",
240 "INTERNAL_DVO1",
241 "EXTERNAL_SDVOA",
242 "EXTERNAL_SDVOB",
243 "TITFP513",
244 "INTERNAL_LVTM1",
245 "VT1623",
246 "HDMI_SI1930",
247 "HDMI_INTERNAL",
248 "INTERNAL_KLDSCP_TMDS1",
249 "INTERNAL_KLDSCP_DVO1",
250 "INTERNAL_KLDSCP_DAC1",
251 "INTERNAL_KLDSCP_DAC2",
252 "SI178",
253 "MVPU_FPGA",
254 "INTERNAL_DDI",
255 "VT1625",
256 "HDMI_SI1932",
257 "DP_AN9801",
258 "DP_DP501",
259 "INTERNAL_UNIPHY",
260 "INTERNAL_KLDSCP_LVTMA",
261 "INTERNAL_UNIPHY1",
262 "INTERNAL_UNIPHY2",
263};
264
196c58d2 265static const char *connector_names[15] = {
771fe6b9
JG		 266 "Unknown",
267 "VGA",
268 "DVI-I",
269 "DVI-D",
270 "DVI-A",
271 "Composite",
272 "S-video",
273 "LVDS",
274 "Component",
275 "DIN",
276 "DisplayPort",
277 "HDMI-A",
278 "HDMI-B",
196c58d2
AD		 279 "TV",
280 "eDP",
771fe6b9
JG		 281};
282
cbd4623d 283static const char *hpd_names[6] = {
eed45b30
AD		 284 "HPD1",
285 "HPD2",
286 "HPD3",
287 "HPD4",
288 "HPD5",
289 "HPD6",
290};
291
771fe6b9
JG		 292static void radeon_print_display_setup(struct drm_device *dev)
293{
294 struct drm_connector *connector;
295 struct radeon_connector *radeon_connector;
296 struct drm_encoder *encoder;
297 struct radeon_encoder *radeon_encoder;
298 uint32_t devices;
299 int i = 0;
300
301 DRM_INFO("Radeon Display Connectors\n");
302 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
303 radeon_connector = to_radeon_connector(connector);
304 DRM_INFO("Connector %d:\n", i);
305 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
eed45b30
AD		 306 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
307 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
4b9d2a21 308 if (radeon_connector->ddc_bus) {
771fe6b9
JG		 309 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
310 radeon_connector->ddc_bus->rec.mask_clk_reg,
311 radeon_connector->ddc_bus->rec.mask_data_reg,
312 radeon_connector->ddc_bus->rec.a_clk_reg,
313 radeon_connector->ddc_bus->rec.a_data_reg,
9b9fe724
AD		 314 radeon_connector->ddc_bus->rec.en_clk_reg,
315 radeon_connector->ddc_bus->rec.en_data_reg,
316 radeon_connector->ddc_bus->rec.y_clk_reg,
317 radeon_connector->ddc_bus->rec.y_data_reg);
26b5bc98
AD		 318 if (radeon_connector->router_bus)
319 DRM_INFO(" DDC Router 0x%x/0x%x\n",
320 radeon_connector->router.mux_control_pin,
321 radeon_connector->router.mux_state);
4b9d2a21
DA		 322 } else {
323 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
324 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
325 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
326 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
327 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
328 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
329 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
330 }
771fe6b9
JG		 331 DRM_INFO(" Encoders:\n");
332 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
333 radeon_encoder = to_radeon_encoder(encoder);
334 devices = radeon_encoder->devices & radeon_connector->devices;
335 if (devices) {
336 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
337 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
338 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
339 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
340 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
341 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
342 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
343 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
344 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
345 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
346 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
347 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
348 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
349 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
350 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
351 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
73758a5d
AD		 352 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
353 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
771fe6b9
JG		 354 if (devices & ATOM_DEVICE_TV1_SUPPORT)
355 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
356 if (devices & ATOM_DEVICE_CV_SUPPORT)
357 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
358 }
359 }
360 i++;
361 }
362}
363
4ce001ab 364static bool radeon_setup_enc_conn(struct drm_device *dev)
771fe6b9
JG		 365{
366 struct radeon_device *rdev = dev->dev_private;
367 struct drm_connector *drm_connector;
368 bool ret = false;
369
370 if (rdev->bios) {
371 if (rdev->is_atom_bios) {
a084e6ee
AD		 372 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
373 if (ret == false)
771fe6b9 374 ret = radeon_get_atom_connector_info_from_object_table(dev);
b9597a1c 375 } else {
771fe6b9 376 ret = radeon_get_legacy_connector_info_from_bios(dev);
b9597a1c
AD		 377 if (ret == false)
378 ret = radeon_get_legacy_connector_info_from_table(dev);
379 }
771fe6b9
JG		 380 } else {
381 if (!ASIC_IS_AVIVO(rdev))
382 ret = radeon_get_legacy_connector_info_from_table(dev);
383 }
384 if (ret) {
1f3b6a45 385 radeon_setup_encoder_clones(dev);
771fe6b9
JG		 386 radeon_print_display_setup(dev);
387 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
388 radeon_ddc_dump(drm_connector);
389 }
390
391 return ret;
392}
393
394int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
395{
3c537889
AD		 396 struct drm_device *dev = radeon_connector->base.dev;
397 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 398 int ret = 0;
399
26b5bc98
AD		 400 /* on hw with routers, select right port */
401 if (radeon_connector->router.valid)
402 radeon_router_select_port(radeon_connector);
403
196c58d2
AD		 404 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
405 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
746c1aa4 406 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
7a15cbd4
DA		 407 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
408 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
9fa05c98 409 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
746c1aa4 410 }
771fe6b9
JG		 411 if (!radeon_connector->ddc_bus)
412 return -1;
4ce001ab 413 if (!radeon_connector->edid) {
0294cf4f 414 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
0294cf4f 415 }
3c537889
AD		 416 /* some servers provide a hardcoded edid in rom for KVMs */
417 if (!radeon_connector->edid)
418 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
0294cf4f
AD		 419 if (radeon_connector->edid) {
420 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
421 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
771fe6b9
JG		 422 return ret;
423 }
424 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
42dea5dd 425 return 0;
771fe6b9
JG		 426}
427
428static int radeon_ddc_dump(struct drm_connector *connector)
429{
430 struct edid *edid;
431 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
432 int ret = 0;
433
26b5bc98
AD		 434 /* on hw with routers, select right port */
435 if (radeon_connector->router.valid)
436 radeon_router_select_port(radeon_connector);
437
771fe6b9
JG		 438 if (!radeon_connector->ddc_bus)
439 return -1;
771fe6b9 440 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
771fe6b9
JG		 441 if (edid) {
442 kfree(edid);
443 }
444 return ret;
445}
446
447static inline uint32_t radeon_div(uint64_t n, uint32_t d)
448{
449 uint64_t mod;
450
451 n += d / 2;
452
453 mod = do_div(n, d);
454 return n;
455}
456
7c27f87d
AD		 457static void radeon_compute_pll_legacy(struct radeon_pll *pll,
458 uint64_t freq,
459 uint32_t *dot_clock_p,
460 uint32_t *fb_div_p,
461 uint32_t *frac_fb_div_p,
462 uint32_t *ref_div_p,
463 uint32_t *post_div_p)
771fe6b9
JG		 464{
465 uint32_t min_ref_div = pll->min_ref_div;
466 uint32_t max_ref_div = pll->max_ref_div;
fc10332b
AD		 467 uint32_t min_post_div = pll->min_post_div;
468 uint32_t max_post_div = pll->max_post_div;
771fe6b9
JG		 469 uint32_t min_fractional_feed_div = 0;
470 uint32_t max_fractional_feed_div = 0;
471 uint32_t best_vco = pll->best_vco;
472 uint32_t best_post_div = 1;
473 uint32_t best_ref_div = 1;
474 uint32_t best_feedback_div = 1;
475 uint32_t best_frac_feedback_div = 0;
476 uint32_t best_freq = -1;
477 uint32_t best_error = 0xffffffff;
478 uint32_t best_vco_diff = 1;
479 uint32_t post_div;
86cb2bbf 480 u32 pll_out_min, pll_out_max;
771fe6b9 481
d9fdaafb 482 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
771fe6b9
JG		 483 freq = freq * 1000;
484
86cb2bbf
AD		 485 if (pll->flags & RADEON_PLL_IS_LCD) {
486 pll_out_min = pll->lcd_pll_out_min;
487 pll_out_max = pll->lcd_pll_out_max;
488 } else {
489 pll_out_min = pll->pll_out_min;
490 pll_out_max = pll->pll_out_max;
491 }
492
fc10332b 493 if (pll->flags & RADEON_PLL_USE_REF_DIV)
771fe6b9
JG		 494 min_ref_div = max_ref_div = pll->reference_div;
495 else {
496 while (min_ref_div < max_ref_div-1) {
497 uint32_t mid = (min_ref_div + max_ref_div) / 2;
498 uint32_t pll_in = pll->reference_freq / mid;
499 if (pll_in < pll->pll_in_min)
500 max_ref_div = mid;
501 else if (pll_in > pll->pll_in_max)
502 min_ref_div = mid;
503 else
504 break;
505 }
506 }
507
fc10332b
AD		 508 if (pll->flags & RADEON_PLL_USE_POST_DIV)
509 min_post_div = max_post_div = pll->post_div;
510
511 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
771fe6b9
JG		 512 min_fractional_feed_div = pll->min_frac_feedback_div;
513 max_fractional_feed_div = pll->max_frac_feedback_div;
514 }
515
fc10332b 516 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
771fe6b9
JG		 517 uint32_t ref_div;
518
fc10332b 519 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
771fe6b9
JG		 520 continue;
521
522 /* legacy radeons only have a few post_divs */
fc10332b 523 if (pll->flags & RADEON_PLL_LEGACY) {
771fe6b9
JG		 524 if ((post_div == 5) ||
525 (post_div == 7) ||
526 (post_div == 9) ||
527 (post_div == 10) ||
528 (post_div == 11) ||
529 (post_div == 13) ||
530 (post_div == 14) ||
531 (post_div == 15))
532 continue;
533 }
534
535 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
536 uint32_t feedback_div, current_freq = 0, error, vco_diff;
537 uint32_t pll_in = pll->reference_freq / ref_div;
538 uint32_t min_feed_div = pll->min_feedback_div;
539 uint32_t max_feed_div = pll->max_feedback_div + 1;
540
541 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
542 continue;
543
544 while (min_feed_div < max_feed_div) {
545 uint32_t vco;
546 uint32_t min_frac_feed_div = min_fractional_feed_div;
547 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
548 uint32_t frac_feedback_div;
549 uint64_t tmp;
550
551 feedback_div = (min_feed_div + max_feed_div) / 2;
552
553 tmp = (uint64_t)pll->reference_freq * feedback_div;
554 vco = radeon_div(tmp, ref_div);
555
86cb2bbf 556 if (vco < pll_out_min) {
771fe6b9
JG		 557 min_feed_div = feedback_div + 1;
558 continue;
86cb2bbf 559 } else if (vco > pll_out_max) {
771fe6b9
JG		 560 max_feed_div = feedback_div;
561 continue;
562 }
563
564 while (min_frac_feed_div < max_frac_feed_div) {
565 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
566 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
567 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
568 current_freq = radeon_div(tmp, ref_div * post_div);
569
fc10332b 570 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
167ffc44
DC		 571 if (freq < current_freq)
572 error = 0xffffffff;
573 else
574 error = freq - current_freq;
d0e275a9
AD		 575 } else
576 error = abs(current_freq - freq);
771fe6b9
JG		 577 vco_diff = abs(vco - best_vco);
578
579 if ((best_vco == 0 && error < best_error) ||
580 (best_vco != 0 &&
167ffc44 581 ((best_error > 100 && error < best_error - 100) ||
771fe6b9
JG		 582 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
583 best_post_div = post_div;
584 best_ref_div = ref_div;
585 best_feedback_div = feedback_div;
586 best_frac_feedback_div = frac_feedback_div;
587 best_freq = current_freq;
588 best_error = error;
589 best_vco_diff = vco_diff;
590 } else if (current_freq == freq) {
591 if (best_freq == -1) {
592 best_post_div = post_div;
593 best_ref_div = ref_div;
594 best_feedback_div = feedback_div;
595 best_frac_feedback_div = frac_feedback_div;
596 best_freq = current_freq;
597 best_error = error;
598 best_vco_diff = vco_diff;
fc10332b
AD		 599 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
600 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
601 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
602 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
603 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
604 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
771fe6b9
JG		 605 best_post_div = post_div;
606 best_ref_div = ref_div;
607 best_feedback_div = feedback_div;
608 best_frac_feedback_div = frac_feedback_div;
609 best_freq = current_freq;
610 best_error = error;
611 best_vco_diff = vco_diff;
612 }
613 }
614 if (current_freq < freq)
615 min_frac_feed_div = frac_feedback_div + 1;
616 else
617 max_frac_feed_div = frac_feedback_div;
618 }
619 if (current_freq < freq)
620 min_feed_div = feedback_div + 1;
621 else
622 max_feed_div = feedback_div;
623 }
624 }
625 }
626
627 *dot_clock_p = best_freq / 10000;
628 *fb_div_p = best_feedback_div;
629 *frac_fb_div_p = best_frac_feedback_div;
630 *ref_div_p = best_ref_div;
631 *post_div_p = best_post_div;
632}
633
383be5d1
AD		 634static bool
635calc_fb_div(struct radeon_pll *pll,
636 uint32_t freq,
637 uint32_t post_div,
638 uint32_t ref_div,
639 uint32_t *fb_div,
640 uint32_t *fb_div_frac)
b27b6375 641{
383be5d1
AD		 642 fixed20_12 feedback_divider, a, b;
643 u32 vco_freq;
b27b6375 644
383be5d1
AD		 645 vco_freq = freq * post_div;
646 /* feedback_divider = vco_freq * ref_div / pll->reference_freq; */
68adac5e
BS		 647 a.full = dfixed_const(pll->reference_freq);
648 feedback_divider.full = dfixed_const(vco_freq);
649 feedback_divider.full = dfixed_div(feedback_divider, a);
650 a.full = dfixed_const(ref_div);
651 feedback_divider.full = dfixed_mul(feedback_divider, a);
b27b6375 652
383be5d1
AD		 653 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
654 /* feedback_divider = floor((feedback_divider * 10.0) + 0.5) * 0.1; */
68adac5e
BS		 655 a.full = dfixed_const(10);
656 feedback_divider.full = dfixed_mul(feedback_divider, a);
657 feedback_divider.full += dfixed_const_half(0);
658 feedback_divider.full = dfixed_floor(feedback_divider);
659 feedback_divider.full = dfixed_div(feedback_divider, a);
383be5d1
AD		 660
661 /* *fb_div = floor(feedback_divider); */
68adac5e
BS		 662 a.full = dfixed_floor(feedback_divider);
663 *fb_div = dfixed_trunc(a);
383be5d1 664 /* *fb_div_frac = fmod(feedback_divider, 1.0) * 10.0; */
68adac5e
BS		 665 a.full = dfixed_const(10);
666 b.full = dfixed_mul(feedback_divider, a);
383be5d1 667
68adac5e
BS		 668 feedback_divider.full = dfixed_floor(feedback_divider);
669 feedback_divider.full = dfixed_mul(feedback_divider, a);
383be5d1 670 feedback_divider.full = b.full - feedback_divider.full;
68adac5e 671 *fb_div_frac = dfixed_trunc(feedback_divider);
383be5d1
AD		 672 } else {
673 /* *fb_div = floor(feedback_divider + 0.5); */
68adac5e
BS		 674 feedback_divider.full += dfixed_const_half(0);
675 feedback_divider.full = dfixed_floor(feedback_divider);
b27b6375 676
68adac5e 677 *fb_div = dfixed_trunc(feedback_divider);
383be5d1
AD		 678 *fb_div_frac = 0;
679 }
b27b6375 680
383be5d1
AD		 681 if (((*fb_div) < pll->min_feedback_div) || ((*fb_div) > pll->max_feedback_div))
682 return false;
683 else
684 return true;
685}
b27b6375 686
383be5d1
AD		 687static bool
688calc_fb_ref_div(struct radeon_pll *pll,
689 uint32_t freq,
690 uint32_t post_div,
691 uint32_t *fb_div,
692 uint32_t *fb_div_frac,
693 uint32_t *ref_div)
694{
695 fixed20_12 ffreq, max_error, error, pll_out, a;
696 u32 vco;
86cb2bbf
AD		 697 u32 pll_out_min, pll_out_max;
698
699 if (pll->flags & RADEON_PLL_IS_LCD) {
700 pll_out_min = pll->lcd_pll_out_min;
701 pll_out_max = pll->lcd_pll_out_max;
702 } else {
703 pll_out_min = pll->pll_out_min;
704 pll_out_max = pll->pll_out_max;
705 }
b27b6375 706
68adac5e 707 ffreq.full = dfixed_const(freq);
383be5d1 708 /* max_error = ffreq * 0.0025; */
68adac5e
BS		 709 a.full = dfixed_const(400);
710 max_error.full = dfixed_div(ffreq, a);
b27b6375 711
383be5d1
AD		 712 for ((*ref_div) = pll->min_ref_div; (*ref_div) < pll->max_ref_div; ++(*ref_div)) {
713 if (calc_fb_div(pll, freq, post_div, (*ref_div), fb_div, fb_div_frac)) {
714 vco = pll->reference_freq * (((*fb_div) * 10) + (*fb_div_frac));
715 vco = vco / ((*ref_div) * 10);
b27b6375 716
86cb2bbf 717 if ((vco < pll_out_min) || (vco > pll_out_max))
383be5d1 718 continue;
b27b6375 719
383be5d1 720 /* pll_out = vco / post_div; */
68adac5e
BS		 721 a.full = dfixed_const(post_div);
722 pll_out.full = dfixed_const(vco);
723 pll_out.full = dfixed_div(pll_out, a);
b27b6375 724
383be5d1
AD		 725 if (pll_out.full >= ffreq.full) {
726 error.full = pll_out.full - ffreq.full;
727 if (error.full <= max_error.full)
728 return true;
729 }
730 }
731 }
732 return false;
733}
b27b6375 734
383be5d1
AD		 735static void radeon_compute_pll_new(struct radeon_pll *pll,
736 uint64_t freq,
737 uint32_t *dot_clock_p,
738 uint32_t *fb_div_p,
739 uint32_t *frac_fb_div_p,
740 uint32_t *ref_div_p,
741 uint32_t *post_div_p)
742{
743 u32 fb_div = 0, fb_div_frac = 0, post_div = 0, ref_div = 0;
744 u32 best_freq = 0, vco_frequency;
86cb2bbf
AD		 745 u32 pll_out_min, pll_out_max;
746
747 if (pll->flags & RADEON_PLL_IS_LCD) {
748 pll_out_min = pll->lcd_pll_out_min;
749 pll_out_max = pll->lcd_pll_out_max;
750 } else {
751 pll_out_min = pll->pll_out_min;
752 pll_out_max = pll->pll_out_max;
753 }
b27b6375 754
383be5d1
AD		 755 /* freq = freq / 10; */
756 do_div(freq, 10);
b27b6375 757
383be5d1
AD		 758 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
759 post_div = pll->post_div;
760 if ((post_div < pll->min_post_div) || (post_div > pll->max_post_div))
761 goto done;
762
763 vco_frequency = freq * post_div;
86cb2bbf 764 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
383be5d1
AD		 765 goto done;
766
767 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
768 ref_div = pll->reference_div;
769 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
770 goto done;
771 if (!calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
772 goto done;
773 }
774 } else {
775 for (post_div = pll->max_post_div; post_div >= pll->min_post_div; --post_div) {
776 if (pll->flags & RADEON_PLL_LEGACY) {
777 if ((post_div == 5) ||
778 (post_div == 7) ||
779 (post_div == 9) ||
780 (post_div == 10) ||
781 (post_div == 11))
782 continue;
783 }
784
785 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
786 continue;
787
788 vco_frequency = freq * post_div;
86cb2bbf 789 if ((vco_frequency < pll_out_min) || (vco_frequency > pll_out_max))
383be5d1
AD		 790 continue;
791 if (pll->flags & RADEON_PLL_USE_REF_DIV) {
792 ref_div = pll->reference_div;
793 if ((ref_div < pll->min_ref_div) || (ref_div > pll->max_ref_div))
794 goto done;
795 if (calc_fb_div(pll, freq, post_div, ref_div, &fb_div, &fb_div_frac))
796 break;
797 } else {
798 if (calc_fb_ref_div(pll, freq, post_div, &fb_div, &fb_div_frac, &ref_div))
799 break;
800 }
b27b6375
AD		 801 }
802 }
803
383be5d1
AD		 804 best_freq = pll->reference_freq * 10 * fb_div;
805 best_freq += pll->reference_freq * fb_div_frac;
806 best_freq = best_freq / (ref_div * post_div);
b27b6375 807
383be5d1
AD		 808done:
809 if (best_freq == 0)
810 DRM_ERROR("Couldn't find valid PLL dividers\n");
b27b6375 811
383be5d1
AD		 812 *dot_clock_p = best_freq / 10;
813 *fb_div_p = fb_div;
814 *frac_fb_div_p = fb_div_frac;
815 *ref_div_p = ref_div;
816 *post_div_p = post_div;
b27b6375 817
d9fdaafb 818 DRM_DEBUG_KMS("%u %d.%d, %d, %d\n", *dot_clock_p, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
b27b6375
AD		 819}
820
7c27f87d
AD		 821void radeon_compute_pll(struct radeon_pll *pll,
822 uint64_t freq,
823 uint32_t *dot_clock_p,
824 uint32_t *fb_div_p,
825 uint32_t *frac_fb_div_p,
826 uint32_t *ref_div_p,
827 uint32_t *post_div_p)
828{
829 switch (pll->algo) {
383be5d1
AD		 830 case PLL_ALGO_NEW:
831 radeon_compute_pll_new(pll, freq, dot_clock_p, fb_div_p,
832 frac_fb_div_p, ref_div_p, post_div_p);
7c27f87d
AD		 833 break;
834 case PLL_ALGO_LEGACY:
835 default:
836 radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
837 frac_fb_div_p, ref_div_p, post_div_p);
838 break;
839 }
b27b6375
AD		 840}
841
771fe6b9
JG		 842static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
843{
844 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
771fe6b9 845
29d08b3e 846 if (radeon_fb->obj) {
bc9025bd 847 drm_gem_object_unreference_unlocked(radeon_fb->obj);
29d08b3e 848 }
771fe6b9
JG		 849 drm_framebuffer_cleanup(fb);
850 kfree(radeon_fb);
851}
852
853static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
854 struct drm_file *file_priv,
855 unsigned int *handle)
856{
857 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
858
859 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
860}
861
862static const struct drm_framebuffer_funcs radeon_fb_funcs = {
863 .destroy = radeon_user_framebuffer_destroy,
864 .create_handle = radeon_user_framebuffer_create_handle,
865};
866
38651674
DA		 867void
868radeon_framebuffer_init(struct drm_device *dev,
869 struct radeon_framebuffer *rfb,
870 struct drm_mode_fb_cmd *mode_cmd,
871 struct drm_gem_object *obj)
771fe6b9 872{
38651674
DA		 873 rfb->obj = obj;
874 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
875 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
771fe6b9
JG		 876}
877
878static struct drm_framebuffer *
879radeon_user_framebuffer_create(struct drm_device *dev,
880 struct drm_file *file_priv,
881 struct drm_mode_fb_cmd *mode_cmd)
882{
883 struct drm_gem_object *obj;
38651674 884 struct radeon_framebuffer *radeon_fb;
771fe6b9
JG		 885
886 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
7e71c9e2
JG		 887 if (obj == NULL) {
888 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
889 "can't create framebuffer\n", mode_cmd->handle);
cce13ff7 890 return ERR_PTR(-ENOENT);
7e71c9e2 891 }
38651674
DA		 892
893 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
cce13ff7
CW		 894 if (radeon_fb == NULL)
895 return ERR_PTR(-ENOMEM);
38651674
DA		 896
897 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
898
899 return &radeon_fb->base;
771fe6b9
JG		 900}
901
eb1f8e4f
DA		 902static void radeon_output_poll_changed(struct drm_device *dev)
903{
904 struct radeon_device *rdev = dev->dev_private;
905 radeon_fb_output_poll_changed(rdev);
906}
907
771fe6b9
JG		 908static const struct drm_mode_config_funcs radeon_mode_funcs = {
909 .fb_create = radeon_user_framebuffer_create,
eb1f8e4f 910 .output_poll_changed = radeon_output_poll_changed
771fe6b9
JG		 911};
912
445282db
DA		 913struct drm_prop_enum_list {
914 int type;
915 char *name;
916};
917
918static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
919{ { 0, "driver" },
920 { 1, "bios" },
921};
922
923static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
924{ { TV_STD_NTSC, "ntsc" },
925 { TV_STD_PAL, "pal" },
926 { TV_STD_PAL_M, "pal-m" },
927 { TV_STD_PAL_60, "pal-60" },
928 { TV_STD_NTSC_J, "ntsc-j" },
929 { TV_STD_SCART_PAL, "scart-pal" },
930 { TV_STD_PAL_CN, "pal-cn" },
931 { TV_STD_SECAM, "secam" },
932};
933
5b1714d3
AD		 934static struct drm_prop_enum_list radeon_underscan_enum_list[] =
935{ { UNDERSCAN_OFF, "off" },
936 { UNDERSCAN_ON, "on" },
937 { UNDERSCAN_AUTO, "auto" },
938};
939
d79766fa 940static int radeon_modeset_create_props(struct radeon_device *rdev)
445282db
DA		 941{
942 int i, sz;
943
944 if (rdev->is_atom_bios) {
945 rdev->mode_info.coherent_mode_property =
946 drm_property_create(rdev->ddev,
947 DRM_MODE_PROP_RANGE,
948 "coherent", 2);
949 if (!rdev->mode_info.coherent_mode_property)
950 return -ENOMEM;
951
952 rdev->mode_info.coherent_mode_property->values[0] = 0;
390d0bbe 953 rdev->mode_info.coherent_mode_property->values[1] = 1;
445282db
DA		 954 }
955
956 if (!ASIC_IS_AVIVO(rdev)) {
957 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
958 rdev->mode_info.tmds_pll_property =
959 drm_property_create(rdev->ddev,
960 DRM_MODE_PROP_ENUM,
961 "tmds_pll", sz);
962 for (i = 0; i < sz; i++) {
963 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
964 i,
965 radeon_tmds_pll_enum_list[i].type,
966 radeon_tmds_pll_enum_list[i].name);
967 }
968 }
969
970 rdev->mode_info.load_detect_property =
971 drm_property_create(rdev->ddev,
972 DRM_MODE_PROP_RANGE,
973 "load detection", 2);
974 if (!rdev->mode_info.load_detect_property)
975 return -ENOMEM;
976 rdev->mode_info.load_detect_property->values[0] = 0;
390d0bbe 977 rdev->mode_info.load_detect_property->values[1] = 1;
445282db
DA		 978
979 drm_mode_create_scaling_mode_property(rdev->ddev);
980
981 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
982 rdev->mode_info.tv_std_property =
983 drm_property_create(rdev->ddev,
984 DRM_MODE_PROP_ENUM,
985 "tv standard", sz);
986 for (i = 0; i < sz; i++) {
987 drm_property_add_enum(rdev->mode_info.tv_std_property,
988 i,
989 radeon_tv_std_enum_list[i].type,
990 radeon_tv_std_enum_list[i].name);
991 }
992
5b1714d3
AD		 993 sz = ARRAY_SIZE(radeon_underscan_enum_list);
994 rdev->mode_info.underscan_property =
995 drm_property_create(rdev->ddev,
996 DRM_MODE_PROP_ENUM,
997 "underscan", sz);
998 for (i = 0; i < sz; i++) {
999 drm_property_add_enum(rdev->mode_info.underscan_property,
1000 i,
1001 radeon_underscan_enum_list[i].type,
1002 radeon_underscan_enum_list[i].name);
1003 }
1004
445282db
DA		 1005 return 0;
1006}
1007
f46c0120
AD		 1008void radeon_update_display_priority(struct radeon_device *rdev)
1009{
1010 /* adjustment options for the display watermarks */
1011 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1012 /* set display priority to high for r3xx, rv515 chips
1013 * this avoids flickering due to underflow to the
1014 * display controllers during heavy acceleration.
45737447
AD		 1015 * Don't force high on rs4xx igp chips as it seems to
1016 * affect the sound card. See kernel bug 15982.
f46c0120 1017 */
45737447
AD		 1018 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1019 !(rdev->flags & RADEON_IS_IGP))
f46c0120
AD		 1020 rdev->disp_priority = 2;
1021 else
1022 rdev->disp_priority = 0;
1023 } else
1024 rdev->disp_priority = radeon_disp_priority;
1025
1026}
1027
771fe6b9
JG		 1028int radeon_modeset_init(struct radeon_device *rdev)
1029{
18917b60 1030 int i;
771fe6b9
JG		 1031 int ret;
1032
1033 drm_mode_config_init(rdev->ddev);
1034 rdev->mode_info.mode_config_initialized = true;
1035
1036 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1037
1038 if (ASIC_IS_AVIVO(rdev)) {
1039 rdev->ddev->mode_config.max_width = 8192;
1040 rdev->ddev->mode_config.max_height = 8192;
1041 } else {
1042 rdev->ddev->mode_config.max_width = 4096;
1043 rdev->ddev->mode_config.max_height = 4096;
1044 }
1045
1046 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1047
445282db
DA		 1048 ret = radeon_modeset_create_props(rdev);
1049 if (ret) {
1050 return ret;
1051 }
dfee5614 1052
f376b94f
AD		 1053 /* init i2c buses */
1054 radeon_i2c_init(rdev);
1055
3c537889
AD		 1056 /* check combios for a valid hardcoded EDID - Sun servers */
1057 if (!rdev->is_atom_bios) {
1058 /* check for hardcoded EDID in BIOS */
1059 radeon_combios_check_hardcoded_edid(rdev);
1060 }
1061
dfee5614 1062 /* allocate crtcs */
18917b60 1063 for (i = 0; i < rdev->num_crtc; i++) {
771fe6b9
JG		 1064 radeon_crtc_init(rdev->ddev, i);
1065 }
1066
1067 /* okay we should have all the bios connectors */
1068 ret = radeon_setup_enc_conn(rdev->ddev);
1069 if (!ret) {
1070 return ret;
1071 }
d4877cf2
AD		 1072 /* initialize hpd */
1073 radeon_hpd_init(rdev);
38651674 1074
ce8f5370
AD		 1075 /* Initialize power management */
1076 radeon_pm_init(rdev);
1077
38651674 1078 radeon_fbdev_init(rdev);
eb1f8e4f
DA		 1079 drm_kms_helper_poll_init(rdev->ddev);
1080
771fe6b9
JG		 1081 return 0;
1082}
1083
1084void radeon_modeset_fini(struct radeon_device *rdev)
1085{
38651674 1086 radeon_fbdev_fini(rdev);
3c537889 1087 kfree(rdev->mode_info.bios_hardcoded_edid);
ce8f5370 1088 radeon_pm_fini(rdev);
3c537889 1089
771fe6b9 1090 if (rdev->mode_info.mode_config_initialized) {
eb1f8e4f 1091 drm_kms_helper_poll_fini(rdev->ddev);
d4877cf2 1092 radeon_hpd_fini(rdev);
771fe6b9
JG		 1093 drm_mode_config_cleanup(rdev->ddev);
1094 rdev->mode_info.mode_config_initialized = false;
1095 }
f376b94f
AD		 1096 /* free i2c buses */
1097 radeon_i2c_fini(rdev);
771fe6b9
JG		 1098}
1099
039ed2d9
AD		 1100static bool is_hdtv_mode(struct drm_display_mode *mode)
1101{
1102 /* try and guess if this is a tv or a monitor */
1103 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1104 (mode->vdisplay == 576) || /* 576p */
1105 (mode->vdisplay == 720) || /* 720p */
1106 (mode->vdisplay == 1080)) /* 1080p */
1107 return true;
1108 else
1109 return false;
1110}
1111
c93bb85b
JG		 1112bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1113 struct drm_display_mode *mode,
1114 struct drm_display_mode *adjusted_mode)
771fe6b9 1115{
c93bb85b 1116 struct drm_device *dev = crtc->dev;
5b1714d3 1117 struct radeon_device *rdev = dev->dev_private;
c93bb85b
JG		 1118 struct drm_encoder *encoder;
1119 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1120 struct radeon_encoder *radeon_encoder;
5b1714d3
AD		 1121 struct drm_connector *connector;
1122 struct radeon_connector *radeon_connector;
c93bb85b 1123 bool first = true;
d65d65b1
AD		 1124 u32 src_v = 1, dst_v = 1;
1125 u32 src_h = 1, dst_h = 1;
771fe6b9 1126
5b1714d3
AD		 1127 radeon_crtc->h_border = 0;
1128 radeon_crtc->v_border = 0;
1129
c93bb85b 1130 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
c93bb85b
JG		 1131 if (encoder->crtc != crtc)
1132 continue;
d65d65b1 1133 radeon_encoder = to_radeon_encoder(encoder);
5b1714d3
AD		 1134 connector = radeon_get_connector_for_encoder(encoder);
1135 radeon_connector = to_radeon_connector(connector);
1136
c93bb85b 1137 if (first) {
80297e87
AD		 1138 /* set scaling */
1139 if (radeon_encoder->rmx_type == RMX_OFF)
1140 radeon_crtc->rmx_type = RMX_OFF;
1141 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1142 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1143 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1144 else
1145 radeon_crtc->rmx_type = RMX_OFF;
1146 /* copy native mode */
c93bb85b 1147 memcpy(&radeon_crtc->native_mode,
80297e87 1148 &radeon_encoder->native_mode,
de2103e4 1149 sizeof(struct drm_display_mode));
ff32a59d
AD		 1150 src_v = crtc->mode.vdisplay;
1151 dst_v = radeon_crtc->native_mode.vdisplay;
1152 src_h = crtc->mode.hdisplay;
1153 dst_h = radeon_crtc->native_mode.hdisplay;
5b1714d3
AD		 1154
1155 /* fix up for overscan on hdmi */
1156 if (ASIC_IS_AVIVO(rdev) &&
e6db0da0 1157 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
5b1714d3
AD		 1158 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1159 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
039ed2d9
AD		 1160 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1161 is_hdtv_mode(mode)))) {
5b1714d3
AD		 1162 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1163 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1164 radeon_crtc->rmx_type = RMX_FULL;
1165 src_v = crtc->mode.vdisplay;
1166 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1167 src_h = crtc->mode.hdisplay;
1168 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1169 }
c93bb85b
JG		 1170 first = false;
1171 } else {
1172 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1173 /* WARNING: Right now this can't happen but
1174 * in the future we need to check that scaling
d65d65b1 1175 * are consistent across different encoder
c93bb85b
JG		 1176 * (ie all encoder can work with the same
1177 * scaling).
1178 */
d65d65b1 1179 DRM_ERROR("Scaling not consistent across encoder.\n");
c93bb85b
JG		 1180 return false;
1181 }
771fe6b9
JG		 1182 }
1183 }
c93bb85b
JG		 1184 if (radeon_crtc->rmx_type != RMX_OFF) {
1185 fixed20_12 a, b;
d65d65b1
AD		 1186 a.full = dfixed_const(src_v);
1187 b.full = dfixed_const(dst_v);
68adac5e 1188 radeon_crtc->vsc.full = dfixed_div(a, b);
d65d65b1
AD		 1189 a.full = dfixed_const(src_h);
1190 b.full = dfixed_const(dst_h);
68adac5e 1191 radeon_crtc->hsc.full = dfixed_div(a, b);
771fe6b9 1192 } else {
68adac5e
BS		 1193 radeon_crtc->vsc.full = dfixed_const(1);
1194 radeon_crtc->hsc.full = dfixed_const(1);
771fe6b9 1195 }
c93bb85b 1196 return true;
771fe6b9 1197}
Clone of davem's net-next-2.6 tree