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drm/radeon/kms: simplify memory controller setup V2
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_device.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <drm/drmP.h>
30#include <drm/drm_crtc_helper.h>
31#include <drm/radeon_drm.h>
28d52043 32#include <linux/vgaarb.h>
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
35#include "radeon_asic.h"
36#include "atom.h"
37
b1e3a6d1
MD		 38/*
39 * Clear GPU surface registers.
40 */
3ce0a23d 41void radeon_surface_init(struct radeon_device *rdev)
b1e3a6d1
MD		 42{
43 /* FIXME: check this out */
44 if (rdev->family < CHIP_R600) {
45 int i;
46
550e2d92
DA		 47 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
48 if (rdev->surface_regs[i].bo)
49 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
50 else
51 radeon_clear_surface_reg(rdev, i);
b1e3a6d1 52 }
e024e110
DA		 53 /* enable surfaces */
54 WREG32(RADEON_SURFACE_CNTL, 0);
b1e3a6d1
MD		 55 }
56}
57
771fe6b9
JG		 58/*
59 * GPU scratch registers helpers function.
60 */
3ce0a23d 61void radeon_scratch_init(struct radeon_device *rdev)
771fe6b9
JG		 62{
63 int i;
64
65 /* FIXME: check this out */
66 if (rdev->family < CHIP_R300) {
67 rdev->scratch.num_reg = 5;
68 } else {
69 rdev->scratch.num_reg = 7;
70 }
71 for (i = 0; i < rdev->scratch.num_reg; i++) {
72 rdev->scratch.free[i] = true;
73 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
74 }
75}
76
77int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
78{
79 int i;
80
81 for (i = 0; i < rdev->scratch.num_reg; i++) {
82 if (rdev->scratch.free[i]) {
83 rdev->scratch.free[i] = false;
84 *reg = rdev->scratch.reg[i];
85 return 0;
86 }
87 }
88 return -EINVAL;
89}
90
91void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
92{
93 int i;
94
95 for (i = 0; i < rdev->scratch.num_reg; i++) {
96 if (rdev->scratch.reg[i] == reg) {
97 rdev->scratch.free[i] = true;
98 return;
99 }
100 }
101}
102
d594e46a
JG		 103/**
104 * radeon_vram_location - try to find VRAM location
105 * @rdev: radeon device structure holding all necessary informations
106 * @mc: memory controller structure holding memory informations
107 * @base: base address at which to put VRAM
108 *
109 * Function will place try to place VRAM at base address provided
110 * as parameter (which is so far either PCI aperture address or
111 * for IGP TOM base address).
112 *
113 * If there is not enough space to fit the unvisible VRAM in the 32bits
114 * address space then we limit the VRAM size to the aperture.
115 *
116 * If we are using AGP and if the AGP aperture doesn't allow us to have
117 * room for all the VRAM than we restrict the VRAM to the PCI aperture
118 * size and print a warning.
119 *
120 * This function will never fails, worst case are limiting VRAM.
121 *
122 * Note: GTT start, end, size should be initialized before calling this
123 * function on AGP platform.
124 *
125 * Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
126 * this shouldn't be a problem as we are using the PCI aperture as a reference.
127 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
128 * not IGP.
129 *
130 * Note: we use mc_vram_size as on some board we need to program the mc to
131 * cover the whole aperture even if VRAM size is inferior to aperture size
132 * Novell bug 204882 + along with lots of ubuntu ones
133 *
134 * Note: when limiting vram it's safe to overwritte real_vram_size because
135 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
136 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
137 * ones)
138 *
139 * Note: IGP TOM addr should be the same as the aperture addr, we don't
140 * explicitly check for that thought.
141 *
142 * FIXME: when reducing VRAM size align new size on power of 2.
771fe6b9 143 */
d594e46a 144void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
771fe6b9 145{
d594e46a
JG		 146 mc->vram_start = base;
147 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
148 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
149 mc->real_vram_size = mc->aper_size;
150 mc->mc_vram_size = mc->aper_size;
151 }
152 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
153 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) {
154 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
155 mc->real_vram_size = mc->aper_size;
156 mc->mc_vram_size = mc->aper_size;
157 }
158 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
159 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
160 mc->mc_vram_size >> 20, mc->vram_start,
161 mc->vram_end, mc->real_vram_size >> 20);
162}
771fe6b9 163
d594e46a
JG		 164/**
165 * radeon_gtt_location - try to find GTT location
166 * @rdev: radeon device structure holding all necessary informations
167 * @mc: memory controller structure holding memory informations
168 *
169 * Function will place try to place GTT before or after VRAM.
170 *
171 * If GTT size is bigger than space left then we ajust GTT size.
172 * Thus function will never fails.
173 *
174 * FIXME: when reducing GTT size align new size on power of 2.
175 */
176void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
177{
178 u64 size_af, size_bf;
179
180 size_af = 0xFFFFFFFF - mc->vram_end;
181 size_bf = mc->vram_start;
182 if (size_bf > size_af) {
183 if (mc->gtt_size > size_bf) {
184 dev_warn(rdev->dev, "limiting GTT\n");
185 mc->gtt_size = size_bf;
771fe6b9 186 }
d594e46a 187 mc->gtt_start = mc->vram_start - mc->gtt_size;
771fe6b9 188 } else {
d594e46a
JG		 189 if (mc->gtt_size > size_af) {
190 dev_warn(rdev->dev, "limiting GTT\n");
191 mc->gtt_size = size_af;
192 }
193 mc->gtt_start = mc->vram_end + 1;
771fe6b9 194 }
d594e46a
JG		 195 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
196 dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
197 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
771fe6b9
JG		 198}
199
771fe6b9
JG		 200/*
201 * GPU helpers function.
202 */
9f022ddf 203bool radeon_card_posted(struct radeon_device *rdev)
771fe6b9
JG		 204{
205 uint32_t reg;
206
207 /* first check CRTCs */
bcc1c2a1
AD		 208 if (ASIC_IS_DCE4(rdev)) {
209 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
210 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
211 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
212 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
213 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
214 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
215 if (reg & EVERGREEN_CRTC_MASTER_EN)
216 return true;
217 } else if (ASIC_IS_AVIVO(rdev)) {
771fe6b9
JG		 218 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
219 RREG32(AVIVO_D2CRTC_CONTROL);
220 if (reg & AVIVO_CRTC_EN) {
221 return true;
222 }
223 } else {
224 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
225 RREG32(RADEON_CRTC2_GEN_CNTL);
226 if (reg & RADEON_CRTC_EN) {
227 return true;
228 }
229 }
230
231 /* then check MEM_SIZE, in case the crtcs are off */
232 if (rdev->family >= CHIP_R600)
233 reg = RREG32(R600_CONFIG_MEMSIZE);
234 else
235 reg = RREG32(RADEON_CONFIG_MEMSIZE);
236
237 if (reg)
238 return true;
239
240 return false;
241
242}
243
72542d77
DA		 244bool radeon_boot_test_post_card(struct radeon_device *rdev)
245{
246 if (radeon_card_posted(rdev))
247 return true;
248
249 if (rdev->bios) {
250 DRM_INFO("GPU not posted. posting now...\n");
251 if (rdev->is_atom_bios)
252 atom_asic_init(rdev->mode_info.atom_context);
253 else
254 radeon_combios_asic_init(rdev->ddev);
255 return true;
256 } else {
257 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
258 return false;
259 }
260}
261
3ce0a23d
JG		 262int radeon_dummy_page_init(struct radeon_device *rdev)
263{
82568565
DA		 264 if (rdev->dummy_page.page)
265 return 0;
3ce0a23d
JG		 266 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
267 if (rdev->dummy_page.page == NULL)
268 return -ENOMEM;
269 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
270 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
271 if (!rdev->dummy_page.addr) {
272 __free_page(rdev->dummy_page.page);
273 rdev->dummy_page.page = NULL;
274 return -ENOMEM;
275 }
276 return 0;
277}
278
279void radeon_dummy_page_fini(struct radeon_device *rdev)
280{
281 if (rdev->dummy_page.page == NULL)
282 return;
283 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
284 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
285 __free_page(rdev->dummy_page.page);
286 rdev->dummy_page.page = NULL;
287}
288
771fe6b9
JG		 289
290/*
291 * Registers accessors functions.
292 */
293uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
294{
295 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
296 BUG_ON(1);
297 return 0;
298}
299
300void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
301{
302 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
303 reg, v);
304 BUG_ON(1);
305}
306
307void radeon_register_accessor_init(struct radeon_device *rdev)
308{
771fe6b9
JG		 309 rdev->mc_rreg = &radeon_invalid_rreg;
310 rdev->mc_wreg = &radeon_invalid_wreg;
311 rdev->pll_rreg = &radeon_invalid_rreg;
312 rdev->pll_wreg = &radeon_invalid_wreg;
771fe6b9
JG		 313 rdev->pciep_rreg = &radeon_invalid_rreg;
314 rdev->pciep_wreg = &radeon_invalid_wreg;
315
316 /* Don't change order as we are overridding accessor. */
317 if (rdev->family < CHIP_RV515) {
de1b2898
DA		 318 rdev->pcie_reg_mask = 0xff;
319 } else {
320 rdev->pcie_reg_mask = 0x7ff;
771fe6b9
JG		 321 }
322 /* FIXME: not sure here */
323 if (rdev->family <= CHIP_R580) {
324 rdev->pll_rreg = &r100_pll_rreg;
325 rdev->pll_wreg = &r100_pll_wreg;
326 }
905b6822
JG		 327 if (rdev->family >= CHIP_R420) {
328 rdev->mc_rreg = &r420_mc_rreg;
329 rdev->mc_wreg = &r420_mc_wreg;
330 }
771fe6b9
JG		 331 if (rdev->family >= CHIP_RV515) {
332 rdev->mc_rreg = &rv515_mc_rreg;
333 rdev->mc_wreg = &rv515_mc_wreg;
334 }
335 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
336 rdev->mc_rreg = &rs400_mc_rreg;
337 rdev->mc_wreg = &rs400_mc_wreg;
338 }
339 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
340 rdev->mc_rreg = &rs690_mc_rreg;
341 rdev->mc_wreg = &rs690_mc_wreg;
342 }
343 if (rdev->family == CHIP_RS600) {
344 rdev->mc_rreg = &rs600_mc_rreg;
345 rdev->mc_wreg = &rs600_mc_wreg;
346 }
bcc1c2a1 347 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
771fe6b9
JG		 348 rdev->pciep_rreg = &r600_pciep_rreg;
349 rdev->pciep_wreg = &r600_pciep_wreg;
350 }
351}
352
353
354/*
355 * ASIC
356 */
357int radeon_asic_init(struct radeon_device *rdev)
358{
359 radeon_register_accessor_init(rdev);
360 switch (rdev->family) {
361 case CHIP_R100:
362 case CHIP_RV100:
363 case CHIP_RS100:
364 case CHIP_RV200:
365 case CHIP_RS200:
44ca7478
PN		 366 rdev->asic = &r100_asic;
367 break;
771fe6b9
JG		 368 case CHIP_R200:
369 case CHIP_RV250:
370 case CHIP_RS300:
371 case CHIP_RV280:
44ca7478 372 rdev->asic = &r200_asic;
771fe6b9
JG		 373 break;
374 case CHIP_R300:
375 case CHIP_R350:
376 case CHIP_RV350:
377 case CHIP_RV380:
d80eeb0f
PN		 378 if (rdev->flags & RADEON_IS_PCIE)
379 rdev->asic = &r300_asic_pcie;
380 else
381 rdev->asic = &r300_asic;
771fe6b9
JG		 382 break;
383 case CHIP_R420:
384 case CHIP_R423:
385 case CHIP_RV410:
386 rdev->asic = &r420_asic;
387 break;
388 case CHIP_RS400:
389 case CHIP_RS480:
390 rdev->asic = &rs400_asic;
391 break;
392 case CHIP_RS600:
393 rdev->asic = &rs600_asic;
394 break;
395 case CHIP_RS690:
396 case CHIP_RS740:
397 rdev->asic = &rs690_asic;
398 break;
399 case CHIP_RV515:
400 rdev->asic = &rv515_asic;
401 break;
402 case CHIP_R520:
403 case CHIP_RV530:
404 case CHIP_RV560:
405 case CHIP_RV570:
406 case CHIP_R580:
407 rdev->asic = &r520_asic;
408 break;
409 case CHIP_R600:
410 case CHIP_RV610:
411 case CHIP_RV630:
412 case CHIP_RV620:
413 case CHIP_RV635:
414 case CHIP_RV670:
415 case CHIP_RS780:
3ce0a23d
JG		 416 case CHIP_RS880:
417 rdev->asic = &r600_asic;
418 break;
771fe6b9
JG		 419 case CHIP_RV770:
420 case CHIP_RV730:
421 case CHIP_RV710:
3ce0a23d
JG		 422 case CHIP_RV740:
423 rdev->asic = &rv770_asic;
424 break;
bcc1c2a1
AD		 425 case CHIP_CEDAR:
426 case CHIP_REDWOOD:
427 case CHIP_JUNIPER:
428 case CHIP_CYPRESS:
429 case CHIP_HEMLOCK:
430 rdev->asic = &evergreen_asic;
431 break;
771fe6b9
JG		 432 default:
433 /* FIXME: not supported yet */
434 return -EINVAL;
435 }
5ea597f3
RM		 436
437 if (rdev->flags & RADEON_IS_IGP) {
438 rdev->asic->get_memory_clock = NULL;
439 rdev->asic->set_memory_clock = NULL;
440 }
441
771fe6b9
JG		 442 return 0;
443}
444
445
446/*
447 * Wrapper around modesetting bits.
448 */
449int radeon_clocks_init(struct radeon_device *rdev)
450{
451 int r;
452
771fe6b9
JG		 453 r = radeon_static_clocks_init(rdev->ddev);
454 if (r) {
455 return r;
456 }
457 DRM_INFO("Clocks initialized !\n");
458 return 0;
459}
460
461void radeon_clocks_fini(struct radeon_device *rdev)
462{
463}
464
465/* ATOM accessor methods */
466static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
467{
468 struct radeon_device *rdev = info->dev->dev_private;
469 uint32_t r;
470
471 r = rdev->pll_rreg(rdev, reg);
472 return r;
473}
474
475static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
476{
477 struct radeon_device *rdev = info->dev->dev_private;
478
479 rdev->pll_wreg(rdev, reg, val);
480}
481
482static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
483{
484 struct radeon_device *rdev = info->dev->dev_private;
485 uint32_t r;
486
487 r = rdev->mc_rreg(rdev, reg);
488 return r;
489}
490
491static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
492{
493 struct radeon_device *rdev = info->dev->dev_private;
494
495 rdev->mc_wreg(rdev, reg, val);
496}
497
498static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
499{
500 struct radeon_device *rdev = info->dev->dev_private;
501
502 WREG32(reg*4, val);
503}
504
505static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
506{
507 struct radeon_device *rdev = info->dev->dev_private;
508 uint32_t r;
509
510 r = RREG32(reg*4);
511 return r;
512}
513
771fe6b9
JG		 514int radeon_atombios_init(struct radeon_device *rdev)
515{
61c4b24b
MF		 516 struct card_info *atom_card_info =
517 kzalloc(sizeof(struct card_info), GFP_KERNEL);
518
519 if (!atom_card_info)
520 return -ENOMEM;
521
522 rdev->mode_info.atom_card_info = atom_card_info;
523 atom_card_info->dev = rdev->ddev;
524 atom_card_info->reg_read = cail_reg_read;
525 atom_card_info->reg_write = cail_reg_write;
526 atom_card_info->mc_read = cail_mc_read;
527 atom_card_info->mc_write = cail_mc_write;
528 atom_card_info->pll_read = cail_pll_read;
529 atom_card_info->pll_write = cail_pll_write;
530
531 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
c31ad97f 532 mutex_init(&rdev->mode_info.atom_context->mutex);
771fe6b9 533 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
d904ef9b 534 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
771fe6b9
JG		 535 return 0;
536}
537
538void radeon_atombios_fini(struct radeon_device *rdev)
539{
4a04a844
JG		 540 if (rdev->mode_info.atom_context) {
541 kfree(rdev->mode_info.atom_context->scratch);
542 kfree(rdev->mode_info.atom_context);
543 }
61c4b24b 544 kfree(rdev->mode_info.atom_card_info);
771fe6b9
JG		 545}
546
547int radeon_combios_init(struct radeon_device *rdev)
548{
549 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
550 return 0;
551}
552
553void radeon_combios_fini(struct radeon_device *rdev)
554{
555}
556
28d52043
DA		 557/* if we get transitioned to only one device, tak VGA back */
558static unsigned int radeon_vga_set_decode(void *cookie, bool state)
559{
560 struct radeon_device *rdev = cookie;
28d52043
DA		 561 radeon_vga_set_state(rdev, state);
562 if (state)
563 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
564 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
565 else
566 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
567}
c1176d6f 568
b574f251
JG		 569void radeon_agp_disable(struct radeon_device *rdev)
570{
571 rdev->flags &= ~RADEON_IS_AGP;
572 if (rdev->family >= CHIP_R600) {
573 DRM_INFO("Forcing AGP to PCIE mode\n");
574 rdev->flags |= RADEON_IS_PCIE;
575 } else if (rdev->family >= CHIP_RV515 ||
576 rdev->family == CHIP_RV380 ||
577 rdev->family == CHIP_RV410 ||
578 rdev->family == CHIP_R423) {
579 DRM_INFO("Forcing AGP to PCIE mode\n");
580 rdev->flags |= RADEON_IS_PCIE;
581 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
582 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
583 } else {
584 DRM_INFO("Forcing AGP to PCI mode\n");
585 rdev->flags |= RADEON_IS_PCI;
586 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
587 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
588 }
700a0cc0 589 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
b574f251 590}
771fe6b9 591
36421338
JG		 592void radeon_check_arguments(struct radeon_device *rdev)
593{
594 /* vramlimit must be a power of two */
595 switch (radeon_vram_limit) {
596 case 0:
597 case 4:
598 case 8:
599 case 16:
600 case 32:
601 case 64:
602 case 128:
603 case 256:
604 case 512:
605 case 1024:
606 case 2048:
607 case 4096:
608 break;
609 default:
610 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
611 radeon_vram_limit);
612 radeon_vram_limit = 0;
613 break;
614 }
615 radeon_vram_limit = radeon_vram_limit << 20;
616 /* gtt size must be power of two and greater or equal to 32M */
617 switch (radeon_gart_size) {
618 case 4:
619 case 8:
620 case 16:
621 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
622 radeon_gart_size);
623 radeon_gart_size = 512;
624 break;
625 case 32:
626 case 64:
627 case 128:
628 case 256:
629 case 512:
630 case 1024:
631 case 2048:
632 case 4096:
633 break;
634 default:
635 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
636 radeon_gart_size);
637 radeon_gart_size = 512;
638 break;
639 }
640 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
641 /* AGP mode can only be -1, 1, 2, 4, 8 */
642 switch (radeon_agpmode) {
643 case -1:
644 case 0:
645 case 1:
646 case 2:
647 case 4:
648 case 8:
649 break;
650 default:
651 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
652 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
653 radeon_agpmode = 0;
654 break;
655 }
656}
657
771fe6b9
JG		 658int radeon_device_init(struct radeon_device *rdev,
659 struct drm_device *ddev,
660 struct pci_dev *pdev,
661 uint32_t flags)
662{
6cf8a3f5 663 int r;
ad49f501 664 int dma_bits;
771fe6b9
JG		 665
666 DRM_INFO("radeon: Initializing kernel modesetting.\n");
667 rdev->shutdown = false;
9f022ddf 668 rdev->dev = &pdev->dev;
771fe6b9
JG		 669 rdev->ddev = ddev;
670 rdev->pdev = pdev;
671 rdev->flags = flags;
672 rdev->family = flags & RADEON_FAMILY_MASK;
673 rdev->is_atom_bios = false;
674 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
675 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
676 rdev->gpu_lockup = false;
733289c2 677 rdev->accel_working = false;
771fe6b9
JG		 678 /* mutex initialization are all done here so we
679 * can recall function without having locking issues */
680 mutex_init(&rdev->cs_mutex);
681 mutex_init(&rdev->ib_pool.mutex);
682 mutex_init(&rdev->cp.mutex);
40bacf16 683 mutex_init(&rdev->dc_hw_i2c_mutex);
d8f60cfc
AD		 684 if (rdev->family >= CHIP_R600)
685 spin_lock_init(&rdev->ih.lock);
4c788679 686 mutex_init(&rdev->gem.mutex);
c913e23a 687 mutex_init(&rdev->pm.mutex);
771fe6b9 688 rwlock_init(&rdev->fence_drv.lock);
9f022ddf 689 INIT_LIST_HEAD(&rdev->gem.objects);
73a6d3fc 690 init_waitqueue_head(&rdev->irq.vblank_queue);
771fe6b9 691
d4877cf2
AD		 692 /* setup workqueue */
693 rdev->wq = create_workqueue("radeon");
694 if (rdev->wq == NULL)
695 return -ENOMEM;
696
4aac0473
JG		 697 /* Set asic functions */
698 r = radeon_asic_init(rdev);
36421338 699 if (r)
4aac0473 700 return r;
36421338 701 radeon_check_arguments(rdev);
4aac0473 702
30256a3f 703 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
b574f251 704 radeon_agp_disable(rdev);
771fe6b9
JG		 705 }
706
ad49f501
DA		 707 /* set DMA mask + need_dma32 flags.
708 * PCIE - can handle 40-bits.
709 * IGP - can handle 40-bits (in theory)
710 * AGP - generally dma32 is safest
711 * PCI - only dma32
712 */
713 rdev->need_dma32 = false;
714 if (rdev->flags & RADEON_IS_AGP)
715 rdev->need_dma32 = true;
716 if (rdev->flags & RADEON_IS_PCI)
717 rdev->need_dma32 = true;
718
719 dma_bits = rdev->need_dma32 ? 32 : 40;
720 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
771fe6b9
JG		 721 if (r) {
722 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
723 }
724
725 /* Registers mapping */
726 /* TODO: block userspace mapping of io register */
727 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
728 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
729 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
730 if (rdev->rmmio == NULL) {
731 return -ENOMEM;
732 }
733 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
734 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
735
28d52043 736 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
93239ea1
DA		 737 /* this will fail for cards that aren't VGA class devices, just
738 * ignore it */
739 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
28d52043 740
3ce0a23d 741 r = radeon_init(rdev);
b574f251 742 if (r)
3ce0a23d 743 return r;
3ce0a23d 744
b574f251
JG		 745 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
746 /* Acceleration not working on AGP card try again
747 * with fallback to PCI or PCIE GART
748 */
1a029b76 749 radeon_gpu_reset(rdev);
b574f251
JG		 750 radeon_fini(rdev);
751 radeon_agp_disable(rdev);
752 r = radeon_init(rdev);
4aac0473
JG		 753 if (r)
754 return r;
771fe6b9 755 }
ecc0b326
MD		 756 if (radeon_testing) {
757 radeon_test_moves(rdev);
758 }
771fe6b9
JG		 759 if (radeon_benchmarking) {
760 radeon_benchmark(rdev);
761 }
6cf8a3f5 762 return 0;
771fe6b9
JG		 763}
764
765void radeon_device_fini(struct radeon_device *rdev)
766{
771fe6b9
JG		 767 DRM_INFO("radeon: finishing device.\n");
768 rdev->shutdown = true;
62a8ea3f 769 radeon_fini(rdev);
d4877cf2 770 destroy_workqueue(rdev->wq);
c1176d6f 771 vga_client_register(rdev->pdev, NULL, NULL, NULL);
771fe6b9
JG		 772 iounmap(rdev->rmmio);
773 rdev->rmmio = NULL;
774}
775
776
777/*
778 * Suspend & resume.
779 */
780int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
781{
875c1866 782 struct radeon_device *rdev;
771fe6b9 783 struct drm_crtc *crtc;
4c788679 784 int r;
771fe6b9 785
875c1866 786 if (dev == NULL || dev->dev_private == NULL) {
771fe6b9
JG		 787 return -ENODEV;
788 }
789 if (state.event == PM_EVENT_PRETHAW) {
790 return 0;
791 }
875c1866
DJ		 792 rdev = dev->dev_private;
793
771fe6b9
JG		 794 /* unpin the front buffers */
795 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
796 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
4c788679 797 struct radeon_bo *robj;
771fe6b9
JG		 798
799 if (rfb == NULL || rfb->obj == NULL) {
800 continue;
801 }
802 robj = rfb->obj->driver_private;
4c788679
JG		 803 if (robj != rdev->fbdev_rbo) {
804 r = radeon_bo_reserve(robj, false);
805 if (unlikely(r == 0)) {
806 radeon_bo_unpin(robj);
807 radeon_bo_unreserve(robj);
808 }
771fe6b9
JG		 809 }
810 }
811 /* evict vram memory */
4c788679 812 radeon_bo_evict_vram(rdev);
771fe6b9
JG		 813 /* wait for gpu to finish processing current batch */
814 radeon_fence_wait_last(rdev);
815
f657c2a7
YZ		 816 radeon_save_bios_scratch_regs(rdev);
817
62a8ea3f 818 radeon_suspend(rdev);
d4877cf2 819 radeon_hpd_fini(rdev);
771fe6b9 820 /* evict remaining vram memory */
4c788679 821 radeon_bo_evict_vram(rdev);
771fe6b9 822
771fe6b9
JG		 823 pci_save_state(dev->pdev);
824 if (state.event == PM_EVENT_SUSPEND) {
825 /* Shut down the device */
826 pci_disable_device(dev->pdev);
827 pci_set_power_state(dev->pdev, PCI_D3hot);
828 }
829 acquire_console_sem();
830 fb_set_suspend(rdev->fbdev_info, 1);
831 release_console_sem();
832 return 0;
833}
834
835int radeon_resume_kms(struct drm_device *dev)
836{
837 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 838
839 acquire_console_sem();
840 pci_set_power_state(dev->pdev, PCI_D0);
841 pci_restore_state(dev->pdev);
842 if (pci_enable_device(dev->pdev)) {
843 release_console_sem();
844 return -1;
845 }
846 pci_set_master(dev->pdev);
0ebf1717
DA		 847 /* resume AGP if in use */
848 radeon_agp_resume(rdev);
62a8ea3f 849 radeon_resume(rdev);
f657c2a7 850 radeon_restore_bios_scratch_regs(rdev);
771fe6b9
JG		 851 fb_set_suspend(rdev->fbdev_info, 0);
852 release_console_sem();
853
d4877cf2
AD		 854 /* reset hpd state */
855 radeon_hpd_init(rdev);
771fe6b9
JG		 856 /* blat the mode back in */
857 drm_helper_resume_force_mode(dev);
858 return 0;
859}
860
861
862/*
863 * Debugfs
864 */
865struct radeon_debugfs {
866 struct drm_info_list *files;
867 unsigned num_files;
868};
869static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
870static unsigned _radeon_debugfs_count = 0;
871
872int radeon_debugfs_add_files(struct radeon_device *rdev,
873 struct drm_info_list *files,
874 unsigned nfiles)
875{
876 unsigned i;
877
878 for (i = 0; i < _radeon_debugfs_count; i++) {
879 if (_radeon_debugfs[i].files == files) {
880 /* Already registered */
881 return 0;
882 }
883 }
884 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
885 DRM_ERROR("Reached maximum number of debugfs files.\n");
886 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
887 return -EINVAL;
888 }
889 _radeon_debugfs[_radeon_debugfs_count].files = files;
890 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
891 _radeon_debugfs_count++;
892#if defined(CONFIG_DEBUG_FS)
893 drm_debugfs_create_files(files, nfiles,
894 rdev->ddev->control->debugfs_root,
895 rdev->ddev->control);
896 drm_debugfs_create_files(files, nfiles,
897 rdev->ddev->primary->debugfs_root,
898 rdev->ddev->primary);
899#endif
900 return 0;
901}
902
903#if defined(CONFIG_DEBUG_FS)
904int radeon_debugfs_init(struct drm_minor *minor)
905{
906 return 0;
907}
908
909void radeon_debugfs_cleanup(struct drm_minor *minor)
910{
911 unsigned i;
912
913 for (i = 0; i < _radeon_debugfs_count; i++) {
914 drm_debugfs_remove_files(_radeon_debugfs[i].files,
915 _radeon_debugfs[i].num_files, minor);
916 }
917}
918#endif
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