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drm/radeon/kms: Fix NULL ptr dereference
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_device.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <drm/drmP.h>
30#include <drm/drm_crtc_helper.h>
31#include <drm/radeon_drm.h>
28d52043 32#include <linux/vgaarb.h>
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
35#include "radeon_asic.h"
36#include "atom.h"
37
b1e3a6d1
MD		 38/*
39 * Clear GPU surface registers.
40 */
3ce0a23d 41void radeon_surface_init(struct radeon_device *rdev)
b1e3a6d1
MD		 42{
43 /* FIXME: check this out */
44 if (rdev->family < CHIP_R600) {
45 int i;
46
47 for (i = 0; i < 8; i++) {
48 WREG32(RADEON_SURFACE0_INFO +
49 i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
50 0);
51 }
e024e110
DA		 52 /* enable surfaces */
53 WREG32(RADEON_SURFACE_CNTL, 0);
b1e3a6d1
MD		 54 }
55}
56
771fe6b9
JG		 57/*
58 * GPU scratch registers helpers function.
59 */
3ce0a23d 60void radeon_scratch_init(struct radeon_device *rdev)
771fe6b9
JG		 61{
62 int i;
63
64 /* FIXME: check this out */
65 if (rdev->family < CHIP_R300) {
66 rdev->scratch.num_reg = 5;
67 } else {
68 rdev->scratch.num_reg = 7;
69 }
70 for (i = 0; i < rdev->scratch.num_reg; i++) {
71 rdev->scratch.free[i] = true;
72 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
73 }
74}
75
76int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
77{
78 int i;
79
80 for (i = 0; i < rdev->scratch.num_reg; i++) {
81 if (rdev->scratch.free[i]) {
82 rdev->scratch.free[i] = false;
83 *reg = rdev->scratch.reg[i];
84 return 0;
85 }
86 }
87 return -EINVAL;
88}
89
90void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
91{
92 int i;
93
94 for (i = 0; i < rdev->scratch.num_reg; i++) {
95 if (rdev->scratch.reg[i] == reg) {
96 rdev->scratch.free[i] = true;
97 return;
98 }
99 }
100}
101
102/*
103 * MC common functions
104 */
105int radeon_mc_setup(struct radeon_device *rdev)
106{
107 uint32_t tmp;
108
109 /* Some chips have an "issue" with the memory controller, the
110 * location must be aligned to the size. We just align it down,
111 * too bad if we walk over the top of system memory, we don't
112 * use DMA without a remapped anyway.
113 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
114 */
115 /* FGLRX seems to setup like this, VRAM a 0, then GART.
116 */
117 /*
118 * Note: from R6xx the address space is 40bits but here we only
119 * use 32bits (still have to see a card which would exhaust 4G
120 * address space).
121 */
122 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
123 /* vram location was already setup try to put gtt after
124 * if it fits */
7a50f01a 125 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
771fe6b9
JG		 126 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
127 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
128 rdev->mc.gtt_location = tmp;
129 } else {
130 if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
131 printk(KERN_ERR "[drm] GTT too big to fit "
132 "before or after vram location.\n");
133 return -EINVAL;
134 }
135 rdev->mc.gtt_location = 0;
136 }
137 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
138 /* gtt location was already setup try to put vram before
139 * if it fits */
7a50f01a 140 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
771fe6b9
JG		 141 rdev->mc.vram_location = 0;
142 } else {
143 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
7a50f01a
DA		 144 tmp += (rdev->mc.mc_vram_size - 1);
145 tmp &= ~(rdev->mc.mc_vram_size - 1);
146 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
771fe6b9
JG		 147 rdev->mc.vram_location = tmp;
148 } else {
149 printk(KERN_ERR "[drm] vram too big to fit "
150 "before or after GTT location.\n");
151 return -EINVAL;
152 }
153 }
154 } else {
155 rdev->mc.vram_location = 0;
17332925
DA		 156 tmp = rdev->mc.mc_vram_size;
157 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
158 rdev->mc.gtt_location = tmp;
771fe6b9 159 }
9f022ddf
JG		 160 rdev->mc.vram_start = rdev->mc.vram_location;
161 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
162 rdev->mc.gtt_start = rdev->mc.gtt_location;
163 rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
3ce0a23d 164 DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
771fe6b9 165 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
3ce0a23d
JG		 166 (unsigned)rdev->mc.vram_location,
167 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
168 DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
771fe6b9 169 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
3ce0a23d
JG		 170 (unsigned)rdev->mc.gtt_location,
171 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
771fe6b9
JG		 172 return 0;
173}
174
175
176/*
177 * GPU helpers function.
178 */
9f022ddf 179bool radeon_card_posted(struct radeon_device *rdev)
771fe6b9
JG		 180{
181 uint32_t reg;
182
183 /* first check CRTCs */
184 if (ASIC_IS_AVIVO(rdev)) {
185 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
186 RREG32(AVIVO_D2CRTC_CONTROL);
187 if (reg & AVIVO_CRTC_EN) {
188 return true;
189 }
190 } else {
191 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
192 RREG32(RADEON_CRTC2_GEN_CNTL);
193 if (reg & RADEON_CRTC_EN) {
194 return true;
195 }
196 }
197
198 /* then check MEM_SIZE, in case the crtcs are off */
199 if (rdev->family >= CHIP_R600)
200 reg = RREG32(R600_CONFIG_MEMSIZE);
201 else
202 reg = RREG32(RADEON_CONFIG_MEMSIZE);
203
204 if (reg)
205 return true;
206
207 return false;
208
209}
210
72542d77
DA		 211bool radeon_boot_test_post_card(struct radeon_device *rdev)
212{
213 if (radeon_card_posted(rdev))
214 return true;
215
216 if (rdev->bios) {
217 DRM_INFO("GPU not posted. posting now...\n");
218 if (rdev->is_atom_bios)
219 atom_asic_init(rdev->mode_info.atom_context);
220 else
221 radeon_combios_asic_init(rdev->ddev);
222 return true;
223 } else {
224 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
225 return false;
226 }
227}
228
3ce0a23d
JG		 229int radeon_dummy_page_init(struct radeon_device *rdev)
230{
231 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
232 if (rdev->dummy_page.page == NULL)
233 return -ENOMEM;
234 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
235 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
236 if (!rdev->dummy_page.addr) {
237 __free_page(rdev->dummy_page.page);
238 rdev->dummy_page.page = NULL;
239 return -ENOMEM;
240 }
241 return 0;
242}
243
244void radeon_dummy_page_fini(struct radeon_device *rdev)
245{
246 if (rdev->dummy_page.page == NULL)
247 return;
248 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
249 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
250 __free_page(rdev->dummy_page.page);
251 rdev->dummy_page.page = NULL;
252}
253
771fe6b9
JG		 254
255/*
256 * Registers accessors functions.
257 */
258uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
259{
260 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
261 BUG_ON(1);
262 return 0;
263}
264
265void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
266{
267 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
268 reg, v);
269 BUG_ON(1);
270}
271
272void radeon_register_accessor_init(struct radeon_device *rdev)
273{
771fe6b9
JG		 274 rdev->mc_rreg = &radeon_invalid_rreg;
275 rdev->mc_wreg = &radeon_invalid_wreg;
276 rdev->pll_rreg = &radeon_invalid_rreg;
277 rdev->pll_wreg = &radeon_invalid_wreg;
771fe6b9
JG		 278 rdev->pciep_rreg = &radeon_invalid_rreg;
279 rdev->pciep_wreg = &radeon_invalid_wreg;
280
281 /* Don't change order as we are overridding accessor. */
282 if (rdev->family < CHIP_RV515) {
de1b2898
DA		 283 rdev->pcie_reg_mask = 0xff;
284 } else {
285 rdev->pcie_reg_mask = 0x7ff;
771fe6b9
JG		 286 }
287 /* FIXME: not sure here */
288 if (rdev->family <= CHIP_R580) {
289 rdev->pll_rreg = &r100_pll_rreg;
290 rdev->pll_wreg = &r100_pll_wreg;
291 }
905b6822
JG		 292 if (rdev->family >= CHIP_R420) {
293 rdev->mc_rreg = &r420_mc_rreg;
294 rdev->mc_wreg = &r420_mc_wreg;
295 }
771fe6b9
JG		 296 if (rdev->family >= CHIP_RV515) {
297 rdev->mc_rreg = &rv515_mc_rreg;
298 rdev->mc_wreg = &rv515_mc_wreg;
299 }
300 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
301 rdev->mc_rreg = &rs400_mc_rreg;
302 rdev->mc_wreg = &rs400_mc_wreg;
303 }
304 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
305 rdev->mc_rreg = &rs690_mc_rreg;
306 rdev->mc_wreg = &rs690_mc_wreg;
307 }
308 if (rdev->family == CHIP_RS600) {
309 rdev->mc_rreg = &rs600_mc_rreg;
310 rdev->mc_wreg = &rs600_mc_wreg;
311 }
312 if (rdev->family >= CHIP_R600) {
313 rdev->pciep_rreg = &r600_pciep_rreg;
314 rdev->pciep_wreg = &r600_pciep_wreg;
315 }
316}
317
318
319/*
320 * ASIC
321 */
322int radeon_asic_init(struct radeon_device *rdev)
323{
324 radeon_register_accessor_init(rdev);
325 switch (rdev->family) {
326 case CHIP_R100:
327 case CHIP_RV100:
328 case CHIP_RS100:
329 case CHIP_RV200:
330 case CHIP_RS200:
331 case CHIP_R200:
332 case CHIP_RV250:
333 case CHIP_RS300:
334 case CHIP_RV280:
335 rdev->asic = &r100_asic;
336 break;
337 case CHIP_R300:
338 case CHIP_R350:
339 case CHIP_RV350:
340 case CHIP_RV380:
341 rdev->asic = &r300_asic;
4aac0473 342 if (rdev->flags & RADEON_IS_PCIE) {
4aac0473
JG		 343 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
344 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
345 }
771fe6b9
JG		 346 break;
347 case CHIP_R420:
348 case CHIP_R423:
349 case CHIP_RV410:
350 rdev->asic = &r420_asic;
351 break;
352 case CHIP_RS400:
353 case CHIP_RS480:
354 rdev->asic = &rs400_asic;
355 break;
356 case CHIP_RS600:
357 rdev->asic = &rs600_asic;
358 break;
359 case CHIP_RS690:
360 case CHIP_RS740:
361 rdev->asic = &rs690_asic;
362 break;
363 case CHIP_RV515:
364 rdev->asic = &rv515_asic;
365 break;
366 case CHIP_R520:
367 case CHIP_RV530:
368 case CHIP_RV560:
369 case CHIP_RV570:
370 case CHIP_R580:
371 rdev->asic = &r520_asic;
372 break;
373 case CHIP_R600:
374 case CHIP_RV610:
375 case CHIP_RV630:
376 case CHIP_RV620:
377 case CHIP_RV635:
378 case CHIP_RV670:
379 case CHIP_RS780:
3ce0a23d
JG		 380 case CHIP_RS880:
381 rdev->asic = &r600_asic;
382 break;
771fe6b9
JG		 383 case CHIP_RV770:
384 case CHIP_RV730:
385 case CHIP_RV710:
3ce0a23d
JG		 386 case CHIP_RV740:
387 rdev->asic = &rv770_asic;
388 break;
771fe6b9
JG		 389 default:
390 /* FIXME: not supported yet */
391 return -EINVAL;
392 }
393 return 0;
394}
395
396
397/*
398 * Wrapper around modesetting bits.
399 */
400int radeon_clocks_init(struct radeon_device *rdev)
401{
402 int r;
403
771fe6b9
JG		 404 r = radeon_static_clocks_init(rdev->ddev);
405 if (r) {
406 return r;
407 }
408 DRM_INFO("Clocks initialized !\n");
409 return 0;
410}
411
412void radeon_clocks_fini(struct radeon_device *rdev)
413{
414}
415
416/* ATOM accessor methods */
417static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
418{
419 struct radeon_device *rdev = info->dev->dev_private;
420 uint32_t r;
421
422 r = rdev->pll_rreg(rdev, reg);
423 return r;
424}
425
426static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
427{
428 struct radeon_device *rdev = info->dev->dev_private;
429
430 rdev->pll_wreg(rdev, reg, val);
431}
432
433static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
434{
435 struct radeon_device *rdev = info->dev->dev_private;
436 uint32_t r;
437
438 r = rdev->mc_rreg(rdev, reg);
439 return r;
440}
441
442static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
443{
444 struct radeon_device *rdev = info->dev->dev_private;
445
446 rdev->mc_wreg(rdev, reg, val);
447}
448
449static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
450{
451 struct radeon_device *rdev = info->dev->dev_private;
452
453 WREG32(reg*4, val);
454}
455
456static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
457{
458 struct radeon_device *rdev = info->dev->dev_private;
459 uint32_t r;
460
461 r = RREG32(reg*4);
462 return r;
463}
464
771fe6b9
JG		 465int radeon_atombios_init(struct radeon_device *rdev)
466{
61c4b24b
MF		 467 struct card_info *atom_card_info =
468 kzalloc(sizeof(struct card_info), GFP_KERNEL);
469
470 if (!atom_card_info)
471 return -ENOMEM;
472
473 rdev->mode_info.atom_card_info = atom_card_info;
474 atom_card_info->dev = rdev->ddev;
475 atom_card_info->reg_read = cail_reg_read;
476 atom_card_info->reg_write = cail_reg_write;
477 atom_card_info->mc_read = cail_mc_read;
478 atom_card_info->mc_write = cail_mc_write;
479 atom_card_info->pll_read = cail_pll_read;
480 atom_card_info->pll_write = cail_pll_write;
481
482 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
771fe6b9 483 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
d904ef9b 484 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
771fe6b9
JG		 485 return 0;
486}
487
488void radeon_atombios_fini(struct radeon_device *rdev)
489{
4a04a844
JG		 490 if (rdev->mode_info.atom_context) {
491 kfree(rdev->mode_info.atom_context->scratch);
492 kfree(rdev->mode_info.atom_context);
493 }
61c4b24b 494 kfree(rdev->mode_info.atom_card_info);
771fe6b9
JG		 495}
496
497int radeon_combios_init(struct radeon_device *rdev)
498{
499 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
500 return 0;
501}
502
503void radeon_combios_fini(struct radeon_device *rdev)
504{
505}
506
28d52043
DA		 507/* if we get transitioned to only one device, tak VGA back */
508static unsigned int radeon_vga_set_decode(void *cookie, bool state)
509{
510 struct radeon_device *rdev = cookie;
28d52043
DA		 511 radeon_vga_set_state(rdev, state);
512 if (state)
513 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
514 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
515 else
516 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
517}
c1176d6f 518
b574f251
JG		 519void radeon_agp_disable(struct radeon_device *rdev)
520{
521 rdev->flags &= ~RADEON_IS_AGP;
522 if (rdev->family >= CHIP_R600) {
523 DRM_INFO("Forcing AGP to PCIE mode\n");
524 rdev->flags |= RADEON_IS_PCIE;
525 } else if (rdev->family >= CHIP_RV515 ||
526 rdev->family == CHIP_RV380 ||
527 rdev->family == CHIP_RV410 ||
528 rdev->family == CHIP_R423) {
529 DRM_INFO("Forcing AGP to PCIE mode\n");
530 rdev->flags |= RADEON_IS_PCIE;
531 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
532 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
533 } else {
534 DRM_INFO("Forcing AGP to PCI mode\n");
535 rdev->flags |= RADEON_IS_PCI;
536 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
537 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
538 }
539}
771fe6b9
JG		 540
541/*
542 * Radeon device.
543 */
544int radeon_device_init(struct radeon_device *rdev,
545 struct drm_device *ddev,
546 struct pci_dev *pdev,
547 uint32_t flags)
548{
6cf8a3f5 549 int r;
ad49f501 550 int dma_bits;
771fe6b9
JG		 551
552 DRM_INFO("radeon: Initializing kernel modesetting.\n");
553 rdev->shutdown = false;
9f022ddf 554 rdev->dev = &pdev->dev;
771fe6b9
JG		 555 rdev->ddev = ddev;
556 rdev->pdev = pdev;
557 rdev->flags = flags;
558 rdev->family = flags & RADEON_FAMILY_MASK;
559 rdev->is_atom_bios = false;
560 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
561 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
562 rdev->gpu_lockup = false;
733289c2 563 rdev->accel_working = false;
771fe6b9
JG		 564 /* mutex initialization are all done here so we
565 * can recall function without having locking issues */
566 mutex_init(&rdev->cs_mutex);
567 mutex_init(&rdev->ib_pool.mutex);
568 mutex_init(&rdev->cp.mutex);
d8f60cfc
AD		 569 if (rdev->family >= CHIP_R600)
570 spin_lock_init(&rdev->ih.lock);
4c788679 571 mutex_init(&rdev->gem.mutex);
771fe6b9 572 rwlock_init(&rdev->fence_drv.lock);
9f022ddf 573 INIT_LIST_HEAD(&rdev->gem.objects);
771fe6b9 574
d4877cf2
AD		 575 /* setup workqueue */
576 rdev->wq = create_workqueue("radeon");
577 if (rdev->wq == NULL)
578 return -ENOMEM;
579
4aac0473
JG		 580 /* Set asic functions */
581 r = radeon_asic_init(rdev);
582 if (r) {
583 return r;
584 }
585
30256a3f 586 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
b574f251 587 radeon_agp_disable(rdev);
771fe6b9
JG		 588 }
589
ad49f501
DA		 590 /* set DMA mask + need_dma32 flags.
591 * PCIE - can handle 40-bits.
592 * IGP - can handle 40-bits (in theory)
593 * AGP - generally dma32 is safest
594 * PCI - only dma32
595 */
596 rdev->need_dma32 = false;
597 if (rdev->flags & RADEON_IS_AGP)
598 rdev->need_dma32 = true;
599 if (rdev->flags & RADEON_IS_PCI)
600 rdev->need_dma32 = true;
601
602 dma_bits = rdev->need_dma32 ? 32 : 40;
603 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
771fe6b9
JG		 604 if (r) {
605 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
606 }
607
608 /* Registers mapping */
609 /* TODO: block userspace mapping of io register */
610 rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
611 rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
612 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
613 if (rdev->rmmio == NULL) {
614 return -ENOMEM;
615 }
616 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
617 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
618
28d52043 619 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
93239ea1
DA		 620 /* this will fail for cards that aren't VGA class devices, just
621 * ignore it */
622 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
28d52043 623
3ce0a23d 624 r = radeon_init(rdev);
b574f251 625 if (r)
3ce0a23d 626 return r;
3ce0a23d 627
b574f251
JG		 628 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
629 /* Acceleration not working on AGP card try again
630 * with fallback to PCI or PCIE GART
631 */
1a029b76 632 radeon_gpu_reset(rdev);
b574f251
JG		 633 radeon_fini(rdev);
634 radeon_agp_disable(rdev);
635 r = radeon_init(rdev);
4aac0473
JG		 636 if (r)
637 return r;
771fe6b9 638 }
ecc0b326
MD		 639 if (radeon_testing) {
640 radeon_test_moves(rdev);
641 }
771fe6b9
JG		 642 if (radeon_benchmarking) {
643 radeon_benchmark(rdev);
644 }
6cf8a3f5 645 return 0;
771fe6b9
JG		 646}
647
648void radeon_device_fini(struct radeon_device *rdev)
649{
771fe6b9
JG		 650 DRM_INFO("radeon: finishing device.\n");
651 rdev->shutdown = true;
62a8ea3f 652 radeon_fini(rdev);
d4877cf2 653 destroy_workqueue(rdev->wq);
c1176d6f 654 vga_client_register(rdev->pdev, NULL, NULL, NULL);
771fe6b9
JG		 655 iounmap(rdev->rmmio);
656 rdev->rmmio = NULL;
657}
658
659
660/*
661 * Suspend & resume.
662 */
663int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
664{
665 struct radeon_device *rdev = dev->dev_private;
666 struct drm_crtc *crtc;
4c788679 667 int r;
771fe6b9
JG		 668
669 if (dev == NULL || rdev == NULL) {
670 return -ENODEV;
671 }
672 if (state.event == PM_EVENT_PRETHAW) {
673 return 0;
674 }
675 /* unpin the front buffers */
676 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
677 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
4c788679 678 struct radeon_bo *robj;
771fe6b9
JG		 679
680 if (rfb == NULL || rfb->obj == NULL) {
681 continue;
682 }
683 robj = rfb->obj->driver_private;
4c788679
JG		 684 if (robj != rdev->fbdev_rbo) {
685 r = radeon_bo_reserve(robj, false);
686 if (unlikely(r == 0)) {
687 radeon_bo_unpin(robj);
688 radeon_bo_unreserve(robj);
689 }
771fe6b9
JG		 690 }
691 }
692 /* evict vram memory */
4c788679 693 radeon_bo_evict_vram(rdev);
771fe6b9
JG		 694 /* wait for gpu to finish processing current batch */
695 radeon_fence_wait_last(rdev);
696
f657c2a7
YZ		 697 radeon_save_bios_scratch_regs(rdev);
698
62a8ea3f 699 radeon_suspend(rdev);
d4877cf2 700 radeon_hpd_fini(rdev);
771fe6b9 701 /* evict remaining vram memory */
4c788679 702 radeon_bo_evict_vram(rdev);
771fe6b9 703
771fe6b9
JG		 704 pci_save_state(dev->pdev);
705 if (state.event == PM_EVENT_SUSPEND) {
706 /* Shut down the device */
707 pci_disable_device(dev->pdev);
708 pci_set_power_state(dev->pdev, PCI_D3hot);
709 }
710 acquire_console_sem();
711 fb_set_suspend(rdev->fbdev_info, 1);
712 release_console_sem();
713 return 0;
714}
715
716int radeon_resume_kms(struct drm_device *dev)
717{
718 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 719
720 acquire_console_sem();
721 pci_set_power_state(dev->pdev, PCI_D0);
722 pci_restore_state(dev->pdev);
723 if (pci_enable_device(dev->pdev)) {
724 release_console_sem();
725 return -1;
726 }
727 pci_set_master(dev->pdev);
0ebf1717
DA		 728 /* resume AGP if in use */
729 radeon_agp_resume(rdev);
62a8ea3f 730 radeon_resume(rdev);
f657c2a7 731 radeon_restore_bios_scratch_regs(rdev);
771fe6b9
JG		 732 fb_set_suspend(rdev->fbdev_info, 0);
733 release_console_sem();
734
d4877cf2
AD		 735 /* reset hpd state */
736 radeon_hpd_init(rdev);
771fe6b9
JG		 737 /* blat the mode back in */
738 drm_helper_resume_force_mode(dev);
739 return 0;
740}
741
742
743/*
744 * Debugfs
745 */
746struct radeon_debugfs {
747 struct drm_info_list *files;
748 unsigned num_files;
749};
750static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
751static unsigned _radeon_debugfs_count = 0;
752
753int radeon_debugfs_add_files(struct radeon_device *rdev,
754 struct drm_info_list *files,
755 unsigned nfiles)
756{
757 unsigned i;
758
759 for (i = 0; i < _radeon_debugfs_count; i++) {
760 if (_radeon_debugfs[i].files == files) {
761 /* Already registered */
762 return 0;
763 }
764 }
765 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
766 DRM_ERROR("Reached maximum number of debugfs files.\n");
767 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
768 return -EINVAL;
769 }
770 _radeon_debugfs[_radeon_debugfs_count].files = files;
771 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
772 _radeon_debugfs_count++;
773#if defined(CONFIG_DEBUG_FS)
774 drm_debugfs_create_files(files, nfiles,
775 rdev->ddev->control->debugfs_root,
776 rdev->ddev->control);
777 drm_debugfs_create_files(files, nfiles,
778 rdev->ddev->primary->debugfs_root,
779 rdev->ddev->primary);
780#endif
781 return 0;
782}
783
784#if defined(CONFIG_DEBUG_FS)
785int radeon_debugfs_init(struct drm_minor *minor)
786{
787 return 0;
788}
789
790void radeon_debugfs_cleanup(struct drm_minor *minor)
791{
792 unsigned i;
793
794 for (i = 0; i < _radeon_debugfs_count; i++) {
795 drm_debugfs_remove_files(_radeon_debugfs[i].files,
796 _radeon_debugfs[i].num_files, minor);
797 }
798}
799#endif
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