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drm/radeon/kms: dont't pass a radeon_connector to radeon_i2c_do_lock()
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06
AD		 52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id);
771fe6b9
JG		 54
55/* from radeon_legacy_encoder.c */
56extern void
57radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
58 uint32_t supported_device);
59
60/* old legacy ATI BIOS routines */
61
62/* COMBIOS table offsets */
63enum radeon_combios_table_offset {
64 /* absolute offset tables */
65 COMBIOS_ASIC_INIT_1_TABLE,
66 COMBIOS_BIOS_SUPPORT_TABLE,
67 COMBIOS_DAC_PROGRAMMING_TABLE,
68 COMBIOS_MAX_COLOR_DEPTH_TABLE,
69 COMBIOS_CRTC_INFO_TABLE,
70 COMBIOS_PLL_INFO_TABLE,
71 COMBIOS_TV_INFO_TABLE,
72 COMBIOS_DFP_INFO_TABLE,
73 COMBIOS_HW_CONFIG_INFO_TABLE,
74 COMBIOS_MULTIMEDIA_INFO_TABLE,
75 COMBIOS_TV_STD_PATCH_TABLE,
76 COMBIOS_LCD_INFO_TABLE,
77 COMBIOS_MOBILE_INFO_TABLE,
78 COMBIOS_PLL_INIT_TABLE,
79 COMBIOS_MEM_CONFIG_TABLE,
80 COMBIOS_SAVE_MASK_TABLE,
81 COMBIOS_HARDCODED_EDID_TABLE,
82 COMBIOS_ASIC_INIT_2_TABLE,
83 COMBIOS_CONNECTOR_INFO_TABLE,
84 COMBIOS_DYN_CLK_1_TABLE,
85 COMBIOS_RESERVED_MEM_TABLE,
86 COMBIOS_EXT_TMDS_INFO_TABLE,
87 COMBIOS_MEM_CLK_INFO_TABLE,
88 COMBIOS_EXT_DAC_INFO_TABLE,
89 COMBIOS_MISC_INFO_TABLE,
90 COMBIOS_CRT_INFO_TABLE,
91 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
92 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
93 COMBIOS_FAN_SPEED_INFO_TABLE,
94 COMBIOS_OVERDRIVE_INFO_TABLE,
95 COMBIOS_OEM_INFO_TABLE,
96 COMBIOS_DYN_CLK_2_TABLE,
97 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
98 COMBIOS_I2C_INFO_TABLE,
99 /* relative offset tables */
100 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
101 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
102 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
103 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
104 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
105 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
106 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
110 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
111};
112
113enum radeon_combios_ddc {
114 DDC_NONE_DETECTED,
115 DDC_MONID,
116 DDC_DVI,
117 DDC_VGA,
118 DDC_CRT2,
119 DDC_LCD,
120 DDC_GPIO,
121};
122
123enum radeon_combios_connector {
124 CONNECTOR_NONE_LEGACY,
125 CONNECTOR_PROPRIETARY_LEGACY,
126 CONNECTOR_CRT_LEGACY,
127 CONNECTOR_DVI_I_LEGACY,
128 CONNECTOR_DVI_D_LEGACY,
129 CONNECTOR_CTV_LEGACY,
130 CONNECTOR_STV_LEGACY,
131 CONNECTOR_UNSUPPORTED_LEGACY
132};
133
134const int legacy_connector_convert[] = {
135 DRM_MODE_CONNECTOR_Unknown,
136 DRM_MODE_CONNECTOR_DVID,
137 DRM_MODE_CONNECTOR_VGA,
138 DRM_MODE_CONNECTOR_DVII,
139 DRM_MODE_CONNECTOR_DVID,
140 DRM_MODE_CONNECTOR_Composite,
141 DRM_MODE_CONNECTOR_SVIDEO,
142 DRM_MODE_CONNECTOR_Unknown,
143};
144
145static uint16_t combios_get_table_offset(struct drm_device *dev,
146 enum radeon_combios_table_offset table)
147{
148 struct radeon_device *rdev = dev->dev_private;
149 int rev;
150 uint16_t offset = 0, check_offset;
151
152 switch (table) {
153 /* absolute offset tables */
154 case COMBIOS_ASIC_INIT_1_TABLE:
155 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
156 if (check_offset)
157 offset = check_offset;
158 break;
159 case COMBIOS_BIOS_SUPPORT_TABLE:
160 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
161 if (check_offset)
162 offset = check_offset;
163 break;
164 case COMBIOS_DAC_PROGRAMMING_TABLE:
165 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
166 if (check_offset)
167 offset = check_offset;
168 break;
169 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
170 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
171 if (check_offset)
172 offset = check_offset;
173 break;
174 case COMBIOS_CRTC_INFO_TABLE:
175 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
176 if (check_offset)
177 offset = check_offset;
178 break;
179 case COMBIOS_PLL_INFO_TABLE:
180 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
181 if (check_offset)
182 offset = check_offset;
183 break;
184 case COMBIOS_TV_INFO_TABLE:
185 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
186 if (check_offset)
187 offset = check_offset;
188 break;
189 case COMBIOS_DFP_INFO_TABLE:
190 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
191 if (check_offset)
192 offset = check_offset;
193 break;
194 case COMBIOS_HW_CONFIG_INFO_TABLE:
195 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
196 if (check_offset)
197 offset = check_offset;
198 break;
199 case COMBIOS_MULTIMEDIA_INFO_TABLE:
200 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
201 if (check_offset)
202 offset = check_offset;
203 break;
204 case COMBIOS_TV_STD_PATCH_TABLE:
205 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
206 if (check_offset)
207 offset = check_offset;
208 break;
209 case COMBIOS_LCD_INFO_TABLE:
210 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
211 if (check_offset)
212 offset = check_offset;
213 break;
214 case COMBIOS_MOBILE_INFO_TABLE:
215 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
216 if (check_offset)
217 offset = check_offset;
218 break;
219 case COMBIOS_PLL_INIT_TABLE:
220 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
221 if (check_offset)
222 offset = check_offset;
223 break;
224 case COMBIOS_MEM_CONFIG_TABLE:
225 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
226 if (check_offset)
227 offset = check_offset;
228 break;
229 case COMBIOS_SAVE_MASK_TABLE:
230 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
231 if (check_offset)
232 offset = check_offset;
233 break;
234 case COMBIOS_HARDCODED_EDID_TABLE:
235 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
236 if (check_offset)
237 offset = check_offset;
238 break;
239 case COMBIOS_ASIC_INIT_2_TABLE:
240 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
241 if (check_offset)
242 offset = check_offset;
243 break;
244 case COMBIOS_CONNECTOR_INFO_TABLE:
245 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
246 if (check_offset)
247 offset = check_offset;
248 break;
249 case COMBIOS_DYN_CLK_1_TABLE:
250 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
251 if (check_offset)
252 offset = check_offset;
253 break;
254 case COMBIOS_RESERVED_MEM_TABLE:
255 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
256 if (check_offset)
257 offset = check_offset;
258 break;
259 case COMBIOS_EXT_TMDS_INFO_TABLE:
260 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
261 if (check_offset)
262 offset = check_offset;
263 break;
264 case COMBIOS_MEM_CLK_INFO_TABLE:
265 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
266 if (check_offset)
267 offset = check_offset;
268 break;
269 case COMBIOS_EXT_DAC_INFO_TABLE:
270 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
271 if (check_offset)
272 offset = check_offset;
273 break;
274 case COMBIOS_MISC_INFO_TABLE:
275 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
276 if (check_offset)
277 offset = check_offset;
278 break;
279 case COMBIOS_CRT_INFO_TABLE:
280 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
281 if (check_offset)
282 offset = check_offset;
283 break;
284 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
285 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
286 if (check_offset)
287 offset = check_offset;
288 break;
289 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
290 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
291 if (check_offset)
292 offset = check_offset;
293 break;
294 case COMBIOS_FAN_SPEED_INFO_TABLE:
295 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
296 if (check_offset)
297 offset = check_offset;
298 break;
299 case COMBIOS_OVERDRIVE_INFO_TABLE:
300 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
301 if (check_offset)
302 offset = check_offset;
303 break;
304 case COMBIOS_OEM_INFO_TABLE:
305 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
306 if (check_offset)
307 offset = check_offset;
308 break;
309 case COMBIOS_DYN_CLK_2_TABLE:
310 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
311 if (check_offset)
312 offset = check_offset;
313 break;
314 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
315 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
316 if (check_offset)
317 offset = check_offset;
318 break;
319 case COMBIOS_I2C_INFO_TABLE:
320 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
321 if (check_offset)
322 offset = check_offset;
323 break;
324 /* relative offset tables */
325 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
326 check_offset =
327 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
328 if (check_offset) {
329 rev = RBIOS8(check_offset);
330 if (rev > 0) {
331 check_offset = RBIOS16(check_offset + 0x3);
332 if (check_offset)
333 offset = check_offset;
334 }
335 }
336 break;
337 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
338 check_offset =
339 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
340 if (check_offset) {
341 rev = RBIOS8(check_offset);
342 if (rev > 0) {
343 check_offset = RBIOS16(check_offset + 0x5);
344 if (check_offset)
345 offset = check_offset;
346 }
347 }
348 break;
349 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
350 check_offset =
351 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
352 if (check_offset) {
353 rev = RBIOS8(check_offset);
354 if (rev > 0) {
355 check_offset = RBIOS16(check_offset + 0x7);
356 if (check_offset)
357 offset = check_offset;
358 }
359 }
360 break;
361 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
362 check_offset =
363 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
364 if (check_offset) {
365 rev = RBIOS8(check_offset);
366 if (rev == 2) {
367 check_offset = RBIOS16(check_offset + 0x9);
368 if (check_offset)
369 offset = check_offset;
370 }
371 }
372 break;
373 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
374 check_offset =
375 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
376 if (check_offset) {
377 while (RBIOS8(check_offset++));
378 check_offset += 2;
379 if (check_offset)
380 offset = check_offset;
381 }
382 break;
383 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
384 check_offset =
385 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
386 if (check_offset) {
387 check_offset = RBIOS16(check_offset + 0x11);
388 if (check_offset)
389 offset = check_offset;
390 }
391 break;
392 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
393 check_offset =
394 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
395 if (check_offset) {
396 check_offset = RBIOS16(check_offset + 0x13);
397 if (check_offset)
398 offset = check_offset;
399 }
400 break;
401 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
402 check_offset =
403 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
404 if (check_offset) {
405 check_offset = RBIOS16(check_offset + 0x15);
406 if (check_offset)
407 offset = check_offset;
408 }
409 break;
410 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
411 check_offset =
412 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
413 if (check_offset) {
414 check_offset = RBIOS16(check_offset + 0x17);
415 if (check_offset)
416 offset = check_offset;
417 }
418 break;
419 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
420 check_offset =
421 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
422 if (check_offset) {
423 check_offset = RBIOS16(check_offset + 0x2);
424 if (check_offset)
425 offset = check_offset;
426 }
427 break;
428 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
429 check_offset =
430 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
431 if (check_offset) {
432 check_offset = RBIOS16(check_offset + 0x4);
433 if (check_offset)
434 offset = check_offset;
435 }
436 break;
437 default:
438 break;
439 }
440
441 return offset;
442
443}
444
445struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
446{
447 struct radeon_i2c_bus_rec i2c;
448
449 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
450 i2c.mask_data_mask = RADEON_GPIO_EN_0;
451 i2c.a_clk_mask = RADEON_GPIO_A_1;
452 i2c.a_data_mask = RADEON_GPIO_A_0;
453 i2c.put_clk_mask = RADEON_GPIO_EN_1;
454 i2c.put_data_mask = RADEON_GPIO_EN_0;
455 i2c.get_clk_mask = RADEON_GPIO_Y_1;
456 i2c.get_data_mask = RADEON_GPIO_Y_0;
457 if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
458 (ddc_line == RADEON_MDGPIO_EN_REG)) {
459 i2c.mask_clk_reg = ddc_line;
460 i2c.mask_data_reg = ddc_line;
461 i2c.a_clk_reg = ddc_line;
462 i2c.a_data_reg = ddc_line;
463 i2c.put_clk_reg = ddc_line;
464 i2c.put_data_reg = ddc_line;
465 i2c.get_clk_reg = ddc_line + 4;
466 i2c.get_data_reg = ddc_line + 4;
467 } else {
468 i2c.mask_clk_reg = ddc_line;
469 i2c.mask_data_reg = ddc_line;
470 i2c.a_clk_reg = ddc_line;
471 i2c.a_data_reg = ddc_line;
472 i2c.put_clk_reg = ddc_line;
473 i2c.put_data_reg = ddc_line;
474 i2c.get_clk_reg = ddc_line;
475 i2c.get_data_reg = ddc_line;
476 }
477
478 if (ddc_line)
479 i2c.valid = true;
480 else
481 i2c.valid = false;
482
483 return i2c;
484}
485
486bool radeon_combios_get_clock_info(struct drm_device *dev)
487{
488 struct radeon_device *rdev = dev->dev_private;
489 uint16_t pll_info;
490 struct radeon_pll *p1pll = &rdev->clock.p1pll;
491 struct radeon_pll *p2pll = &rdev->clock.p2pll;
492 struct radeon_pll *spll = &rdev->clock.spll;
493 struct radeon_pll *mpll = &rdev->clock.mpll;
494 int8_t rev;
495 uint16_t sclk, mclk;
496
497 if (rdev->bios == NULL)
498 return NULL;
499
500 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
501 if (pll_info) {
502 rev = RBIOS8(pll_info);
503
504 /* pixel clocks */
505 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
506 p1pll->reference_div = RBIOS16(pll_info + 0x10);
507 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
508 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
509
510 if (rev > 9) {
511 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
512 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
513 } else {
514 p1pll->pll_in_min = 40;
515 p1pll->pll_in_max = 500;
516 }
517 *p2pll = *p1pll;
518
519 /* system clock */
520 spll->reference_freq = RBIOS16(pll_info + 0x1a);
521 spll->reference_div = RBIOS16(pll_info + 0x1c);
522 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
523 spll->pll_out_max = RBIOS32(pll_info + 0x22);
524
525 if (rev > 10) {
526 spll->pll_in_min = RBIOS32(pll_info + 0x48);
527 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
528 } else {
529 /* ??? */
530 spll->pll_in_min = 40;
531 spll->pll_in_max = 500;
532 }
533
534 /* memory clock */
535 mpll->reference_freq = RBIOS16(pll_info + 0x26);
536 mpll->reference_div = RBIOS16(pll_info + 0x28);
537 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
538 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
539
540 if (rev > 10) {
541 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
542 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
543 } else {
544 /* ??? */
545 mpll->pll_in_min = 40;
546 mpll->pll_in_max = 500;
547 }
548
549 /* default sclk/mclk */
550 sclk = RBIOS16(pll_info + 0xa);
551 mclk = RBIOS16(pll_info + 0x8);
552 if (sclk == 0)
553 sclk = 200 * 100;
554 if (mclk == 0)
555 mclk = 200 * 100;
556
557 rdev->clock.default_sclk = sclk;
558 rdev->clock.default_mclk = mclk;
559
560 return true;
561 }
562 return false;
563}
564
565struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
566 radeon_encoder
567 *encoder)
568{
569 struct drm_device *dev = encoder->base.dev;
570 struct radeon_device *rdev = dev->dev_private;
571 uint16_t dac_info;
572 uint8_t rev, bg, dac;
573 struct radeon_encoder_primary_dac *p_dac = NULL;
574
575 if (rdev->bios == NULL)
576 return NULL;
577
578 /* check CRT table */
579 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
580 if (dac_info) {
581 p_dac =
582 kzalloc(sizeof(struct radeon_encoder_primary_dac),
583 GFP_KERNEL);
584
585 if (!p_dac)
586 return NULL;
587
588 rev = RBIOS8(dac_info) & 0x3;
589 if (rev < 2) {
590 bg = RBIOS8(dac_info + 0x2) & 0xf;
591 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
592 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
593 } else {
594 bg = RBIOS8(dac_info + 0x2) & 0xf;
595 dac = RBIOS8(dac_info + 0x3) & 0xf;
596 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
597 }
598
599 }
600
601 return p_dac;
602}
603
604static enum radeon_tv_std
605radeon_combios_get_tv_info(struct radeon_encoder *encoder)
606{
607 struct drm_device *dev = encoder->base.dev;
608 struct radeon_device *rdev = dev->dev_private;
609 uint16_t tv_info;
610 enum radeon_tv_std tv_std = TV_STD_NTSC;
611
612 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
613 if (tv_info) {
614 if (RBIOS8(tv_info + 6) == 'T') {
615 switch (RBIOS8(tv_info + 7) & 0xf) {
616 case 1:
617 tv_std = TV_STD_NTSC;
618 DRM_INFO("Default TV standard: NTSC\n");
619 break;
620 case 2:
621 tv_std = TV_STD_PAL;
622 DRM_INFO("Default TV standard: PAL\n");
623 break;
624 case 3:
625 tv_std = TV_STD_PAL_M;
626 DRM_INFO("Default TV standard: PAL-M\n");
627 break;
628 case 4:
629 tv_std = TV_STD_PAL_60;
630 DRM_INFO("Default TV standard: PAL-60\n");
631 break;
632 case 5:
633 tv_std = TV_STD_NTSC_J;
634 DRM_INFO("Default TV standard: NTSC-J\n");
635 break;
636 case 6:
637 tv_std = TV_STD_SCART_PAL;
638 DRM_INFO("Default TV standard: SCART-PAL\n");
639 break;
640 default:
641 tv_std = TV_STD_NTSC;
642 DRM_INFO
643 ("Unknown TV standard; defaulting to NTSC\n");
644 break;
645 }
646
647 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
648 case 0:
649 DRM_INFO("29.498928713 MHz TV ref clk\n");
650 break;
651 case 1:
652 DRM_INFO("28.636360000 MHz TV ref clk\n");
653 break;
654 case 2:
655 DRM_INFO("14.318180000 MHz TV ref clk\n");
656 break;
657 case 3:
658 DRM_INFO("27.000000000 MHz TV ref clk\n");
659 break;
660 default:
661 break;
662 }
663 }
664 }
665 return tv_std;
666}
667
668static const uint32_t default_tvdac_adj[CHIP_LAST] = {
669 0x00000000, /* r100 */
670 0x00280000, /* rv100 */
671 0x00000000, /* rs100 */
672 0x00880000, /* rv200 */
673 0x00000000, /* rs200 */
674 0x00000000, /* r200 */
675 0x00770000, /* rv250 */
676 0x00290000, /* rs300 */
677 0x00560000, /* rv280 */
678 0x00780000, /* r300 */
679 0x00770000, /* r350 */
680 0x00780000, /* rv350 */
681 0x00780000, /* rv380 */
682 0x01080000, /* r420 */
683 0x01080000, /* r423 */
684 0x01080000, /* rv410 */
685 0x00780000, /* rs400 */
686 0x00780000, /* rs480 */
687};
688
6a719e05
DA		 689static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
690 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 691{
771fe6b9
JG		 692 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
693 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
694 tv_dac->ps2_tvdac_adj = 0x00880000;
695 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
696 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 697 return;
771fe6b9
JG		 698}
699
700struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
701 radeon_encoder
702 *encoder)
703{
704 struct drm_device *dev = encoder->base.dev;
705 struct radeon_device *rdev = dev->dev_private;
706 uint16_t dac_info;
707 uint8_t rev, bg, dac;
708 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 709 int found = 0;
710
711 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
712 if (!tv_dac)
713 return NULL;
771fe6b9
JG		 714
715 if (rdev->bios == NULL)
6a719e05 716 goto out;
771fe6b9
JG		 717
718 /* first check TV table */
719 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
720 if (dac_info) {
771fe6b9
JG		 721 rev = RBIOS8(dac_info + 0x3);
722 if (rev > 4) {
723 bg = RBIOS8(dac_info + 0xc) & 0xf;
724 dac = RBIOS8(dac_info + 0xd) & 0xf;
725 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
726
727 bg = RBIOS8(dac_info + 0xe) & 0xf;
728 dac = RBIOS8(dac_info + 0xf) & 0xf;
729 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
730
731 bg = RBIOS8(dac_info + 0x10) & 0xf;
732 dac = RBIOS8(dac_info + 0x11) & 0xf;
733 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 734 found = 1;
771fe6b9
JG		 735 } else if (rev > 1) {
736 bg = RBIOS8(dac_info + 0xc) & 0xf;
737 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
738 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
739
740 bg = RBIOS8(dac_info + 0xd) & 0xf;
741 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
742 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
743
744 bg = RBIOS8(dac_info + 0xe) & 0xf;
745 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
746 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 747 found = 1;
771fe6b9 748 }
771fe6b9 749 tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
6a719e05
DA		 750 }
751 if (!found) {
771fe6b9
JG		 752 /* then check CRT table */
753 dac_info =
754 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
755 if (dac_info) {
771fe6b9
JG		 756 rev = RBIOS8(dac_info) & 0x3;
757 if (rev < 2) {
758 bg = RBIOS8(dac_info + 0x3) & 0xf;
759 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
760 tv_dac->ps2_tvdac_adj =
761 (bg << 16) | (dac << 20);
762 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
763 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 764 found = 1;
771fe6b9
JG		 765 } else {
766 bg = RBIOS8(dac_info + 0x4) & 0xf;
767 dac = RBIOS8(dac_info + 0x5) & 0xf;
768 tv_dac->ps2_tvdac_adj =
769 (bg << 16) | (dac << 20);
770 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
771 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 772 found = 1;
771fe6b9 773 }
6fe7ac3f
AD		 774 } else {
775 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 776 }
777 }
778
6a719e05
DA		 779out:
780 if (!found) /* fallback to defaults */
781 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
782
771fe6b9
JG		 783 return tv_dac;
784}
785
786static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
787 radeon_device
788 *rdev)
789{
790 struct radeon_encoder_lvds *lvds = NULL;
791 uint32_t fp_vert_stretch, fp_horz_stretch;
792 uint32_t ppll_div_sel, ppll_val;
8b5c7444 793 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 794
795 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
796
797 if (!lvds)
798 return NULL;
799
800 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
801 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
802
8b5c7444
MD		 803 /* These should be fail-safe defaults, fingers crossed */
804 lvds->panel_pwr_delay = 200;
805 lvds->panel_vcc_delay = 2000;
806
807 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
808 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
809 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
810
771fe6b9 811 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 812 lvds->native_mode.vdisplay =
771fe6b9
JG		 813 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
814 RADEON_VERT_PANEL_SHIFT) + 1;
815 else
de2103e4 816 lvds->native_mode.vdisplay =
771fe6b9
JG		 817 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
818
819 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 820 lvds->native_mode.hdisplay =
771fe6b9
JG		 821 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
822 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
823 else
de2103e4 824 lvds->native_mode.hdisplay =
771fe6b9
JG		 825 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
826
de2103e4
AD		 827 if ((lvds->native_mode.hdisplay < 640) ||
828 (lvds->native_mode.vdisplay < 480)) {
829 lvds->native_mode.hdisplay = 640;
830 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 831 }
832
833 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
834 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
835 if ((ppll_val & 0x000707ff) == 0x1bb)
836 lvds->use_bios_dividers = false;
837 else {
838 lvds->panel_ref_divider =
839 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
840 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
841 lvds->panel_fb_divider = ppll_val & 0x7ff;
842
843 if ((lvds->panel_ref_divider != 0) &&
844 (lvds->panel_fb_divider > 3))
845 lvds->use_bios_dividers = true;
846 }
847 lvds->panel_vcc_delay = 200;
848
849 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 850 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
851 lvds->native_mode.vdisplay);
771fe6b9
JG		 852
853 return lvds;
854}
855
856struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
857 *encoder)
858{
859 struct drm_device *dev = encoder->base.dev;
860 struct radeon_device *rdev = dev->dev_private;
861 uint16_t lcd_info;
862 uint32_t panel_setup;
863 char stmp[30];
864 int tmp, i;
865 struct radeon_encoder_lvds *lvds = NULL;
866
8dfaa8a7
MD		 867 if (rdev->bios == NULL) {
868 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
869 goto out;
870 }
771fe6b9
JG		 871
872 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
873
874 if (lcd_info) {
875 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
876
877 if (!lvds)
878 return NULL;
879
880 for (i = 0; i < 24; i++)
881 stmp[i] = RBIOS8(lcd_info + i + 1);
882 stmp[24] = 0;
883
884 DRM_INFO("Panel ID String: %s\n", stmp);
885
de2103e4
AD		 886 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
887 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 888
de2103e4
AD		 889 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
890 lvds->native_mode.vdisplay);
771fe6b9
JG		 891
892 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
893 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
894 lvds->panel_vcc_delay = 2000;
895
896 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
897 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
898 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
899
900 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
901 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
902 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
903 if ((lvds->panel_ref_divider != 0) &&
904 (lvds->panel_fb_divider > 3))
905 lvds->use_bios_dividers = true;
906
907 panel_setup = RBIOS32(lcd_info + 0x39);
908 lvds->lvds_gen_cntl = 0xff00;
909 if (panel_setup & 0x1)
910 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
911
912 if ((panel_setup >> 4) & 0x1)
913 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
914
915 switch ((panel_setup >> 8) & 0x7) {
916 case 0:
917 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
918 break;
919 case 1:
920 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
921 break;
922 case 2:
923 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
924 break;
925 default:
926 break;
927 }
928
929 if ((panel_setup >> 16) & 0x1)
930 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
931
932 if ((panel_setup >> 17) & 0x1)
933 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
934
935 if ((panel_setup >> 18) & 0x1)
936 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
937
938 if ((panel_setup >> 23) & 0x1)
939 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
940
941 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
942
943 for (i = 0; i < 32; i++) {
944 tmp = RBIOS16(lcd_info + 64 + i * 2);
945 if (tmp == 0)
946 break;
947
de2103e4 948 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
771fe6b9 949 (RBIOS16(tmp + 2) ==
de2103e4
AD		 950 lvds->native_mode.vdisplay)) {
951 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
952 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
953 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
954 RBIOS16(tmp + 21)) * 8;
955
956 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
957 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
958 lvds->native_mode.vsync_end =
959 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
960 (RBIOS16(tmp + 28) & 0x7ff);
961
962 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 963 lvds->native_mode.flags = 0;
de2103e4
AD		 964 /* set crtc values */
965 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
966
771fe6b9
JG		 967 }
968 }
6fe7ac3f 969 } else {
771fe6b9 970 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 971 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 972 }
8dfaa8a7
MD		 973out:
974 if (lvds)
975 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 976 return lvds;
977}
978
979static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
980 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
981 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
982 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
983 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
984 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
985 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
986 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
987 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
988 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
989 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
990 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
991 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
992 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
993 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
994 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
995 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
996 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS400 */
997 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS480 */
998};
999
445282db
DA		 1000bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1001 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1002{
445282db
DA		 1003 struct drm_device *dev = encoder->base.dev;
1004 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1005 int i;
771fe6b9
JG		 1006
1007 for (i = 0; i < 4; i++) {
1008 tmds->tmds_pll[i].value =
445282db 1009 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1010 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1011 }
1012
445282db 1013 return true;
771fe6b9
JG		 1014}
1015
445282db
DA		 1016bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1017 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1018{
1019 struct drm_device *dev = encoder->base.dev;
1020 struct radeon_device *rdev = dev->dev_private;
1021 uint16_t tmds_info;
1022 int i, n;
1023 uint8_t ver;
771fe6b9
JG		 1024
1025 if (rdev->bios == NULL)
445282db 1026 return false;
771fe6b9
JG		 1027
1028 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1029
1030 if (tmds_info) {
771fe6b9
JG		 1031
1032 ver = RBIOS8(tmds_info);
1033 DRM_INFO("DFP table revision: %d\n", ver);
1034 if (ver == 3) {
1035 n = RBIOS8(tmds_info + 5) + 1;
1036 if (n > 4)
1037 n = 4;
1038 for (i = 0; i < n; i++) {
1039 tmds->tmds_pll[i].value =
1040 RBIOS32(tmds_info + i * 10 + 0x08);
1041 tmds->tmds_pll[i].freq =
1042 RBIOS16(tmds_info + i * 10 + 0x10);
1043 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1044 tmds->tmds_pll[i].freq,
1045 tmds->tmds_pll[i].value);
1046 }
1047 } else if (ver == 4) {
1048 int stride = 0;
1049 n = RBIOS8(tmds_info + 5) + 1;
1050 if (n > 4)
1051 n = 4;
1052 for (i = 0; i < n; i++) {
1053 tmds->tmds_pll[i].value =
1054 RBIOS32(tmds_info + stride + 0x08);
1055 tmds->tmds_pll[i].freq =
1056 RBIOS16(tmds_info + stride + 0x10);
1057 if (i == 0)
1058 stride += 10;
1059 else
1060 stride += 6;
1061 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1062 tmds->tmds_pll[i].freq,
1063 tmds->tmds_pll[i].value);
1064 }
1065 }
1066 } else
1067 DRM_INFO("No TMDS info found in BIOS\n");
445282db
DA		 1068 return true;
1069}
1070
1071struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
1072{
1073 struct radeon_encoder_int_tmds *tmds = NULL;
1074 bool ret;
1075
1076 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1077
1078 if (!tmds)
1079 return NULL;
1080
1081 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1082 if (ret == false)
1083 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1084
771fe6b9
JG		 1085 return tmds;
1086}
1087
1088void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
1089{
1090 struct drm_device *dev = encoder->base.dev;
1091 struct radeon_device *rdev = dev->dev_private;
1092 uint16_t ext_tmds_info;
1093 uint8_t ver;
1094
1095 if (rdev->bios == NULL)
1096 return;
1097
1098 ext_tmds_info =
1099 combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1100 if (ext_tmds_info) {
1101 ver = RBIOS8(ext_tmds_info);
1102 DRM_INFO("External TMDS Table revision: %d\n", ver);
1103 // TODO
1104 }
1105}
1106
1107bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1108{
1109 struct radeon_device *rdev = dev->dev_private;
1110 struct radeon_i2c_bus_rec ddc_i2c;
1111
1112 rdev->mode_info.connector_table = radeon_connector_table;
1113 if (rdev->mode_info.connector_table == CT_NONE) {
1114#ifdef CONFIG_PPC_PMAC
1115 if (machine_is_compatible("PowerBook3,3")) {
1116 /* powerbook with VGA */
1117 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1118 } else if (machine_is_compatible("PowerBook3,4") ||
1119 machine_is_compatible("PowerBook3,5")) {
1120 /* powerbook with internal tmds */
1121 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1122 } else if (machine_is_compatible("PowerBook5,1") ||
1123 machine_is_compatible("PowerBook5,2") ||
1124 machine_is_compatible("PowerBook5,3") ||
1125 machine_is_compatible("PowerBook5,4") ||
1126 machine_is_compatible("PowerBook5,5")) {
1127 /* powerbook with external single link tmds (sil164) */
1128 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1129 } else if (machine_is_compatible("PowerBook5,6")) {
1130 /* powerbook with external dual or single link tmds */
1131 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1132 } else if (machine_is_compatible("PowerBook5,7") ||
1133 machine_is_compatible("PowerBook5,8") ||
1134 machine_is_compatible("PowerBook5,9")) {
1135 /* PowerBook6,2 ? */
1136 /* powerbook with external dual link tmds (sil1178?) */
1137 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1138 } else if (machine_is_compatible("PowerBook4,1") ||
1139 machine_is_compatible("PowerBook4,2") ||
1140 machine_is_compatible("PowerBook4,3") ||
1141 machine_is_compatible("PowerBook6,3") ||
1142 machine_is_compatible("PowerBook6,5") ||
1143 machine_is_compatible("PowerBook6,7")) {
1144 /* ibook */
1145 rdev->mode_info.connector_table = CT_IBOOK;
1146 } else if (machine_is_compatible("PowerMac4,4")) {
1147 /* emac */
1148 rdev->mode_info.connector_table = CT_EMAC;
1149 } else if (machine_is_compatible("PowerMac10,1")) {
1150 /* mini with internal tmds */
1151 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1152 } else if (machine_is_compatible("PowerMac10,2")) {
1153 /* mini with external tmds */
1154 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1155 } else if (machine_is_compatible("PowerMac12,1")) {
1156 /* PowerMac8,1 ? */
1157 /* imac g5 isight */
1158 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1159 } else
1160#endif /* CONFIG_PPC_PMAC */
1161 rdev->mode_info.connector_table = CT_GENERIC;
1162 }
1163
1164 switch (rdev->mode_info.connector_table) {
1165 case CT_GENERIC:
1166 DRM_INFO("Connector Table: %d (generic)\n",
1167 rdev->mode_info.connector_table);
1168 /* these are the most common settings */
1169 if (rdev->flags & RADEON_SINGLE_CRTC) {
1170 /* VGA - primary dac */
1171 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1172 radeon_add_legacy_encoder(dev,
1173 radeon_get_encoder_id(dev,
1174 ATOM_DEVICE_CRT1_SUPPORT,
1175 1),
1176 ATOM_DEVICE_CRT1_SUPPORT);
1177 radeon_add_legacy_connector(dev, 0,
1178 ATOM_DEVICE_CRT1_SUPPORT,
1179 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1180 &ddc_i2c,
1181 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1182 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1183 /* LVDS */
1184 ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
1185 radeon_add_legacy_encoder(dev,
1186 radeon_get_encoder_id(dev,
1187 ATOM_DEVICE_LCD1_SUPPORT,
1188 0),
1189 ATOM_DEVICE_LCD1_SUPPORT);
1190 radeon_add_legacy_connector(dev, 0,
1191 ATOM_DEVICE_LCD1_SUPPORT,
1192 DRM_MODE_CONNECTOR_LVDS,
b75fad06
AD		 1193 &ddc_i2c,
1194 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1195
1196 /* VGA - primary dac */
1197 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1198 radeon_add_legacy_encoder(dev,
1199 radeon_get_encoder_id(dev,
1200 ATOM_DEVICE_CRT1_SUPPORT,
1201 1),
1202 ATOM_DEVICE_CRT1_SUPPORT);
1203 radeon_add_legacy_connector(dev, 1,
1204 ATOM_DEVICE_CRT1_SUPPORT,
1205 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1206 &ddc_i2c,
1207 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1208 } else {
1209 /* DVI-I - tv dac, int tmds */
1210 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1211 radeon_add_legacy_encoder(dev,
1212 radeon_get_encoder_id(dev,
1213 ATOM_DEVICE_DFP1_SUPPORT,
1214 0),
1215 ATOM_DEVICE_DFP1_SUPPORT);
1216 radeon_add_legacy_encoder(dev,
1217 radeon_get_encoder_id(dev,
1218 ATOM_DEVICE_CRT2_SUPPORT,
1219 2),
1220 ATOM_DEVICE_CRT2_SUPPORT);
1221 radeon_add_legacy_connector(dev, 0,
1222 ATOM_DEVICE_DFP1_SUPPORT |
1223 ATOM_DEVICE_CRT2_SUPPORT,
1224 DRM_MODE_CONNECTOR_DVII,
b75fad06
AD		 1225 &ddc_i2c,
1226 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1227
1228 /* VGA - primary dac */
1229 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1230 radeon_add_legacy_encoder(dev,
1231 radeon_get_encoder_id(dev,
1232 ATOM_DEVICE_CRT1_SUPPORT,
1233 1),
1234 ATOM_DEVICE_CRT1_SUPPORT);
1235 radeon_add_legacy_connector(dev, 1,
1236 ATOM_DEVICE_CRT1_SUPPORT,
1237 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1238 &ddc_i2c,
1239 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1240 }
1241
1242 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1243 /* TV - tv dac */
1244 radeon_add_legacy_encoder(dev,
1245 radeon_get_encoder_id(dev,
1246 ATOM_DEVICE_TV1_SUPPORT,
1247 2),
1248 ATOM_DEVICE_TV1_SUPPORT);
1249 radeon_add_legacy_connector(dev, 2,
1250 ATOM_DEVICE_TV1_SUPPORT,
1251 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1252 &ddc_i2c,
1253 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1254 }
1255 break;
1256 case CT_IBOOK:
1257 DRM_INFO("Connector Table: %d (ibook)\n",
1258 rdev->mode_info.connector_table);
1259 /* LVDS */
1260 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1261 radeon_add_legacy_encoder(dev,
1262 radeon_get_encoder_id(dev,
1263 ATOM_DEVICE_LCD1_SUPPORT,
1264 0),
1265 ATOM_DEVICE_LCD1_SUPPORT);
1266 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1267 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1268 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1269 /* VGA - TV DAC */
1270 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1271 radeon_add_legacy_encoder(dev,
1272 radeon_get_encoder_id(dev,
1273 ATOM_DEVICE_CRT2_SUPPORT,
1274 2),
1275 ATOM_DEVICE_CRT2_SUPPORT);
1276 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1277 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1278 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1279 /* TV - TV DAC */
1280 radeon_add_legacy_encoder(dev,
1281 radeon_get_encoder_id(dev,
1282 ATOM_DEVICE_TV1_SUPPORT,
1283 2),
1284 ATOM_DEVICE_TV1_SUPPORT);
1285 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1286 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1287 &ddc_i2c,
1288 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1289 break;
1290 case CT_POWERBOOK_EXTERNAL:
1291 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1292 rdev->mode_info.connector_table);
1293 /* LVDS */
1294 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1295 radeon_add_legacy_encoder(dev,
1296 radeon_get_encoder_id(dev,
1297 ATOM_DEVICE_LCD1_SUPPORT,
1298 0),
1299 ATOM_DEVICE_LCD1_SUPPORT);
1300 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1301 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1302 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1303 /* DVI-I - primary dac, ext tmds */
1304 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1305 radeon_add_legacy_encoder(dev,
1306 radeon_get_encoder_id(dev,
1307 ATOM_DEVICE_DFP2_SUPPORT,
1308 0),
1309 ATOM_DEVICE_DFP2_SUPPORT);
1310 radeon_add_legacy_encoder(dev,
1311 radeon_get_encoder_id(dev,
1312 ATOM_DEVICE_CRT1_SUPPORT,
1313 1),
1314 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1315 /* XXX some are SL */
771fe6b9
JG		 1316 radeon_add_legacy_connector(dev, 1,
1317 ATOM_DEVICE_DFP2_SUPPORT |
1318 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1319 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1320 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I);
771fe6b9
JG		 1321 /* TV - TV DAC */
1322 radeon_add_legacy_encoder(dev,
1323 radeon_get_encoder_id(dev,
1324 ATOM_DEVICE_TV1_SUPPORT,
1325 2),
1326 ATOM_DEVICE_TV1_SUPPORT);
1327 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1328 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1329 &ddc_i2c,
1330 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1331 break;
1332 case CT_POWERBOOK_INTERNAL:
1333 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1334 rdev->mode_info.connector_table);
1335 /* LVDS */
1336 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1337 radeon_add_legacy_encoder(dev,
1338 radeon_get_encoder_id(dev,
1339 ATOM_DEVICE_LCD1_SUPPORT,
1340 0),
1341 ATOM_DEVICE_LCD1_SUPPORT);
1342 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1343 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1344 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1345 /* DVI-I - primary dac, int tmds */
1346 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1347 radeon_add_legacy_encoder(dev,
1348 radeon_get_encoder_id(dev,
1349 ATOM_DEVICE_DFP1_SUPPORT,
1350 0),
1351 ATOM_DEVICE_DFP1_SUPPORT);
1352 radeon_add_legacy_encoder(dev,
1353 radeon_get_encoder_id(dev,
1354 ATOM_DEVICE_CRT1_SUPPORT,
1355 1),
1356 ATOM_DEVICE_CRT1_SUPPORT);
1357 radeon_add_legacy_connector(dev, 1,
1358 ATOM_DEVICE_DFP1_SUPPORT |
1359 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1360 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1361 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1362 /* TV - TV DAC */
1363 radeon_add_legacy_encoder(dev,
1364 radeon_get_encoder_id(dev,
1365 ATOM_DEVICE_TV1_SUPPORT,
1366 2),
1367 ATOM_DEVICE_TV1_SUPPORT);
1368 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1369 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1370 &ddc_i2c,
1371 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1372 break;
1373 case CT_POWERBOOK_VGA:
1374 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1375 rdev->mode_info.connector_table);
1376 /* LVDS */
1377 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1378 radeon_add_legacy_encoder(dev,
1379 radeon_get_encoder_id(dev,
1380 ATOM_DEVICE_LCD1_SUPPORT,
1381 0),
1382 ATOM_DEVICE_LCD1_SUPPORT);
1383 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1384 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1385 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1386 /* VGA - primary dac */
1387 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1388 radeon_add_legacy_encoder(dev,
1389 radeon_get_encoder_id(dev,
1390 ATOM_DEVICE_CRT1_SUPPORT,
1391 1),
1392 ATOM_DEVICE_CRT1_SUPPORT);
1393 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1394 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1395 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1396 /* TV - TV DAC */
1397 radeon_add_legacy_encoder(dev,
1398 radeon_get_encoder_id(dev,
1399 ATOM_DEVICE_TV1_SUPPORT,
1400 2),
1401 ATOM_DEVICE_TV1_SUPPORT);
1402 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1403 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1404 &ddc_i2c,
1405 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1406 break;
1407 case CT_MINI_EXTERNAL:
1408 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1409 rdev->mode_info.connector_table);
1410 /* DVI-I - tv dac, ext tmds */
1411 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1412 radeon_add_legacy_encoder(dev,
1413 radeon_get_encoder_id(dev,
1414 ATOM_DEVICE_DFP2_SUPPORT,
1415 0),
1416 ATOM_DEVICE_DFP2_SUPPORT);
1417 radeon_add_legacy_encoder(dev,
1418 radeon_get_encoder_id(dev,
1419 ATOM_DEVICE_CRT2_SUPPORT,
1420 2),
1421 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1422 /* XXX are any DL? */
771fe6b9
JG		 1423 radeon_add_legacy_connector(dev, 0,
1424 ATOM_DEVICE_DFP2_SUPPORT |
1425 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1426 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1427 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1428 /* TV - TV DAC */
1429 radeon_add_legacy_encoder(dev,
1430 radeon_get_encoder_id(dev,
1431 ATOM_DEVICE_TV1_SUPPORT,
1432 2),
1433 ATOM_DEVICE_TV1_SUPPORT);
1434 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1435 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1436 &ddc_i2c,
1437 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1438 break;
1439 case CT_MINI_INTERNAL:
1440 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1441 rdev->mode_info.connector_table);
1442 /* DVI-I - tv dac, int tmds */
1443 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1444 radeon_add_legacy_encoder(dev,
1445 radeon_get_encoder_id(dev,
1446 ATOM_DEVICE_DFP1_SUPPORT,
1447 0),
1448 ATOM_DEVICE_DFP1_SUPPORT);
1449 radeon_add_legacy_encoder(dev,
1450 radeon_get_encoder_id(dev,
1451 ATOM_DEVICE_CRT2_SUPPORT,
1452 2),
1453 ATOM_DEVICE_CRT2_SUPPORT);
1454 radeon_add_legacy_connector(dev, 0,
1455 ATOM_DEVICE_DFP1_SUPPORT |
1456 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1457 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1458 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1459 /* TV - TV DAC */
1460 radeon_add_legacy_encoder(dev,
1461 radeon_get_encoder_id(dev,
1462 ATOM_DEVICE_TV1_SUPPORT,
1463 2),
1464 ATOM_DEVICE_TV1_SUPPORT);
1465 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1466 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1467 &ddc_i2c,
1468 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1469 break;
1470 case CT_IMAC_G5_ISIGHT:
1471 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1472 rdev->mode_info.connector_table);
1473 /* DVI-D - int tmds */
1474 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1475 radeon_add_legacy_encoder(dev,
1476 radeon_get_encoder_id(dev,
1477 ATOM_DEVICE_DFP1_SUPPORT,
1478 0),
1479 ATOM_DEVICE_DFP1_SUPPORT);
1480 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06
AD		 1481 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1482 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D);
771fe6b9
JG		 1483 /* VGA - tv dac */
1484 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1485 radeon_add_legacy_encoder(dev,
1486 radeon_get_encoder_id(dev,
1487 ATOM_DEVICE_CRT2_SUPPORT,
1488 2),
1489 ATOM_DEVICE_CRT2_SUPPORT);
1490 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1491 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1492 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1493 /* TV - TV DAC */
1494 radeon_add_legacy_encoder(dev,
1495 radeon_get_encoder_id(dev,
1496 ATOM_DEVICE_TV1_SUPPORT,
1497 2),
1498 ATOM_DEVICE_TV1_SUPPORT);
1499 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1500 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1501 &ddc_i2c,
1502 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1503 break;
1504 case CT_EMAC:
1505 DRM_INFO("Connector Table: %d (emac)\n",
1506 rdev->mode_info.connector_table);
1507 /* VGA - primary dac */
1508 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1509 radeon_add_legacy_encoder(dev,
1510 radeon_get_encoder_id(dev,
1511 ATOM_DEVICE_CRT1_SUPPORT,
1512 1),
1513 ATOM_DEVICE_CRT1_SUPPORT);
1514 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1515 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1516 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1517 /* VGA - tv dac */
1518 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1519 radeon_add_legacy_encoder(dev,
1520 radeon_get_encoder_id(dev,
1521 ATOM_DEVICE_CRT2_SUPPORT,
1522 2),
1523 ATOM_DEVICE_CRT2_SUPPORT);
1524 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1525 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1526 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1527 /* TV - TV DAC */
1528 radeon_add_legacy_encoder(dev,
1529 radeon_get_encoder_id(dev,
1530 ATOM_DEVICE_TV1_SUPPORT,
1531 2),
1532 ATOM_DEVICE_TV1_SUPPORT);
1533 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1534 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1535 &ddc_i2c,
1536 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1537 break;
1538 default:
1539 DRM_INFO("Connector table: %d (invalid)\n",
1540 rdev->mode_info.connector_table);
1541 return false;
1542 }
1543
1544 radeon_link_encoder_connector(dev);
1545
1546 return true;
1547}
1548
1549static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1550 int bios_index,
1551 enum radeon_combios_connector
1552 *legacy_connector,
1553 struct radeon_i2c_bus_rec *ddc_i2c)
1554{
1555 struct radeon_device *rdev = dev->dev_private;
1556
1557 /* XPRESS DDC quirks */
1558 if ((rdev->family == CHIP_RS400 ||
1559 rdev->family == CHIP_RS480) &&
1560 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1561 *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1562 else if ((rdev->family == CHIP_RS400 ||
1563 rdev->family == CHIP_RS480) &&
1564 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1565 ddc_i2c->valid = true;
1566 ddc_i2c->mask_clk_mask = (0x20 << 8);
1567 ddc_i2c->mask_data_mask = 0x80;
1568 ddc_i2c->a_clk_mask = (0x20 << 8);
1569 ddc_i2c->a_data_mask = 0x80;
1570 ddc_i2c->put_clk_mask = (0x20 << 8);
1571 ddc_i2c->put_data_mask = 0x80;
1572 ddc_i2c->get_clk_mask = (0x20 << 8);
1573 ddc_i2c->get_data_mask = 0x80;
1574 ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
1575 ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
1576 ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
1577 ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
1578 ddc_i2c->put_clk_reg = RADEON_GPIOPAD_EN;
1579 ddc_i2c->put_data_reg = RADEON_GPIOPAD_EN;
1580 ddc_i2c->get_clk_reg = RADEON_LCD_GPIO_Y_REG;
1581 ddc_i2c->get_data_reg = RADEON_LCD_GPIO_Y_REG;
1582 }
1583
1584 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1585 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1586 if (dev->pdev->device == 0x515e &&
1587 dev->pdev->subsystem_vendor == 0x1014) {
1588 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1589 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1590 return false;
1591 }
1592
1593 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1594 if (dev->pdev->device == 0x5159 &&
1595 dev->pdev->subsystem_vendor == 0x1002 &&
1596 dev->pdev->subsystem_device == 0x013a) {
1597 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1598 *legacy_connector = CONNECTOR_CRT_LEGACY;
1599
1600 }
1601
1602 /* X300 card with extra non-existent DVI port */
1603 if (dev->pdev->device == 0x5B60 &&
1604 dev->pdev->subsystem_vendor == 0x17af &&
1605 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1606 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1607 return false;
1608 }
1609
1610 return true;
1611}
1612
790cfb34
AD		 1613static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1614{
1615 /* Acer 5102 has non-existent TV port */
1616 if (dev->pdev->device == 0x5975 &&
1617 dev->pdev->subsystem_vendor == 0x1025 &&
1618 dev->pdev->subsystem_device == 0x009f)
1619 return false;
1620
fc7f7119
AD		 1621 /* HP dc5750 has non-existent TV port */
1622 if (dev->pdev->device == 0x5974 &&
1623 dev->pdev->subsystem_vendor == 0x103c &&
1624 dev->pdev->subsystem_device == 0x280a)
1625 return false;
1626
790cfb34
AD		 1627 return true;
1628}
1629
b75fad06
AD		 1630static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1631{
1632 struct radeon_device *rdev = dev->dev_private;
1633 uint32_t ext_tmds_info;
1634
1635 if (rdev->flags & RADEON_IS_IGP) {
1636 if (is_dvi_d)
1637 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1638 else
1639 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1640 }
1641 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1642 if (ext_tmds_info) {
1643 uint8_t rev = RBIOS8(ext_tmds_info);
1644 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1645 if (rev >= 3) {
1646 if (is_dvi_d)
1647 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1648 else
1649 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1650 } else {
1651 if (flags & 1) {
1652 if (is_dvi_d)
1653 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1654 else
1655 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1656 }
1657 }
1658 }
1659 if (is_dvi_d)
1660 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1661 else
1662 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1663}
1664
771fe6b9
JG		 1665bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1666{
1667 struct radeon_device *rdev = dev->dev_private;
1668 uint32_t conn_info, entry, devices;
b75fad06 1669 uint16_t tmp, connector_object_id;
771fe6b9
JG		 1670 enum radeon_combios_ddc ddc_type;
1671 enum radeon_combios_connector connector;
1672 int i = 0;
1673 struct radeon_i2c_bus_rec ddc_i2c;
1674
1675 if (rdev->bios == NULL)
1676 return false;
1677
1678 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1679 if (conn_info) {
1680 for (i = 0; i < 4; i++) {
1681 entry = conn_info + 2 + i * 2;
1682
1683 if (!RBIOS16(entry))
1684 break;
1685
1686 tmp = RBIOS16(entry);
1687
1688 connector = (tmp >> 12) & 0xf;
1689
1690 ddc_type = (tmp >> 8) & 0xf;
1691 switch (ddc_type) {
1692 case DDC_MONID:
1693 ddc_i2c =
1694 combios_setup_i2c_bus(RADEON_GPIO_MONID);
1695 break;
1696 case DDC_DVI:
1697 ddc_i2c =
1698 combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1699 break;
1700 case DDC_VGA:
1701 ddc_i2c =
1702 combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1703 break;
1704 case DDC_CRT2:
1705 ddc_i2c =
1706 combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1707 break;
1708 default:
1709 break;
1710 }
1711
2d152c6b
AD		 1712 if (!radeon_apply_legacy_quirks(dev, i, &connector,
1713 &ddc_i2c))
1714 continue;
771fe6b9
JG		 1715
1716 switch (connector) {
1717 case CONNECTOR_PROPRIETARY_LEGACY:
1718 if ((tmp >> 4) & 0x1)
1719 devices = ATOM_DEVICE_DFP2_SUPPORT;
1720 else
1721 devices = ATOM_DEVICE_DFP1_SUPPORT;
1722 radeon_add_legacy_encoder(dev,
1723 radeon_get_encoder_id
1724 (dev, devices, 0),
1725 devices);
1726 radeon_add_legacy_connector(dev, i, devices,
1727 legacy_connector_convert
1728 [connector],
b75fad06
AD		 1729 &ddc_i2c,
1730 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D);
771fe6b9
JG		 1731 break;
1732 case CONNECTOR_CRT_LEGACY:
1733 if (tmp & 0x1) {
1734 devices = ATOM_DEVICE_CRT2_SUPPORT;
1735 radeon_add_legacy_encoder(dev,
1736 radeon_get_encoder_id
1737 (dev,
1738 ATOM_DEVICE_CRT2_SUPPORT,
1739 2),
1740 ATOM_DEVICE_CRT2_SUPPORT);
1741 } else {
1742 devices = ATOM_DEVICE_CRT1_SUPPORT;
1743 radeon_add_legacy_encoder(dev,
1744 radeon_get_encoder_id
1745 (dev,
1746 ATOM_DEVICE_CRT1_SUPPORT,
1747 1),
1748 ATOM_DEVICE_CRT1_SUPPORT);
1749 }
1750 radeon_add_legacy_connector(dev,
1751 i,
1752 devices,
1753 legacy_connector_convert
1754 [connector],
b75fad06
AD		 1755 &ddc_i2c,
1756 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1757 break;
1758 case CONNECTOR_DVI_I_LEGACY:
1759 devices = 0;
1760 if (tmp & 0x1) {
1761 devices |= ATOM_DEVICE_CRT2_SUPPORT;
1762 radeon_add_legacy_encoder(dev,
1763 radeon_get_encoder_id
1764 (dev,
1765 ATOM_DEVICE_CRT2_SUPPORT,
1766 2),
1767 ATOM_DEVICE_CRT2_SUPPORT);
1768 } else {
1769 devices |= ATOM_DEVICE_CRT1_SUPPORT;
1770 radeon_add_legacy_encoder(dev,
1771 radeon_get_encoder_id
1772 (dev,
1773 ATOM_DEVICE_CRT1_SUPPORT,
1774 1),
1775 ATOM_DEVICE_CRT1_SUPPORT);
1776 }
1777 if ((tmp >> 4) & 0x1) {
1778 devices |= ATOM_DEVICE_DFP2_SUPPORT;
1779 radeon_add_legacy_encoder(dev,
1780 radeon_get_encoder_id
1781 (dev,
1782 ATOM_DEVICE_DFP2_SUPPORT,
1783 0),
1784 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 1785 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 1786 } else {
1787 devices |= ATOM_DEVICE_DFP1_SUPPORT;
1788 radeon_add_legacy_encoder(dev,
1789 radeon_get_encoder_id
1790 (dev,
1791 ATOM_DEVICE_DFP1_SUPPORT,
1792 0),
1793 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 1794 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 1795 }
1796 radeon_add_legacy_connector(dev,
1797 i,
1798 devices,
1799 legacy_connector_convert
1800 [connector],
b75fad06
AD		 1801 &ddc_i2c,
1802 connector_object_id);
771fe6b9
JG		 1803 break;
1804 case CONNECTOR_DVI_D_LEGACY:
b75fad06 1805 if ((tmp >> 4) & 0x1) {
771fe6b9 1806 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 1807 connector_object_id = combios_check_dl_dvi(dev, 1);
1808 } else {
771fe6b9 1809 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 1810 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1811 }
771fe6b9
JG		 1812 radeon_add_legacy_encoder(dev,
1813 radeon_get_encoder_id
1814 (dev, devices, 0),
1815 devices);
1816 radeon_add_legacy_connector(dev, i, devices,
1817 legacy_connector_convert
1818 [connector],
b75fad06
AD		 1819 &ddc_i2c,
1820 connector_object_id);
771fe6b9
JG		 1821 break;
1822 case CONNECTOR_CTV_LEGACY:
1823 case CONNECTOR_STV_LEGACY:
1824 radeon_add_legacy_encoder(dev,
1825 radeon_get_encoder_id
1826 (dev,
1827 ATOM_DEVICE_TV1_SUPPORT,
1828 2),
1829 ATOM_DEVICE_TV1_SUPPORT);
1830 radeon_add_legacy_connector(dev, i,
1831 ATOM_DEVICE_TV1_SUPPORT,
1832 legacy_connector_convert
1833 [connector],
b75fad06
AD		 1834 &ddc_i2c,
1835 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1836 break;
1837 default:
1838 DRM_ERROR("Unknown connector type: %d\n",
1839 connector);
1840 continue;
1841 }
1842
1843 }
1844 } else {
1845 uint16_t tmds_info =
1846 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1847 if (tmds_info) {
1848 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
1849
1850 radeon_add_legacy_encoder(dev,
1851 radeon_get_encoder_id(dev,
1852 ATOM_DEVICE_CRT1_SUPPORT,
1853 1),
1854 ATOM_DEVICE_CRT1_SUPPORT);
1855 radeon_add_legacy_encoder(dev,
1856 radeon_get_encoder_id(dev,
1857 ATOM_DEVICE_DFP1_SUPPORT,
1858 0),
1859 ATOM_DEVICE_DFP1_SUPPORT);
1860
1861 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1862 radeon_add_legacy_connector(dev,
1863 0,
1864 ATOM_DEVICE_CRT1_SUPPORT |
1865 ATOM_DEVICE_DFP1_SUPPORT,
1866 DRM_MODE_CONNECTOR_DVII,
b75fad06
AD		 1867 &ddc_i2c,
1868 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9 1869 } else {
d0c403e9
AD		 1870 uint16_t crt_info =
1871 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1872 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
1873 if (crt_info) {
1874 radeon_add_legacy_encoder(dev,
1875 radeon_get_encoder_id(dev,
1876 ATOM_DEVICE_CRT1_SUPPORT,
1877 1),
1878 ATOM_DEVICE_CRT1_SUPPORT);
1879 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1880 radeon_add_legacy_connector(dev,
1881 0,
1882 ATOM_DEVICE_CRT1_SUPPORT,
1883 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1884 &ddc_i2c,
1885 CONNECTOR_OBJECT_ID_VGA);
d0c403e9
AD		 1886 } else {
1887 DRM_DEBUG("No connector info found\n");
1888 return false;
1889 }
771fe6b9
JG		 1890 }
1891 }
1892
1893 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
1894 uint16_t lcd_info =
1895 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1896 if (lcd_info) {
1897 uint16_t lcd_ddc_info =
1898 combios_get_table_offset(dev,
1899 COMBIOS_LCD_DDC_INFO_TABLE);
1900
1901 radeon_add_legacy_encoder(dev,
1902 radeon_get_encoder_id(dev,
1903 ATOM_DEVICE_LCD1_SUPPORT,
1904 0),
1905 ATOM_DEVICE_LCD1_SUPPORT);
1906
1907 if (lcd_ddc_info) {
1908 ddc_type = RBIOS8(lcd_ddc_info + 2);
1909 switch (ddc_type) {
1910 case DDC_MONID:
1911 ddc_i2c =
1912 combios_setup_i2c_bus
1913 (RADEON_GPIO_MONID);
1914 break;
1915 case DDC_DVI:
1916 ddc_i2c =
1917 combios_setup_i2c_bus
1918 (RADEON_GPIO_DVI_DDC);
1919 break;
1920 case DDC_VGA:
1921 ddc_i2c =
1922 combios_setup_i2c_bus
1923 (RADEON_GPIO_VGA_DDC);
1924 break;
1925 case DDC_CRT2:
1926 ddc_i2c =
1927 combios_setup_i2c_bus
1928 (RADEON_GPIO_CRT2_DDC);
1929 break;
1930 case DDC_LCD:
1931 ddc_i2c =
1932 combios_setup_i2c_bus
1933 (RADEON_LCD_GPIO_MASK);
1934 ddc_i2c.mask_clk_mask =
1935 RBIOS32(lcd_ddc_info + 3);
1936 ddc_i2c.mask_data_mask =
1937 RBIOS32(lcd_ddc_info + 7);
1938 ddc_i2c.a_clk_mask =
1939 RBIOS32(lcd_ddc_info + 3);
1940 ddc_i2c.a_data_mask =
1941 RBIOS32(lcd_ddc_info + 7);
1942 ddc_i2c.put_clk_mask =
1943 RBIOS32(lcd_ddc_info + 3);
1944 ddc_i2c.put_data_mask =
1945 RBIOS32(lcd_ddc_info + 7);
1946 ddc_i2c.get_clk_mask =
1947 RBIOS32(lcd_ddc_info + 3);
1948 ddc_i2c.get_data_mask =
1949 RBIOS32(lcd_ddc_info + 7);
1950 break;
1951 case DDC_GPIO:
1952 ddc_i2c =
1953 combios_setup_i2c_bus
1954 (RADEON_MDGPIO_EN_REG);
1955 ddc_i2c.mask_clk_mask =
1956 RBIOS32(lcd_ddc_info + 3);
1957 ddc_i2c.mask_data_mask =
1958 RBIOS32(lcd_ddc_info + 7);
1959 ddc_i2c.a_clk_mask =
1960 RBIOS32(lcd_ddc_info + 3);
1961 ddc_i2c.a_data_mask =
1962 RBIOS32(lcd_ddc_info + 7);
1963 ddc_i2c.put_clk_mask =
1964 RBIOS32(lcd_ddc_info + 3);
1965 ddc_i2c.put_data_mask =
1966 RBIOS32(lcd_ddc_info + 7);
1967 ddc_i2c.get_clk_mask =
1968 RBIOS32(lcd_ddc_info + 3);
1969 ddc_i2c.get_data_mask =
1970 RBIOS32(lcd_ddc_info + 7);
1971 break;
1972 default:
1973 ddc_i2c.valid = false;
1974 break;
1975 }
1976 DRM_DEBUG("LCD DDC Info Table found!\n");
1977 } else
1978 ddc_i2c.valid = false;
1979
1980 radeon_add_legacy_connector(dev,
1981 5,
1982 ATOM_DEVICE_LCD1_SUPPORT,
1983 DRM_MODE_CONNECTOR_LVDS,
b75fad06
AD		 1984 &ddc_i2c,
1985 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1986 }
1987 }
1988
1989 /* check TV table */
1990 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1991 uint32_t tv_info =
1992 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1993 if (tv_info) {
1994 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34
AD		 1995 if (radeon_apply_legacy_tv_quirks(dev)) {
1996 radeon_add_legacy_encoder(dev,
1997 radeon_get_encoder_id
1998 (dev,
1999 ATOM_DEVICE_TV1_SUPPORT,
2000 2),
2001 ATOM_DEVICE_TV1_SUPPORT);
2002 radeon_add_legacy_connector(dev, 6,
2003 ATOM_DEVICE_TV1_SUPPORT,
2004 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 2005 &ddc_i2c,
2006 CONNECTOR_OBJECT_ID_SVIDEO);
790cfb34 2007 }
771fe6b9
JG		 2008 }
2009 }
2010 }
2011
2012 radeon_link_encoder_connector(dev);
2013
2014 return true;
2015}
2016
2017static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2018{
2019 struct radeon_device *rdev = dev->dev_private;
2020
2021 if (offset) {
2022 while (RBIOS16(offset)) {
2023 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2024 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2025 uint32_t val, and_mask, or_mask;
2026 uint32_t tmp;
2027
2028 offset += 2;
2029 switch (cmd) {
2030 case 0:
2031 val = RBIOS32(offset);
2032 offset += 4;
2033 WREG32(addr, val);
2034 break;
2035 case 1:
2036 val = RBIOS32(offset);
2037 offset += 4;
2038 WREG32(addr, val);
2039 break;
2040 case 2:
2041 and_mask = RBIOS32(offset);
2042 offset += 4;
2043 or_mask = RBIOS32(offset);
2044 offset += 4;
2045 tmp = RREG32(addr);
2046 tmp &= and_mask;
2047 tmp |= or_mask;
2048 WREG32(addr, tmp);
2049 break;
2050 case 3:
2051 and_mask = RBIOS32(offset);
2052 offset += 4;
2053 or_mask = RBIOS32(offset);
2054 offset += 4;
2055 tmp = RREG32(addr);
2056 tmp &= and_mask;
2057 tmp |= or_mask;
2058 WREG32(addr, tmp);
2059 break;
2060 case 4:
2061 val = RBIOS16(offset);
2062 offset += 2;
2063 udelay(val);
2064 break;
2065 case 5:
2066 val = RBIOS16(offset);
2067 offset += 2;
2068 switch (addr) {
2069 case 8:
2070 while (val--) {
2071 if (!
2072 (RREG32_PLL
2073 (RADEON_CLK_PWRMGT_CNTL) &
2074 RADEON_MC_BUSY))
2075 break;
2076 }
2077 break;
2078 case 9:
2079 while (val--) {
2080 if ((RREG32(RADEON_MC_STATUS) &
2081 RADEON_MC_IDLE))
2082 break;
2083 }
2084 break;
2085 default:
2086 break;
2087 }
2088 break;
2089 default:
2090 break;
2091 }
2092 }
2093 }
2094}
2095
2096static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2097{
2098 struct radeon_device *rdev = dev->dev_private;
2099
2100 if (offset) {
2101 while (RBIOS8(offset)) {
2102 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2103 uint8_t addr = (RBIOS8(offset) & 0x3f);
2104 uint32_t val, shift, tmp;
2105 uint32_t and_mask, or_mask;
2106
2107 offset++;
2108 switch (cmd) {
2109 case 0:
2110 val = RBIOS32(offset);
2111 offset += 4;
2112 WREG32_PLL(addr, val);
2113 break;
2114 case 1:
2115 shift = RBIOS8(offset) * 8;
2116 offset++;
2117 and_mask = RBIOS8(offset) << shift;
2118 and_mask |= ~(0xff << shift);
2119 offset++;
2120 or_mask = RBIOS8(offset) << shift;
2121 offset++;
2122 tmp = RREG32_PLL(addr);
2123 tmp &= and_mask;
2124 tmp |= or_mask;
2125 WREG32_PLL(addr, tmp);
2126 break;
2127 case 2:
2128 case 3:
2129 tmp = 1000;
2130 switch (addr) {
2131 case 1:
2132 udelay(150);
2133 break;
2134 case 2:
2135 udelay(1000);
2136 break;
2137 case 3:
2138 while (tmp--) {
2139 if (!
2140 (RREG32_PLL
2141 (RADEON_CLK_PWRMGT_CNTL) &
2142 RADEON_MC_BUSY))
2143 break;
2144 }
2145 break;
2146 case 4:
2147 while (tmp--) {
2148 if (RREG32_PLL
2149 (RADEON_CLK_PWRMGT_CNTL) &
2150 RADEON_DLL_READY)
2151 break;
2152 }
2153 break;
2154 case 5:
2155 tmp =
2156 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2157 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2158#if 0
2159 uint32_t mclk_cntl =
2160 RREG32_PLL
2161 (RADEON_MCLK_CNTL);
2162 mclk_cntl &= 0xffff0000;
2163 /*mclk_cntl |= 0x00001111;*//* ??? */
2164 WREG32_PLL(RADEON_MCLK_CNTL,
2165 mclk_cntl);
2166 udelay(10000);
2167#endif
2168 WREG32_PLL
2169 (RADEON_CLK_PWRMGT_CNTL,
2170 tmp &
2171 ~RADEON_CG_NO1_DEBUG_0);
2172 udelay(10000);
2173 }
2174 break;
2175 default:
2176 break;
2177 }
2178 break;
2179 default:
2180 break;
2181 }
2182 }
2183 }
2184}
2185
2186static void combios_parse_ram_reset_table(struct drm_device *dev,
2187 uint16_t offset)
2188{
2189 struct radeon_device *rdev = dev->dev_private;
2190 uint32_t tmp;
2191
2192 if (offset) {
2193 uint8_t val = RBIOS8(offset);
2194 while (val != 0xff) {
2195 offset++;
2196
2197 if (val == 0x0f) {
2198 uint32_t channel_complete_mask;
2199
2200 if (ASIC_IS_R300(rdev))
2201 channel_complete_mask =
2202 R300_MEM_PWRUP_COMPLETE;
2203 else
2204 channel_complete_mask =
2205 RADEON_MEM_PWRUP_COMPLETE;
2206 tmp = 20000;
2207 while (tmp--) {
2208 if ((RREG32(RADEON_MEM_STR_CNTL) &
2209 channel_complete_mask) ==
2210 channel_complete_mask)
2211 break;
2212 }
2213 } else {
2214 uint32_t or_mask = RBIOS16(offset);
2215 offset += 2;
2216
2217 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2218 tmp &= RADEON_SDRAM_MODE_MASK;
2219 tmp |= or_mask;
2220 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2221
2222 or_mask = val << 24;
2223 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2224 tmp &= RADEON_B3MEM_RESET_MASK;
2225 tmp |= or_mask;
2226 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2227 }
2228 val = RBIOS8(offset);
2229 }
2230 }
2231}
2232
2233static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2234 int mem_addr_mapping)
2235{
2236 struct radeon_device *rdev = dev->dev_private;
2237 uint32_t mem_cntl;
2238 uint32_t mem_size;
2239 uint32_t addr = 0;
2240
2241 mem_cntl = RREG32(RADEON_MEM_CNTL);
2242 if (mem_cntl & RV100_HALF_MODE)
2243 ram /= 2;
2244 mem_size = ram;
2245 mem_cntl &= ~(0xff << 8);
2246 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2247 WREG32(RADEON_MEM_CNTL, mem_cntl);
2248 RREG32(RADEON_MEM_CNTL);
2249
2250 /* sdram reset ? */
2251
2252 /* something like this???? */
2253 while (ram--) {
2254 addr = ram * 1024 * 1024;
2255 /* write to each page */
2256 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2257 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2258 /* read back and verify */
2259 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2260 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2261 return 0;
2262 }
2263
2264 return mem_size;
2265}
2266
2267static void combios_write_ram_size(struct drm_device *dev)
2268{
2269 struct radeon_device *rdev = dev->dev_private;
2270 uint8_t rev;
2271 uint16_t offset;
2272 uint32_t mem_size = 0;
2273 uint32_t mem_cntl = 0;
2274
2275 /* should do something smarter here I guess... */
2276 if (rdev->flags & RADEON_IS_IGP)
2277 return;
2278
2279 /* first check detected mem table */
2280 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2281 if (offset) {
2282 rev = RBIOS8(offset);
2283 if (rev < 3) {
2284 mem_cntl = RBIOS32(offset + 1);
2285 mem_size = RBIOS16(offset + 5);
2286 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2287 ((dev->pdev->device != 0x515e)
2288 && (dev->pdev->device != 0x5969)))
2289 WREG32(RADEON_MEM_CNTL, mem_cntl);
2290 }
2291 }
2292
2293 if (!mem_size) {
2294 offset =
2295 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2296 if (offset) {
2297 rev = RBIOS8(offset - 1);
2298 if (rev < 1) {
2299 if (((rdev->flags & RADEON_FAMILY_MASK) <
2300 CHIP_R200)
2301 && ((dev->pdev->device != 0x515e)
2302 && (dev->pdev->device != 0x5969))) {
2303 int ram = 0;
2304 int mem_addr_mapping = 0;
2305
2306 while (RBIOS8(offset)) {
2307 ram = RBIOS8(offset);
2308 mem_addr_mapping =
2309 RBIOS8(offset + 1);
2310 if (mem_addr_mapping != 0x25)
2311 ram *= 2;
2312 mem_size =
2313 combios_detect_ram(dev, ram,
2314 mem_addr_mapping);
2315 if (mem_size)
2316 break;
2317 offset += 2;
2318 }
2319 } else
2320 mem_size = RBIOS8(offset);
2321 } else {
2322 mem_size = RBIOS8(offset);
2323 mem_size *= 2; /* convert to MB */
2324 }
2325 }
2326 }
2327
2328 mem_size *= (1024 * 1024); /* convert to bytes */
2329 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2330}
2331
2332void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2333{
2334 uint16_t dyn_clk_info =
2335 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2336
2337 if (dyn_clk_info)
2338 combios_parse_pll_table(dev, dyn_clk_info);
2339}
2340
2341void radeon_combios_asic_init(struct drm_device *dev)
2342{
2343 struct radeon_device *rdev = dev->dev_private;
2344 uint16_t table;
2345
2346 /* port hardcoded mac stuff from radeonfb */
2347 if (rdev->bios == NULL)
2348 return;
2349
2350 /* ASIC INIT 1 */
2351 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2352 if (table)
2353 combios_parse_mmio_table(dev, table);
2354
2355 /* PLL INIT */
2356 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2357 if (table)
2358 combios_parse_pll_table(dev, table);
2359
2360 /* ASIC INIT 2 */
2361 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2362 if (table)
2363 combios_parse_mmio_table(dev, table);
2364
2365 if (!(rdev->flags & RADEON_IS_IGP)) {
2366 /* ASIC INIT 4 */
2367 table =
2368 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2369 if (table)
2370 combios_parse_mmio_table(dev, table);
2371
2372 /* RAM RESET */
2373 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2374 if (table)
2375 combios_parse_ram_reset_table(dev, table);
2376
2377 /* ASIC INIT 3 */
2378 table =
2379 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2380 if (table)
2381 combios_parse_mmio_table(dev, table);
2382
2383 /* write CONFIG_MEMSIZE */
2384 combios_write_ram_size(dev);
2385 }
2386
2387 /* DYN CLK 1 */
2388 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2389 if (table)
2390 combios_parse_pll_table(dev, table);
2391
2392}
2393
2394void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2395{
2396 struct radeon_device *rdev = dev->dev_private;
2397 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2398
2399 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2400 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2401 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2402
2403 /* let the bios control the backlight */
2404 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2405
2406 /* tell the bios not to handle mode switching */
2407 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2408 RADEON_ACC_MODE_CHANGE);
2409
2410 /* tell the bios a driver is loaded */
2411 bios_7_scratch |= RADEON_DRV_LOADED;
2412
2413 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2414 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2415 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2416}
2417
2418void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2419{
2420 struct drm_device *dev = encoder->dev;
2421 struct radeon_device *rdev = dev->dev_private;
2422 uint32_t bios_6_scratch;
2423
2424 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2425
2426 if (lock)
2427 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2428 else
2429 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2430
2431 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2432}
2433
2434void
2435radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2436 struct drm_encoder *encoder,
2437 bool connected)
2438{
2439 struct drm_device *dev = connector->dev;
2440 struct radeon_device *rdev = dev->dev_private;
2441 struct radeon_connector *radeon_connector =
2442 to_radeon_connector(connector);
2443 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2444 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2445 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2446
2447 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2448 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2449 if (connected) {
2450 DRM_DEBUG("TV1 connected\n");
2451 /* fix me */
2452 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2453 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2454 bios_5_scratch |= RADEON_TV1_ON;
2455 bios_5_scratch |= RADEON_ACC_REQ_TV1;
2456 } else {
2457 DRM_DEBUG("TV1 disconnected\n");
2458 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2459 bios_5_scratch &= ~RADEON_TV1_ON;
2460 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2461 }
2462 }
2463 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2464 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2465 if (connected) {
2466 DRM_DEBUG("LCD1 connected\n");
2467 bios_4_scratch |= RADEON_LCD1_ATTACHED;
2468 bios_5_scratch |= RADEON_LCD1_ON;
2469 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2470 } else {
2471 DRM_DEBUG("LCD1 disconnected\n");
2472 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2473 bios_5_scratch &= ~RADEON_LCD1_ON;
2474 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2475 }
2476 }
2477 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2478 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2479 if (connected) {
2480 DRM_DEBUG("CRT1 connected\n");
2481 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2482 bios_5_scratch |= RADEON_CRT1_ON;
2483 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2484 } else {
2485 DRM_DEBUG("CRT1 disconnected\n");
2486 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2487 bios_5_scratch &= ~RADEON_CRT1_ON;
2488 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2489 }
2490 }
2491 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2492 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2493 if (connected) {
2494 DRM_DEBUG("CRT2 connected\n");
2495 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2496 bios_5_scratch |= RADEON_CRT2_ON;
2497 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2498 } else {
2499 DRM_DEBUG("CRT2 disconnected\n");
2500 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2501 bios_5_scratch &= ~RADEON_CRT2_ON;
2502 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2503 }
2504 }
2505 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2506 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2507 if (connected) {
2508 DRM_DEBUG("DFP1 connected\n");
2509 bios_4_scratch |= RADEON_DFP1_ATTACHED;
2510 bios_5_scratch |= RADEON_DFP1_ON;
2511 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2512 } else {
2513 DRM_DEBUG("DFP1 disconnected\n");
2514 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2515 bios_5_scratch &= ~RADEON_DFP1_ON;
2516 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2517 }
2518 }
2519 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2520 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2521 if (connected) {
2522 DRM_DEBUG("DFP2 connected\n");
2523 bios_4_scratch |= RADEON_DFP2_ATTACHED;
2524 bios_5_scratch |= RADEON_DFP2_ON;
2525 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2526 } else {
2527 DRM_DEBUG("DFP2 disconnected\n");
2528 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2529 bios_5_scratch &= ~RADEON_DFP2_ON;
2530 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2531 }
2532 }
2533 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2534 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2535}
2536
2537void
2538radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2539{
2540 struct drm_device *dev = encoder->dev;
2541 struct radeon_device *rdev = dev->dev_private;
2542 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2543 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2544
2545 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2546 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2547 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2548 }
2549 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2550 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2551 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2552 }
2553 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2554 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2555 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2556 }
2557 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2558 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2559 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2560 }
2561 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2562 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2563 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2564 }
2565 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2566 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
2567 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
2568 }
2569 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2570}
2571
2572void
2573radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2574{
2575 struct drm_device *dev = encoder->dev;
2576 struct radeon_device *rdev = dev->dev_private;
2577 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2578 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2579
2580 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
2581 if (on)
2582 bios_6_scratch |= RADEON_TV_DPMS_ON;
2583 else
2584 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
2585 }
2586 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2587 if (on)
2588 bios_6_scratch |= RADEON_CRT_DPMS_ON;
2589 else
2590 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
2591 }
2592 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2593 if (on)
2594 bios_6_scratch |= RADEON_LCD_DPMS_ON;
2595 else
2596 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
2597 }
2598 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
2599 if (on)
2600 bios_6_scratch |= RADEON_DFP_DPMS_ON;
2601 else
2602 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
2603 }
2604 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2605}
Clone of davem's net-next-2.6 tree