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drm/radeon/kms/pm: voltage fixes
[net-next-2.6.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
03047cdf
MD		 153 if (!rdev->bios)
154 return 0;
155
771fe6b9
JG		 156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328 /* relative offset tables */
329 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447}
448
3c537889
AD		 449bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450{
451 int edid_info;
452 struct edid *edid;
7466f4cc 453 unsigned char *raw;
3c537889
AD		 454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
455 if (!edid_info)
456 return false;
457
7466f4cc
AJ		 458 raw = rdev->bios + edid_info;
459 edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
3c537889
AD		 460 if (edid == NULL)
461 return false;
462
7466f4cc 463 memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
3c537889
AD		 464
465 if (!drm_edid_is_valid(edid)) {
466 kfree(edid);
467 return false;
468 }
469
470 rdev->mode_info.bios_hardcoded_edid = edid;
471 return true;
472}
473
474struct edid *
475radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
476{
477 if (rdev->mode_info.bios_hardcoded_edid)
478 return rdev->mode_info.bios_hardcoded_edid;
479 return NULL;
480}
481
6a93cb25
AD		 482static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
483 int ddc_line)
771fe6b9
JG		 484{
485 struct radeon_i2c_bus_rec i2c;
486
6a93cb25
AD		 487 if (ddc_line == RADEON_GPIOPAD_MASK) {
488 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
489 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
490 i2c.a_clk_reg = RADEON_GPIOPAD_A;
491 i2c.a_data_reg = RADEON_GPIOPAD_A;
492 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
493 i2c.en_data_reg = RADEON_GPIOPAD_EN;
494 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
495 i2c.y_data_reg = RADEON_GPIOPAD_Y;
496 } else if (ddc_line == RADEON_MDGPIO_MASK) {
497 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
498 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
499 i2c.a_clk_reg = RADEON_MDGPIO_A;
500 i2c.a_data_reg = RADEON_MDGPIO_A;
501 i2c.en_clk_reg = RADEON_MDGPIO_EN;
502 i2c.en_data_reg = RADEON_MDGPIO_EN;
503 i2c.y_clk_reg = RADEON_MDGPIO_Y;
504 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9 505 } else {
6a93cb25
AD		 506 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
507 i2c.mask_data_mask = RADEON_GPIO_EN_0;
508 i2c.a_clk_mask = RADEON_GPIO_A_1;
509 i2c.a_data_mask = RADEON_GPIO_A_0;
510 i2c.en_clk_mask = RADEON_GPIO_EN_1;
511 i2c.en_data_mask = RADEON_GPIO_EN_0;
512 i2c.y_clk_mask = RADEON_GPIO_Y_1;
513 i2c.y_data_mask = RADEON_GPIO_Y_0;
514
771fe6b9
JG		 515 i2c.mask_clk_reg = ddc_line;
516 i2c.mask_data_reg = ddc_line;
517 i2c.a_clk_reg = ddc_line;
518 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 519 i2c.en_clk_reg = ddc_line;
520 i2c.en_data_reg = ddc_line;
521 i2c.y_clk_reg = ddc_line;
522 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 523 }
524
40bacf16
AD		 525 switch (rdev->family) {
526 case CHIP_R100:
527 case CHIP_RV100:
528 case CHIP_RS100:
529 case CHIP_RV200:
530 case CHIP_RS200:
531 case CHIP_RS300:
532 switch (ddc_line) {
533 case RADEON_GPIO_DVI_DDC:
b28ea411 534 i2c.hw_capable = true;
40bacf16
AD		 535 break;
536 default:
537 i2c.hw_capable = false;
538 break;
539 }
540 break;
541 case CHIP_R200:
542 switch (ddc_line) {
543 case RADEON_GPIO_DVI_DDC:
544 case RADEON_GPIO_MONID:
545 i2c.hw_capable = true;
546 break;
547 default:
548 i2c.hw_capable = false;
549 break;
550 }
551 break;
552 case CHIP_RV250:
553 case CHIP_RV280:
554 switch (ddc_line) {
555 case RADEON_GPIO_VGA_DDC:
556 case RADEON_GPIO_DVI_DDC:
557 case RADEON_GPIO_CRT2_DDC:
558 i2c.hw_capable = true;
559 break;
560 default:
561 i2c.hw_capable = false;
562 break;
563 }
564 break;
565 case CHIP_R300:
566 case CHIP_R350:
567 switch (ddc_line) {
568 case RADEON_GPIO_VGA_DDC:
569 case RADEON_GPIO_DVI_DDC:
570 i2c.hw_capable = true;
571 break;
572 default:
573 i2c.hw_capable = false;
574 break;
575 }
576 break;
577 case CHIP_RV350:
578 case CHIP_RV380:
579 case CHIP_RS400:
580 case CHIP_RS480:
6a93cb25
AD		 581 switch (ddc_line) {
582 case RADEON_GPIO_VGA_DDC:
583 case RADEON_GPIO_DVI_DDC:
584 i2c.hw_capable = true;
585 break;
586 case RADEON_GPIO_MONID:
587 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
588 * reliably on some pre-r4xx hardware; not sure why.
589 */
590 i2c.hw_capable = false;
591 break;
592 default:
593 i2c.hw_capable = false;
594 break;
595 }
40bacf16
AD		 596 break;
597 default:
598 i2c.hw_capable = false;
599 break;
6a93cb25
AD		 600 }
601 i2c.mm_i2c = false;
602 i2c.i2c_id = 0;
8e36ed00 603 i2c.hpd = RADEON_HPD_NONE;
6a93cb25 604
771fe6b9
JG		 605 if (ddc_line)
606 i2c.valid = true;
607 else
608 i2c.valid = false;
609
610 return i2c;
611}
612
613bool radeon_combios_get_clock_info(struct drm_device *dev)
614{
615 struct radeon_device *rdev = dev->dev_private;
616 uint16_t pll_info;
617 struct radeon_pll *p1pll = &rdev->clock.p1pll;
618 struct radeon_pll *p2pll = &rdev->clock.p2pll;
619 struct radeon_pll *spll = &rdev->clock.spll;
620 struct radeon_pll *mpll = &rdev->clock.mpll;
621 int8_t rev;
622 uint16_t sclk, mclk;
623
771fe6b9
JG		 624 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
625 if (pll_info) {
626 rev = RBIOS8(pll_info);
627
628 /* pixel clocks */
629 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
630 p1pll->reference_div = RBIOS16(pll_info + 0x10);
631 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
632 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
86cb2bbf
AD		 633 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
634 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
771fe6b9
JG		 635
636 if (rev > 9) {
637 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
638 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
639 } else {
640 p1pll->pll_in_min = 40;
641 p1pll->pll_in_max = 500;
642 }
643 *p2pll = *p1pll;
644
645 /* system clock */
646 spll->reference_freq = RBIOS16(pll_info + 0x1a);
647 spll->reference_div = RBIOS16(pll_info + 0x1c);
648 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
649 spll->pll_out_max = RBIOS32(pll_info + 0x22);
650
651 if (rev > 10) {
652 spll->pll_in_min = RBIOS32(pll_info + 0x48);
653 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
654 } else {
655 /* ??? */
656 spll->pll_in_min = 40;
657 spll->pll_in_max = 500;
658 }
659
660 /* memory clock */
661 mpll->reference_freq = RBIOS16(pll_info + 0x26);
662 mpll->reference_div = RBIOS16(pll_info + 0x28);
663 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
664 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
665
666 if (rev > 10) {
667 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
668 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
669 } else {
670 /* ??? */
671 mpll->pll_in_min = 40;
672 mpll->pll_in_max = 500;
673 }
674
675 /* default sclk/mclk */
676 sclk = RBIOS16(pll_info + 0xa);
677 mclk = RBIOS16(pll_info + 0x8);
678 if (sclk == 0)
679 sclk = 200 * 100;
680 if (mclk == 0)
681 mclk = 200 * 100;
682
683 rdev->clock.default_sclk = sclk;
684 rdev->clock.default_mclk = mclk;
685
686 return true;
687 }
688 return false;
689}
690
06b6476d
AD		 691bool radeon_combios_sideport_present(struct radeon_device *rdev)
692{
693 struct drm_device *dev = rdev->ddev;
694 u16 igp_info;
695
696 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
697
698 if (igp_info) {
699 if (RBIOS16(igp_info + 0x4))
700 return true;
701 }
702 return false;
703}
704
246263cc
AD		 705static const uint32_t default_primarydac_adj[CHIP_LAST] = {
706 0x00000808, /* r100 */
707 0x00000808, /* rv100 */
708 0x00000808, /* rs100 */
709 0x00000808, /* rv200 */
710 0x00000808, /* rs200 */
711 0x00000808, /* r200 */
712 0x00000808, /* rv250 */
713 0x00000000, /* rs300 */
714 0x00000808, /* rv280 */
715 0x00000808, /* r300 */
716 0x00000808, /* r350 */
717 0x00000808, /* rv350 */
718 0x00000808, /* rv380 */
719 0x00000808, /* r420 */
720 0x00000808, /* r423 */
721 0x00000808, /* rv410 */
722 0x00000000, /* rs400 */
723 0x00000000, /* rs480 */
724};
725
726static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
727 struct radeon_encoder_primary_dac *p_dac)
728{
729 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
730 return;
731}
732
771fe6b9
JG		 733struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
734 radeon_encoder
735 *encoder)
736{
737 struct drm_device *dev = encoder->base.dev;
738 struct radeon_device *rdev = dev->dev_private;
739 uint16_t dac_info;
740 uint8_t rev, bg, dac;
741 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 742 int found = 0;
771fe6b9 743
246263cc
AD		 744 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
745 GFP_KERNEL);
746
747 if (!p_dac)
771fe6b9
JG		 748 return NULL;
749
750 /* check CRT table */
751 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
752 if (dac_info) {
771fe6b9
JG		 753 rev = RBIOS8(dac_info) & 0x3;
754 if (rev < 2) {
755 bg = RBIOS8(dac_info + 0x2) & 0xf;
756 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
757 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
758 } else {
759 bg = RBIOS8(dac_info + 0x2) & 0xf;
760 dac = RBIOS8(dac_info + 0x3) & 0xf;
761 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
762 }
3a89b4a9
AD		 763 /* if the values are all zeros, use the table */
764 if (p_dac->ps2_pdac_adj)
765 found = 1;
771fe6b9
JG		 766 }
767
246263cc
AD		 768 if (!found) /* fallback to defaults */
769 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
770
771fe6b9
JG		 771 return p_dac;
772}
773
d79766fa
AD		 774enum radeon_tv_std
775radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 776{
d79766fa 777 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 778 uint16_t tv_info;
779 enum radeon_tv_std tv_std = TV_STD_NTSC;
780
781 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
782 if (tv_info) {
783 if (RBIOS8(tv_info + 6) == 'T') {
784 switch (RBIOS8(tv_info + 7) & 0xf) {
785 case 1:
786 tv_std = TV_STD_NTSC;
787 DRM_INFO("Default TV standard: NTSC\n");
788 break;
789 case 2:
790 tv_std = TV_STD_PAL;
791 DRM_INFO("Default TV standard: PAL\n");
792 break;
793 case 3:
794 tv_std = TV_STD_PAL_M;
795 DRM_INFO("Default TV standard: PAL-M\n");
796 break;
797 case 4:
798 tv_std = TV_STD_PAL_60;
799 DRM_INFO("Default TV standard: PAL-60\n");
800 break;
801 case 5:
802 tv_std = TV_STD_NTSC_J;
803 DRM_INFO("Default TV standard: NTSC-J\n");
804 break;
805 case 6:
806 tv_std = TV_STD_SCART_PAL;
807 DRM_INFO("Default TV standard: SCART-PAL\n");
808 break;
809 default:
810 tv_std = TV_STD_NTSC;
811 DRM_INFO
812 ("Unknown TV standard; defaulting to NTSC\n");
813 break;
814 }
815
816 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
817 case 0:
818 DRM_INFO("29.498928713 MHz TV ref clk\n");
819 break;
820 case 1:
821 DRM_INFO("28.636360000 MHz TV ref clk\n");
822 break;
823 case 2:
824 DRM_INFO("14.318180000 MHz TV ref clk\n");
825 break;
826 case 3:
827 DRM_INFO("27.000000000 MHz TV ref clk\n");
828 break;
829 default:
830 break;
831 }
832 }
833 }
834 return tv_std;
835}
836
837static const uint32_t default_tvdac_adj[CHIP_LAST] = {
838 0x00000000, /* r100 */
839 0x00280000, /* rv100 */
840 0x00000000, /* rs100 */
841 0x00880000, /* rv200 */
842 0x00000000, /* rs200 */
843 0x00000000, /* r200 */
844 0x00770000, /* rv250 */
845 0x00290000, /* rs300 */
846 0x00560000, /* rv280 */
847 0x00780000, /* r300 */
848 0x00770000, /* r350 */
849 0x00780000, /* rv350 */
850 0x00780000, /* rv380 */
851 0x01080000, /* r420 */
852 0x01080000, /* r423 */
853 0x01080000, /* rv410 */
854 0x00780000, /* rs400 */
855 0x00780000, /* rs480 */
856};
857
6a719e05
DA		 858static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
859 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 860{
771fe6b9
JG		 861 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
862 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
863 tv_dac->ps2_tvdac_adj = 0x00880000;
864 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
865 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 866 return;
771fe6b9
JG		 867}
868
869struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
870 radeon_encoder
871 *encoder)
872{
873 struct drm_device *dev = encoder->base.dev;
874 struct radeon_device *rdev = dev->dev_private;
875 uint16_t dac_info;
876 uint8_t rev, bg, dac;
877 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 878 int found = 0;
879
880 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
881 if (!tv_dac)
882 return NULL;
771fe6b9 883
771fe6b9
JG		 884 /* first check TV table */
885 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
886 if (dac_info) {
771fe6b9
JG		 887 rev = RBIOS8(dac_info + 0x3);
888 if (rev > 4) {
889 bg = RBIOS8(dac_info + 0xc) & 0xf;
890 dac = RBIOS8(dac_info + 0xd) & 0xf;
891 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
892
893 bg = RBIOS8(dac_info + 0xe) & 0xf;
894 dac = RBIOS8(dac_info + 0xf) & 0xf;
895 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
896
897 bg = RBIOS8(dac_info + 0x10) & 0xf;
898 dac = RBIOS8(dac_info + 0x11) & 0xf;
899 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 900 /* if the values are all zeros, use the table */
901 if (tv_dac->ps2_tvdac_adj)
902 found = 1;
771fe6b9
JG		 903 } else if (rev > 1) {
904 bg = RBIOS8(dac_info + 0xc) & 0xf;
905 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
906 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
907
908 bg = RBIOS8(dac_info + 0xd) & 0xf;
909 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
910 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
911
912 bg = RBIOS8(dac_info + 0xe) & 0xf;
913 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
914 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 915 /* if the values are all zeros, use the table */
916 if (tv_dac->ps2_tvdac_adj)
917 found = 1;
771fe6b9 918 }
d79766fa 919 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 920 }
921 if (!found) {
771fe6b9
JG		 922 /* then check CRT table */
923 dac_info =
924 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
925 if (dac_info) {
771fe6b9
JG		 926 rev = RBIOS8(dac_info) & 0x3;
927 if (rev < 2) {
928 bg = RBIOS8(dac_info + 0x3) & 0xf;
929 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
930 tv_dac->ps2_tvdac_adj =
931 (bg << 16) | (dac << 20);
932 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
933 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 934 /* if the values are all zeros, use the table */
935 if (tv_dac->ps2_tvdac_adj)
936 found = 1;
771fe6b9
JG		 937 } else {
938 bg = RBIOS8(dac_info + 0x4) & 0xf;
939 dac = RBIOS8(dac_info + 0x5) & 0xf;
940 tv_dac->ps2_tvdac_adj =
941 (bg << 16) | (dac << 20);
942 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
943 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 944 /* if the values are all zeros, use the table */
945 if (tv_dac->ps2_tvdac_adj)
946 found = 1;
771fe6b9 947 }
6fe7ac3f
AD		 948 } else {
949 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 950 }
951 }
952
6a719e05
DA		 953 if (!found) /* fallback to defaults */
954 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
955
771fe6b9
JG		 956 return tv_dac;
957}
958
959static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
960 radeon_device
961 *rdev)
962{
963 struct radeon_encoder_lvds *lvds = NULL;
964 uint32_t fp_vert_stretch, fp_horz_stretch;
965 uint32_t ppll_div_sel, ppll_val;
8b5c7444 966 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 967
968 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
969
970 if (!lvds)
971 return NULL;
972
973 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
974 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
975
8b5c7444
MD		 976 /* These should be fail-safe defaults, fingers crossed */
977 lvds->panel_pwr_delay = 200;
978 lvds->panel_vcc_delay = 2000;
979
980 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
981 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
982 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
983
771fe6b9 984 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 985 lvds->native_mode.vdisplay =
771fe6b9
JG		 986 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
987 RADEON_VERT_PANEL_SHIFT) + 1;
988 else
de2103e4 989 lvds->native_mode.vdisplay =
771fe6b9
JG		 990 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
991
992 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 993 lvds->native_mode.hdisplay =
771fe6b9
JG		 994 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
995 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
996 else
de2103e4 997 lvds->native_mode.hdisplay =
771fe6b9
JG		 998 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
999
de2103e4
AD		 1000 if ((lvds->native_mode.hdisplay < 640) ||
1001 (lvds->native_mode.vdisplay < 480)) {
1002 lvds->native_mode.hdisplay = 640;
1003 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 1004 }
1005
1006 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1007 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1008 if ((ppll_val & 0x000707ff) == 0x1bb)
1009 lvds->use_bios_dividers = false;
1010 else {
1011 lvds->panel_ref_divider =
1012 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1013 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1014 lvds->panel_fb_divider = ppll_val & 0x7ff;
1015
1016 if ((lvds->panel_ref_divider != 0) &&
1017 (lvds->panel_fb_divider > 3))
1018 lvds->use_bios_dividers = true;
1019 }
1020 lvds->panel_vcc_delay = 200;
1021
1022 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 1023 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1024 lvds->native_mode.vdisplay);
771fe6b9
JG		 1025
1026 return lvds;
1027}
1028
1029struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1030 *encoder)
1031{
1032 struct drm_device *dev = encoder->base.dev;
1033 struct radeon_device *rdev = dev->dev_private;
1034 uint16_t lcd_info;
1035 uint32_t panel_setup;
1036 char stmp[30];
1037 int tmp, i;
1038 struct radeon_encoder_lvds *lvds = NULL;
1039
771fe6b9
JG		 1040 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1041
1042 if (lcd_info) {
1043 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1044
1045 if (!lvds)
1046 return NULL;
1047
1048 for (i = 0; i < 24; i++)
1049 stmp[i] = RBIOS8(lcd_info + i + 1);
1050 stmp[24] = 0;
1051
1052 DRM_INFO("Panel ID String: %s\n", stmp);
1053
de2103e4
AD		 1054 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1055 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 1056
de2103e4
AD		 1057 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1058 lvds->native_mode.vdisplay);
771fe6b9
JG		 1059
1060 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
94cf6434 1061 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
771fe6b9
JG		 1062
1063 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1064 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1065 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1066
1067 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1068 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1069 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1070 if ((lvds->panel_ref_divider != 0) &&
1071 (lvds->panel_fb_divider > 3))
1072 lvds->use_bios_dividers = true;
1073
1074 panel_setup = RBIOS32(lcd_info + 0x39);
1075 lvds->lvds_gen_cntl = 0xff00;
1076 if (panel_setup & 0x1)
1077 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1078
1079 if ((panel_setup >> 4) & 0x1)
1080 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1081
1082 switch ((panel_setup >> 8) & 0x7) {
1083 case 0:
1084 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1085 break;
1086 case 1:
1087 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1088 break;
1089 case 2:
1090 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1091 break;
1092 default:
1093 break;
1094 }
1095
1096 if ((panel_setup >> 16) & 0x1)
1097 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1098
1099 if ((panel_setup >> 17) & 0x1)
1100 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1101
1102 if ((panel_setup >> 18) & 0x1)
1103 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1104
1105 if ((panel_setup >> 23) & 0x1)
1106 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1107
1108 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1109
1110 for (i = 0; i < 32; i++) {
1111 tmp = RBIOS16(lcd_info + 64 + i * 2);
1112 if (tmp == 0)
1113 break;
1114
de2103e4 1115 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
68b61a7f
AD		 1116 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1117 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1118 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1119 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1120 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1121 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1122 (RBIOS8(tmp + 23) * 8);
1123
1124 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1125 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1126 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1127 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1128 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1129 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
de2103e4
AD		 1130
1131 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1132 lvds->native_mode.flags = 0;
de2103e4
AD		 1133 /* set crtc values */
1134 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1135
771fe6b9
JG		 1136 }
1137 }
6fe7ac3f 1138 } else {
771fe6b9 1139 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1140 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1141 }
03047cdf 1142
8dfaa8a7
MD		 1143 if (lvds)
1144 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1145 return lvds;
1146}
1147
1148static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1149 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1150 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1151 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1152 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1153 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1154 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1155 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1156 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1157 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1158 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1159 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1160 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1161 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1162 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1163 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1164 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1165 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1166 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1167};
1168
445282db
DA		 1169bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1170 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1171{
445282db
DA		 1172 struct drm_device *dev = encoder->base.dev;
1173 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1174 int i;
771fe6b9
JG		 1175
1176 for (i = 0; i < 4; i++) {
1177 tmds->tmds_pll[i].value =
445282db 1178 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1179 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1180 }
1181
445282db 1182 return true;
771fe6b9
JG		 1183}
1184
445282db
DA		 1185bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1186 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1187{
1188 struct drm_device *dev = encoder->base.dev;
1189 struct radeon_device *rdev = dev->dev_private;
1190 uint16_t tmds_info;
1191 int i, n;
1192 uint8_t ver;
771fe6b9 1193
771fe6b9
JG		 1194 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1195
1196 if (tmds_info) {
771fe6b9
JG		 1197 ver = RBIOS8(tmds_info);
1198 DRM_INFO("DFP table revision: %d\n", ver);
1199 if (ver == 3) {
1200 n = RBIOS8(tmds_info + 5) + 1;
1201 if (n > 4)
1202 n = 4;
1203 for (i = 0; i < n; i++) {
1204 tmds->tmds_pll[i].value =
1205 RBIOS32(tmds_info + i * 10 + 0x08);
1206 tmds->tmds_pll[i].freq =
1207 RBIOS16(tmds_info + i * 10 + 0x10);
1208 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1209 tmds->tmds_pll[i].freq,
1210 tmds->tmds_pll[i].value);
1211 }
1212 } else if (ver == 4) {
1213 int stride = 0;
1214 n = RBIOS8(tmds_info + 5) + 1;
1215 if (n > 4)
1216 n = 4;
1217 for (i = 0; i < n; i++) {
1218 tmds->tmds_pll[i].value =
1219 RBIOS32(tmds_info + stride + 0x08);
1220 tmds->tmds_pll[i].freq =
1221 RBIOS16(tmds_info + stride + 0x10);
1222 if (i == 0)
1223 stride += 10;
1224 else
1225 stride += 6;
1226 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1227 tmds->tmds_pll[i].freq,
1228 tmds->tmds_pll[i].value);
1229 }
1230 }
fcec570b 1231 } else {
771fe6b9 1232 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1233 return false;
1234 }
445282db
DA		 1235 return true;
1236}
1237
fcec570b
AD		 1238bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1239 struct radeon_encoder_ext_tmds *tmds)
445282db 1240{
fcec570b
AD		 1241 struct drm_device *dev = encoder->base.dev;
1242 struct radeon_device *rdev = dev->dev_private;
1243 struct radeon_i2c_bus_rec i2c_bus;
445282db 1244
fcec570b 1245 /* default for macs */
6a93cb25 1246 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1247 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
445282db 1248
fcec570b
AD		 1249 /* XXX some macs have duallink chips */
1250 switch (rdev->mode_info.connector_table) {
1251 case CT_POWERBOOK_EXTERNAL:
1252 case CT_MINI_EXTERNAL:
1253 default:
1254 tmds->dvo_chip = DVO_SIL164;
1255 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1256 break;
1257 }
445282db 1258
fcec570b 1259 return true;
771fe6b9
JG		 1260}
1261
fcec570b
AD		 1262bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1263 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1264{
1265 struct drm_device *dev = encoder->base.dev;
1266 struct radeon_device *rdev = dev->dev_private;
fcec570b
AD		 1267 uint16_t offset;
1268 uint8_t ver, id, blocks, clk, data;
1269 int i;
1270 enum radeon_combios_ddc gpio;
1271 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1272
fcec570b
AD		 1273 tmds->i2c_bus = NULL;
1274 if (rdev->flags & RADEON_IS_IGP) {
1275 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1276 if (offset) {
1277 ver = RBIOS8(offset);
1278 DRM_INFO("GPIO Table revision: %d\n", ver);
1279 blocks = RBIOS8(offset + 2);
1280 for (i = 0; i < blocks; i++) {
1281 id = RBIOS8(offset + 3 + (i * 5) + 0);
1282 if (id == 136) {
1283 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1284 data = RBIOS8(offset + 3 + (i * 5) + 4);
1285 i2c_bus.valid = true;
1286 i2c_bus.mask_clk_mask = (1 << clk);
1287 i2c_bus.mask_data_mask = (1 << data);
1288 i2c_bus.a_clk_mask = (1 << clk);
1289 i2c_bus.a_data_mask = (1 << data);
1290 i2c_bus.en_clk_mask = (1 << clk);
1291 i2c_bus.en_data_mask = (1 << data);
1292 i2c_bus.y_clk_mask = (1 << clk);
1293 i2c_bus.y_data_mask = (1 << data);
1294 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1295 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1296 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1297 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1298 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1299 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1300 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1301 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1302 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1303 tmds->dvo_chip = DVO_SIL164;
1304 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1305 break;
1306 }
1307 }
1308 }
1309 } else {
1310 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1311 if (offset) {
1312 ver = RBIOS8(offset);
1313 DRM_INFO("External TMDS Table revision: %d\n", ver);
1314 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1315 tmds->slave_addr >>= 1; /* 7 bit addressing */
1316 gpio = RBIOS8(offset + 4 + 3);
1317 switch (gpio) {
1318 case DDC_MONID:
6a93cb25 1319 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b
AD		 1320 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1321 break;
1322 case DDC_DVI:
6a93cb25 1323 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b
AD		 1324 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1325 break;
1326 case DDC_VGA:
6a93cb25 1327 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
fcec570b
AD		 1328 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1329 break;
1330 case DDC_CRT2:
1331 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1332 if (rdev->family >= CHIP_R300)
6a93cb25 1333 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1334 else
6a93cb25 1335 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
fcec570b
AD		 1336 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1337 break;
1338 case DDC_LCD: /* MM i2c */
40bacf16
AD		 1339 i2c_bus.valid = true;
1340 i2c_bus.hw_capable = true;
1341 i2c_bus.mm_i2c = true;
1342 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
fcec570b
AD		 1343 break;
1344 default:
1345 DRM_ERROR("Unsupported gpio %d\n", gpio);
1346 break;
1347 }
1348 }
771fe6b9 1349 }
fcec570b
AD		 1350
1351 if (!tmds->i2c_bus) {
1352 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1353 return false;
1354 }
1355
1356 return true;
771fe6b9
JG		 1357}
1358
1359bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1360{
1361 struct radeon_device *rdev = dev->dev_private;
1362 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1363 struct radeon_hpd hpd;
771fe6b9
JG		 1364
1365 rdev->mode_info.connector_table = radeon_connector_table;
1366 if (rdev->mode_info.connector_table == CT_NONE) {
1367#ifdef CONFIG_PPC_PMAC
71a157e8 1368 if (of_machine_is_compatible("PowerBook3,3")) {
771fe6b9
JG		 1369 /* powerbook with VGA */
1370 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
71a157e8
GL		 1371 } else if (of_machine_is_compatible("PowerBook3,4") ||
1372 of_machine_is_compatible("PowerBook3,5")) {
771fe6b9
JG		 1373 /* powerbook with internal tmds */
1374 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
71a157e8
GL		 1375 } else if (of_machine_is_compatible("PowerBook5,1") ||
1376 of_machine_is_compatible("PowerBook5,2") ||
1377 of_machine_is_compatible("PowerBook5,3") ||
1378 of_machine_is_compatible("PowerBook5,4") ||
1379 of_machine_is_compatible("PowerBook5,5")) {
771fe6b9
JG		 1380 /* powerbook with external single link tmds (sil164) */
1381 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8 1382 } else if (of_machine_is_compatible("PowerBook5,6")) {
771fe6b9
JG		 1383 /* powerbook with external dual or single link tmds */
1384 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1385 } else if (of_machine_is_compatible("PowerBook5,7") ||
1386 of_machine_is_compatible("PowerBook5,8") ||
1387 of_machine_is_compatible("PowerBook5,9")) {
771fe6b9
JG		 1388 /* PowerBook6,2 ? */
1389 /* powerbook with external dual link tmds (sil1178?) */
1390 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1391 } else if (of_machine_is_compatible("PowerBook4,1") ||
1392 of_machine_is_compatible("PowerBook4,2") ||
1393 of_machine_is_compatible("PowerBook4,3") ||
1394 of_machine_is_compatible("PowerBook6,3") ||
1395 of_machine_is_compatible("PowerBook6,5") ||
1396 of_machine_is_compatible("PowerBook6,7")) {
771fe6b9
JG		 1397 /* ibook */
1398 rdev->mode_info.connector_table = CT_IBOOK;
71a157e8 1399 } else if (of_machine_is_compatible("PowerMac4,4")) {
771fe6b9
JG		 1400 /* emac */
1401 rdev->mode_info.connector_table = CT_EMAC;
71a157e8 1402 } else if (of_machine_is_compatible("PowerMac10,1")) {
771fe6b9
JG		 1403 /* mini with internal tmds */
1404 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
71a157e8 1405 } else if (of_machine_is_compatible("PowerMac10,2")) {
771fe6b9
JG		 1406 /* mini with external tmds */
1407 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
71a157e8 1408 } else if (of_machine_is_compatible("PowerMac12,1")) {
771fe6b9
JG		 1409 /* PowerMac8,1 ? */
1410 /* imac g5 isight */
1411 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1412 } else
1413#endif /* CONFIG_PPC_PMAC */
1414 rdev->mode_info.connector_table = CT_GENERIC;
1415 }
1416
1417 switch (rdev->mode_info.connector_table) {
1418 case CT_GENERIC:
1419 DRM_INFO("Connector Table: %d (generic)\n",
1420 rdev->mode_info.connector_table);
1421 /* these are the most common settings */
1422 if (rdev->flags & RADEON_SINGLE_CRTC) {
1423 /* VGA - primary dac */
6a93cb25 1424 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1425 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1426 radeon_add_legacy_encoder(dev,
1427 radeon_get_encoder_id(dev,
1428 ATOM_DEVICE_CRT1_SUPPORT,
1429 1),
1430 ATOM_DEVICE_CRT1_SUPPORT);
1431 radeon_add_legacy_connector(dev, 0,
1432 ATOM_DEVICE_CRT1_SUPPORT,
1433 DRM_MODE_CONNECTOR_VGA,
b75fad06 1434 &ddc_i2c,
eed45b30
AD		 1435 CONNECTOR_OBJECT_ID_VGA,
1436 &hpd);
771fe6b9
JG		 1437 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1438 /* LVDS */
6a93cb25 1439 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
eed45b30 1440 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1441 radeon_add_legacy_encoder(dev,
1442 radeon_get_encoder_id(dev,
1443 ATOM_DEVICE_LCD1_SUPPORT,
1444 0),
1445 ATOM_DEVICE_LCD1_SUPPORT);
1446 radeon_add_legacy_connector(dev, 0,
1447 ATOM_DEVICE_LCD1_SUPPORT,
1448 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1449 &ddc_i2c,
eed45b30
AD		 1450 CONNECTOR_OBJECT_ID_LVDS,
1451 &hpd);
771fe6b9
JG		 1452
1453 /* VGA - primary dac */
6a93cb25 1454 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1455 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1456 radeon_add_legacy_encoder(dev,
1457 radeon_get_encoder_id(dev,
1458 ATOM_DEVICE_CRT1_SUPPORT,
1459 1),
1460 ATOM_DEVICE_CRT1_SUPPORT);
1461 radeon_add_legacy_connector(dev, 1,
1462 ATOM_DEVICE_CRT1_SUPPORT,
1463 DRM_MODE_CONNECTOR_VGA,
b75fad06 1464 &ddc_i2c,
eed45b30
AD		 1465 CONNECTOR_OBJECT_ID_VGA,
1466 &hpd);
771fe6b9
JG		 1467 } else {
1468 /* DVI-I - tv dac, int tmds */
6a93cb25 1469 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1470 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 1471 radeon_add_legacy_encoder(dev,
1472 radeon_get_encoder_id(dev,
1473 ATOM_DEVICE_DFP1_SUPPORT,
1474 0),
1475 ATOM_DEVICE_DFP1_SUPPORT);
1476 radeon_add_legacy_encoder(dev,
1477 radeon_get_encoder_id(dev,
1478 ATOM_DEVICE_CRT2_SUPPORT,
1479 2),
1480 ATOM_DEVICE_CRT2_SUPPORT);
1481 radeon_add_legacy_connector(dev, 0,
1482 ATOM_DEVICE_DFP1_SUPPORT |
1483 ATOM_DEVICE_CRT2_SUPPORT,
1484 DRM_MODE_CONNECTOR_DVII,
b75fad06 1485 &ddc_i2c,
eed45b30
AD		 1486 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1487 &hpd);
771fe6b9
JG		 1488
1489 /* VGA - primary dac */
6a93cb25 1490 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1491 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1492 radeon_add_legacy_encoder(dev,
1493 radeon_get_encoder_id(dev,
1494 ATOM_DEVICE_CRT1_SUPPORT,
1495 1),
1496 ATOM_DEVICE_CRT1_SUPPORT);
1497 radeon_add_legacy_connector(dev, 1,
1498 ATOM_DEVICE_CRT1_SUPPORT,
1499 DRM_MODE_CONNECTOR_VGA,
b75fad06 1500 &ddc_i2c,
eed45b30
AD		 1501 CONNECTOR_OBJECT_ID_VGA,
1502 &hpd);
771fe6b9
JG		 1503 }
1504
1505 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1506 /* TV - tv dac */
eed45b30
AD		 1507 ddc_i2c.valid = false;
1508 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1509 radeon_add_legacy_encoder(dev,
1510 radeon_get_encoder_id(dev,
1511 ATOM_DEVICE_TV1_SUPPORT,
1512 2),
1513 ATOM_DEVICE_TV1_SUPPORT);
1514 radeon_add_legacy_connector(dev, 2,
1515 ATOM_DEVICE_TV1_SUPPORT,
1516 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1517 &ddc_i2c,
eed45b30
AD		 1518 CONNECTOR_OBJECT_ID_SVIDEO,
1519 &hpd);
771fe6b9
JG		 1520 }
1521 break;
1522 case CT_IBOOK:
1523 DRM_INFO("Connector Table: %d (ibook)\n",
1524 rdev->mode_info.connector_table);
1525 /* LVDS */
6a93cb25 1526 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1527 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1528 radeon_add_legacy_encoder(dev,
1529 radeon_get_encoder_id(dev,
1530 ATOM_DEVICE_LCD1_SUPPORT,
1531 0),
1532 ATOM_DEVICE_LCD1_SUPPORT);
1533 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1534 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1535 CONNECTOR_OBJECT_ID_LVDS,
1536 &hpd);
771fe6b9 1537 /* VGA - TV DAC */
6a93cb25 1538 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1539 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1540 radeon_add_legacy_encoder(dev,
1541 radeon_get_encoder_id(dev,
1542 ATOM_DEVICE_CRT2_SUPPORT,
1543 2),
1544 ATOM_DEVICE_CRT2_SUPPORT);
1545 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1546 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1547 CONNECTOR_OBJECT_ID_VGA,
1548 &hpd);
771fe6b9 1549 /* TV - TV DAC */
eed45b30
AD		 1550 ddc_i2c.valid = false;
1551 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1552 radeon_add_legacy_encoder(dev,
1553 radeon_get_encoder_id(dev,
1554 ATOM_DEVICE_TV1_SUPPORT,
1555 2),
1556 ATOM_DEVICE_TV1_SUPPORT);
1557 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1558 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1559 &ddc_i2c,
eed45b30
AD		 1560 CONNECTOR_OBJECT_ID_SVIDEO,
1561 &hpd);
771fe6b9
JG		 1562 break;
1563 case CT_POWERBOOK_EXTERNAL:
1564 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1565 rdev->mode_info.connector_table);
1566 /* LVDS */
6a93cb25 1567 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1568 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1569 radeon_add_legacy_encoder(dev,
1570 radeon_get_encoder_id(dev,
1571 ATOM_DEVICE_LCD1_SUPPORT,
1572 0),
1573 ATOM_DEVICE_LCD1_SUPPORT);
1574 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1575 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1576 CONNECTOR_OBJECT_ID_LVDS,
1577 &hpd);
771fe6b9 1578 /* DVI-I - primary dac, ext tmds */
6a93cb25 1579 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1580 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1581 radeon_add_legacy_encoder(dev,
1582 radeon_get_encoder_id(dev,
1583 ATOM_DEVICE_DFP2_SUPPORT,
1584 0),
1585 ATOM_DEVICE_DFP2_SUPPORT);
1586 radeon_add_legacy_encoder(dev,
1587 radeon_get_encoder_id(dev,
1588 ATOM_DEVICE_CRT1_SUPPORT,
1589 1),
1590 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1591 /* XXX some are SL */
771fe6b9
JG		 1592 radeon_add_legacy_connector(dev, 1,
1593 ATOM_DEVICE_DFP2_SUPPORT |
1594 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1595 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1596 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1597 &hpd);
771fe6b9 1598 /* TV - TV DAC */
eed45b30
AD		 1599 ddc_i2c.valid = false;
1600 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1601 radeon_add_legacy_encoder(dev,
1602 radeon_get_encoder_id(dev,
1603 ATOM_DEVICE_TV1_SUPPORT,
1604 2),
1605 ATOM_DEVICE_TV1_SUPPORT);
1606 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1607 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1608 &ddc_i2c,
eed45b30
AD		 1609 CONNECTOR_OBJECT_ID_SVIDEO,
1610 &hpd);
771fe6b9
JG		 1611 break;
1612 case CT_POWERBOOK_INTERNAL:
1613 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1614 rdev->mode_info.connector_table);
1615 /* LVDS */
6a93cb25 1616 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1617 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1618 radeon_add_legacy_encoder(dev,
1619 radeon_get_encoder_id(dev,
1620 ATOM_DEVICE_LCD1_SUPPORT,
1621 0),
1622 ATOM_DEVICE_LCD1_SUPPORT);
1623 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1624 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1625 CONNECTOR_OBJECT_ID_LVDS,
1626 &hpd);
771fe6b9 1627 /* DVI-I - primary dac, int tmds */
6a93cb25 1628 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1629 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1630 radeon_add_legacy_encoder(dev,
1631 radeon_get_encoder_id(dev,
1632 ATOM_DEVICE_DFP1_SUPPORT,
1633 0),
1634 ATOM_DEVICE_DFP1_SUPPORT);
1635 radeon_add_legacy_encoder(dev,
1636 radeon_get_encoder_id(dev,
1637 ATOM_DEVICE_CRT1_SUPPORT,
1638 1),
1639 ATOM_DEVICE_CRT1_SUPPORT);
1640 radeon_add_legacy_connector(dev, 1,
1641 ATOM_DEVICE_DFP1_SUPPORT |
1642 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1643 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1644 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1645 &hpd);
771fe6b9 1646 /* TV - TV DAC */
eed45b30
AD		 1647 ddc_i2c.valid = false;
1648 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1649 radeon_add_legacy_encoder(dev,
1650 radeon_get_encoder_id(dev,
1651 ATOM_DEVICE_TV1_SUPPORT,
1652 2),
1653 ATOM_DEVICE_TV1_SUPPORT);
1654 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1655 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1656 &ddc_i2c,
eed45b30
AD		 1657 CONNECTOR_OBJECT_ID_SVIDEO,
1658 &hpd);
771fe6b9
JG		 1659 break;
1660 case CT_POWERBOOK_VGA:
1661 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1662 rdev->mode_info.connector_table);
1663 /* LVDS */
6a93cb25 1664 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1665 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1666 radeon_add_legacy_encoder(dev,
1667 radeon_get_encoder_id(dev,
1668 ATOM_DEVICE_LCD1_SUPPORT,
1669 0),
1670 ATOM_DEVICE_LCD1_SUPPORT);
1671 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1672 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1673 CONNECTOR_OBJECT_ID_LVDS,
1674 &hpd);
771fe6b9 1675 /* VGA - primary dac */
6a93cb25 1676 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1677 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1678 radeon_add_legacy_encoder(dev,
1679 radeon_get_encoder_id(dev,
1680 ATOM_DEVICE_CRT1_SUPPORT,
1681 1),
1682 ATOM_DEVICE_CRT1_SUPPORT);
1683 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1684 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1685 CONNECTOR_OBJECT_ID_VGA,
1686 &hpd);
771fe6b9 1687 /* TV - TV DAC */
eed45b30
AD		 1688 ddc_i2c.valid = false;
1689 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1690 radeon_add_legacy_encoder(dev,
1691 radeon_get_encoder_id(dev,
1692 ATOM_DEVICE_TV1_SUPPORT,
1693 2),
1694 ATOM_DEVICE_TV1_SUPPORT);
1695 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1696 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1697 &ddc_i2c,
eed45b30
AD		 1698 CONNECTOR_OBJECT_ID_SVIDEO,
1699 &hpd);
771fe6b9
JG		 1700 break;
1701 case CT_MINI_EXTERNAL:
1702 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1703 rdev->mode_info.connector_table);
1704 /* DVI-I - tv dac, ext tmds */
6a93cb25 1705 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1706 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1707 radeon_add_legacy_encoder(dev,
1708 radeon_get_encoder_id(dev,
1709 ATOM_DEVICE_DFP2_SUPPORT,
1710 0),
1711 ATOM_DEVICE_DFP2_SUPPORT);
1712 radeon_add_legacy_encoder(dev,
1713 radeon_get_encoder_id(dev,
1714 ATOM_DEVICE_CRT2_SUPPORT,
1715 2),
1716 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1717 /* XXX are any DL? */
771fe6b9
JG		 1718 radeon_add_legacy_connector(dev, 0,
1719 ATOM_DEVICE_DFP2_SUPPORT |
1720 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1721 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1722 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1723 &hpd);
771fe6b9 1724 /* TV - TV DAC */
eed45b30
AD		 1725 ddc_i2c.valid = false;
1726 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1727 radeon_add_legacy_encoder(dev,
1728 radeon_get_encoder_id(dev,
1729 ATOM_DEVICE_TV1_SUPPORT,
1730 2),
1731 ATOM_DEVICE_TV1_SUPPORT);
1732 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1733 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1734 &ddc_i2c,
eed45b30
AD		 1735 CONNECTOR_OBJECT_ID_SVIDEO,
1736 &hpd);
771fe6b9
JG		 1737 break;
1738 case CT_MINI_INTERNAL:
1739 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1740 rdev->mode_info.connector_table);
1741 /* DVI-I - tv dac, int tmds */
6a93cb25 1742 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1743 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1744 radeon_add_legacy_encoder(dev,
1745 radeon_get_encoder_id(dev,
1746 ATOM_DEVICE_DFP1_SUPPORT,
1747 0),
1748 ATOM_DEVICE_DFP1_SUPPORT);
1749 radeon_add_legacy_encoder(dev,
1750 radeon_get_encoder_id(dev,
1751 ATOM_DEVICE_CRT2_SUPPORT,
1752 2),
1753 ATOM_DEVICE_CRT2_SUPPORT);
1754 radeon_add_legacy_connector(dev, 0,
1755 ATOM_DEVICE_DFP1_SUPPORT |
1756 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1757 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1758 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1759 &hpd);
771fe6b9 1760 /* TV - TV DAC */
eed45b30
AD		 1761 ddc_i2c.valid = false;
1762 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1763 radeon_add_legacy_encoder(dev,
1764 radeon_get_encoder_id(dev,
1765 ATOM_DEVICE_TV1_SUPPORT,
1766 2),
1767 ATOM_DEVICE_TV1_SUPPORT);
1768 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1769 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1770 &ddc_i2c,
eed45b30
AD		 1771 CONNECTOR_OBJECT_ID_SVIDEO,
1772 &hpd);
771fe6b9
JG		 1773 break;
1774 case CT_IMAC_G5_ISIGHT:
1775 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1776 rdev->mode_info.connector_table);
1777 /* DVI-D - int tmds */
6a93cb25 1778 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
eed45b30 1779 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1780 radeon_add_legacy_encoder(dev,
1781 radeon_get_encoder_id(dev,
1782 ATOM_DEVICE_DFP1_SUPPORT,
1783 0),
1784 ATOM_DEVICE_DFP1_SUPPORT);
1785 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1786 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1787 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1788 &hpd);
771fe6b9 1789 /* VGA - tv dac */
6a93cb25 1790 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1791 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1792 radeon_add_legacy_encoder(dev,
1793 radeon_get_encoder_id(dev,
1794 ATOM_DEVICE_CRT2_SUPPORT,
1795 2),
1796 ATOM_DEVICE_CRT2_SUPPORT);
1797 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1798 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1799 CONNECTOR_OBJECT_ID_VGA,
1800 &hpd);
771fe6b9 1801 /* TV - TV DAC */
eed45b30
AD		 1802 ddc_i2c.valid = false;
1803 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1804 radeon_add_legacy_encoder(dev,
1805 radeon_get_encoder_id(dev,
1806 ATOM_DEVICE_TV1_SUPPORT,
1807 2),
1808 ATOM_DEVICE_TV1_SUPPORT);
1809 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1810 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1811 &ddc_i2c,
eed45b30
AD		 1812 CONNECTOR_OBJECT_ID_SVIDEO,
1813 &hpd);
771fe6b9
JG		 1814 break;
1815 case CT_EMAC:
1816 DRM_INFO("Connector Table: %d (emac)\n",
1817 rdev->mode_info.connector_table);
1818 /* VGA - primary dac */
6a93cb25 1819 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1820 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1821 radeon_add_legacy_encoder(dev,
1822 radeon_get_encoder_id(dev,
1823 ATOM_DEVICE_CRT1_SUPPORT,
1824 1),
1825 ATOM_DEVICE_CRT1_SUPPORT);
1826 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1827 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1828 CONNECTOR_OBJECT_ID_VGA,
1829 &hpd);
771fe6b9 1830 /* VGA - tv dac */
6a93cb25 1831 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1832 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1833 radeon_add_legacy_encoder(dev,
1834 radeon_get_encoder_id(dev,
1835 ATOM_DEVICE_CRT2_SUPPORT,
1836 2),
1837 ATOM_DEVICE_CRT2_SUPPORT);
1838 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1839 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1840 CONNECTOR_OBJECT_ID_VGA,
1841 &hpd);
771fe6b9 1842 /* TV - TV DAC */
eed45b30
AD		 1843 ddc_i2c.valid = false;
1844 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1845 radeon_add_legacy_encoder(dev,
1846 radeon_get_encoder_id(dev,
1847 ATOM_DEVICE_TV1_SUPPORT,
1848 2),
1849 ATOM_DEVICE_TV1_SUPPORT);
1850 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1851 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1852 &ddc_i2c,
eed45b30
AD		 1853 CONNECTOR_OBJECT_ID_SVIDEO,
1854 &hpd);
771fe6b9
JG		 1855 break;
1856 default:
1857 DRM_INFO("Connector table: %d (invalid)\n",
1858 rdev->mode_info.connector_table);
1859 return false;
1860 }
1861
1862 radeon_link_encoder_connector(dev);
1863
1864 return true;
1865}
1866
1867static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1868 int bios_index,
1869 enum radeon_combios_connector
1870 *legacy_connector,
eed45b30
AD		 1871 struct radeon_i2c_bus_rec *ddc_i2c,
1872 struct radeon_hpd *hpd)
771fe6b9
JG		 1873{
1874 struct radeon_device *rdev = dev->dev_private;
1875
1876 /* XPRESS DDC quirks */
1877 if ((rdev->family == CHIP_RS400 ||
1878 rdev->family == CHIP_RS480) &&
1879 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1880 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 1881 else if ((rdev->family == CHIP_RS400 ||
1882 rdev->family == CHIP_RS480) &&
1883 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
6a93cb25 1884 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 1885 ddc_i2c->mask_clk_mask = (0x20 << 8);
1886 ddc_i2c->mask_data_mask = 0x80;
1887 ddc_i2c->a_clk_mask = (0x20 << 8);
1888 ddc_i2c->a_data_mask = 0x80;
9b9fe724
AD		 1889 ddc_i2c->en_clk_mask = (0x20 << 8);
1890 ddc_i2c->en_data_mask = 0x80;
1891 ddc_i2c->y_clk_mask = (0x20 << 8);
1892 ddc_i2c->y_data_mask = 0x80;
771fe6b9
JG		 1893 }
1894
fcec570b
AD		 1895 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1896 if ((rdev->family >= CHIP_R300) &&
1897 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1898 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b 1899
771fe6b9
JG		 1900 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1901 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1902 if (dev->pdev->device == 0x515e &&
1903 dev->pdev->subsystem_vendor == 0x1014) {
1904 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1905 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1906 return false;
1907 }
1908
1909 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1910 if (dev->pdev->device == 0x5159 &&
1911 dev->pdev->subsystem_vendor == 0x1002 &&
1912 dev->pdev->subsystem_device == 0x013a) {
1913 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1914 *legacy_connector = CONNECTOR_CRT_LEGACY;
1915
1916 }
1917
1918 /* X300 card with extra non-existent DVI port */
1919 if (dev->pdev->device == 0x5B60 &&
1920 dev->pdev->subsystem_vendor == 0x17af &&
1921 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1922 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1923 return false;
1924 }
1925
1926 return true;
1927}
1928
790cfb34
AD		 1929static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1930{
1931 /* Acer 5102 has non-existent TV port */
1932 if (dev->pdev->device == 0x5975 &&
1933 dev->pdev->subsystem_vendor == 0x1025 &&
1934 dev->pdev->subsystem_device == 0x009f)
1935 return false;
1936
fc7f7119
AD		 1937 /* HP dc5750 has non-existent TV port */
1938 if (dev->pdev->device == 0x5974 &&
1939 dev->pdev->subsystem_vendor == 0x103c &&
1940 dev->pdev->subsystem_device == 0x280a)
1941 return false;
1942
fd874ad0
AD		 1943 /* MSI S270 has non-existent TV port */
1944 if (dev->pdev->device == 0x5955 &&
1945 dev->pdev->subsystem_vendor == 0x1462 &&
1946 dev->pdev->subsystem_device == 0x0131)
1947 return false;
1948
790cfb34
AD		 1949 return true;
1950}
1951
b75fad06
AD		 1952static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1953{
1954 struct radeon_device *rdev = dev->dev_private;
1955 uint32_t ext_tmds_info;
1956
1957 if (rdev->flags & RADEON_IS_IGP) {
1958 if (is_dvi_d)
1959 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1960 else
1961 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1962 }
1963 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1964 if (ext_tmds_info) {
1965 uint8_t rev = RBIOS8(ext_tmds_info);
1966 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1967 if (rev >= 3) {
1968 if (is_dvi_d)
1969 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1970 else
1971 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1972 } else {
1973 if (flags & 1) {
1974 if (is_dvi_d)
1975 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1976 else
1977 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1978 }
1979 }
1980 }
1981 if (is_dvi_d)
1982 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1983 else
1984 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1985}
1986
771fe6b9
JG		 1987bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1988{
1989 struct radeon_device *rdev = dev->dev_private;
1990 uint32_t conn_info, entry, devices;
b75fad06 1991 uint16_t tmp, connector_object_id;
771fe6b9
JG		 1992 enum radeon_combios_ddc ddc_type;
1993 enum radeon_combios_connector connector;
1994 int i = 0;
1995 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1996 struct radeon_hpd hpd;
771fe6b9 1997
771fe6b9
JG		 1998 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1999 if (conn_info) {
2000 for (i = 0; i < 4; i++) {
2001 entry = conn_info + 2 + i * 2;
2002
2003 if (!RBIOS16(entry))
2004 break;
2005
2006 tmp = RBIOS16(entry);
2007
2008 connector = (tmp >> 12) & 0xf;
2009
2010 ddc_type = (tmp >> 8) & 0xf;
2011 switch (ddc_type) {
2012 case DDC_MONID:
2013 ddc_i2c =
6a93cb25 2014 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2015 break;
2016 case DDC_DVI:
2017 ddc_i2c =
6a93cb25 2018 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2019 break;
2020 case DDC_VGA:
2021 ddc_i2c =
6a93cb25 2022 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2023 break;
2024 case DDC_CRT2:
2025 ddc_i2c =
6a93cb25 2026 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2027 break;
2028 default:
2029 break;
2030 }
2031
eed45b30
AD		 2032 switch (connector) {
2033 case CONNECTOR_PROPRIETARY_LEGACY:
2034 case CONNECTOR_DVI_I_LEGACY:
2035 case CONNECTOR_DVI_D_LEGACY:
2036 if ((tmp >> 4) & 0x1)
2037 hpd.hpd = RADEON_HPD_2;
2038 else
2039 hpd.hpd = RADEON_HPD_1;
2040 break;
2041 default:
2042 hpd.hpd = RADEON_HPD_NONE;
2043 break;
2044 }
2045
2d152c6b 2046 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 2047 &ddc_i2c, &hpd))
2d152c6b 2048 continue;
771fe6b9
JG		 2049
2050 switch (connector) {
2051 case CONNECTOR_PROPRIETARY_LEGACY:
2052 if ((tmp >> 4) & 0x1)
2053 devices = ATOM_DEVICE_DFP2_SUPPORT;
2054 else
2055 devices = ATOM_DEVICE_DFP1_SUPPORT;
2056 radeon_add_legacy_encoder(dev,
2057 radeon_get_encoder_id
2058 (dev, devices, 0),
2059 devices);
2060 radeon_add_legacy_connector(dev, i, devices,
2061 legacy_connector_convert
2062 [connector],
b75fad06 2063 &ddc_i2c,
eed45b30
AD		 2064 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2065 &hpd);
771fe6b9
JG		 2066 break;
2067 case CONNECTOR_CRT_LEGACY:
2068 if (tmp & 0x1) {
2069 devices = ATOM_DEVICE_CRT2_SUPPORT;
2070 radeon_add_legacy_encoder(dev,
2071 radeon_get_encoder_id
2072 (dev,
2073 ATOM_DEVICE_CRT2_SUPPORT,
2074 2),
2075 ATOM_DEVICE_CRT2_SUPPORT);
2076 } else {
2077 devices = ATOM_DEVICE_CRT1_SUPPORT;
2078 radeon_add_legacy_encoder(dev,
2079 radeon_get_encoder_id
2080 (dev,
2081 ATOM_DEVICE_CRT1_SUPPORT,
2082 1),
2083 ATOM_DEVICE_CRT1_SUPPORT);
2084 }
2085 radeon_add_legacy_connector(dev,
2086 i,
2087 devices,
2088 legacy_connector_convert
2089 [connector],
b75fad06 2090 &ddc_i2c,
eed45b30
AD		 2091 CONNECTOR_OBJECT_ID_VGA,
2092 &hpd);
771fe6b9
JG		 2093 break;
2094 case CONNECTOR_DVI_I_LEGACY:
2095 devices = 0;
2096 if (tmp & 0x1) {
2097 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2098 radeon_add_legacy_encoder(dev,
2099 radeon_get_encoder_id
2100 (dev,
2101 ATOM_DEVICE_CRT2_SUPPORT,
2102 2),
2103 ATOM_DEVICE_CRT2_SUPPORT);
2104 } else {
2105 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2106 radeon_add_legacy_encoder(dev,
2107 radeon_get_encoder_id
2108 (dev,
2109 ATOM_DEVICE_CRT1_SUPPORT,
2110 1),
2111 ATOM_DEVICE_CRT1_SUPPORT);
2112 }
2113 if ((tmp >> 4) & 0x1) {
2114 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2115 radeon_add_legacy_encoder(dev,
2116 radeon_get_encoder_id
2117 (dev,
2118 ATOM_DEVICE_DFP2_SUPPORT,
2119 0),
2120 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2121 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2122 } else {
2123 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2124 radeon_add_legacy_encoder(dev,
2125 radeon_get_encoder_id
2126 (dev,
2127 ATOM_DEVICE_DFP1_SUPPORT,
2128 0),
2129 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2130 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2131 }
2132 radeon_add_legacy_connector(dev,
2133 i,
2134 devices,
2135 legacy_connector_convert
2136 [connector],
b75fad06 2137 &ddc_i2c,
eed45b30
AD		 2138 connector_object_id,
2139 &hpd);
771fe6b9
JG		 2140 break;
2141 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2142 if ((tmp >> 4) & 0x1) {
771fe6b9 2143 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2144 connector_object_id = combios_check_dl_dvi(dev, 1);
2145 } else {
771fe6b9 2146 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2147 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2148 }
771fe6b9
JG		 2149 radeon_add_legacy_encoder(dev,
2150 radeon_get_encoder_id
2151 (dev, devices, 0),
2152 devices);
2153 radeon_add_legacy_connector(dev, i, devices,
2154 legacy_connector_convert
2155 [connector],
b75fad06 2156 &ddc_i2c,
eed45b30
AD		 2157 connector_object_id,
2158 &hpd);
771fe6b9
JG		 2159 break;
2160 case CONNECTOR_CTV_LEGACY:
2161 case CONNECTOR_STV_LEGACY:
2162 radeon_add_legacy_encoder(dev,
2163 radeon_get_encoder_id
2164 (dev,
2165 ATOM_DEVICE_TV1_SUPPORT,
2166 2),
2167 ATOM_DEVICE_TV1_SUPPORT);
2168 radeon_add_legacy_connector(dev, i,
2169 ATOM_DEVICE_TV1_SUPPORT,
2170 legacy_connector_convert
2171 [connector],
b75fad06 2172 &ddc_i2c,
eed45b30
AD		 2173 CONNECTOR_OBJECT_ID_SVIDEO,
2174 &hpd);
771fe6b9
JG		 2175 break;
2176 default:
2177 DRM_ERROR("Unknown connector type: %d\n",
2178 connector);
2179 continue;
2180 }
2181
2182 }
2183 } else {
2184 uint16_t tmds_info =
2185 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2186 if (tmds_info) {
2187 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2188
2189 radeon_add_legacy_encoder(dev,
2190 radeon_get_encoder_id(dev,
2191 ATOM_DEVICE_CRT1_SUPPORT,
2192 1),
2193 ATOM_DEVICE_CRT1_SUPPORT);
2194 radeon_add_legacy_encoder(dev,
2195 radeon_get_encoder_id(dev,
2196 ATOM_DEVICE_DFP1_SUPPORT,
2197 0),
2198 ATOM_DEVICE_DFP1_SUPPORT);
2199
6a93cb25 2200 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
8e36ed00 2201 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 2202 radeon_add_legacy_connector(dev,
2203 0,
2204 ATOM_DEVICE_CRT1_SUPPORT |
2205 ATOM_DEVICE_DFP1_SUPPORT,
2206 DRM_MODE_CONNECTOR_DVII,
b75fad06 2207 &ddc_i2c,
eed45b30
AD		 2208 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2209 &hpd);
771fe6b9 2210 } else {
d0c403e9
AD		 2211 uint16_t crt_info =
2212 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2213 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2214 if (crt_info) {
2215 radeon_add_legacy_encoder(dev,
2216 radeon_get_encoder_id(dev,
2217 ATOM_DEVICE_CRT1_SUPPORT,
2218 1),
2219 ATOM_DEVICE_CRT1_SUPPORT);
6a93cb25 2220 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 2221 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2222 radeon_add_legacy_connector(dev,
2223 0,
2224 ATOM_DEVICE_CRT1_SUPPORT,
2225 DRM_MODE_CONNECTOR_VGA,
b75fad06 2226 &ddc_i2c,
eed45b30
AD		 2227 CONNECTOR_OBJECT_ID_VGA,
2228 &hpd);
d0c403e9
AD		 2229 } else {
2230 DRM_DEBUG("No connector info found\n");
2231 return false;
2232 }
771fe6b9
JG		 2233 }
2234 }
2235
2236 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2237 uint16_t lcd_info =
2238 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2239 if (lcd_info) {
2240 uint16_t lcd_ddc_info =
2241 combios_get_table_offset(dev,
2242 COMBIOS_LCD_DDC_INFO_TABLE);
2243
2244 radeon_add_legacy_encoder(dev,
2245 radeon_get_encoder_id(dev,
2246 ATOM_DEVICE_LCD1_SUPPORT,
2247 0),
2248 ATOM_DEVICE_LCD1_SUPPORT);
2249
2250 if (lcd_ddc_info) {
2251 ddc_type = RBIOS8(lcd_ddc_info + 2);
2252 switch (ddc_type) {
2253 case DDC_MONID:
2254 ddc_i2c =
2255 combios_setup_i2c_bus
6a93cb25 2256 (rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2257 break;
2258 case DDC_DVI:
2259 ddc_i2c =
2260 combios_setup_i2c_bus
6a93cb25 2261 (rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2262 break;
2263 case DDC_VGA:
2264 ddc_i2c =
2265 combios_setup_i2c_bus
6a93cb25 2266 (rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2267 break;
2268 case DDC_CRT2:
2269 ddc_i2c =
2270 combios_setup_i2c_bus
6a93cb25 2271 (rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2272 break;
2273 case DDC_LCD:
2274 ddc_i2c =
2275 combios_setup_i2c_bus
6a93cb25 2276 (rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 2277 ddc_i2c.mask_clk_mask =
2278 RBIOS32(lcd_ddc_info + 3);
2279 ddc_i2c.mask_data_mask =
2280 RBIOS32(lcd_ddc_info + 7);
2281 ddc_i2c.a_clk_mask =
2282 RBIOS32(lcd_ddc_info + 3);
2283 ddc_i2c.a_data_mask =
2284 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2285 ddc_i2c.en_clk_mask =
771fe6b9 2286 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2287 ddc_i2c.en_data_mask =
771fe6b9 2288 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2289 ddc_i2c.y_clk_mask =
771fe6b9 2290 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2291 ddc_i2c.y_data_mask =
771fe6b9
JG		 2292 RBIOS32(lcd_ddc_info + 7);
2293 break;
2294 case DDC_GPIO:
2295 ddc_i2c =
2296 combios_setup_i2c_bus
6a93cb25 2297 (rdev, RADEON_MDGPIO_MASK);
771fe6b9
JG		 2298 ddc_i2c.mask_clk_mask =
2299 RBIOS32(lcd_ddc_info + 3);
2300 ddc_i2c.mask_data_mask =
2301 RBIOS32(lcd_ddc_info + 7);
2302 ddc_i2c.a_clk_mask =
2303 RBIOS32(lcd_ddc_info + 3);
2304 ddc_i2c.a_data_mask =
2305 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2306 ddc_i2c.en_clk_mask =
771fe6b9 2307 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2308 ddc_i2c.en_data_mask =
771fe6b9 2309 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2310 ddc_i2c.y_clk_mask =
771fe6b9 2311 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2312 ddc_i2c.y_data_mask =
771fe6b9
JG		 2313 RBIOS32(lcd_ddc_info + 7);
2314 break;
2315 default:
2316 ddc_i2c.valid = false;
2317 break;
2318 }
2319 DRM_DEBUG("LCD DDC Info Table found!\n");
2320 } else
2321 ddc_i2c.valid = false;
2322
eed45b30 2323 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2324 radeon_add_legacy_connector(dev,
2325 5,
2326 ATOM_DEVICE_LCD1_SUPPORT,
2327 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2328 &ddc_i2c,
eed45b30
AD		 2329 CONNECTOR_OBJECT_ID_LVDS,
2330 &hpd);
771fe6b9
JG		 2331 }
2332 }
2333
2334 /* check TV table */
2335 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2336 uint32_t tv_info =
2337 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2338 if (tv_info) {
2339 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2340 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2341 hpd.hpd = RADEON_HPD_NONE;
790cfb34
AD		 2342 radeon_add_legacy_encoder(dev,
2343 radeon_get_encoder_id
2344 (dev,
2345 ATOM_DEVICE_TV1_SUPPORT,
2346 2),
2347 ATOM_DEVICE_TV1_SUPPORT);
2348 radeon_add_legacy_connector(dev, 6,
2349 ATOM_DEVICE_TV1_SUPPORT,
2350 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2351 &ddc_i2c,
eed45b30
AD		 2352 CONNECTOR_OBJECT_ID_SVIDEO,
2353 &hpd);
790cfb34 2354 }
771fe6b9
JG		 2355 }
2356 }
2357 }
2358
2359 radeon_link_encoder_connector(dev);
2360
2361 return true;
2362}
2363
56278a8e
AD		 2364void radeon_combios_get_power_modes(struct radeon_device *rdev)
2365{
2366 struct drm_device *dev = rdev->ddev;
2367 u16 offset, misc, misc2 = 0;
2368 u8 rev, blocks, tmp;
2369 int state_index = 0;
2370
a48b9b4e 2371 rdev->pm.default_power_state_index = -1;
56278a8e 2372
56278a8e
AD		 2373 if (rdev->flags & RADEON_IS_MOBILITY) {
2374 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2375 if (offset) {
2376 rev = RBIOS8(offset);
2377 blocks = RBIOS8(offset + 0x2);
2378 /* power mode 0 tends to be the only valid one */
2379 rdev->pm.power_state[state_index].num_clock_modes = 1;
2380 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2381 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2382 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2383 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2384 goto default_mode;
0ec0e74f
AD		 2385 rdev->pm.power_state[state_index].type =
2386 POWER_STATE_TYPE_BATTERY;
56278a8e
AD		 2387 misc = RBIOS16(offset + 0x5 + 0x0);
2388 if (rev > 4)
2389 misc2 = RBIOS16(offset + 0x5 + 0xe);
79daedc9
AD		 2390 rdev->pm.power_state[state_index].misc = misc;
2391 rdev->pm.power_state[state_index].misc2 = misc2;
56278a8e
AD		 2392 if (misc & 0x4) {
2393 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2394 if (misc & 0x8)
2395 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2396 true;
2397 else
2398 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2399 false;
2400 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2401 if (rev < 6) {
2402 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2403 RBIOS16(offset + 0x5 + 0xb) * 4;
2404 tmp = RBIOS8(offset + 0x5 + 0xd);
2405 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2406 } else {
2407 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2408 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2409 if (entries && voltage_table_offset) {
2410 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2411 RBIOS16(voltage_table_offset) * 4;
2412 tmp = RBIOS8(voltage_table_offset + 0x2);
2413 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2414 } else
2415 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2416 }
2417 switch ((misc2 & 0x700) >> 8) {
2418 case 0:
2419 default:
2420 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2421 break;
2422 case 1:
2423 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2424 break;
2425 case 2:
2426 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2427 break;
2428 case 3:
2429 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2430 break;
2431 case 4:
2432 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2433 break;
2434 }
2435 } else
2436 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2437 if (rev > 6)
79daedc9 2438 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e 2439 RBIOS8(offset + 0x5 + 0x10);
d7311171 2440 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e
AD		 2441 state_index++;
2442 } else {
2443 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2444 }
2445 } else {
2446 /* XXX figure out some good default low power mode for desktop cards */
2447 }
2448
2449default_mode:
2450 /* add the default mode */
0ec0e74f
AD		 2451 rdev->pm.power_state[state_index].type =
2452 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2453 rdev->pm.power_state[state_index].num_clock_modes = 1;
2454 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2455 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2456 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
84d88f4c
AD		 2457 if ((state_index > 0) &&
2458 (rdev->pm.power_state[0].clock_info[0].voltage.type = VOLTAGE_GPIO))
2459 rdev->pm.power_state[state_index].clock_info[0].voltage =
2460 rdev->pm.power_state[0].clock_info[0].voltage;
2461 else
2462 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2463 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2464 rdev->pm.power_state[state_index].flags = 0;
2465 rdev->pm.default_power_state_index = state_index;
56278a8e 2466 rdev->pm.num_power_states = state_index + 1;
9038dfdf 2467
a48b9b4e
AD		 2468 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2469 rdev->pm.current_clock_mode_index = 0;
56278a8e
AD		 2470}
2471
fcec570b
AD		 2472void radeon_external_tmds_setup(struct drm_encoder *encoder)
2473{
2474 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2475 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2476
2477 if (!tmds)
2478 return;
2479
2480 switch (tmds->dvo_chip) {
2481 case DVO_SIL164:
2482 /* sil 164 */
5a6f98f5
AD		 2483 radeon_i2c_put_byte(tmds->i2c_bus,
2484 tmds->slave_addr,
2485 0x08, 0x30);
2486 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2487 tmds->slave_addr,
2488 0x09, 0x00);
5a6f98f5
AD		 2489 radeon_i2c_put_byte(tmds->i2c_bus,
2490 tmds->slave_addr,
2491 0x0a, 0x90);
2492 radeon_i2c_put_byte(tmds->i2c_bus,
2493 tmds->slave_addr,
2494 0x0c, 0x89);
2495 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2496 tmds->slave_addr,
2497 0x08, 0x3b);
fcec570b
AD		 2498 break;
2499 case DVO_SIL1178:
2500 /* sil 1178 - untested */
2501 /*
2502 * 0x0f, 0x44
2503 * 0x0f, 0x4c
2504 * 0x0e, 0x01
2505 * 0x0a, 0x80
2506 * 0x09, 0x30
2507 * 0x0c, 0xc9
2508 * 0x0d, 0x70
2509 * 0x08, 0x32
2510 * 0x08, 0x33
2511 */
2512 break;
2513 default:
2514 break;
2515 }
2516
2517}
2518
2519bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2520{
2521 struct drm_device *dev = encoder->dev;
2522 struct radeon_device *rdev = dev->dev_private;
2523 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2524 uint16_t offset;
2525 uint8_t blocks, slave_addr, rev;
2526 uint32_t index, id;
2527 uint32_t reg, val, and_mask, or_mask;
2528 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2529
fcec570b
AD		 2530 if (!tmds)
2531 return false;
2532
2533 if (rdev->flags & RADEON_IS_IGP) {
2534 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2535 rev = RBIOS8(offset);
2536 if (offset) {
2537 rev = RBIOS8(offset);
2538 if (rev > 1) {
2539 blocks = RBIOS8(offset + 3);
2540 index = offset + 4;
2541 while (blocks > 0) {
2542 id = RBIOS16(index);
2543 index += 2;
2544 switch (id >> 13) {
2545 case 0:
2546 reg = (id & 0x1fff) * 4;
2547 val = RBIOS32(index);
2548 index += 4;
2549 WREG32(reg, val);
2550 break;
2551 case 2:
2552 reg = (id & 0x1fff) * 4;
2553 and_mask = RBIOS32(index);
2554 index += 4;
2555 or_mask = RBIOS32(index);
2556 index += 4;
2557 val = RREG32(reg);
2558 val = (val & and_mask) | or_mask;
2559 WREG32(reg, val);
2560 break;
2561 case 3:
2562 val = RBIOS16(index);
2563 index += 2;
2564 udelay(val);
2565 break;
2566 case 4:
2567 val = RBIOS16(index);
2568 index += 2;
2569 udelay(val * 1000);
2570 break;
2571 case 6:
2572 slave_addr = id & 0xff;
2573 slave_addr >>= 1; /* 7 bit addressing */
2574 index++;
2575 reg = RBIOS8(index);
2576 index++;
2577 val = RBIOS8(index);
2578 index++;
5a6f98f5
AD		 2579 radeon_i2c_put_byte(tmds->i2c_bus,
2580 slave_addr,
2581 reg, val);
fcec570b
AD		 2582 break;
2583 default:
2584 DRM_ERROR("Unknown id %d\n", id >> 13);
2585 break;
2586 }
2587 blocks--;
2588 }
2589 return true;
2590 }
2591 }
2592 } else {
2593 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2594 if (offset) {
2595 index = offset + 10;
2596 id = RBIOS16(index);
2597 while (id != 0xffff) {
2598 index += 2;
2599 switch (id >> 13) {
2600 case 0:
2601 reg = (id & 0x1fff) * 4;
2602 val = RBIOS32(index);
2603 WREG32(reg, val);
2604 break;
2605 case 2:
2606 reg = (id & 0x1fff) * 4;
2607 and_mask = RBIOS32(index);
2608 index += 4;
2609 or_mask = RBIOS32(index);
2610 index += 4;
2611 val = RREG32(reg);
2612 val = (val & and_mask) | or_mask;
2613 WREG32(reg, val);
2614 break;
2615 case 4:
2616 val = RBIOS16(index);
2617 index += 2;
2618 udelay(val);
2619 break;
2620 case 5:
2621 reg = id & 0x1fff;
2622 and_mask = RBIOS32(index);
2623 index += 4;
2624 or_mask = RBIOS32(index);
2625 index += 4;
2626 val = RREG32_PLL(reg);
2627 val = (val & and_mask) | or_mask;
2628 WREG32_PLL(reg, val);
2629 break;
2630 case 6:
2631 reg = id & 0x1fff;
2632 val = RBIOS8(index);
2633 index += 1;
5a6f98f5
AD		 2634 radeon_i2c_put_byte(tmds->i2c_bus,
2635 tmds->slave_addr,
2636 reg, val);
fcec570b
AD		 2637 break;
2638 default:
2639 DRM_ERROR("Unknown id %d\n", id >> 13);
2640 break;
2641 }
2642 id = RBIOS16(index);
2643 }
2644 return true;
2645 }
2646 }
2647 return false;
2648}
2649
771fe6b9
JG		 2650static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2651{
2652 struct radeon_device *rdev = dev->dev_private;
2653
2654 if (offset) {
2655 while (RBIOS16(offset)) {
2656 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2657 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2658 uint32_t val, and_mask, or_mask;
2659 uint32_t tmp;
2660
2661 offset += 2;
2662 switch (cmd) {
2663 case 0:
2664 val = RBIOS32(offset);
2665 offset += 4;
2666 WREG32(addr, val);
2667 break;
2668 case 1:
2669 val = RBIOS32(offset);
2670 offset += 4;
2671 WREG32(addr, val);
2672 break;
2673 case 2:
2674 and_mask = RBIOS32(offset);
2675 offset += 4;
2676 or_mask = RBIOS32(offset);
2677 offset += 4;
2678 tmp = RREG32(addr);
2679 tmp &= and_mask;
2680 tmp |= or_mask;
2681 WREG32(addr, tmp);
2682 break;
2683 case 3:
2684 and_mask = RBIOS32(offset);
2685 offset += 4;
2686 or_mask = RBIOS32(offset);
2687 offset += 4;
2688 tmp = RREG32(addr);
2689 tmp &= and_mask;
2690 tmp |= or_mask;
2691 WREG32(addr, tmp);
2692 break;
2693 case 4:
2694 val = RBIOS16(offset);
2695 offset += 2;
2696 udelay(val);
2697 break;
2698 case 5:
2699 val = RBIOS16(offset);
2700 offset += 2;
2701 switch (addr) {
2702 case 8:
2703 while (val--) {
2704 if (!
2705 (RREG32_PLL
2706 (RADEON_CLK_PWRMGT_CNTL) &
2707 RADEON_MC_BUSY))
2708 break;
2709 }
2710 break;
2711 case 9:
2712 while (val--) {
2713 if ((RREG32(RADEON_MC_STATUS) &
2714 RADEON_MC_IDLE))
2715 break;
2716 }
2717 break;
2718 default:
2719 break;
2720 }
2721 break;
2722 default:
2723 break;
2724 }
2725 }
2726 }
2727}
2728
2729static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2730{
2731 struct radeon_device *rdev = dev->dev_private;
2732
2733 if (offset) {
2734 while (RBIOS8(offset)) {
2735 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2736 uint8_t addr = (RBIOS8(offset) & 0x3f);
2737 uint32_t val, shift, tmp;
2738 uint32_t and_mask, or_mask;
2739
2740 offset++;
2741 switch (cmd) {
2742 case 0:
2743 val = RBIOS32(offset);
2744 offset += 4;
2745 WREG32_PLL(addr, val);
2746 break;
2747 case 1:
2748 shift = RBIOS8(offset) * 8;
2749 offset++;
2750 and_mask = RBIOS8(offset) << shift;
2751 and_mask |= ~(0xff << shift);
2752 offset++;
2753 or_mask = RBIOS8(offset) << shift;
2754 offset++;
2755 tmp = RREG32_PLL(addr);
2756 tmp &= and_mask;
2757 tmp |= or_mask;
2758 WREG32_PLL(addr, tmp);
2759 break;
2760 case 2:
2761 case 3:
2762 tmp = 1000;
2763 switch (addr) {
2764 case 1:
2765 udelay(150);
2766 break;
2767 case 2:
2768 udelay(1000);
2769 break;
2770 case 3:
2771 while (tmp--) {
2772 if (!
2773 (RREG32_PLL
2774 (RADEON_CLK_PWRMGT_CNTL) &
2775 RADEON_MC_BUSY))
2776 break;
2777 }
2778 break;
2779 case 4:
2780 while (tmp--) {
2781 if (RREG32_PLL
2782 (RADEON_CLK_PWRMGT_CNTL) &
2783 RADEON_DLL_READY)
2784 break;
2785 }
2786 break;
2787 case 5:
2788 tmp =
2789 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2790 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2791#if 0
2792 uint32_t mclk_cntl =
2793 RREG32_PLL
2794 (RADEON_MCLK_CNTL);
2795 mclk_cntl &= 0xffff0000;
2796 /*mclk_cntl |= 0x00001111;*//* ??? */
2797 WREG32_PLL(RADEON_MCLK_CNTL,
2798 mclk_cntl);
2799 udelay(10000);
2800#endif
2801 WREG32_PLL
2802 (RADEON_CLK_PWRMGT_CNTL,
2803 tmp &
2804 ~RADEON_CG_NO1_DEBUG_0);
2805 udelay(10000);
2806 }
2807 break;
2808 default:
2809 break;
2810 }
2811 break;
2812 default:
2813 break;
2814 }
2815 }
2816 }
2817}
2818
2819static void combios_parse_ram_reset_table(struct drm_device *dev,
2820 uint16_t offset)
2821{
2822 struct radeon_device *rdev = dev->dev_private;
2823 uint32_t tmp;
2824
2825 if (offset) {
2826 uint8_t val = RBIOS8(offset);
2827 while (val != 0xff) {
2828 offset++;
2829
2830 if (val == 0x0f) {
2831 uint32_t channel_complete_mask;
2832
2833 if (ASIC_IS_R300(rdev))
2834 channel_complete_mask =
2835 R300_MEM_PWRUP_COMPLETE;
2836 else
2837 channel_complete_mask =
2838 RADEON_MEM_PWRUP_COMPLETE;
2839 tmp = 20000;
2840 while (tmp--) {
2841 if ((RREG32(RADEON_MEM_STR_CNTL) &
2842 channel_complete_mask) ==
2843 channel_complete_mask)
2844 break;
2845 }
2846 } else {
2847 uint32_t or_mask = RBIOS16(offset);
2848 offset += 2;
2849
2850 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2851 tmp &= RADEON_SDRAM_MODE_MASK;
2852 tmp |= or_mask;
2853 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2854
2855 or_mask = val << 24;
2856 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2857 tmp &= RADEON_B3MEM_RESET_MASK;
2858 tmp |= or_mask;
2859 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2860 }
2861 val = RBIOS8(offset);
2862 }
2863 }
2864}
2865
2866static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2867 int mem_addr_mapping)
2868{
2869 struct radeon_device *rdev = dev->dev_private;
2870 uint32_t mem_cntl;
2871 uint32_t mem_size;
2872 uint32_t addr = 0;
2873
2874 mem_cntl = RREG32(RADEON_MEM_CNTL);
2875 if (mem_cntl & RV100_HALF_MODE)
2876 ram /= 2;
2877 mem_size = ram;
2878 mem_cntl &= ~(0xff << 8);
2879 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2880 WREG32(RADEON_MEM_CNTL, mem_cntl);
2881 RREG32(RADEON_MEM_CNTL);
2882
2883 /* sdram reset ? */
2884
2885 /* something like this???? */
2886 while (ram--) {
2887 addr = ram * 1024 * 1024;
2888 /* write to each page */
2889 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2890 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2891 /* read back and verify */
2892 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2893 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2894 return 0;
2895 }
2896
2897 return mem_size;
2898}
2899
2900static void combios_write_ram_size(struct drm_device *dev)
2901{
2902 struct radeon_device *rdev = dev->dev_private;
2903 uint8_t rev;
2904 uint16_t offset;
2905 uint32_t mem_size = 0;
2906 uint32_t mem_cntl = 0;
2907
2908 /* should do something smarter here I guess... */
2909 if (rdev->flags & RADEON_IS_IGP)
2910 return;
2911
2912 /* first check detected mem table */
2913 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2914 if (offset) {
2915 rev = RBIOS8(offset);
2916 if (rev < 3) {
2917 mem_cntl = RBIOS32(offset + 1);
2918 mem_size = RBIOS16(offset + 5);
2919 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2920 ((dev->pdev->device != 0x515e)
2921 && (dev->pdev->device != 0x5969)))
2922 WREG32(RADEON_MEM_CNTL, mem_cntl);
2923 }
2924 }
2925
2926 if (!mem_size) {
2927 offset =
2928 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2929 if (offset) {
2930 rev = RBIOS8(offset - 1);
2931 if (rev < 1) {
2932 if (((rdev->flags & RADEON_FAMILY_MASK) <
2933 CHIP_R200)
2934 && ((dev->pdev->device != 0x515e)
2935 && (dev->pdev->device != 0x5969))) {
2936 int ram = 0;
2937 int mem_addr_mapping = 0;
2938
2939 while (RBIOS8(offset)) {
2940 ram = RBIOS8(offset);
2941 mem_addr_mapping =
2942 RBIOS8(offset + 1);
2943 if (mem_addr_mapping != 0x25)
2944 ram *= 2;
2945 mem_size =
2946 combios_detect_ram(dev, ram,
2947 mem_addr_mapping);
2948 if (mem_size)
2949 break;
2950 offset += 2;
2951 }
2952 } else
2953 mem_size = RBIOS8(offset);
2954 } else {
2955 mem_size = RBIOS8(offset);
2956 mem_size *= 2; /* convert to MB */
2957 }
2958 }
2959 }
2960
2961 mem_size *= (1024 * 1024); /* convert to bytes */
2962 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2963}
2964
2965void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2966{
2967 uint16_t dyn_clk_info =
2968 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2969
2970 if (dyn_clk_info)
2971 combios_parse_pll_table(dev, dyn_clk_info);
2972}
2973
2974void radeon_combios_asic_init(struct drm_device *dev)
2975{
2976 struct radeon_device *rdev = dev->dev_private;
2977 uint16_t table;
2978
2979 /* port hardcoded mac stuff from radeonfb */
2980 if (rdev->bios == NULL)
2981 return;
2982
2983 /* ASIC INIT 1 */
2984 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2985 if (table)
2986 combios_parse_mmio_table(dev, table);
2987
2988 /* PLL INIT */
2989 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2990 if (table)
2991 combios_parse_pll_table(dev, table);
2992
2993 /* ASIC INIT 2 */
2994 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2995 if (table)
2996 combios_parse_mmio_table(dev, table);
2997
2998 if (!(rdev->flags & RADEON_IS_IGP)) {
2999 /* ASIC INIT 4 */
3000 table =
3001 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3002 if (table)
3003 combios_parse_mmio_table(dev, table);
3004
3005 /* RAM RESET */
3006 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3007 if (table)
3008 combios_parse_ram_reset_table(dev, table);
3009
3010 /* ASIC INIT 3 */
3011 table =
3012 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3013 if (table)
3014 combios_parse_mmio_table(dev, table);
3015
3016 /* write CONFIG_MEMSIZE */
3017 combios_write_ram_size(dev);
3018 }
3019
3020 /* DYN CLK 1 */
3021 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3022 if (table)
3023 combios_parse_pll_table(dev, table);
3024
3025}
3026
3027void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3028{
3029 struct radeon_device *rdev = dev->dev_private;
3030 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3031
3032 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3033 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3034 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3035
3036 /* let the bios control the backlight */
3037 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3038
3039 /* tell the bios not to handle mode switching */
3040 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3041 RADEON_ACC_MODE_CHANGE);
3042
3043 /* tell the bios a driver is loaded */
3044 bios_7_scratch |= RADEON_DRV_LOADED;
3045
3046 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3047 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3048 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3049}
3050
3051void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3052{
3053 struct drm_device *dev = encoder->dev;
3054 struct radeon_device *rdev = dev->dev_private;
3055 uint32_t bios_6_scratch;
3056
3057 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3058
3059 if (lock)
3060 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3061 else
3062 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3063
3064 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3065}
3066
3067void
3068radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3069 struct drm_encoder *encoder,
3070 bool connected)
3071{
3072 struct drm_device *dev = connector->dev;
3073 struct radeon_device *rdev = dev->dev_private;
3074 struct radeon_connector *radeon_connector =
3075 to_radeon_connector(connector);
3076 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3077 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3078 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3079
3080 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3081 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3082 if (connected) {
3083 DRM_DEBUG("TV1 connected\n");
3084 /* fix me */
3085 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3086 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3087 bios_5_scratch |= RADEON_TV1_ON;
3088 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3089 } else {
3090 DRM_DEBUG("TV1 disconnected\n");
3091 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3092 bios_5_scratch &= ~RADEON_TV1_ON;
3093 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3094 }
3095 }
3096 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3097 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3098 if (connected) {
3099 DRM_DEBUG("LCD1 connected\n");
3100 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3101 bios_5_scratch |= RADEON_LCD1_ON;
3102 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3103 } else {
3104 DRM_DEBUG("LCD1 disconnected\n");
3105 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3106 bios_5_scratch &= ~RADEON_LCD1_ON;
3107 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3108 }
3109 }
3110 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3111 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3112 if (connected) {
3113 DRM_DEBUG("CRT1 connected\n");
3114 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3115 bios_5_scratch |= RADEON_CRT1_ON;
3116 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3117 } else {
3118 DRM_DEBUG("CRT1 disconnected\n");
3119 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3120 bios_5_scratch &= ~RADEON_CRT1_ON;
3121 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3122 }
3123 }
3124 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3125 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3126 if (connected) {
3127 DRM_DEBUG("CRT2 connected\n");
3128 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3129 bios_5_scratch |= RADEON_CRT2_ON;
3130 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3131 } else {
3132 DRM_DEBUG("CRT2 disconnected\n");
3133 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3134 bios_5_scratch &= ~RADEON_CRT2_ON;
3135 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3136 }
3137 }
3138 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3139 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3140 if (connected) {
3141 DRM_DEBUG("DFP1 connected\n");
3142 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3143 bios_5_scratch |= RADEON_DFP1_ON;
3144 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3145 } else {
3146 DRM_DEBUG("DFP1 disconnected\n");
3147 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3148 bios_5_scratch &= ~RADEON_DFP1_ON;
3149 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3150 }
3151 }
3152 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3153 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3154 if (connected) {
3155 DRM_DEBUG("DFP2 connected\n");
3156 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3157 bios_5_scratch |= RADEON_DFP2_ON;
3158 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3159 } else {
3160 DRM_DEBUG("DFP2 disconnected\n");
3161 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3162 bios_5_scratch &= ~RADEON_DFP2_ON;
3163 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3164 }
3165 }
3166 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3167 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3168}
3169
3170void
3171radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3172{
3173 struct drm_device *dev = encoder->dev;
3174 struct radeon_device *rdev = dev->dev_private;
3175 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3176 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3177
3178 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3179 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3180 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3181 }
3182 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3183 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3184 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3185 }
3186 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3187 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3188 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3189 }
3190 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3191 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3192 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3193 }
3194 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3195 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3196 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3197 }
3198 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3199 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3200 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3201 }
3202 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3203}
3204
3205void
3206radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3207{
3208 struct drm_device *dev = encoder->dev;
3209 struct radeon_device *rdev = dev->dev_private;
3210 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3211 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3212
3213 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3214 if (on)
3215 bios_6_scratch |= RADEON_TV_DPMS_ON;
3216 else
3217 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3218 }
3219 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3220 if (on)
3221 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3222 else
3223 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3224 }
3225 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3226 if (on)
3227 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3228 else
3229 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3230 }
3231 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3232 if (on)
3233 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3234 else
3235 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3236 }
3237 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3238}
Clone of davem's net-next-2.6 tree